NCP59763AMN080TBG [ONSEMI]
LDO Regulator, 3 A, High Accuracy (1%), Low Noise (4.3 VRMS), Low Dropout (70 mV);
| 型号： | NCP59763AMN080TBG |
| 厂家： | 
ONSEMI |
| 描述： | LDO Regulator, 3 A, High Accuracy (1%), Low Noise (4.3 VRMS), Low Dropout (70 mV) |
| 文件： | 总35页 (文件大小：6016K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LDO Regulator, 3 A, High
Accuracy (1%), Low Noise
(4.3 mVRMS), Low Dropout
(70 mV)
NCP59763
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The NCP59763 is a 3 A capable, low noise (4.3 μV
), ultra low
RMS
dropout (70 mV max. at 3 A), fast load transient response linear
regulator (LDO) equipped with an NMOS pass transistor without the
need of external bias voltage. The device output voltage is adjustable
from 0.5 V to 2.0 V through the use of an external resistor divider and
also available in fixed output versions.
1
The combination of high output current capability, ultra high PSRR
across a wide frequency range and low noise makes this LDO ideal for
powering noise sensitive high speed communication devices. Power
sequencing application flexibility through enable pin, a user
programmable soft−start and a user programmable delayed power good
circuit. Very low dropout voltage (70 mV) and high output voltage
accuracy (1%) enables low input voltage and higher power efficiency.
These set of features makes NCP59763 LDO an ideal solution for
powering analog, digital and mixed signal high current demanding
circuits like analog−to−digital converters (ADCs), digital−to−analog
converters (DACs), high performance serializers and deserializers
(SerDes), application specific integrated circuits (ASICs), field
programmable gate arrays (FPGAs), digital signal processors (DSPs).
DFN10, 3x3
CASE 506EH
MARKING DIAGRAM
59763
Pxxxy
ALYWG
G
59763P = Specific Device Code
xxx
y
A
= Output Voltage Version
= Output Discharge Version
= Assembly Location
= Wafer Lot
Features
L
Y
= Year
= Work Week
= Pb−Free Package
• High Output Current 3 A
W
G
• High Accuracy 1% Including Line/Load Regulation and
Temperature Variation
(Note: Microdot may be in either location)
• Input Voltage Range: 1.1 V to 3.6 V
• Adjustable and Fixed Output Voltage Options Available
♦ Adj Voltage Range: 0.5 V to 2.0 V
ORDERING INFORMATION
See detailed ordering and shipping information on page 33 of
this data sheet.
♦ Fixed: 0.5 V, 0.8 V, 1.0 V, 1.2 V
• Dropout Voltage: 70 mV Typ. at 3 A
• Very Low Output Voltage Noise: 4.3 mV
Typ. (10 Hz – 100 kHz)
RMS
• Excellent Transient Response (20 mV Undershoot at 0.1−3 A Step)
• High PSRR: 70 dB
Typical Applications
• High Speed Analog VCO, ADC, DAC
• FPGAs, DSPs, SerDes
• Imaging Sensors and ASICs
• Communications, Test, Measurement
• Programmable Soft Start
• Open Drain Power Good Output with Programmable Delay
• DFN10 3.0 x 3.0 mm with Enhanced Thermal Performance
• Pb−Free, Halogen Free/BFR Free and are RoHS Compliant
C
10nF
FF
NCP59763
1.1V−3.6V
IN
0.5V−2.0V / 3A
R
ADJ1
IN
OUT
OUT
C
10uF
C
OUT
47uF
IN
EN
FB
CF
R
PG
100k
C
10nF
CF
R
ADJ2
NR/ SS
DELAY
C
NR/SS
100nF
PG
PG
GND
C
DELAY
2.2nF
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
June, 2021 − Rev. 4
NCP59763/D
NCP59763
Current
Limit
IN
OUT
Charge
Pump
Output
discharge
CF
R
NR
Progr.
Voltage
EA
Reference
I
SS
FB
NR/SS
PG
NR/SS
Discharge
90%
of
UVLO
EN
V
REF
I
DELAY
1.0V
0.8V
DELAY
PG
EN
Logic
&
0.8V
Delays
Thermal
Shutdown
Figure 2. Simplified Schematic Block Diagram
1
2
3
4
5
10
9
IN
IN
OUT
OUT
FB
8
CF
GND
7
PG
NR/SS
EN
6
DELAY
(Top View)
Figure 3. Pin Assignment
Table 1. PIN FUNCTION DESCRIPTION
Pin
1,2
3
Name
IN
Description
Input voltage supply pins.
Internal supply filtering capacitor.
Power−Good (PG) is an open−drain, active−high output that indicates the status of V
CF
4
PG
. When V
OUT OUT
OUT
exceeds the PG trip threshold, the PG pin goes into a high−impedance state. When V
is below this
threshold the pin is driven to a low−impedance state. A pull−up resistor from 10 kW to 1 MW should be
connected from this pin to a supply up to 3.6 V. The supply can be higher than the input voltage. Alter-
natively, the PG pin can be left floating if output monitoring is not necessary.
5
DELAY
This pin is intended for adjusting the delay for signaling “V
needs. Capacitor connected from this pin to GND with capacitance of 2.2 nF corresponds to 1 ms delay.
The maximum delay applicable is 100 ms. If delay not necessary the DELAY pin can be left floating.
is OK” according to the user application
OUT
6
7
EN
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shut-
down mode. This pin must not be left floating.
NR/SS
Noise−reduction and soft−start pin. Connecting an external capacitor between this pin and ground
reduces reference voltage noise and also enables the soft−start function. Although not required, a
10 nF or larger capacitor is recommended to be connected from NR/SS to GND (as close to the pin as
possible) to maximize ac performance.
8
FB
This pin is the feedback connection to the center tap of an external resistor divider network that sets
the output voltage. Connect this pin to OUT pin directly when output voltage adjustment is not needed
(then the output voltage V
will be equal to the nominal voltage V
).
OUT
NOM
9,10
TAB
OUT
GND
Regulated output voltage. It is recommended that the output capacitor effective capacitance ≥ 47 mF.
Ground and thermal pad.
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NCP59763
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
−0.3 to +3.6
Unit
V
Input Voltage Range (Note 1)
Enable Voltage Range
V
IN
EN
PG
PG
V
V
−0.3 to +3.6
V
Power−Good Voltage Range
PG Sink Current
−0.3 to +3.6
V
I
0 to +5.0
mA
V
NR/SS Pin Voltage Range
V
NR/SS
Connecting to external voltage not allowed
Connecting to external voltage not allowed
Connecting to external voltage not allowed
−0.3 to +3.6
CF Pin Voltage Range
V
CF
V
DELAY Pin Voltage Range
V
DELAY
V
FB Pin Voltage Range (Adjustable Devices)
Output Voltage Range
V
FB
V
V
−0.3 to (V + 0.3) ≤ 3.6
V
OUT
OUT
IN
Maximum Output Current
I
Internally Limited
Output Short Circuit Duration
Continuous Total Power Dissipation
Maximum Junction Temperature
Storage Junction Temperature Range
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
Indefinite
P
See Thermal Characteristics Table and Formula
D
T
+150
−55 to +150
2000
°C
°C
V
JMAX
T
STG
ESD
ESD
HBM
750
V
CDM
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001, EIA/JESD22−A114
ESD Charged Device Model tested per ANSI/ESDA/JEDEC JS−002, EIA/JESD22−C101
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
Table 3. THERMAL CHARACTERISTICS (Note 3)
Rating
Thermal Resistance, Junction−to−Ambient (Note 4)
Thermal Resistance, Junction−to−Case (top)
Thermal Resistance, Junction−to−Case (bottom) (Note 5)
Thermal Resistance, Junction−to−Board
Symbol
Value
24
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
R
q
JA
R
68
q
JC(top)
R
3.0
3.3
1.3
3.3
q
JC(bot)
R
q
JB
Characterization Parameter, Junction−to−Top
Characterization Parameter, Junction−to−Board
y
JT
y
JB
3. Thermal data based on thermal simulation methodology specified in the JEDEC JESD51 series standards. The following assumptions are
used in the simulations:
These data were generated with only a single device at the center of a high−K (2s2p) board with 3 in x 3 in copper area which follows the
JEDEC51.7 guidelines. Top and bottom layer 2 oz. copper, inner planes 1 oz. copper.
The GND pad connected to the PCB inner GND plane layer through a 3x5 thermal via array. All the vias are 0.3 mm diameter, plated.
4. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7
guidelines with assumptions as above, in an environment described in JESD51−2a.
5. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can
be found in the ANSI SEMI standard G30−88.
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NCP59763
Table 4. RECOMMENDED OPERATING CONDITIONS (Note 6)
Rating
Symbol
Min
1.1
0.5
0
Max
3.6
2.0
3.6
3.6
125
Unit
V
Input Voltage
V
IN
Output Voltage
V
OUT
V
Power−Good Voltage
Enable Voltage Range
Junction Temperature
V
V
PG
EN
V
0
V
T
J
−40
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
Table 5. ELECTRICAL CHARACTERISTICS
At V = 1.2 V or V = V
+ 0.4 V whichever is greater, V = 1.1 V, FB connected to OUT, C = 10 nF, C
= 100 nF, C
NR/SS IN
IN
IN
OUT(NOM)
EN
CF
= 10 mF, C
= 47 mF, I
= 50 mA, T = −40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. (Note 7, 8, 9, 10)
OUT
O
U
T
J
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
OUT
Output voltage range
External resistor divider used
V
OUT
2.0
V
(NOM)
Output voltage accuracy
(Note 11)
V
V
≥ 0.8 V T = −40°C to 125°C −1.0
1.0
1.0
1.0
%
OUT(NOM)
J
< 0.8 V T = −40°C to 100°C −1.0
OUT(NOM)
J
T = 100°C to 125°C −2.0
J
ΔV
/ΔV
Line regulation
V
≥ 1.2 V, V ≥ (V
+ 0.4 V)
0.05
0.01
70
mV/V
%/A
mV
OUT
IN
IN
IN
OUT(NOM)
ΔV
/ΔI
Load regulation
0 mA ≤ I
≤ 3 A
OUT OUT
OUT
V
IN−OUT dropout voltage
I
= 3 A, V = 0 V, V = V
,
130
DO
OUT
FB
IN
OUT
V
V
V
V
≥ 1.2 V
IN
I
Output current limit
≥ 90% x V
3.2
4.0
1.00
0.1
1.1
1
5.2
A
V
CL
OUT
OUT(NOM)
V
Input voltage UVLO threshold
Input voltage UVLO hysteresis
Ground current
rising
0.85
1.15
UVLO−TH
IN
IN
V
falling
V
UVLO−HYS
I
I
= 0 to 3 A
1.8
15
mA
mA
nA
dB
GND
OUT
I
Shutdown supply current
FB pin current
V
V
I
≤ 0.4 V
SHDN
EN
FB
I
= V
−250
10
250
FB
OUT
PSRR
Noise
Power supply rejection ratio
= 1 A
1 kHz
70
OUT
10 kHz
500 kHz
50
35
Output noise voltage
10 Hz to 100 kHz, l
= 3 A
4.3
17
mV
RMS
OUT
dV
OUT OUT
/dI
Output voltage load transient
response
I
= 50 mA to 3 A at 1 A/ms
mV
OUT
t
Minimum startup time (Note 12)
I
= 3 A, NR/SS = open
200
6.0
ms
START
OUT
I
SS
Soft−start charging current
V
= 0 V
V
≤ 0.9 V
> 0.9 V
mA
NR/SS
OUT(NOM)
OUT(NOM)
V
12.0
160
R
Soft−start discharging resistance V = 2.4 V, V = 0.5 V
W
V
SS−DIS
IN
SS
V
Enable input threshold
Enable pin hysteresis
Enable pin current
PG trip threshold
V
V
V
V
V
rising
0.4
0.9
EN−TH
EN
V
falling
= 3.6 V
50
0.3
90
3
mV
mA
EN−HYS
EN
I
1
EN
EN
V
falling
rising
86.5
93.5
%V
%V
PG−TH
OUT
OUT
OUT(NOM)
V
PG trip hysteresis
PG−HYS
OUT(NOM)
V
PG output low voltage
PG leakage current
I
= 1 mA (sinking), V
< V
PG−TH
0.3
1
V
PG−LO
PG
OUT
I
V
= 3.6 V, V
> V
PG−TH
0.01
mA
PG−LK
PG
OUT
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NCP59763
Table 5. ELECTRICAL CHARACTERISTICS
At V = 1.2 V or V = V
+ 0.4 V whichever is greater, V = 1.1 V, FB connected to OUT, C = 10 nF, C
= 100 nF, C
NR/SS IN
IN
IN
OUT(NOM)
EN
CF
= 10 mF, C
= 47 mF, I
= 50 mA, T = −40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. (Note 7, 8, 9, 10)
OUT
O
U
T
J
J
Symbol
Parameter
Test Conditions
Min
Typ
20
Max
Unit
ms
t
PG deglitch time
PG−DGL
I
DELAY pin charging current
DELAY trip threshold
V
V
V
V
= 0 V
1.8
800
30
mA
DELAY
DELAY
DELAY
DELAY
V
rising
falling
mV
mV
W
-
DELAY TH
V
DELAY trip hysteresis
-
DELAY HYS
R
Output Active Discharge
Resistance
= 0 V, V = 3.3 V, V = 2.0 V
OUT
100
AD
EN
IN
TSD
Thermal shutdown temperature Temperature rising
threshold high
165
140
°C
Thermal shutdown temperature Temperature falling
threshold low
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T = 25°C.
A
8. V
is the output voltage specified by OPN. It could be seen at the output pin when FB pin is connected to OUT pin directly (without
OUT(NOM)
resistor divider).
9. Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
10.The device is not tested under conditions where the power dissipation is higher than the maximum rating of the package.
11. Additional test conditions: V ≥ 1.2 V and V ≥ (V
+ 0.4 V), I
= 50 mA to 3 A.
IN
IN
OUT(NOM)
OUT
12.Minimum startup time is a time measured from EN rising edge to a point where V
reaches 95% of V
.
OUT
NOM
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NCP59763
TYPICAL CHARACTERISTICS
V
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C
= 2.2 nF, C = 10 nF,
IN
OUT−NOM
IN
EN
OUT
CF
NR/SS
DELAY FF
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
2.0
1.25
V
IN
V
IN
= (V
≥ 1.2 V
+ 0.4 V) to 3.6 V,
OUT_NOM
1.00
0.75
0.50
0.25
0.00
1.5
1.0
Hi Lim
V
V
= (V
≥ 1.2 V,
= 50 mA to I
+ 0.4 V) to 3.6 V,
IN
IN
OUT_NOM
I
OUT
NOM
0.5
V
OUT
0.0
−0.25
−0.50
−0.75
−0.5
−1.0
Lo Lim
−1.5
−2.0
−1.00
−1.25
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 4. Output Voltage vs. Temperature
Figure 5. Line Regulation vs. Temperature
0.09
0.06
0.03
0.00
0.03
140
130
120
I
= 0 mA to 3 A
OUT
Hi Lim
0.02
0.01
0.00
110
100
90
Vdo
80
70
−0.03
−0.06
−0.09
−0.01
−0.02
−0.03
60
50
I
= 3 A
OUT
40
30
V
IN
= V
NOM
−40 −20
0
20 40 60 80 100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 6. Load Regulation vs. Temperature
Figure 7. Dropout Voltage vs. Temperature
70
69
68
67
66
65
64
63
62
61
60
70
60
50
40
30
20
I
V
= 3 A
OUT
V
IN
= V
NOM
= V
IN
NOM
10
0
0
0.5
1
1.5
2
2.5
3
1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9
2
I , OUTPUT CURRENT (A)
OUT
V
NOM
, NOMINAL OUTPUT VOLTAGE (V)
Figure 8. Dropout Voltage vs. Output Current,
All Voltage Versions
Figure 9. Dropout Voltage vs. VNOM
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NCP59763
TYPICAL CHARACTERISTICS
V
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C
= 2.2 nF, C = 10 nF,
IN
OUT−NOM
IN
EN
OUT
CF
NR/SS
DELAY FF
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
1.9
1.8
Hi Lim
V
= 0.9 x V
OUT_NOM
I
= 0 mA
Hi Lim
OUT_FORCED
OUT
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
I
CL
I
Q
Lo Lim
3.2
3.0
−40 −20
0.8
0.7
−40 −20
0
20
40
60
80
100 120
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 10. Current Limit vs. Temperature
Figure 11. Quiescent Current vs. Temperature
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
V
= V
= I
+ 0.4 V,
V
= 3.6 V,
= I
Hi Lim
Hi Lim
IN
OUT_NOM
IN
I
I
OUT
NOM
OUT NOM
I
GND2
I
GND1
0.8
0.7
−40 −20
0.8
0.7
−40 −20
0
20
40
60
80
100 120
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 12. Ground Current vs. Temperature
Figure 13. Ground Current vs. Temperature
300
250
200
150
100
50
16
15
14
13
12
11
10
9
Hi Lim
V
EN
≤ 0.4 V
Hi Lim
I
FB
8
0
7
−50
−100
−150
−200
6
5
4
3
Lo Lim
2
1
0
I
−250
−300
SHDN
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 14. Shutdown Current vs. Temperature
Figure 15. Feedback Current vs. Temperature
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NCP59763
TYPICAL CHARACTERISTICS
V
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C
= 2.2 nF, C = 10 nF,
IN
OUT−NOM
IN
EN
OUT
CF
NR/SS
DELAY FF
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
160
1.0
V
EN
rising
V
EN
falling
140
120
100
80
0.9
0.8
0.7
0.6
0.5
Hi Lim
V
EN_TH
60
40
Lo Lim
0.4
0.3
20
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 16. Enable Threshold Voltage vs.
Temperature
Figure 17. Enable Hysteresis vs. Temperature
600
500
400
300
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
NR/SS pin open
V
EN
= 3.6 V
Hi Lim
I
EN
200
100
0
0.1
0.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 18. Enable Input Current vs.
Temperature
Figure 19. Minimum Startup Time vs.
Temperature
14
12
10
8
250
200
150
100
V
SS
= 0 V
V
V
= 2.4 V
= 0.5 V
IN
SS
V
V
≤ 0.9 V
OUT(NOM)
> 0.9 V
OUT(NOM)
6
4
50
0
2
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 20. Soft−Start Charging Current vs.
Figure 21. Soft−Start Discharging Resistance
Temperature
vs. Temperature
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8
NCP59763
TYPICAL CHARACTERISTICS
V
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C
= 2.2 nF, C = 10 nF,
IN
OUT−NOM
IN
EN
OUT
CF
NR/SS
DELAY FF
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
1.20
1.15
1.10
1.05
1.00
0.95
0.30
V
IN
rising
V
IN
falling
0.25
0.20
0.15
Hi Lim
V
UVLO_TH
0.10
0.05
0.00
Lo Lim
0.90
0.85
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 22. UVLO Threshold Voltage vs.
Temperature
Figure 23. UVLO Hysteresis vs. Temperature
94
93
92
91
90
89
88
6
5
4
3
2
V
OUT
rising
V
OUT
falling
Hi Lim
V
PG_TH
1
0
Lo Lim
87
86
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 24. PG Trip Threshold Voltage vs.
Temperature
Figure 25. PG Trip Hysteresis vs. Temperature
0.35
0.30
0.25
0.20
0.15
0.10
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
V
V
= 3.6 V
Hi Lim
PG
I
V
= 1 mA
Hi Lim
PG
> V
OUT
PG_TH
< V
OUT
PG_TH
V
PG_LO
V
PG_LK
0.05
0.00
0.0
−0.1
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 26. PG Output Low Voltage vs.
Temperature
Figure 27. PG Leakage Current vs.
Temperature
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NCP59763
TYPICAL CHARACTERISTICS
V
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C
= 2.2 nF, C = 10 nF,
IN
OUT−NOM
IN
EN
OUT
CF
NR/SS
DELAY FF
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
820
810
800
790
780
70
V
DELAY
rising
V
DELAY
falling
60
50
40
30
770
760
750
20
10
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 28. DELAY Threshold Voltage vs.
Temperature
Figure 29. DELAY Hysteresis vs. Temperature
2.6
2.4
2.2
2.0
1.8
1.6
1.5
1.4
1.3
1.2
V
DELAY
= 1.0 V
V
DELAY
= 1.0 V
1.4
1.2
1.0
1.1
1.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 30. DELAY Discharging Resistance vs.
Temperature
Figure 31. DELAY Charging Current vs.
Temperature
110
108
106
104
102
100
98
V
V
V
= 0 V,
= 3.3 V,
EN
IN
= 2.0 V
OUT
96
94
92
90
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
Figure 32. Active Dischare Resistance vs.
Temperature
www.onsemi.com
10
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
1
1
*1
*2
*1 *2
ADJ V
ADJ V
FIX V
= 1 V
= 1 V
= V
V
V
= 0.5 V
= 0.5 V
C
FF
C
FF
C
FF
= 0 nF
10.9 20.7 mV
OUT
OUT
NOM
RMS
RMS
RMS
V
NOM
V
NOM
V
NOM
V
NOM
V
NOM
V
NOM
= 0.5 V 4.4 9.5 mV
= 0.8 V 4.1 8.9 mV
= 1.0 V 4.3 9.3 mV
= 1.2 V 4.6 9.7 mV
= 1.8 V 4.4 9.9 mV
= 2.0 V 5.3 9.8 mV
RMS
= 10 nF 4.8
= NA 4.3
9.7
9.3
mV
mV
NOM
= 1.0 V
RMS
RMS
RMS
RMS
RMS
OUT
NOM
R
and R
according to Table 6.
set
ADJ1
ADJ2
0.1
0.1
0.01
0.01
I = 1 A
OUT
I
= 1 A
OUT
V
IN
= V
+ 0.2 V & V ≥ 1.2 V
V
IN
= 1.2 V
NOM
IN
*1: Integral noise 10 Hz − 100 kHz
*2: Integral noise 10 Hz − 1 MHz
*1: Integral noise 10 Hz − 100 kHz
*2: Integral noise 10 Hz − 1 MHz
0.001
10
0.001
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 34. Output Noise Spectral Density of
ADJ (w/ and w/o CFF) and FIX Applications
Figure 33. Output Noise Spectral Density vs. Device
Voltage Version (VNOM), FIX Application
1
1
*1 *2
*1 *2
V
IN
V
IN
V
IN
= 1.2 V 4.3 9.3 mV
= 1.5 V 4.5 9.7 mV
= 1.8 V 4.9 10.1 mV
V
IN
V
IN
V
IN
V
IN
= 2.2 V 5.3 9.8 mV
= 2.8 V 6.4 11.3 mV
= 3.3 V 7.0 12.0 mV
= 3.6 V 7.2 12.4 mV
RMS
RMS
RMS
RMS
RMS
RMS
RMS
0.1
0.01
0.1
0.01
I = 1 A
OUT
I = 1 A
OUT
V
OUT
= V
= 1.0 V (FIX appl)
V
OUT
= V
= 2.0 V (FIX appl)
NOM
NOM
*1: Integral noise 10 Hz − 100 kHz
*2: Integral noise 10 Hz − 1 MHz
*1: Integral noise 10 Hz − 100 kHz
*2: Integral noise 10 Hz − 1 MHz
0.001
0.001
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 35. Output Noise Spectral Density vs. Input
Voltage (VIN), FIX Application
Figure 36. Output Noise Spectral Density vs. Input
Voltage (VIN), FIX Application
1
1
*1
*2
*1 *2
C
C
C
C
C
= 0 nF
= 1 nF
25.1 26.5 mV
11.9 14.6 mV
NR
NR
NR
NR
NR
RMS
I
I
I
= 1 A 4.0 10.3 mV
= 2 A 4.1 11.1 mV
= 3 A 4.3 11.5 mV
OUT
OUT
OUT
RMS
RMS
RMS
RMS
RMS
RMS
RMS
= 10 nF 6.1
= 100 nF 4.6
= 300 nF 4.4
10.5 mV
9.7
9.6
mV
mV
0.1
0.01
0.1
0.01
I
V
= 1 A
V
V
= V
= 1.2 V
= 0.8 V (FIX appl)
OUT
OUT
NOM
= V
= 1.2 V (FIX appl)
OUT
NOM
IN
*1: Integral noise 10 Hz − 100 kHz
*2: Integral noise 10 Hz − 1 MHz
*1: Integral noise 10 Hz − 100 kHz
*2: Integral noise 10 Hz − 1 MHz
0.001
0.001
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 37. Output Noise Spectral Density vs.
Noise Reduction Capacitor (CNR), FIX Application
Figure 38. Output Noise Spectral Density vs.
Load Current, VNOM = 0.8 V, FIX Application
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11
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
1
1
*1
= 0.01 A 5.7
= 0.1 A 5.9
= 0.5 A 4.5
*2
*1 *2
I
I
I
I
I
I
5.9
8.0
8.9
9.7
10.2 mV
10.4 mV
mV
mV
mV
mV
OUT
OUT
OUT
OUT
OUT
OUT
RMS
V
V
V
V
= 0.5 V (FIX) 4.3 9.3 mV
= 1.0 V (ADJ) 4.7 9.4 mV
= 1.2 V (ADJ) 5.0 9.7 mV
= 1.8 V (ADJ) 5.6 10.4 mV
OUT
OUT
OUT
OUT
RMS
RMS
RMS
RMS
RMS
RMS
RMS
RMS
RMS
= 1 A
= 2 A
= 3 A
4.6
4.7
4.9
0.1
0.1
0.01
R
and R
set
ADJ1
ADJ2
according to Table 6.
V
V
= V
NOM
+ 0.2 V & V ≥ 1.2 V
= 0.5 V (FIX & ADJ apps)
0.01
IN
IN
V
V
= V
= 1.4 V
= 1.2 V (FIX appl)
OUT
NOM
NOM
IN
I
= 1 A
OUT
*1: Integral noise 10 Hz − 100 kHz
*2: Integral noise 10 Hz − 1 MHz
*1: 10 Hz − 100 kHz
*2: 10 Hz − 1 MHz
0.001
10
0.001
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 39. Output Noise Spectral Density vs.
Load Current, VNOM = 1.2 V, FIX Application
Figure 40. Output Noise Spectral Density vs. VOUT,
V
NOM = 0.5 V, FIX & ADJ Applications
110
100
90
80
70
60
50
40
30
20
10
0
1
*1 *2
= 0.5 V 5.6 10.4 mV
Vin = 1.1 V
V
V
Vin = 1.2 V
Vin = 1.4 V
Vin = 2.6 V
Vin = 3.0 V
NOM
NOM
RM
= 1.2 V 5.0 10.3 mV
RMS
V
V
= V
+ 0.2 V
IN
OUT
= 1.8 V (ADJ apps)
= 1 A
*1: 10 Hz − 100 kHz
*2: 10 Hz − 1 MHz
OUT
0.1
0.01
I
OUT
FIX application
V
OUT
= V
= 0.5 V
NOM
R
and R
set
ADJ1
ADJ2
I
= 1 A
OUT
according to Table 6.
C
= None
IN
0.001
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 41. Output Noise Spectral Density vs.
VNOM, VOUT = 1.8 V, ADJ Application
Figure 42. PSRR vs. Frequency and VIN,
V
NOM = 0.5V, FIX Application
110
100
90
80
70
60
50
40
30
20
10
0
110
100
90
80
70
60
50
40
30
20
10
0
Cff = 0 n
Cff = 1 n
Cff = 10 n
ADJ application
Vin = 1.2 V
Vin = 1.4 V
V
V
V
= 0.5 V
= 1.0 V
= 1.4 V
NOM
OUT
FIX application
IN
V
I
C
= V
= 1.0 V
OUT
NOM
I
= 1 A
OUT
= 1 A
= None
OUT
C
= None
IN
IN
R
and R
set
ADJ1
ADJ2
according to Table 6.
100k 1M
FREQUENCY (Hz)
10
100
1k
10k
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 43. PSRR vs. Frequency and CFF,
NOM = 0.5 V, ADJ Application
Figure 44. PSRR vs. Frequency and VIN,
NOM = 1.0 V, FIX Application
V
V
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12
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
110
100
90
80
70
60
50
40
30
20
10
0
110
Io=10 mA
Vin = 1.4 V
100
90
80
70
60
50
40
30
20
10
0
Io = 0.1 A
Io = 0.2 A
Io = 0.5 A
Io = 1 A
Vin = 1.6 V
Vin = 1.8 V
Vin = 2.2 V
Vin = 3.2 V
Io = 2 A
FIX application
FIX application
V
V
C
= V
= 1.6 V
= None
= 1.2 V
V
I
= V
= 1 A
= 1.2 V
OUT
NOM
OUT
NOM
IN
OUT
C
= None
IN
IN
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 45. PSRR vs. Frequency and VIN,
Figure 46. PSRR vs. Frequency and IOUT
,
V
NOM = 1.2 V, FIX Application
VNOM = 1.2 V, FIX Application
110
100
90
80
70
60
50
40
30
20
10
0
110
100
90
80
70
60
50
40
30
20
10
0
Co = 47 m + 10 m + 100 n
Co = 100 m + 47 m + 10 m + 100 n
Co = 1000 m + 47 m + 10 m + 100 n
Cnr = 0 n
Cnr = 1 n
Cnr = 10 n
Cnr = 100 n
FIX application
= V = 1.2 V
V
OUT
NOM
I
= 1 A
= None
OUT
C
IN
FIX application
V
V
= V
= 1.6 V
= 1.2 V
OUT
NOM
IN
I
= 1 A
OUT
C
= None
IN
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 47. PSRR vs. Frequency and COUT
,
Figure 48. PSRR vs. Frequency and CNR/SS
,
V
NOM = 1.2 V, FIX Application
V
NOM = 1.2 V, FIX Application
110
100
90
80
70
60
50
40
30
20
10
0
110
100
90
80
70
60
50
40
30
20
10
0
Vnom = 0.5 V (ADJ)
Vnom = 1.0 V (FIX)
Vin = 2.2 V
Vin = 2.3 V
Vin = 2.4 V
Vin = 3.0 V
Vin = 3.4 V
R
and R
set
ADJ1
ADJ2
according to Table 6.
R
and R
set
ADJ1
ADJ2
according to Table 6.
ADJ vs. FIX app
V
V
I
= 1.0 V
= 1.4 V
= 1 A
FIX application
OUT
V
I
= V
= 2.0 V
1k
IN
OUT
NOM
= 1 A
= None
OUT
OUT
C
= None
C
IN
IN
10
100
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 49. PSRR vs. Frequency and VIN,
NOM = 2.0 V, FIX Application
Figure 50. PSRR vs. Frequency of FIX (1.0 V) and
ADJ (0.5 V set to 1.0 V) Applications
V
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13
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
Figure 51. Load Transient Response, FIX−0.5V
Figure 52. Load Transient Response, FIX−0.5V
Figure 53. Load Transient Response, FIX−0.5V
Figure 54. Load Transient Response, FIX−0.5V
Note A
Figure 55. Load Transient Response, FIX−0.5V
Figure 56. Load Transient Response, FIX−0.5V
Note A: The V
cycling after transient going from high to idle (low) load current is not a feedback loop oscillation, it is just a combination of two different actions: small overshoot
OUT
above V
(caused by limited error amp speed and light load condition at once) what is LDO related and slow C
discharging by the light load current, what is related to
OUT
OUT−NOM
C
and idle I
only. Bigger C
capacitor value and lower idle state load current makes the cycling amplitude and count higher.
OUT
OUT
OUT
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14
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
Note A
Figure 57. Load Transient Response, FIX−0.5V
Figure 58. Load Transient Response, FIX−0.5V
Figure 59. Load Transient Response, FIX−1.2V
Figure 60. Load Transient Response, FIX−1.2V
Figure 61. Load Transient Response, FIX−1.2V
Figure 62. Load Transient Response, FIX−1.2V
Note A: The V
cycling after transient going from high to idle (low) load current is not a feedback loop oscillation, it is just a combination of two different actions: small overshoot
OUT
above V
(caused by limited error amp speed and light load condition at once) what is LDO related and slow C
discharging by the light load current, what is related to
OUT
OUT−NOM
C
and idle I
only. Bigger C
capacitor value and lower idle state load current makes the cycling amplitude and count higher.
OUT
OUT
OUT
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15
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
Note A
Note A
Figure 63. Load Transient Response, FIX−1.2V
Figure 64. Load Transient Response, FIX−1.2V
Note A
Note A
Figure 65. Load Transient Response,
Figure 66. Load Transient Response,
ADJ−0.5V set to 1.2V
ADJ−0.5V set to 1.2V
Note A
Figure 67. Load Transient Response,
ADJ−0.5V set to 1.2V
Note A: The V
cycling after transient going from high to idle (low) load current is not a feedback loop oscillation, it is just a combination of two different actions: small overshoot
OUT
above V
(caused by limited error amp speed and light load condition at once) what is LDO related and slow C
discharging by the light load current, what is related to
OUT
OUT−NOM
C
and idle I
only. Bigger C
capacitor value and lower idle state load current makes the cycling amplitude and count higher.
OUT
OUT
OUT
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16
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
Figure 68. Load Transient Response,
Figure 69. Load Transient Response,
ADJ−0.5V set to 1.2V
ADJ−0.5V set to 1.2V
Figure 70. Load Transient Response,
ADJ−0.5V set to 1.2V
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17
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
Figure 71. Load Transient Response,
Figure 72. Load Transient Response,
ADJ−0.5V set to 1.2V
ADJ−0.5V set to 1.2V
Figure 73. Load Transient Response,
Figure 74. Load Transient Response,
ADJ−0.5V set to 1.2V
ADJ−0.5V set to 1.2V
Figure 75. Load Transient Response,
ADJ−0.5V set to 1.2V
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18
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
Figure 76. Load Transient Response,
Figure 77. Load Transient Response,
ADJ−0.5V set to 1.2V
ADJ−0.5V set to 1.2V
Figure 78. Load Transient Response,
Figure 79. Load Transient Response,
ADJ−0.5V set to 1.2V
ADJ−0.5V set to 1.2V
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19
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
Figure 80. Load Transient Response,
Figure 81. Load Transient Response,
ADJ−0.5V set to 1.2V
ADJ−0.5V set to 1.2V
Figure 82. Load Transient Response,
Figure 83. Load Transient Response,
ADJ−0.5V set to 1.2V
ADJ−0.5V set to 1.2V
Figure 84. Load Transient Response,
Figure 85. Load Transient Response,
ADJ−0.5V set to 1.2V
ADJ−0.5V set to 1.2V
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NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C = 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT J
Figure 86. Load Transient Response,
ADJ−0.5V set to 1.2V
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21
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
VOUT =1.2V (ADJ), VNOM=0.5V, IOUT=100mA
VOUT =1.2V (ADJ), VNOM=0.5V, IOUT=100mA
tPG−DELAY
(by CDELAY
VEN−TH
)
VEN−TH
C1: V
200mV/div
200mV/div
200mV/div
200mV/div
2ms/div
C1: V
200mV/div
200mV/div
200mV/div
200mV/div
2ms/div
IN
IN
C2: VOUT
C3: VEN
C4: VPG
C2: VOUT
C3: VEN
C4: VPG
Figure 87. EN−pin Startup, Fast Ramp Up
Figure 88. EN−pin Startup, Slow Ramp Up
VOUT=1.2V (ADJ),VNOM=0.5V, IOUT=100mA
VOUT=1.2V (ADJ),VNOM=0.5V,
OUT=100mA
CNR/SS=1nF CNR/SS=10nF
I
C =1nF
FF
VUVLO−TH
CNR/SS=33nF
C =10nF
FF
CFF=33nF
CNR/SS=100nF
C1: V =VEN 200mV/div
2ms/div
C1: V =VEN 200mV/div
500μs/div
IN
IN
C2: VOUT
200mV/div
C2: VOUT
C3: VFB
200mV/div
200mV/div
Figure 90. IN−pin Startup for Different CFF,
Figure 89. N−pin Startup for Different CNR/SS
,
ADJ Application
ADJ Application
VOUT=1.2V (FIX), VNOM=1.2V,
OUT=100mA
=100kΩ
VOUT=1.2V (ADJ),VNOM=0.5V, IOUT=100mA, RPG
CNR/SS=1nF CNR/SS=10nF
I
VPG−TH
VUVLO−TH
VUVLO−TH
CNR/SS=33nF
VDELAY−TH
CNR/SS=100nF
C1: V =VEN 200mV/div
2ms/div
C1: V =VEN 200mV/div
2ms/div
IN
IN
C2: VOUT
200mV/div
C2: VOUT
C3: VDELAY
C4: VPG
200mV/div
200mV/div
200mV/div
Figure 91. IN−pin Startup for Different CNR/SS,
Figure 92. Startup DELAY and PG Behavior
FIX Application
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NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C = 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT J
=100kΩ
V
OUT=1.2V (FIX), VNOM=1.2V, IOUT=100mA
VOUT=1.2V (FIX), VNOM=1.2V, IOUT=100mA, RPG
VPG−TH + VPG−TH
VPG−TH+VPG−HYS
VPG−TH
< tPG−DGL
tPG−DGL
VDELAY−TH
No DELAY &PG
reaction
CDELAY =0nF
CDELAY =2.2nF
CDELAY =10nF
CDELAY=330pF
=100kW
RPG
C1: V =VEN 200mV/div
5ms/div
C1: V =VEN 200mV/div
100μs/div
IN
IN
C2: VOUT
C4: VPG
200mV/div
200mV/div
C2: VOUT
C3: VDELAY
C4: VPG
200mV/div
200mV/div
200mV/div
Figure 93. Startup PG Behavior for Different CDELAY
Figure 94. DELAY and PG Signals Behavior During
OUT Drops
V
EN = IN
ADJ1 =12.7k
ADJ2 =9k1
100mA (load resitance 12Ohm)
R
R
V
C
is delayed to V and rounded because of
FB
IIN
OUT
(info in appl. section). But V is at 90% of
FF
FB
V
what triggers C
charging
DELAY
NOM
V
IN
= 1.4 V
CIN discharging −by power supply (sink)
V
OUT
= 1.2 V
V
IN
= V
UVLO−TH
VPG
V
IN
= V
− V
=> turn−off
UVLO−TH
UVLO−HY
V
DLY
= V
DLY−TH
V
NR/SS
= V
= 0.5 V
REF
All=0V
VIN =200mV/div VOUT =200mV/div VPG=200mV/div VNR/SS=200mV/div VDLY=200mV/div IIN =100mA/div
1ms/div
Figure 95. Start−up and Shut−down by VIN Voltage, ADJ Application, VNOM = 0.5 V, VOUT = 1.2 V
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23
NCP59763
TYPICAL CHARACTERISTICS
V
IN
= V
+ 0.4 V and V ≥ 1.2 V, V = 1.1 V, FB = OUT, I
= 50 mA, C = 10 nF, C
= 100 nF, C = 2.2 nF, C = 10 nF,
DELAY FF
OUT−NOM
IN
EN
OUT
CF
NR/SS
C
IN
= 1 mF (polymer) + 100 mF (C1210) + 10 mF + 100 nF, C
= 47 mF (C1210) + 10 mF + 100 nF, T = 25°C, unless otherwise noted.
OUT
J
28
3,5
5
R
= 24°C/W
R
= 24°C/W
q
q
JA
JA
27
26
25
24
23
22
21
20
4,8
4,6
4,4
4,2
4
3,0
2,5
2,0
1,5
1,0
0,5
0,0
Vout = 0.6 V
Vout = 0.8 V
Vout = 1.0 V
Vout = 1.2 V
Vout = 1.8 V
3,8
3,6
3,4
1
1,5
2
2,5
3
3,5
0
200
400
600
800
2
V
IN
, INPUT VOLTAGE (V)
Copper Heat Spreader Area (mm )
Theta−JA Curve With PCB Copper Thick: 1 oz
Theta−JA Curve With PCB Copper Thick: 2 oz
Power Curve With PCB Copper Thick: 1 oz
Power Curve With PCB Copper Thick: 2 oz
Figure 97. Max. Allowable Output Current vs. VIN,
FIX & ADJ Applications, TA = 255C
Figure 96. RqJA and PDIS(MAX) vs. Copper Area
3,5
3,0
2,5
2,0
1,5
1,0
0,5
0,0
3,5
R
= 24°C/W
R
= 24°C/W
q
q
JA
JA
3,0
2,5
2,0
1,5
1,0
0,5
0,0
Vout = 0.6 V
Vout = 0.8 V
Vout = 1.0 V
Vout = 1.2 V
Vout = 1.8 V
Vout = 0.6 V
Vout = 0.8 V
Vout = 1.0 V
Vout = 1.2 V
Vout = 1.8 V
1
1,5
2
2,5
3
3,5
1
1,5
2
2,5
3
3,5
V
IN
, INPUT VOLTAGE (V)
V
IN
, INPUT VOLTAGE (V)
Figure 99. Max. Allowable Output Current vs. VIN,
Figure 98. Max. Allowable Output Current vs. VIN,
FIX & ADJ Applications, TA = 755C
FIX & ADJ Applications, TA = 505C
Additional Information to Figures on this Page
Thermal data are based on thermal simulation
methodology specified in the JEDEC JESD51 series
standards. The following assumptions are used in the
simulations:
These data were generated with only a single device at the
center of a high−K (2s2p) board which follows the
JEDEC51.7 guidelines. Top and bottom layer 2 oz. copper,
inner planes 1 oz. copper. The GND pad connected to the
PCB inner GND plane layer through a 3x5 thermal via array.
All the vias are 0.3 mm diameter, plated.
The junction−to−ambient thermal resistance under
natural convection is obtained in a simulation on a high−K
board, following the JEDEC51.7 guidelines with
assumptions as above, in an environment described in
JESD51−2a.
TA = 25°C, TJ = TJ(MAX) = 125°C, unless otherwise noted.
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24
NCP59763
APPLICATIONS INFORMATION
Input Capacitor Selection (CIN)
When adjustment of output voltage is not needed then
simply connect the FB pin to OUT pin and the output voltage
will be equal to the nominal output voltage specified by
Input capacitor connected as close as possible is necessary
to ensure device stability. The ceramic X7R or X5R
capacitor should be used for reliable performance over
temperature range. The value of the input capacitor should
be at least 10 mF, recommended value is parallel
combination of 47 mF + 100 nF. Maximum value is not
limited and the higher means better for the LDO, as this
capacitor will provide a low impedance path for unwanted
AC signals or noise modulated onto the input voltage. There
is no requirement for the ESR of the input capacitor but it is
recommended to use ceramic capacitor for its low ESR and
ESL. A good input capacitor will limit the influence of input
trace inductance and source resistance during load current
changes. When a large load transients (like 10 mA to 3 A)
happens in the application the input power source of the
LDO needs to provide enough power and the input voltage
must not go below the level defined by this equation:
OPN: V
= V . If the adjustment is important,
NOM
OUT
connect the output voltage resistor divider between OUT,
FB and GND pins. Then the output voltage can be computed
by the following equation:
RADJ1
ǒ1 ) Ǔ
VOUT + VNOM
) IFB RADJ1
(eq. 1)
RADJ2
Where:
V
OUT
is output voltage of the circuit with resistor divider
(adjustable application).
V
NOM
is the LDO’s nominal output voltage given by
OPN.
I
is the LDO’s FB pin input current.
FB
R
R
is the upper resistor in resistor divider.
is the lower resistor in resistor divider.
ADJ1
V
IN
= V + V otherwise the output voltage drop
OUT−NOM DO
ADJ2
will be significantly higher (because LDO will enter the
dropout state). In cases when LDO’s input power supply has
a poor load transient response or when there is a long
connection between LDO and its power source then the
input capacitor needs to be significantly bigger (in range of
hundreds of mF).
Recommended values of R
and R
are in range
ADJ2
ADJ1
from 1 kW to about 300 kW.
Both circuits of FIX (non−adjustable) and ADJ
(adjustable) applications are shown at the following figures.
CFF
10 nF
NCP 59763
1.1 V − 3.6 V
IN
0.5 V − 2.0 V/3 A
RADJ1
Output Capacitor Selection (COUT
)
IN
OUT
FB
OUT
COUT
47 mF +
10 mF +
The LDO requires the output capacitor connected as close
as possible to the output and ground pins. The LDO is
designed to remain stable with output capacitor’s effective
capacitance in range from 40 mF to 1000 mF and ESR from
1 mW to 50 mW. The ceramic X5R or better type is
recommended due to its low capacitance variations over the
specified temperature range and low ESR. When selecting
the output capacitor the value change with temperature and
DC bias voltage needs to be taken into account. Especially
for small package size capacitors such as 0805 or smaller the
effective capacitance drops rapidly with the applied DC bias
voltage (refer the capacitor’s datasheet for details).
Recommended is parallel combination of ceramic
capacitors 47 mF (1210 package) + 10 mF (0805 package) +
100 nF (any small package like 0603, 0402 etc.).
CIN
10 mF
EN
100 nF
RPG
100 kW
CF
CCF
10 nF
R
ADJ2
NR / SS
DELAY
Optional
CNR/SS
100 nF
PG
PG
GND
CDE LAY
2.2 nF
Optional
Figure 100. ADJ (Adjustable) Application Schematic
NCP 59763
1.1 V − 3.6 V
0.5 V − 2.0 V/3 A
IN
OUT
FB
IN
OUT
COUT
47 mF +
10 mF +
100 nF
CIN
EN
10 mF
CF
RPG
Larger capacitance and lower capacitor ESR improves the
load transient response, PSRR and output voltage noise.
CCF
10 nF
100 kW
Optional
NR / SS
DELAY
CNR/SS
100 nF
PG
PG
GND
Internal Supply Bypass Capacitor (CCF
)
CDE LAY
2.2 nF
Optional
This capacitor is needed to stabilize the internal power rail
generated by the on−chip high frequency charge pump. This
charge pump generates a minimal amount of noise but is
suppressed to almost zero with additional on−chip isolation
and circuits.
Figure 101. FIX (Non−adjustable) Application Schematic
At the ADJ application, the external resistor divider with
input FB pin capacity and FB pin PCB trace capacity to
GND makes a low pass filter what negatively affects the
dynamic behavior of the LDO. This unwanted dynamic
performance degradation could be compensated by adding
Output Voltage
NCP59763 part is available in several output voltage
options (see OPNs table). All of these options could be used
in fixed (non−adjustable) or adjustable application circuit.
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25
NCP59763
of feed−forward capacitor C
across R
resistor.
ADJ1
FF
Table 6. RECOMMENDED FEEDBACK PART VALUES
Recommended value is 10 nF and its influence to several
parameters is shown at figures in Typical characteristics
section.
V
Part
V
R R V
Diff
[%]
OUT
NOM ADJ1 ADJ2 OUT2
[V]
0.5
0.6
0.7
0.8
(OPN)
[V] [kW] [kW] [V]
NCP59763AMN050
NCP59763AMN050
NCP59763AMN050
NCP59763AMN050
NCP59763AMN080
NCP59763AMN050
NCP59763AMN080
NCP59763AMN050
NCP59763AMN080
NCP59763AMN100
NCP59763AMN050
NCP59763AMN080
NCP59763AMN100
NCP59763AMN050
NCP59763AMN080
NCP59763AMN100
NCP59763AMN120
NCP59763AMN050
NCP59763AMN080
NCP59763AMN100
NCP59763AMN120
NCP59763AMN050
NCP59763AMN080
NCP59763AMN100
NCP59763AMN120
NCP59763AMN050
NCP59763AMN080
NCP59763AMN100
NCP59763AMN120
0.5 Short None 0.500 0.0
The C capacitor on one hand improves dynamic
FF
behavior of LDO in ADJ application but on the other hand
0.5
0.5
0.5
15
12
12
75 0.600 0.0
30 0.700 0.0
20 0.800 0.0
it rounds and delays the V
voltage at the startup. Next
OUT
picture shows V
voltage for three different C
OUT
FF
capacitors. It can be seen that for none C capacitor the
FF
0.8 Short None 0.800 0.0
V
OUT
perfectly follows the V voltage while with C
FB FF
0.9
1.0
0.5
0.8
0.5
0.8
12
15
10
7.5
15 0.900 0.0
120 0.900 0.0
10 1.000 0.0
30 1.000 0.0
capacitor it doesn’t. The different shape and small delay is
probably not an issue. But when the PG is needed in the
application, then this phenomenon causes troubles with
timing. Because the internal PG comparator checks FB
voltage (not OUT voltage) and compares it to the internal
1.0 Short None 1.000 0.0
thresholds then the PG rises during startup when V
FB
1.1
1.2
0.5
0.8
1.0
0.5
0.8
1.0
12
9.1
10
51
10
15
10 1.100 0.0
24 1.103 0.3
100 1.100 0.0
36 1.208 0.7
20 1.200 0.0
75 1.200 0.0
reaches 93% of V
(typ). Without C the V
rises the
. But
OUT
NOM
FF
OUT
same as V so PG indicates also 93% of the V
FB
when C is used, V
is delayed to V which reaches the
FF
OUT
FB
threshold sooner than V . This results too early rise of the
OUT
PG signal and it looks like the threshold related to V
is
OUT
false (but it is just the effect of the V
delay). It is needed
OUT
to be told that such behavior is common for all ADJ LDOs
with PG, not just for NCP59763.
1.2 Short None 1.200 0.0
To overcome this C delay issue we can simply tune the
FF
1.5
1.8
2.0
0.5
0.8
1.0
1.2
0.5
0.8
1.0
1.2
0.5
0.8
1.0
1.2
20
16
10
9.1
39
15
12
11
30
15
10
10
10 1.500 0.0
18 1.511 0.7
20 1.500 0.0
36 1.503 0.2
15 1.800 0.0
12 1.800 0.0
15 1.800 0.0
22 1.800 0.0
10 2.000 0.0
10 2.000 0.0
10 2.000 0.0
15 2.000 0.0
value of the C
capacitor and postpone the PG reaction
DELAY
for the same or longer delay time. This is shown at the next
picture as V curves.
PG
Of course this situation needs care only at the ADJ
application when C is used (as C is not applicable at FIX
FF
FF
application).
VOUT without CFF perfectly tracks VFB multiplied by
R
ADJ1 / RADJ2, but with CFF the signal is rounded and
delayed (as CFF with RADJ1/2 creates a OUT−to−FB filter)
1.4 V
1.2 V
VIN=VEN
VOUT
CFF=0 nF
VUVLO−TH
CFF=10 nF
The PG reacts sooner, not at the 93% of VOUT, because PG
is related to VFB not VOUT, which is delayed by CFF. We can
overcome this by using CDELAY and postpone PG reaction.
CFF=33 nF
0.5 V
VFB=VSS/NR
VPG
93% of VFB (= VPG−TH + VPG−HYS
)
VPG without CDELAY
PG delay by CDELAY
VPG with CDELAY
Where:
Time
V
V
V
[V] is desired output voltage.
OUT
[V] is selected part nominal voltage.
[V] is calculated output voltage.
NOM
OUT2
Figure 102. PG Reaction Influenced by CFF Capacitor,
ADJ Application, VNOM = 0.5 V, VOUT = 1.2 V
Diff [%] is difference between desired and calculated
output voltage.
Next table shows recommended feedback part values
(R
, R
and C ) selected from E24 (resistors) and E6
AD1 AD2 FF
Of course the table above is just an example and other
values of output voltage divider parts are possible.
(capacitor) series. Higher output voltages can be created by
several combinations of OPN and divider. It is
recommended to select the part with the nearest nominal
voltage do desired output voltage for the best dynamic
performance. For example, the part with V
= 0.5 V set
NOM
to V
= 1.8 V has slightly worse output voltage noise than
OUT
part with V
= 1.2 V, set to the same V
= 1.8 V, see
NOM
OUT
Typical characteristics section for details.
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26
NCP59763
Startup and Shutdown
In the NCP59763 device there are two main internal
signals which triggers the startup process, the under−voltage
lockout (UVLO) signal and enable signal. The first one
comes from UVLO comparator, which monitors if the IN
pin voltages is high enough, while the second one comes
from EN pin comparator. Both comparators have embedded
hysteresis to be insensitive to input noise.
VUVLO−TH
VIN=VEN
VUVLO−TH –VUVLO−HYS
VEN−TH
VEN−TH –VEN−HYS
VOUT−NOM
95% of VOUT−NOM
Time
VOUT
tSS
tSTART
tPD
Current
Limit
IN
OUT
Figure 106. IN & EN Pins Initiated Startup/Shutdown
Charge
Pump
Output
discharge
Where:
CF
RNR
t
t
t
is the soft−start time (described below)
Progr.
Voltage
Reference
SS
EA
is the overall startup time
START
ISS
is the internal propagation delay (170 ms typ.)
FB
PD
NR/SS
PG
NR/SS
Discharge
PG Output
90%
of VREF
NCP59763 device contains PG circuit for the output
voltage level monitoring. Internally it is combined from PG
comparator, DELAY comparator, logic block with deglitch
timer, DELAY pin current source and discharge NMOS
transistor and PG output NMOS transistor (all highlighted
by red color at the following picture). The PG comparator
UVLO
EN
1.0 V
0.8 V
IDELAY
EN
DELAY
PG
Logic
&
0.8 V
Delays
Thermal
Shutdown
compares internal feedback signal voltage (V ) with the
FB
Figure 103. Internal Block Diagram
(UVLO and EN Blocks Highlighted)
90% of V
voltage what means that the V
drop below
REF
OUT
90% is detected. Output signal from this comparator is
blanked by deglitch timer (typ. 20 ms) to filter out possible
short spikes at the output voltage. This means that only
pulses longer than about 20 ms and lower than 90% of set
Next figures show three startup/shutdown cases, initiated
by input, enable or both signals assertion.
V
OUT
are detected. When the PG comparator output signal
passes through this deglitch timer it turns ON the DELAY
pin discharge NMOS which discharges external delay
VUVLO−TH
VIN
VEN
VUVLO−TH – VUVLO−HYS
capacitor (C
NMOS.
) and also turns ON the PG output
DELAY
VEN−TH
VEN−TH – VEN−HYS
For proper operation the PG output needs external pull−up
resistor which defines the voltage level at the non−fault time.
Recommended values range is from 3.9 kW to 100 kW.
When the output drop event disappears, the DELAY pin
discharge NMOS is turned back OFF and the external delay
VOUT−NOM
95% of VOUT−NOM
Time
VOUT
tSS
capacitor is charged by internal I
current source.
tSTART
DELAY
tPD
When the DELAY voltage reaches 0.8 V (typ.), what is the
internal DELAY comparator threshold voltage, the PG
output NMOS transistor is turned OFF to indicate normal
condition. This DELAY capacitor charging time is in fact a
Figure 104. EN Pin Initiated Startup/Shutdown
VUVLO−TH
VUVLO−TH – VUVLO−HYS
C
DELAY
capacitor programmable delay time, what could be
VIN
VEN
needed by external monitoring circuit (for example MCU
connected to PG). In case very short delay is acceptable for
VEN−TH
VEN−TH – VEN−HYS
the application the C
capacitor could be omitted.
DELAY
Then the delay between rising edges of PG to V
30 ms.
is about
OUT
VOUT−NOM
95% of VOUT−NOM
Time
VOUT
tSS
tSTART
tPD
Figure 105. IN Pin Initiated Startup/Shutdown
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27
NCP59763
At adjustable application when C capacitor is used, the
output voltage settling time could be several times longer
current flowing into this capacitor, given by the following
equation:
FF
than FB voltage settling time (caused by C with R
and
FF
ADJ1
dVC(t)
IC(t) + C
R
ADJ2
). And because the PG comparator monitors the FB
(eq. 3)
dt
voltage, it could indicate “power ok” state based on settled
FB voltage at a time when output voltage is still too low. At
The dV (t)/dt is the slope of capacitor voltage change.
C
The higher V voltage change or the higher capacitor value,
C
such case the PG delay must be set by C
capacitor to
DELAY
the bigger capacitor charge current.
In LDO application, there are two capacitors used, C
, and both of them are charged during power−up
what could generate very high input current, which is caller
inrush current.
a longer value than output voltage settling time is.
When the overall PG function is not needed than both
IN
and C
OUT
C
DELAY
capacitor and R resistor could be omitted.
PG
OUT
Current
Inrush current of LDO application consist of the sum of:
Limit
• C charge current (can’t be influenced by the LDO,
IN
could be influenced by previous power stage only by
EA
Output
discharge
setting of LDO’s V slope)
IN
• C
charge current (influenced by the LDO)
OUT
FB
• LDO’s ground current (negligible)
• LDO’s load current I (t)
PG
RPG
10 kW
Optional
LOAD
90%
of VREF
DELAY
PG
This relations could be written in equation:
CDE LAY
2.2 nF
Optional
IINRUSH(t) + ICIN(t) ) ICOUT(t) ) ILOAD(t)
IDE LAY
(eq. 4)
DELAY
Logic
&
dVOUT(t)
dt
dVIN(t)
dt
IINRUSH(t) + CIN
) COUT
) ILOAD(t)
(eq. 5)
0.8 V
Delays
PG
Where:
dV (t)/dt is the slope of V ramp
IN
IN
Figure 107. Internal Block Diagram
(PG Circuit Highlighted)
dV
(t)/dt is the slope of V
ramp
OUT
OUT
From the equation above we can see that in reel
application we need to care about both C and C
Delay time could be computed by the following equation:
IN
OUT
VDELAY*TH
capacitor values and about both V and V
voltage
IN
OUT
tDELAY + tDELAY*MIN
)
CDELAY +
slopes. Only the V
slope is influenced by the LDO while
IDELAY
OUT
the V slope is influenced by previous power stage (defined
by its soft−start time). The last part of the equation, the
IN
0.8
+ 30 m )
CDELAY + 30 ) 444 CDELAY [ms; nF]
1.8 m
I
(t) current, could be dependent to the immediate value
LOAD
(eq. 2)
of rising V
voltage and generally it could vary in time.
OUT
Where:
Because it is part of the inrush current, the LDO should care
about it as well and it does by load current limiting during
t
is minimum delay time without capacitor
is DELAY pin threshold voltage
DELAY−MIN
start−up by the current limit feature to I
level (see
(about 30 ms)
CL
Electrical characteristics table).
V
DELAY−TH
Back to the soft−start feature, the externally connected
capacitor is charged by internal current source I
I
is DELAY capacitor charging current
DELAY
C
NR/SS
.
SS
The C
the V
value and size of the I current together define
NR/SS
SS
Soft−start and Noise Reduction
The NR/SS pin has two functions – program LDO’s
output voltage rise time and reduce the output voltage
noise − both by the same externally connected C
capacitor.
Startup situation very often needs a special care, because
the charge currents of capacitors connected to power rails
could cause used power supplies overcurrent events.
Generally, any capacitor voltage change generates charge
voltage rise time. The voltage at the C
OUT
NR/SS
capacitor rises linearly in time and is followed by the LDO’s
output voltage.
When the NR/SS pin voltages reaches the internal voltage
NR/SS
reference value the I current source is turned OFF and the
SS
C
NR/SS
capacitor in combination with internal R resistor
NR
behaves as an internal reference filter. The bigger C
value the lower LDO’s output voltage noise.
NR/SS
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28
NCP59763
Active Output Discharge
Recommended range of C
capacitor is from 10 nF to
NR/SS
Active output discharge function discharges the output
capacitor when the LDO is disabled by EN pin.
100 nF. See the Typical characteristics section for C
capacitor influence to output voltage noise and startup time
as well.
NR/SS
Current
Limit
IN
OUT
Current
IN
OUT
Charge
Pump.
Limit
Charge
Pump
Output
CF
discharge
Output
discharge
CF
RNR
Progr
Voltage
Reference
RNR
Progr.
Voltage
EA
EA
Reference
ISS
ISS
FB
NR/SS
NR/SS
FB
PG
NR/SS
CNR/SS
100 nF
PG
NR/SS
Discharge
Discharge
90%
of VREF
90%
of VREF
UVLO
EN
UVLO
EN
1.0 V
0.8 V
IDELAY
1.0 V
0.8 V
IDELAY
EN
DELAY
PG
Logic
Logic
EN
DELAY
PG
&
&
0.8 V
Delays
0.8 V
Delays
Thermal
Shutdown
Thermal
Shutdown
Figure 109. Internal Block Diagram
(Output Discharge Related Blocks Highlighted)
Figure 108. Internal Block Diagram
(Startup Circuit Highlighted)
When EN pin is turned to low state (when V is still
Soft−start time (t ) represents the length of the output
IN
SS
present), the output voltage is discharged continuously for
the whole EN pin low level period. The slope and shape of
discharged output voltage is given by resistance of internal
discharge NMOS transistor, load resistance and total output
capacitance.
voltage rise time at the startup (not the overall startup time
from UVLO or EN assertion). It could be computed by the
following equation:
VNOM
tSS + tSS*MIN
)
CNRńSS
(eq. 6)
ISS
Output voltage during the discharge period could be
described by:
Where:
VOUT(t) + VNOM e*tńt
t
is minimum soft−start time without C
NR/SS
SS−MIN
(eq. 7)
capacitor (about 50 ms)
t + (RACT ) RLOAD) COUT
V
is nominal LDO’s output voltage
(eq. 8)
NOM
I
is soft−start capacitor charging current
SS
Where:
V
V
(t) is immediate voltage at desired time point
Note that the t
characteristics table is not the same time as t
mentioned here. t
measured from EN rising edge to a point where V
parameter listed in the Electrical
OUT
START
SS−MIN
is the nominal output voltage
NOM
is overall minimum startup time
START
t is the desired time
OUT
τ is the RC time constant
reaches 95% of V
while t
time is just an output
NOM
SS−MIN
R
R
is resistance of int. active discharge NMOS
voltage rise time (it means it is a part of t
).
ACT
START
is load resistance
LOAD
From time perspective, we can say that after one RC time
constant (τ), the output voltage is discharged to 36.6%, after
two τ to 13.5%, after four τ to 1.8% etc.
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29
NCP59763
Next picture shows waveforms for discussed situation.
decreases by the thermal shutdown hysteresis value. Then
the LDO is back enabled.
The thermal shutdown feature provides the protection
against overheating due to application failure and it is not
intended to be used as a normal working function.
VUVLO−TH
VUVLO−TH – VUVLO−HYS
VIN
VEN−TH
VEN−TH – VEN−HYS
Power Dissipation
VEN
Power dissipation caused by voltage drop across the LDO
and by the output current flowing through the device needs
to be dissipated out from the chip. The maximum power
dissipation is dependent on the PCB layout, number of used
Cu layers, Cu layers thickness and the ambient temperature.
The maximum power dissipation can be computed by one of
the following equations:
ON
Active
output
discharge
OFF
VOUT−NOM
VOUT(t) = VNOM * exp (−t / ((RACT + RLOAD) * COUT))
VOUT
Time
TJ * TA
Figure 110. Active Output Discharge Activated by
EN Pin
PDIS
+
[W]
(eq. 9)
RqJA
Or
It is important to mention a different situation, when LDO
is not disabled by EN pin, but turned off by input voltage
TJ * TB
PDIS
+
[W]
(eq. 10)
(EN pin held high or connected to IN pin and V is forced
RqJB
IN
low). At this case the output discharge function is also
activated but just for a short period of time, starting when
input voltage falls below the low UVLO threshold
(0.9 V typ.) and ending when falls below the minimum
Where:
T is the desired junction temperature
J
T is the ambient temperature
A
discharge block operational level (V
, 0.8 V typ.).
AOD−MIN
T is the board temperature (on the trace within 1 mm of
B
We can see that there is a small input voltage window where
the discharge function is active (0.9 V – to – 0.8 V). Based
on this fact the proper output voltage discharge to 0V is not
possible. Simply, LDO’s active output discharge block can’t
be functional because the LDO’s power supply is turned off.
The situation is shown at the next picture.
the package body)
R
qJA
R
qJB
is junction to ambient thermal resistance
is junction to board thermal resistance
If we enter the maximum junction temperature value
(125°C) as a T , we obtain a maximum allowable power
J
dissipation P
dissipation
. Then, when applying higher power
DIS(MAX)
to
this
max.
power
dissipation
0.9V typ.
0.8V typ.
VUVLO−TH – VUVLO−HYS
VEN−TH – VEN−HYS
VAOD−MIN
(P > P
), the device will be overheated
DIS(MAX)
DIS
VIN=VEN
(T > T
J
).
J(MAX)
We can substitute for the power dissipation the following
equation:
ON
Active
output
PDIS + (VIN * VOUT) IOUT
(eq. 11)
discharge
OFF
To obtain equation for the output current:
VOUT−NOM
VOUT is not discharged
VOUT
PDIS
TJ * TX
IOUT
+
+
Time
VIN * VOUT
RqJX (VIN * VOUT)
(eq. 12)
Figure 111. Active Output Discharge Activated by
Falling VIN
Where:
T is T resp. T
X
A
B
At a situation of the high falling input voltage slope, it
could happen that the activated output discharge function
theoretical time window is shorter than internal delays,
resulting the discharge function will not be activated (fast
R
is R
resp. R
qJX
qJA qJB
And similarly, if we enter the maximum junction
temperature value (125°C) as a T , we obtain a maximum
allowable load current I
J
. Then, when applying
OUT(MAX)
falling V slope means no output discharge).
IN
higher load current to this max. load current
(I > I ), the device will be overheated
Thermal protection
OUT
OUT(MAX)
When the LDO’s die temperature exceeds the thermal
shutdown threshold value, the device is internally disabled.
The IC will remain in disabled state until the die temperature
(T > T
).
J
J(MAX)
Maximum power dissipation and maximum allowable
output currant charts are shown at figures 96 to 99.
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30
NCP59763
PCB Layout Recommendations
To obtain good LDO’s stability and the best transient,
PSRR and output voltage noise performance, place both C
current transients (note that this is different situation to
normal application where the distance of the LDO to its
power source is short so it need special care). In such case
it is recommended to assemble low ESR electrolytic input
capacitor to the spare place (C4) on the evaluation board
(recommended is aluminum organic polymer capacitor
560 mF to 2.2 mF for 6.3V or higher with ESR about
10 − 30 mW, 10 mm of diameter, through−hole with 5 mm
pin pitch to fit the PCB, for example Kemet
A750MV108M1EAAE014).
IN
and C
capacitors as close as possible to the device pins,
OUT
make the PCB traces wide and short and place capacitors to
the same PCB Cu layer as the LDO is (avoid connections
through vias). The same rules should be applied to the
connections between C
and the load – the less parasitic
OUT
impedance the better dynamic performance at the point of
load.
Regarding high impedance ADJ pin, prevent capacitive
coupling of this trace to any switching signals in the
circuitry.
The same applies to high impedance NR/SS pin, which is
very sensitive to coupled noise. Therefore make the trace to
Besides the main LDO application circuit, evaluation
board includes some supporting staff:
• Two positions for optional through−hole SMB connectors
for IN and OUT signals, mainly for line/load transients,
PSRR and noise testing (recommended connectors are
Molex 73100−0258 or compatible).
C
NR/SS
as short as possible.
When routing the trance to C capacitor, use also as short
CF
• Edge connector where all these signal leads to (the
as possible connection.
Other traces like PG, DELAY and EN don’t need any
special care.
appropriate
receptacle
type
is
SAMTEC
MECF−20−01−L−DV−WT).
• Three diodes as temperature sensors.
Demo Board Quick Overview
First it should be noted that more detailed evaluation
board information are provided in separate documents on
company web pages.
Below are schematic and board pictures of the
NCP59763AMN050TBGEVB evaluation board. The board
has been used during product evaluation to capture the data
shown in this datasheet (transients, PSRR, noise, startups
etc.).
By the solder jumper JP6 (label FIX) the application
circuit could be changed from the default adjustable type
(trimmer resistor RT1 sets the V
) to fixed. By default the
OUT
Figure 112. NCP59763AMN050TBGEVB Schematic
(Edge Connector Pinout)
board is supplied with LDO NCP59763AMN050
(V = 0.5 V) but it can handle any other OPN (on
NOM
request).
There is also a picture showing the layout in detail, which
could be taken as a recommended layout.
Generally, when testing LDOs dynamic performance on
evaluation board connected to laboratory power supply
typically by long cables, the device would need additional
input capacitor. This capacitor will cover voltage drops
created at the long connection cables impedance by the load
Figure 113. NCP59763AMN050TBGEVB Schematic
(Three Diodes as Temperature Sensors)
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31
NCP59763
Figure 114. NCP59763AMN050TBGEVB Schematic (Main Part)
Figure 115. NCP59763AMN050TBGEVB Board
Figure 116. NCP59763AMN050TBGEVB Board Center Detail
www.onsemi.com
32
NCP59763
ORDERING INFORMATION
Device
Output Voltage (V
)
Marking
Package
Shipping†
NOM
NCP59763AMN050TBG
0.5 V
0.8 V
1.0 V
1.2 V
59763
P050A
NCP59763AMN080TBG
NCP59763AMN100TBG
NCP59763AMN120TBG
59763
P080A
DFN10 3x3, 0.5P
3000
Tape & Reel
(Pb−Free)
59763
P100A
59763
P120A
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
33
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN10 3x3, 0.5P
CASE 506EH
ISSUE O
DATE 24 JUL 2018
1
GENERIC
MARKING DIAGRAM*
A
L
= Assembly Location
= Wafer Lot
*This information is generic. Please refer to
XXXXXX
XXXXXX
ALYWG
G
Y
W
G
= Year
= Work Week
= Pb−Free Package
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON94098G
DFN10 3x3, 0.5P
PAGE 1 OF 1
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