NCP6356BSNFCCT1G [ONSEMI]
1-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA20;
| 型号： | NCP6356BSNFCCT1G |
| 厂家： | 
ONSEMI |
| 描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA20 |
| 文件： | 总31页 (文件大小：1562K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP6356B
Configurable 5.0 A ACOT
Step Down Converter
The NCP6356B is a synchronous ACOT (Adaptive Constant
On−time) buck converter optimized to supply the different sub
systems of portable applications powered by one cell Li−Ion or three
cell Alkaline/NiCd/NiMH batteries. The device is able to deliver up to
5.0 A, with programmable output voltage from 0.6 V to 1.4 V.
Operation at up to 2.4 MHz switching frequency allows the use of
small components. Synchronous rectification and automatic PFM
Pseudo−PWM (PPWM) transitions improve overall solution
efficiency. The NCP6356B is in a space saving, low profile
2.0 x 1.6 mm CSP−20 package.
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MARKING
DIAGRAM
6356Bx
AWLYWW
G
WLCSP20
CASE 568AG
Features
• Input Voltage Range from 2.5 V to 5.5 V: Battery and 5 V Rail
Powered Applications
• Programmable Output Voltage: 0.6 V to 1.4 V in 6.25 mV Steps
• Up to 2.4 MHz Switching Frequency with On Chip Oscillator
• Uses 330 nH Inductor and at least 22 mF Capacitors for Optimized
Footprint and Solution Thickness
x
= blank: production
= S: 0.95 V
= N: 1.20 V
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
Y
G
= Pb−Free Package
• PFM/PPWM Operation for Optimum Efficiency
• Low 60 mA Quiescent Current
Pb−Free indicator, G or microdot (G),
may or may not be present
2
• I C Control Interface with Interrupt and Dynamic Voltage Scaling
Support
PIN OUT
2
• Enable / VSEL Pins, Power Good / Interrupt Signaling
• Thermal Protections and Temperature Management
• Transient Load Helper: Share the Same Rail with Another Rail
• Small 2.0 x 1.6 mm / 0.4 mm Pitch CSP Package
• These are Pb−Free Devices
1
3
4
A
VSEL
EN
SCL
FB
PGND
INTB*
PGND
PG*
B
SDA
PGND
AVIN
PVIN
AGND
PGND
Typical Applications
• Smartphones
• Webtablets
C
D
E
PGND
PGND
NCP6356B
AVIN
D1
SW
SW
SW
PVIN
PVIN
PVIN
D2
Supply Input
Core
AGND
E1
B4
E2
4.7 uF
Thermal
Protection
SW
D3
D4
E3
E4
DCDC
5.0 A
SW
Enable Control EN
A2
A1
Operating
Mode
Control
Input
330 nH
(Top View)
*Optional
Voltage
VSEL
Selection
22 uF
C1
PGND
FB
Output
Monitoring
PGND
PG
B3
C2
C3
C4
Power Fail
Interrupt
ORDERING INFORMATION
PGND
INTB
B2
B1
A4
See detailed ordering and shipping information on page 30 of
this data sheet.
DCDC
Up to 2.4 MHz
Controller
Processor
Core
SDA
Sense
22 uF
I@C
Processor I@C
Control Interface
SCL
A3
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
May, 2016 − Rev. 0
NCP6356B/D
NCP6356B
PVIN
POWER INPUT
PVIN
PVIN
SUPPLY INPUT
AVIN
Core
ANALOG GROUND
AGND
SW
SW
5.0 A
DC−DC
SWITCH NODE
Thermal
Protection
SW
SW
POWER GOOD
(optional)
Output Voltage
Monitoring
PG
ENABLE CONTROL INPUT
EN
Up to 2.4 MHz
DC−DC converter
Controller
Operating
Mode Control
PGND
VOLTAGE SELECTION VSEL
PGND
PGND
PGND
POWER GROUND
FEEDBACK
INTERRUPT OUTPUT
INTB
(optional)
Logic Control
Interrupt
I2C
PROCESSOR I2C
CONTROL INTERFACE
FB
SCL
Sense
SDA
Figure 2. Simplified Block Diagram
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2
NCP6356B
1
2
3
4
A
VSEL
EN
SCL
FB
PGND
INTB*
PGND
PG*
B
SDA
PGND
AVIN
AGND
PGND
SW
C
D
E
PGND
PGND
SW
PVIN
PVIN
SW
PVIN
SW
*Optional
Figure 3. Pin Out (Top View)
PIN FUNCTION DESCRIPTION
Pin
Name
Type
Description
REFERENCE
D1
AVIN
Analog Input
Analog Supply. This pin is the device analog and digital supply. Can be connected
directly to the VIN plane just next to the 4.7 mF PVIN capacitor or to a dedicated
1.0 mF ceramic capacitor. Must be equal to PVIN.
B4
AGND
Analog Ground
Analog Ground. Analog and digital modules ground. Must be connected to the
system ground.
CONTROL AND SERIAL INTERFACE
A2
EN
Digital Input
Enable Control. Active high will enable the part. There is an internal pull down
resistor on this pin.
A1
VSEL
Digital Input
Output voltage / Mode Selection. The level determines which of two programmable
configurations to utilize (operating mode / output voltage). There is an internal pull
down resistor on this pin; can be left unconnected if not used.
2
A3
B1
B3
SCL
SDA
Digital Input
I C interface Clock line. There is an internal pull down resistor on this pin; can be left
unconnected if not used
2
Digital
Input/Output
I C interface Bi−directional Data line. There is an internal pull down resistor on this
pin; can be left unconnected if not used
PGND
PG
Digital Output
Power Good open drain output. Must be connected to the ground plane if not used.
Analog Ground
B2
PGND
INTB
Digital Output
Interrupt open drain output. Must be connected to the ground plane if not used.
Analog Ground
DC to DC CONVERTER
D2, E1, E2
PVIN
SW
Power Input
Power Output
Power Ground
Switch Supply. These pins must be decoupled to ground by a 4.7 mF ceramic capa-
citor. It should be placed as close as possible to these pins. All pins must be used
with short thick connections. Must be equal to AVIN.
D3, D4,
E3, E4
Switch Node. These pins supply drive power to the inductor. Typical application uses
0.33 mH inductor; refer to application section for more information.
All pins must be used with short thick connections.
C1, C2,
C3, C4
PGND
Switch Ground. This pin is the power ground and carries the high switching current.
High quality ground must be provided to prevent noise spikes. To avoid high−density
current flow in a limited PCB track, a local ground plane that connects all PGND pins
together is recommended. Analog and power grounds should only be connected
together in one location with a trace.
A4
FB
Analog Input
Feedback Voltage input. Must be connected to the output capacitor positive termin-
al with a trace, not to a plane. This is the positive input to the error amplifier.
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3
NCP6356B
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Analog and power pins: AVIN, PVIN, SW, INTB, FB (Note 1)
V
A
−0.3 to +6.0
−0.3 to +6.0
2
I C pins: SDA, SCL
V 2
I C
V
Digital pins: EN, VSEL
Input Voltage
V
I
−0.3 to V + 0.3 ≤ 6.0
V
mA
DG
DG
A
10
Input Current
Human Body Model (HBM) ESD Rating (Note 2)
Charged Device Model (CDM) ESD Rating (Note 2)
ESD HBM
ESD CDM
2500
1250
V
V
Latch Up Current: (Note 3)
Digital Pins
I
LU
mA
10
100
All Other Pins
Storage Temperature Range
Maximum Junction Temperature
Moisture Sensitivity (Note 4)
T
−65 to +150
−40 to +150
Level 1
°C
°C
STG
T
JMAX
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM) 2.5 kV per JEDEC standard: JESD22−A114.
Charged Device Model (CDM) 1.25 V per JEDEC standard: JESD22−C101 Class IV
3. Latch up Current per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
OPERATING CONDITIONS
Symbol
Parameter
Conditions
AV = PV
IN
Min
2.5
−40
−40
−
Typ
Max
5.5
+85
+125
−
Unit
V
AV PV
Power Supply
IN,
IN
IN
T
A
Ambient Temperature Range
25
25
°C
T
J
Junction Temperature Range (Note 6)
Thermal Resistance Junction to Ambient (Note 7)
Power Dissipation Rating (Note 8)
°C
R
CSP−20 on Demo−board
≤ 85°C
55
°C/W
mW
mW
mH
q
JA
P
T
A
−
727
1090
0.33
−
−
D
D
P
Power Dissipation Rating (Note 8)
T = 65°C
A
−
−
L
Inductor for DC to DC converter (Note 5)
Output Capacitor for DC to DC Converter (Note 5)
Input Capacitor for DC to DC Converter (Note 5)
0.26
15
0.56
150
−
Co
mF
Cin
4.5
−
mF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Including de−ratings (Refer to the Application Information section of this document for further details)
6. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
7. The R
is dependent of the PCB heat dissipation. Board used to drive this data was a NCP6356BEVB board. It is a multilayer board with
q
JA
1−once internal power and ground planes and 2−once copper traces on top and bottom of the board.
8. The maximum power dissipation (P ) is dependent by input voltage, maximum output current and external components selected.
D
125 * TA
RqJA
+
PD
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4
NCP6356B
ELECTRICAL CHARACTERISTICS (Note 9)
Min and Max Limits apply for T = −40°C to +85°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
A
Typical values are referenced to T = +25°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
A
Symbol
SUPPLY CURRENT: PINS AVIN – PVINx
Operating quiescent current PPWM DCDC active in Forced PPWM, no load
Parameter
Conditions
Min
Typ
Max
Unit
I
−
−
22
60
40
mA
Q−PPWM
I
Operating quiescent current PFM
DCDC active in Auto mode
no load − minimal switching
100
mA
Q PFM
I
Product sleep mode current
EN high, DCDC off or
EN low and I C pull up
−
−
5
10
3
mA
mA
SLEEP
2
V
IN
= 5.5 V
I
Product in off mode
EN, VSEL and Sleep_Mode low,
0.8
OFF
2
No I C pull up
V
IN
= 5.5 V
DC to DC CONVERTER
PV
Input Voltage Range
2.5
3.5
4.0
4.5
5.0
−1.5
−2
−
−
−
−
−
−
−
5.5
−
V
A
IN
OUTMAX
I
Maximum Output Current
Ipeak[1..0] = 00 (Note 11)
Ipeak[1..0] = 01 (Note 11)
Ipeak[1..0] = 10 (Note 11)
Ipeak[1..0] = 11 (Note 11)
−
−
−
D
Output Voltage DC Error
Switching Frequency
Forced PPWM mode, V range, No load
1.5
2
%
VOUT
IN
Forced PPWM mode, V range,
IN
I
up to I
(Note 11)
OUT
OUTMAX
Auto mode, V range,
−3
−
2
IN
(Note 11)
OUTMAX
I
up to I
OUT
F
SW
2.16
−
2.40
22
2.64
32
MHz
R
P−Channel MOSFET On
Resistance
From PVIN to SW
= 5.0 V
mW
ONHS
V
IN
R
N−Channel MOSFET On
Resistance
From SW to PGND
= 5.0 V
−
12
18
mW
ONLS
V
IN
I
Peak Inductor Current
Open loop – Ipeak[1..0] = 00 (Note 11)
Open loop – Ipeak[1..0] = 01 (Note 11)
Open loop – Ipeak[1..0] = 10 (Note 11)
Open loop – Ipeak[1..0] = 11
4.6
5.2
5.6
6.2
−
5.2
5.8
6.2
6.8
5
5.8
6.4
6.8
7.4
−
A
PK
DC
Load Regulation
I
from 0 A to I (Note 11)
OUTMAX
mV
mV
mV
mV
LOAD
OUT
Forced PPWM mode
DC
Line Regulation
2.5 V ≤ V ≤ 5.5 V (Note 11)
−
−
−
6
−
−
−
LINE
IN
Forced PPWM mode
AC
Transient Load Response
Transient Line Response
t = t = 100 ns
20
20
LOAD
r
f
Load step 1.5 A (Note 11)
AC
t = t = 10 ms
LINE
r
f
Line step 3.3 V / 3.9 V (Note 11)
D
Maximum Duty Cycle
Turn on time
−
−
100
100
−
%
t
Time from EN transitions from Low to
High to 90% of Output Voltage
(DVS[1..0] = 00b)
130
ms
START
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Refer to the Application Information section of this data sheet for more details.
2
10.Devices that use non−standard supply voltages which do not conform to the intent I C bus system levels must relate their input levels
to the V voltage to which the pull−up resistors R are connected.
DD
P
11. Guaranteed by design and characterized.
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5
NCP6356B
ELECTRICAL CHARACTERISTICS (Note 9)
Min and Max Limits apply for T = −40°C to +85°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
A
Typical values are referenced to T = +25°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DC to DC CONVERTER
R
DCDC Active Output Discharge
V
OUT
= 1.15 V
−
12
25
W
DISDCDC
EN, VSEL
V
High input voltage
Low input voltage
Digital input X Filter
1.05
−
−
−
−
−
V
V
IH
V
0.4
4.5
IL
T
FTR
EN, VSEL rising and falling
DBN_Time = 01 (Note 11)
0.5
ms
I
Digital input X Pull−Down
(input bias current)
For EN and VSEL pins
−
0.05
1.00
mA
PD
PG (Optional)
V
Power Good Threshold
Power Good Hysteresis
Falling edge as a percentage of
nominal output voltage
86
0
90
3
94
5
%
PGL
V
%
PGHYS
T
RT
Power Good Reaction Time for
DCDC
Falling (Note 11)
Rising (Note 11)
−
3.5
3.5
−
−
14
ms
V
Power Good low output voltage
Power Good leakage current
Power Good high output voltage
I
= 5 mA
−
−
−
−
−
−
0.2
100
5.5
V
nA
V
PGL
PG
PG
3.6 V at PG pin when power good valid
Open drain
LK
V
PGH
INTB (Optional)
V
INTB low output voltage
INTB high output voltage
INTB leakage current
I
= 5 mA
0
−
−
−
−
−
0.2
5.5
V
V
INTBL
INTBH
INT
V
Open drain
INTB
3.6 V at INTB pin when INTB valid
100
nA
LK
2
I C
V 2
I CIL
SCL, SDA low input voltage
SCL high input voltage
SDA high input voltage
SDA low output voltage
SCL, SDA pin (Notes 10, 11)
SCL pin (Notes 10, 11)
SDA pin (Notes 10, 11)
−
1.6
1.2
−
−
−
−
−
−
0.4
−
V
V
V 2
I CIH
−
V 2
I COL
I
= 3 mA (Note 11)
0.4
3.4
V
SINK
2
F
SCL
I C clock frequency
(Note 11)
−
MHz
TOTAL DEVICE
V
Under Voltage Lockout
V
V
falling
rising
−
60
−
−
−
2.5
200
−
V
mV
°C
°C
°C
°C
°C
°C
UVLO
IN
V
Under Voltage Lockout Hysteresis
Thermal Shut Down Protection
Warning Rising Edge
UVLOH
IN
T
150
135
105
30
15
6
SD
T
−
−
WARNING
2
T
PWTH
Pre − Warning Threshold
I C default value
−
−
T
Thermal Shut Down Hysteresis
Thermal warning Hysteresis
Thermal pre−warning Hysteresis
−
−
SDH
T
−
−
WARNINGH
T
−
−
PWTH H
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Refer to the Application Information section of this data sheet for more details.
2
10.Devices that use non−standard supply voltages which do not conform to the intent I C bus system levels must relate their input levels
to the V voltage to which the pull−up resistors R are connected.
DD
P
11. Guaranteed by design and characterized.
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NCP6356B
TYPICAL OPERATING CHARACTERISTICS
AV = PV = 3.6 V, T = +25°C, DCDC = 1.15 V, L = 0.33 mH DFE252012F – C
= 2 x 22 mF 0603, C = 10 mF 0603
IN
IN
IN
J
OUT
Figure 4. Efficiency vs. ILOAD and VIN
VOUT = 1.39375 V, SPM5030 Inductor
Figure 5. Efficiency vs. ILOAD and Temperature
OUT = 1.39375 V, SPM5030 Inductor
V
Figure 6. Efficiency vs. ILOAD and VIN
VOUT = 1.15 V, SPM5030 Inductor
Figure 7. Efficiency vs. ILOAD and Temperature
OUT = 1.15 V, SPM5030 Inductor
V
Figure 8. Efficiency vs. ILOAD and VIN
VOUT = 0.60 V, SPM5030 Inductor
Figure 9. Efficiency vs. ILOAD and Temperature
OUT = 0.60 V, SPM5030 Inductor
V
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NCP6356B
TYPICAL OPERATING CHARACTERISTICS
AV = PV = 3.6 V, T = +25°C, DCDC = 1.15 V, L = 0.33 mH DFE252012F – C
= 2 x 22 mF 0603, C = 10 mF 0603
IN
IN
IN
J
OUT
Figure 10. Efficiency vs. ILOAD and VIN
VOUT = 1.15 V
Figure 11. Efficiency vs. ILOAD and Temperature
OUT = 1.15 V
V
Figure 12. VOUT Accuracy vs. ILOAD and VIN
VOUT = 1.15 V
Figure 13. VOUT Accuracy vs. VIN and
Temperature, VOUT = 1.15 V
Figure 14. VOUT Accuracy vs. ILOAD and VIN
VOUT = 0.60 V
Figure 15. VOUT Accuracy vs. ILOAD and VIN
VOUT = 1.39375 V
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NCP6356B
TYPICAL OPERATING CHARACTERISTICS
AV = PV = 3.6 V, T = +25°C, DCDC = 1.15 V, L = 0.33 mH DFE252012F – C
= 2 x 22 mF 0603, C = 10 mF 0603
IN
IN
IN
J
OUT
Figure 16. HSS RON vs. VIN and Temperature
Figure 18. IOFF vs. VIN and Temperature
Figure 20. IQ PFM vs. VIN and Temperature
Figure 17. LSS RON vs. VIN and Temperature
Figure 19. ISLEEP vs. VIN and Temperature
Figure 21. IQ PPWM vs. VIN and Temperature
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NCP6356B
TYPICAL OPERATING CHARACTERISTICS
AV = PV = 3.6 V, T = +25°C, DCDC = 1.15 V, L = 0.33 mH DFE252012F – C
= 2 x 22 mF 0603, C = 10 mF 0603
IN
IN
IN
J
OUT
Figure 22. Switchover Point VOUT = 1.15 V
Figure 23. Switchover Point VOUT = 1.4 V
Figure 24. Ripple
Figure 25. Normal Power Up, VOUT = 1.15 V,
DVS[1..0] = 00
Figure 26. Transient Load 3.5 A to 5.0 A − VIN = 3.2 V
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NCP6356B
TYPICAL OPERATING CHARACTERISTICS
AV = PV = 3.6 V, T = +25°C, DCDC = 1.15 V, L = 0.33 mH DFE252012F – C
= 2 x 22 mF 0603, C = 10 mF 0603
IN
IN
IN
J
OUT
Figure 27. Transient Load 0.01 to 1.5 A
Transient Line 3.9 to 3.3 V − Auto Mode
Figure 28. Transient Load 0.01 to 1.5 A
Transient Line 3.3 to 3.9 V − Auto Mode
Figure 29. Transient Load 1 to 2.5 A
Figure 30. Transient Load 1 to 2.5 A
Transient Line 3.9 to 3.3 V − Auto Mode
Transient Line 3.3 to 3.9 V − Auto Mode
Figure 31. Transient Load 1 to 2.5 A during
Transient Line 3.9 − 3.3 V Auto Mode
Figure 32. Transient Load 1 to 2.5 A during
Transient Line 3.3 to 3.9 V − Auto Mode
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NCP6356B
DETAILED OPERATING DESCRIPTION
Detailed Description
Inductor Peak Current Limitation / Short Protection
During normal operation, peak current limitation monitors
and limits the inductor current by checking the current in the
P−MOSFET switch. When this current exceeds the Ipeak
threshold, the P−MOSFET is immediately opened.
The NCP6356B is voltage mode stand−alone DC to DC
converter optimized to supply different sub systems of
portable applications powered by one cell Li−Ion or three
2
cells Alkaline/NiCd/NiMh. It can deliver up to 5 A at an I C
selectable voltage ranging from 0.6 V to 1.40 V. The
switching frequency up to 2.4 MHz allows the use of small
output filter components. Power Good indicator and
Interrupt management are available. Operating modes,
configuration, and output power can be easily selected either
by using digital I/O pins or by programming a set of registers
To protect again excessive load or short circuit, the
number of consecutive Ipeak is counted. When the counter
reaches 16, the DCDC is powered down during about 2 ms
and the ISHORT interrupt is flagged. It will re−start
following the REARM bit in the LIMCONF register:
• If REARM = 0, then NCP6356B does not re−start
automatically, an EN pin toggle is required.
• If REARM = 1, NCP6356B re−starts automatically
after the 2 ms with register values set prior the fault
condition.
2
using an I C compatible interface capable of operation up to
2
3.4 MHz. Default I C settings are factory programmable.
DC to DC Converter Operation
The converter integrates both high side and low side
(synchronous) switches. Neither external transistors nor
diodes are required for NCP6356B operation. Feedback and
compensation network are also fully integrated.
This current limitation is particularly useful to protect the
inductor. The peak current can be set by writing
IPEAK[1..0] bits in the LIMCONF register.
It uses the ACOT (Adaptive Constant On−Time) control
scheme and can operate in two different modes: PFM and
PPWM (Pseudo−PWM). The transition between modes can
occur automatically or the switcher can be placed in forced
Table 1. IPEAK VALUES
IPEAK[1..0]
Inductor Peak Current (A)
5.2 − for 3.5 output current
5.8 − for 4.0 output current
6.2 − for 4.5 output current
6.8 − for 5.0 output current
00
01
10
11
2
PPWM mode by I C programming (PPWMVSEL0 /
PPWMVSEL1 bits of COMMAND register).
PPWM (Pseudo Pulse Width Modulation) Operating Mode
In medium and high load conditions, NCP6356B operates
in PPWM mode to regulate the desired output voltage. In
this mode, the inductor current is in CCM (Continuous
Output Voltage
Conduction Mode) and the ACOT guaranties
a
The output voltage is set internally by an integrated
resistor bridge and no extra components are needed to set the
output voltage. Writing in the VoutVSEL0[6..0] bits of the
PROGVSEL0 register or VoutVSEL1[6..0] bits of the
PROGVSEL1 register will change the output voltage. The
output voltage level can be programmed by 6.26 mV steps
between 0.6 V to 1.39375 V. The VSEL pin and VSELGT
bit will determine which register between PROGVSEL0
and PROGVSEL1 will set the output voltage.
• If VSELGT = 1 AND VSEL=0 ³ Output voltage is set
by VoutVSEL0[6..0] bits (PROGVSEL0 register)
• Else ³ Output voltage is set by VoutVSEL1[6..0] bits
(PROGVSEL1 register)
pseudo−fixed frequency with 10% accuracy. The internal
N−MOSFET switch operates as a synchronous rectifier and
is driven complementary to the P−MOSFET switch.
PFM (Pulse Frequency Modulation) Operating Mode
In order to save power and improve efficiency at low
loads, the NCP6356B operates in PFM mode as the inductor
current drops into DCM (Discontinuous Conduction Mode).
The upper FET on−time is kept constant and the switching
frequency becomes proportional to the loading current. As
it does in PPWM mode, the internal N−MOSFET operates
as a synchronous rectifier after each P−MOSFET on−pulse
until there is no longer current in the coil.
When the load increases and the current in the inductor
become continuous again, the controller automatically turns
back to PPWM mode.
Under Voltage Lock Out (UVLO)
The NCP6356B core does not operate for voltages below
the Under Voltage Lock Out (UVLO) level. Below the
UVLO threshold, all internal circuitry (both analog and
digital) is held in reset. The NCP6356B operation is
guaranteed down to UVLO as the battery voltage is
dropping off. To avoid erratic on / off behavior, a maximum
200 mV hysteresis is implemented. Restart is guaranteed at
2.7 V when the VBAT voltage is recovering or rising.
Forced PPWM
The NCP6356B can be programmed to only use PPWM
and the transition to PFM can be disabled if so desired,
2
thanks to the PPWMVSEL0 or PPWMVSEL1 I C bits
(COMMAND register).
Output Stage
NCP6356B is a 3.5 A to 5.0 A output current capable DC
to DC converter with both high side and low side
(synchronous) switches integrated.
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12
NCP6356B
2
Thermal Management
• Enx I C bit is high, the DC to DC converter is
activated.
Thermal Shut Down (TSD)
2
• Enx I C is low, the DC to DC converter is turned off
The thermal capability of the NCP6356B can be exceeded
due to the step down converter output stage power level. A
thermal protection circuitry with associated interrupt is
therefore implemented to prevent the IC from damage. This
protection circuitry is only activated when the core is in
active mode (output voltage is turned on). During thermal
shut down, output voltage is turned off. During thermal shut
down, output voltage is turned off.
During thermal shutdown, the output voltage is turned off.
When the NCP6356B returns from thermal shutdown, it can
re−start in 2 different configurations depending on the
REARM bit in the LIMCONF register (refer to the register
description section):
and the device enters in Sleep Mode.
A built in pull down resistor disables the device when this
pin is left unconnected or not driven. EN pin activity does
not generate any digital reset.
Power Up Sequence (PUS)
In order to power up the circuit, the input voltage AVIN
has to rise above the VUVLO threshold. This triggers the
internal core circuitry power up which is the “Wake Up
Time” (including “Bias Time”).
This delay is internal and cannot be bypassed. EN pin
transition within this delay corresponds to the “Initial power
up sequence” (IPUS):
If REARM = 0, the NCP6356B does not re−start after
TSD. To restart, an EN pin toggle is required. If REARM
= 1, the NCP6356B re−starts with register values set prior to
thermal shutdown.
AVIN
UVLO
POR
The thermal shut down threshold is set at 150°C (typical)
and a 30°C hysteresis is implemented in order to avoid
erratic on / off behavior. After a typical 150°C thermal shut
down, the NCP6356B will resume to normal operation when
the die temperature cools to 120°C.
EN
DELAY[2..0]
VOUT
~ 80 us
32 us
Thermal Warnings
Wake up
Time
Init DVS ramp
Time
Time
In addition to the TSD, the die temperature monitoring
circuitry includes
a thermal warning and thermal
Figure 33. Initial Power Up Sequence
pre−warning sensor and interrupts. These sensors can
inform the processor that the NCP6356B is close to its
thermal shutdown and preventive measures to cool down die
temperature can be taken by software.
The Warning threshold is set by hardware to 135°C
typical. The Pre−Warning threshold is set by default to
105°C but it can be changed by setting the TPWTH[1..0]
bits in the LIMCONF register.
In addition a user programmable delay will also take place
between the Wake Up Time and the Init time: The
DELAY[2..0] bits of the TIME register will set this user
programmable delay with a 2 ms resolution. With default
delay of 0 ms, the NCP6356B IPUS takes roughly 100 ms,
and the DC to DC converter output voltage will be ready
within 150 ms.
The power up output voltage is defined by the VSEL state.
Active Output Discharge
2
NOTE: During the Wake Up time, the I C interface is not
To make sure that no residual voltage remains in the power
supply rail when disabled, an active discharge path can
ground the NCP6356B output voltage. For maximum
flexibility, this feature can be easily disabled or enabled with
the DISCHG bit in the PGOOD register. By default the
discharge path is enabled and is activated during the first
100 ms after battery insertion.
2
active. Any I C request to the IC during this time period will
result in a NACK reply.
Normal, Quick and Fast Power Up Sequence
The previous description applies only when the EN
transitions during the internal core circuitry power up (Wake
up and calibration time). Otherwise 3 different cases are
possible:
Enabling
• Enabling the part by setting the EN pin from Off Mode
will result in “Normal power up sequence” (NPUS,
with DELAY;[2..0]).
• Enabling the part by setting the EN pin from Sleep
Mode will result in “Quick power up sequence”
(QPUS, with DELAY;[2..0]).
• Enabling the DC to DC converter, whereas EN is
already high, either by setting the ENVSEL0 or
ENVSEL1 bits or by VSEL pin transition will results in
The EN pin controls the NCP6356B start up. EN pin Low
to High transition starts the power up sequencer. If EN is low,
the DC to DC converter is turned off and device enters:
2
• Sleep Mode if Sleep_Mode I C bit is high or VSEL is
high,
2
• Off Mode if Sleep_Mode I C bit and VSEL are low.
When EN pin is set to a high level, the DC to DC converter can
be enabled / disabled by writing the ENVSEL0 or ENVSEL1
bit of the PROGVSEL0 and PROGVSEL1 registers:
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13
NCP6356B
“Fast power up sequence” (FPUS, without
DELAY[2..0]).
In hardware shutdown (EN = 0), the internal core is still
active and I C accessible.
2
The internal core of the NCP6356B shuts down when
AVIN falls below UVLO
Sleep mode is when VSEL is high and EN low, or when
Sleep_Mode I C bit is set and EN is low, or finally when DC
2
to DC converter is off and EN high.
Dynamic Voltage Scaling (DVS)
The NCP6356B supports dynamic voltage scaling (DVS)
allowing the output voltage to be reprogrammed via I C
AVIN
2
UVLO
POR
commands and provides the different voltages required by
the processor. The change between set points is managed in
a smooth fashion without disturbing the operation of the
processor.
EN
O
F
F
When programming a higher voltage, the output raises
with controlled dV/dt defined by DVS[1..0] bits in the TIME
register. When programming a lower voltage the output
voltage will decrease accordingly. The DVS step is fixed and
the speed is programmable.
The DVS sequence is automatically initiated by changing
the output voltage settings. There are two ways to change
these settings:
DELAY[2..0]
VOUT
M
O
D
E
60 us
32 us
TFTR Bias
Time
Init
Time
DVS ramp
Time
Figure 34. Normal Power Up Sequence
AVIN
UVLO
POR
• Directly change the active setting register value
(VoutVSEL0[6..0] of the PROGVSEL0 register or
VoutVSEL1[6..0] of the PROGVSEL1 register) via an
S
L
E
E
P
EN
2
I C command
DELAY[2..0]
VOUT
M
O
D
E
• Change the VSEL internal signal level by toggling the
10 us
32 us
VSEL pin.
2
TFTR Bias
Time
Init
Time
DVS ramp
Time
The second method eliminates the I C latency and is
therefore faster.
Figure 35. Quick Power Up Sequence
The DVS transition mode can be changed with the
DVSMODE bit in the COMMAND register:
• In forced PPWM mode when accurate output voltage
control is needed. Rise and fall time are controlled with
the DVS[1..0] bits.
AVIN
UVLO
POR
S
L
VSEL
E
E
P
V2
Internal
Output
VOUT
M
O
D
E
Reference
Voltage
32 us
nV
TFTR Init
Time
DVS ramp
Time
nt
V1
Figure 36. Fast Power Up Sequence
Figure 37. DVS in Forced PPWM Mode Diagram
In addition the delay set in DELAY[2..0] bits in TIME
register will apply only for the EN pins turn ON sequence
(NPUS and QPUS).
• In Auto mode when the output voltage must not be
discharged. Rise time is controlled by the DVS[1..0],
and fall time depends on the load and cannot be faster
than the DVS[1..0] settings.
The power up output voltage is defined by VSEL state.
DC to DC Converter Shut Down
When shutting down the device, no shut down sequence
is required. The output voltage is disabled and, depending on
the DISCHG bit state of the PGOOD register, the output may
be discharged.
Output
Voltage
V2
Internal
Reference
nV
DC to DC converter shutdown is initiated by either
grounding the EN pin (Hardware Shutdown) or, depending
on the VSEL internal signal level, by clearing the ENVSEL0
or ENVSEL1 bits (Software shutdown) in the PROGVSEL0
or PROGVSEL1 registers.
nt
V1
Figure 38. DVS in Auto Mode Diagram
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14
NCP6356B
Digital IO Settings
its final value and when the Power Good pin is released to
a high level.
VSEL Pin
Vout
By changing the VSEL pin levels, the user has a latency
free way to change the NCP6356B configuration: the
operating mode, the output voltage as well as the enable (see
Table 2).
PG
No
TOR[2:0]
Delay
Table 2. VSEL PIN PARAMETERS
Parameter VSEL
Pin Can Set
REGISTER
VSEL = LOW
REGISTER
VSEL = HIGH
Delay Programmed in
TOR [2:0]
Figure 40. Power Good Operation
Interrupt Pin (Optional)
The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when a
system status change is detected (dual edge monitoring).
ENABLE
ENVSEL0
PROGVSEL0[7]
ENVSEL1
PROGVSEL1[7]
VOUT
VoutVSEL0[6..0]
VoutVSEL1[6..0]
OPERATING MODE
(Auto / PPWM Forced)
PWMVSEL0
COMMAND[7]
PWMVSEL1
COMMAND[6]
VSEL pin action can be masked by writing 0 to the VSELGT
bit in the COMMAND register. In that case the I C bit
corresponding to VSEL high will be taken into account.
Table 3. INTERRUPT SOURCES
2
Interrupt Name
TSD
Description
Thermal Shut Down
EN Pin
TWARN
TPREW
UVLO
Thermal Warning
The EN pin can be gated by writing the ENVSEL0 or
ENVSEL1 bits of the PROGVSEL0 and PROGVSEL1
registers, depending on which register is activated by the
VSEL internal signal.
Thermal Pre Warning
Under Voltage Lock Out
IDCDC
DC to DC converter Current Over /
below limit
Power Good Pin (Optional)
ISHORT
PG
DC to DC converter Short−Circuit Protection
Power Good
To indicate the output voltage level is established, a power
good signal is available.
The power good signal is low when the DC to DC
converter is off. Once the output voltage reaches 95% of the
expected output level, the power good logic signal becomes
high and the open drain output becomes high impedance.
During a positive DVS sequence when the target voltage
is higher than the initial voltage, the Power Good logic
signal will be set low during the output voltage ramping and
will transition to high once the output voltage reaches 95%
of the target voltage. When the target voltage is lower than
the initial voltage, the Power Good pin will remain at a high
level during the transition.
Individual bits generating interrupts will be set to 1 in the
INT_ACK register (I C read only registers), indicating the
2
interrupt source. INT_ACK register is automatically reset
2
by an I C read. The INT_SEN register (read only register)
contains real time indicators of interrupt sources.
All interrupt sources can be masked by writing in register
INT_MSK. Masked sources will never generate an interrupt
request on the INTB pin.
The INTB pin is an open drain output. A non−masked
interrupt request will result in the INTB pin being driven low.
When the host reads the INT_ACK registers the INTB pin
is released to high impedance and the interrupt register
INT_ACK is cleared.
The Power Good signal during normal operation can be
disabled by clearing the PGDCDC bit in the PGOOD register.
The Power Good operation during DVS can be controlled
by setting / clearing the PGDVS bit in the PGOOD register.
Figure 41 is an example of an UVLO event of the INTB
2
pin with INT_SEN/INT_MSK/INT_ACK and an I C read
DCDC_EN
access behavior.
95%
90%
UVLO
32 us
min
DCDC
3.5−
14 us
SEN−UVLO
MSK_UVLO
3.5−
14 us
3.5 us
PG
ACK_UVLO
Figure 39. Power Good Signal
INTB
Power Good Delay
In order to generate a Reset signal, a delay can be
programmed between when the output voltage gets 95% of
@
I C access on INT_ACK
read
read
read
read
Figure 41. Interrupt Operation Example
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15
NCP6356B
Configurations
Default output voltages, enables, DCDC modes, current limit and other parameters can be factory programmed upon request.
Below are the pre−defined default configurations:
Table 4. NCP6356B CONFIGURATION
5.0 A
4.0 A
4.0 A
NCP6356B
NCP6356BS
NCP6356BSN
Configuration
2
Default I C address
0x14
19h
Metal
00h
0x1C
19h
Metal
08h
0x1C
19h
Metal
09h
PID product identification
RID revision identification
FID feature identification
Default VOUT – VSEL=1
Default VOUT – VSEL=0
Default Enable – VSEL=1
Default Enable – VSEL=0
Default MODE – VSEL=1
Default MODE – VSEL=0
Default IPEAK
1.15 V
1.15 V
0.95 V
0.95 V
1.20 V
1.20 V
ON
ON
ON
ON
ON
ON
Forced PWM
Auto mode
6.8 A
Auto mode
Auto mode
5.8 A
Auto mode
Auto mode
5.8 A
OPN
NCP6356BFCCT1G
6356B
NCP6356BSFCCT1G
6356BS
NCP6356BSNFCCT1G
6356BN
Marking
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16
NCP6356B
2
I C Compatible Interface
The NCP6356B can support a subset of the I C protocol as detailed below.
2
I2C Communication Description
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
1
0
DATA 1
IC ADDRESS
ACK
ACK
/ACK
READ OUT FROM PART
START
ACK
ACK
DATA n
DATA n
STOP
STOP
1
READ
à
/ACK
ACK
IC ADDRESS
DATA 1
WRITE INSIDE PART
START
If PART does not Acknowledge, the /NACK will be followed by a STOP or Sr (repeated start).
If PART Acknowledges, the ACK can be followed by another data or STOP or Sr
0
WRITE
à
Figure 42. General Protocol Description
The first byte transmitted is the Chip address (with the LSB bit set to 1 for a read operation, or set to 0 for a Write operation).
The following data will be:
• During a Write operation, the register address (@REG) is written in followed by the data. The writing process is
auto−incremental, so the first data will be written in @REG, the contents of @REG are incremented and the next data
byte is placed in the location pointed to by @REG + 1 …, etc.
• During a Read operation, the NCP6356B will output the data from the last register that has been accessed by the last
write operation. Like the writing process, the reading process is auto−incremental.
Read Sequence
The Master will first make a “Pseudo Write” transaction with no data to set the internal address register. Then, a stop then
start or a Repeated Start will initiate the read transaction from the register address the initial write transaction has pointed to:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
0
ACK
ACK STOP
IC ADDRESS
REGISTER ADDRESS
START
0
WRITE
à
/ACK
1
DATA 1
DATA n
STOP
START
IC ADDRESS
ACK
ACK
REGISTER ADDRESS + (n−1)
VALUE
REGISTER ADDRESS
VALUE
n REGISTERS READ
1
READ
à
Figure 43. Read Sequence
The first WRITE sequence will set the internal pointer to the register that is selected. Then the read transaction will start at
the address the write transaction has initiated.
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17
NCP6356B
Write Sequence
Write operation will be achieved by only one transaction. After chip address, the REG address has to be set, then following
data will be the data we want to write in REG, REG + 1, REG + 2, …, REG +n.
Write n Registers:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
WRITE VALUE IN
REGISTER REG0 + (n−1)
WRITE VALUE IN
REGISTER REG0
START
IC ADDRESS
0
ACK
REGISTER REG0 ADDRESS
REG VALUE
ACK
REG + (n−1) VALUE
ACK
STOP
ACK
n REGISTERS WRITE
0àWRITE
Figure 44. Write Sequence
Write then Read Sequence
With Stop Then Start
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
WRITE VALUE IN
REGISTER REG0 + (n−1)
WRITE VALUE IN
REGISTER REG0
ACK
START
IC ADDRESS
0
REGISTER REG0 ADDRESS
ACK
REG VALUE
ACK
REG+ (n– 1) VALUE
ACK
STOP
n REGISTERS WRITE
à
0
WRITE
ACK
START
IC ADDRESS
1
DATA 1
ACK
DATA k
/ACK
STOP
REGISTER REG + (n−1)
VALUE
REGISTER ADDRESS + (n−1) +
(k−1) VALUE
k REGISTERS READ
à
1
READ
Figure 45. Write Followed by Read Transaction
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18
NCP6356B
I2C Address
2
The NCP6356B has 8 available I C addresses selectable by factory settings (ADD0 to ADD7). Different address settings
can be generated upon request to ON Semiconductor. See Table 4 (NCP6356B Configuration) for the default I C address.
2
Table 5. I2C ADDRESS
2
I C Address
Hex
A7
A6
A5
A4
A3
A2
A1
A0
ADD0
W 0x20
R 0x21
0
0
1
0
0
0
0
R/W
Add
0x10
0
−
ADD1
ADD2
ADD3
ADD4
ADD5
ADD6
ADD7
W 0x28
R 0x29
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
Add
0x14
1
−
W 0x30
R 0x31
R/W
Add
0x18
1
−
W 0x38
R 0x39
R/W
Add
0x1C
0
−
W 0xC0
R 0xC1
R/W
Add
0x60
0
−
W 0xC8
R 0xC9
R/W
Add
0x64
1
−
W 0xD0
R 0xD1
R/W
Add
0x68
1
−
W 0xD8
R 0xD9
R/W
Add
0x6C
−
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19
NCP6356B
Register Map
The tables below describe the I C registers.
Registers / bits Operations:
2
R
RC
Read only register
Read then Clear
RW
Read and Write register
Reserved
Spare
Address is reserved and register / bit is not physically designed
Address is reserved and register / bit is physically designed
Table 6. I2C REGISTERS MAP CONFIGURATION (NCP6356B)
Add.
00h
Register Name
INT_ACK
INT_SEN
INT_MSK
PID
Type
RC
R
Def.
00h
00h
FFh
19h
Metal
00h
−
Function
Interrupt register
01h
Sense register (real time status)
02h
RW
R
Mask register to enable or disable interrupt sources (trim)
Product Identification
03h
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 0Fh
10h
−
−
Reserved for future use
PROGVSEL1
PROGVSEL0
PGOOD
TIME
RW
RW
RW
RW
RW
−
D8h
D8h
10h
09h
43h
−
Output voltage settings and EN for VSEL pin = High (trim)
Output voltage settings and EN for VSEL pin = Low (trim)
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
11h
12h
13h
14h
COMMAND
−
Enabling and Operating mode Command register (trim)
Reserved for future use
15h
16h
LIMCONF
−
RW
−
E3h
−
Reset and limit configuration register (trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
Table 7. I2C REGISTERS MAP CONFIGURATION (NCP6356BS)
Add.
00h
Register Name
INT_ACK
INT_SEN
INT_MSK
PID
Type
RC
R
Def.
00h
00h
FFh
19h
Metal
08h
−
Function
Interrupt register
01h
Sense register (real time status)
02h
RW
R
Mask register to enable or disable interrupt sources (trim)
Product Identification
03h
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 0Fh
10h
−
−
Reserved for future use
PROGVSEL1
PROGVSEL0
PGOOD
TIME
RW
RW
RW
RW
RW
−
B8h
B8h
10h
01h
03h
−
Output voltage settings and EN for VSEL pin = High (trim)
Output voltage settings and EN for VSEL pin = Low (trim)
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
11h
12h
13h
14h
COMMAND
−
Enabling and Operating mode Command register (trim)
Reserved for future use
15h
16h
LIMCONF
−
RW
−
63h
−
Reset and limit configuration register (trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
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20
NCP6356B
Table 8. I2C REGISTERS MAP CONFIGURATION (NCP6356BSN)
Add.
00h
Register Name
INT_ACK
INT_SEN
INT_MSK
PID
Type
RC
R
Def.
00h
00h
FFh
19h
Metal
09h
−
Function
Interrupt register
01h
Sense register (real time status)
02h
RW
R
Mask register to enable or disable interrupt sources (trim)
Product Identification
03h
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 0Fh
10h
−
−
Reserved for future use
PROGVSEL1
PROGVSEL0
PGOOD
TIME
RW
RW
RW
RW
RW
−
E0h
E0h
10h
01h
03h
−
Output voltage settings and EN for VSEL pin = High (trim)
Output voltage settings and EN for VSEL pin = Low (trim)
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
11h
12h
13h
14h
COMMAND
−
Enabling and Operating mode Command register (trim)
Reserved for future use
15h
16h
LIMCONF
−
RW
−
63h
−
Reset and limit configuration register (trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
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21
NCP6356B
Registers Description
Table 9. INTERRUPT ACKNOWLEDGE REGISTER
Name: INTACK
Address: 00h
Default: 00000000b (00h)
Type: RC
Trigger: Dual Edge [D7..D0]
D7
D6
D5
D4
D3
D2
D1
D0
ACK_TSD
ACK_TWARN
ACK_TPREW
Spare = 0
ACK_ISHORT
ACK_UVLO
ACK_IDCDC
ACK_PG
Bit
Bit Description
ACK_PG
ACK_IDCDC
ACK_UVLO
ACK_ISHORT
ACK_TPREW
ACK_TWARN
ACK_TSD
Power Good Sense Acknowledgement
0: Cleared
1: DCDC Power Good Event detected
DCDC Over Current Sense Acknowledgement
0: Cleared
1: DCDC Over Current Event detected
Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event detected
DCDC Short−Circuit Protection Sense Acknowledgement
0: Cleared
1: DCDC Short circuit protection detected
Thermal Pre Warning Sense Acknowledgement
0: Cleared
1: Thermal Pre Warning Event detected
Thermal Warning Sense Acknowledgement
0: Cleared
1: Thermal Warning Event detected
Thermal Shutdown Sense Acknowledgement
0: Cleared
1: Thermal Shutdown Event detected
Table 10. INTERRUPT SENSE REGISTER
Name: INTSEN
Type: R
Address: 01h
Default: 00000000b (00h)
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
SEN_TSD
SEN_TWARN
SEN_TPREW
Spare = 0
SEN_ISHORT
SEN_UVLO
SEN_IDCDC
SEN_PG
Bit
Bit Description
SEN_PG
SEN_IDCDC
SEN_UVLO
SEN_ISHORT
SEN_TPREW
SEN _TWARN
SEN _TSD
Power Good Sense
0: DCDC Output Voltage below target
1: DCDC Output Voltage within nominal range
DCDC over current sense
0: DCDC output current is below limit
1: DCDC output current is over limit
Under Voltage Sense
0: Input Voltage higher than UVLO threshold
1: Input Voltage lower than UVLO threshold
DCDC Short−Circuit Protection Sense
0: Short−Circuit detected not detected
1: Short−Circuit not detected
Thermal Pre Warning Sense
0: Junction temperature below thermal pre−warning limit
1: Junction temperature over thermal pre−warning limit
Thermal Warning Sense
0: Junction temperature below thermal warning limit
1: Junction temperature over thermal warning limit
Thermal Shutdown Sense
0: Junction temperature below thermal shutdown limit
1: Junction temperature over thermal shutdown limit
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22
NCP6356B
Table 11. INTERRUPT MASK REGISTER
Name: INTMSK
Type: RW
Address: 02h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
MSK_TSD
MSK_TWARN
MSK_TPREW
Spare = 1
MSK_ISHORT
MSK_UVLO
MSK_IDCDC
MASK_PG
Bit
Bit Description
MSK_PG
MSK_IDCDC
MSK_UVLO
MSK_ISHORT
MSK_TPREW
MSK_TWARN
MSK_TSD
Power Good interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
DCDC over current interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Under Voltage interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
DCDC Short−Circuit Protection source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Thermal Pre Warning interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Thermal Warning interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Thermal Shutdown interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Table 12. PRODUCT ID REGISTER
Name: PID
Type: R
Address: 03h
Default: 00011001b (19h)
Reset on N/A
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
PID_7
PID_6
PID_5
PID_4
PID_3
PID_2
PID_1
PID_0
Table 13. REVISION ID REGISTER
Name: RID
Type: R
Address: 04h
Default: Metal
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
RID_7
RID_6
RID_5
RID_4
RID_3
RID_2
RID_1
RID_0
Bit
RID[7..0]
Bit Description
Revision Identification
0000000X: Prototype Silicon
00000010: Production
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23
NCP6356B
Table 14. FEATURE ID REGISTER
Name: FID
Type: R
Address: 05h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare
Spare
Spare
Spare
FID_3
FID_2
FID_1
FID_0
Bit
FID[3..0]
Bit Description
Feature Identification
See Table 4: NCP6356B Configuration
Table 15. DC TO DC VOLTAGE PROG (VSEL = 1) REGISTER
Name: PROGVSEL1
Type: RW
Trigger: N/A
D7
Address: 10h
Default: See Register map
D6
D5
D4
D3
D2
D1
D0
ENVSEL1
Bit
VoutVSEL1[6..0]
Bit Description
VoutVSEL1[6..0]
Sets the DC to DC converter output voltage when VSEL pin = 1 and VSEL pin function is enabled in register
COMMAND.D0, or when VSEL pin function is disabled in register COMMAND.D0
0000000b = 600 mV – 1111111b = 1393.75 mV (steps of 6.25 mV)
ENVSEL1
EN Pin Gating for VSEL internal signal = High
0: Disabled
1: Enabled
Table 16. DC TO DC VOLTAGE PROG (VSEL = 0) REGISTER
Name: PROGVSEL0
Type: RW
Address: 11h
Default: See Register map
Trigger: N/A
D7
ENVSEL0
Bit
D6
D5
D4
D3
D2
D1
D0
VoutVSEL0[6..0]
Bit Description
VoutVSEL0[6..0]
Sets the DC to DC converter output voltage when VSEL pin = 0 and VSEL pin function is enabled in register
COMMAND.D0
0000000b = 600 mV – 1111111b = 1393.75 mV (steps of 6.25 mV)
ENVSEL0
EN Pin Gating for VSEL internal signal = Low
0: Disabled
1: Enabled
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24
NCP6356B
Table 17. POWER GOOD REGISTER
Name: PGOOD
Address: 12h
Default: See Register map
Type: RW
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 0
Bit
Spare = 0
Spare = 0
DISCHG
TOR[1..0]
PGDVS
PGDCDC
Bit Description
PGDCDC
Power Good Enabling
0 = Disabled
1 = Enabled
PGDVS
Power Good Active On DVS
0 = Disabled
1 = Enabled
TOR[1..0]
Time out Reset settings for Power Good
00 = 0 ms
01 = 8 ms
10 = 32 ms
11 = 64 ms
DISCHG
Active discharge bit Enabling
0 = Discharge path disabled
1 = Discharge path enabled
Table 18. TIMING REGISTER
Name: TIME
Address: 13h
Default: See Register map
Type: RW
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
DELAY[2..0]
DVS[1..0]
Spare = 0
DBN_Time[1..0]
Bit
Bit Description
DBN_Time[1..0]
DVS[1..0]
EN and VSEL debounce time
00 = No debounce
01 = 1−2 ms
10 = 2−3 ms
11 = 3−4 ms
DVS Speed
00 = 6.25 mV step / 0.333 ms
01 = 6.25 mV step / 0.666 ms
10 = 6.25 mV step / 1.333 ms
11 = 6.25 mV step / 2.666 ms
DELAY[2..0]
Delay applied upon enabling (ms)
000b = 0 ms − 111b = 14 ms (Steps of 2 ms)
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25
NCP6356B
Table 19. COMMAND REGISTER
Name: COMMAND
Type: RW
Address: 14h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
PPWMVSEL0 PPWMVSEL1
DVSMODE
Sleep_Mode
Spare = 0
Spare = 0
Spare
VSELGT
Bit
Bit Description
VSELGT
VSEL Pin Gating
0 = Disabled
1 = Enabled
Sleep_Mode
DVSMODE
Sleep mode
0 = Low Iq mode when EN and VSEL low
1 = Force product in sleep mode (when EN and VSEL are low)
DVS transition mode selection
0 = Auto
1 = Forced PPWM
PPWMVSEL1
PPWMVSEL0
Operating mode for MODE internal signal = High
0 = Auto
1 = Forced PPWM
Operating mode for MODE internal signal = Low
0 = Auto
1 = Forced PPWM
Table 20. LIMITS CONFIGURATION REGISTER
Name: LIMCONF
Type: RW
Adress: 16h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
IPEAK[1..0]
TPWTH[1..0]
Spare = 0
FORCERST
RSTSTATUS
REARM
Bit
Bit Description
REARM
Rearming of device after TSD / ISHORT
0: No re−arming after TSD / ISHORT
2
1: Re−arming active after TSD / ISHORT with no reset of I C registers: new power−up sequence is initiated
2
with previously programmed I C registers values
RSTSTATUS
FORCERST
TPWTH[1..0]
Reset Indicator Bit
0: Must be written to 0 after register reset
1: Default (loaded after Registers reset)
Force Reset Bit
0: Default value. Self cleared to 0
1: Force reset of internal registers to default
Thermal pre−Warning threshold settings
00 = 83°C
01 = 94°C
10 = 105°C
11 = 116°C
IPEAK
Inductor peak current settings
00 = 5.2 A (for 3.5 A output current)
01 = 5.8 A (for 4.0 A output current)
10 = 6.2 A (for 4.5 A output current)
11 = 6.8 A (for 5.0 A output current)
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26
NCP6356B
APPLICATION INFORMATION
NCP6356B
AVIN
PVIN
D1
D2
E1
E2
Supply Input
Core
AGND
B4
4.7 uF
Thermal
Protection
D3
D4
E3
E4
DCDC
5.0 A
SW
Enable Control EN
A2
A1
Operating
Mode
Control
Input
330 nH
Voltage
VSEL
Selection
22 uF
C1
C2
C3
C4
PGND
FB
Output
Monitoring
PGND
PG
B3
B2
B1
Power Fail
Interrupt
PGND
INTB
A4
DCDC
Up to 2.4 MHz
Controller
Processor
Core
SDA
Sense
22 uF
I@C
Processor I@C
Control Interface
SCL
A3
Figure 46. Typical Application Schematic
Output Filter Considerations
The output filter introduces a double pole in the system at
a frequency of:
Components Selection
Inductor Selection
The inductance of the inductor is chosen such that the
peak−to−peak ripple current I is approximately 20% to
L_PP
1
fLC
+
50% of the maximum output current I
. This
OUT_MAX
(eq. 1)
Ǹ
2 @ p @ L @ C
provides the best trade−off between transient response and
output ripple. The inductance corresponding to a given
current ripple is:
The NCP6356B internal compensation network is
optimized for a typical output filter comprising a 330 nH
inductor and 47 mF capacitor as described in the basic
application schematic in Figure 46.
ǒ
Ǔ
VIN * VOUT @ VOUT
(eq. 2)
L +
VIN @ fSW @ IL_PP
Voltage Sensing Considerations
The selected inductor must have a saturation current
rating higher than the maximum peak current which is
calculated by:
In order to regulate the power supply rail, the NCP6356B
must sense its output voltage. The IC can support two
sensing methods:
• Normal sensing: The FB pin should be connected to the
IL_PP
(eq. 3)
IL_MAX + IOUT_MAX
)
output capacitor positive terminal (voltage to regulate).
2
• Remote sensing: The power supply rail sense should be
made close to the system powered by the NCP6356B.
The voltage to the system is more accurate, since the
PCB line impedance voltage drop is within the
regulation loop. In this case, we recommend connecting
the FB pin to the system decoupling capacitor positive
terminal.
The inductor must also have a high enough current rating
to avoid self−heating. A low DCR is therefore preferred.
Refer to Table 21 for recommended inductors.
www.onsemi.com
27
NCP6356B
Table 21. INDUCTOR SELECTION
Value
Size (mm)
(L x l x T) (mm)
Saturation
Current Max (A)
DCR Max at 255C
(mW)
(mH)
0.33
0.33
0.33
0.33
0.33
0.33
0.33
0.35
Supplier
Cyntec
Cyntec
Cyntec
TOKO
TOKO
TOKO
TDK
Part #
PIFE20161B−R33MS−11
PIFE25201B−R33MS−11
PIFE32251B−R33MS−11
DFE252012F−H−R33M
DFE201612E−H−R33M
FDSD0412−H−R33M
VLS252012HBX−R33M
SPM5030T−R35M
2.0 x 1.6 x 1.2
2.5 x 2.0 x 1.2
3.2 x 2.5 x 1.2
2.5 x 2.0 x 1.2
2.0 x 1.6 x 1.2
4.2 x 4.2 x 1.2
2.5 x 2.0 x 1.2
7.1 x 6.5 x 3.0
4.0
5.2
6.5
5.1
4.8
7.5
5.3
14.9
33
17
14
13
21
19
25
4
TDK
Output Capacitor Selection
2
ǒ
Ǔ
IOUT_MAX @ D * D
The output capacitor selection is determined by output
voltage ripple and load transient response requirement. For
high transient load performance a high output capacitor
value must be used. For a given peak−to−peak ripple current
(eq. 10)
(eq. 11)
CIN_MIN
+
VIN_PP @ fSW
where
VOUT
I
in the inductor of the output filter, the output voltage
L_PP
D +
VIN
ripple across the output capacitor is the sum of three
components as shown below.
In addition, the input capacitor must be able to absorb the
input current, which has a RMS value of
VOUT_PP [ VOUT_PP(C) ) VOUT_PP(ESR) ) VOUT_PP(ESL)
,
Ǹ
IIN_RMS + IOUT_MAX @ D * D2
(eq. 4)
(eq. 12)
With:
The input capacitor also must be sufficient to protect the
device from over voltage spikes, and a 4.7 mF capacitor or
greater is required. The input capacitor should be located as
close as possible to the IC. All PGND pins must be
connected together to the ground terminal of the input cap
which then must be connected to the ground plane. All PVIN
pins must be connected together to the Vbat terminal of the
input cap which then connects to the Vbat plane.
IL_PP
(eq. 5)
VOUT_PP(C)
+
,
8 @ C @ fSW
VOUT_PP(ESR) + IL_PP @ ESR
(eq. 6)
(eq. 7)
ESL
VOUT_PP(ESL)
+
@ VIN
ESL ) L
Where the peak−to−peak ripple current is given by
Power Capability
The NCP6356B’s power capability is driven by the
difference in temperature between the junction (T ) and
ǒ
Ǔ
VIN * VOUT @ VOUT
(eq. 8)
IL_PP
+
J
VIN @ fSW @ L
ambient (T ), the junction−to−ambient thermal resistance
A
In applications with all ceramic output capacitors, the
main ripple component of the output ripple is V
(R ), and the on−chip power dissipation (P ).
qJA
IC
.
OUT_PP(C)
The on−chip power dissipation P can be determined as P
IC
IC
The minimum output capacitance can be calculated based on
= P − P with the total power losses P being
T
L
T
a given output ripple requirement V
in PPWM
OUT_PP
1
ǒ
* 1Ǔ
(eq. 13)
operation mode.
PT + VOUT IOUT
h
IL_PP
(eq. 9)
CMIN
+
where h is the efficiency and P the simplified inductor
L
8 @ VOUT_PP @ fSW
2
power losses P = I
x DCR.
L
LOAD
Now the junction temperature T can easily be calculated
J
Input Capacitor Selection
as T = R
x P + T .
IC A
J
qJA
One of the input capacitor selection requirements is the
input voltage ripple. To minimize the input voltage ripple
and get better decoupling at the input power supply rail, a
ceramic capacitor is recommended due to low ESR and ESL.
The minimum input capacitance with respect to the input
Please note that the T should stay within the recommended
operating conditions.
J
The R is a function of the PCB layout (number of layers
qJA
and copper and PCB size). For example, the NCP6356B
mounted on the EVB has a R
about 55°C/W.
qJA
ripple voltage V
is
IN_PP
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28
NCP6356B
Layout Considerations
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• Use multiple vias around the IC to connect the inner
ground layers to reduce thermal impedance.
Electrical Rules
Good electrical layout is key to proper operation, high
efficiency, and noise reduction. Electrical layout guidelines
are:
• Use wide and short traces for power paths (such as
PVIN, VOUT, SW, and PGND) to reduce parasitic
inductance and high−frequency loop area. It is also
good for efficiency improvement.
• Use a large and thick copper area especially in the top
layer for good thermal conduction and radiation.
• Use two layers or more for the high current paths
(PVIN, PGND, SW) in order to split current into
different paths and limit PCB copper self−heating.
• The device should be well decoupled by input capacitor
and the input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission.
• SW track should be wide and short to reduce losses and
noise radiation.
Component Placement
• Input capacitor placed as close as possible to the IC.
• PVIN directly connected to Cin input capacitor, and
then connected to the Vin plane. Local mini planes used
on the top layer (green) and the layer just below the top
layer (yellow) with laser vias.
• It is recommended to have separated ground planes for
PGND and AGND and connect the two planes at one
point. Try to avoid overlap of input ground loop and
output ground loop to prevent noise impact on output
regulation.
• AVIN connected to the Vin plane just after the capacitor.
• AGND directly connected to the GND plane.
• PGND directly connected to Cin input capacitor, and
then connected to the GND plane: Local mini planes
used on the top layer (green) and the layer just below
the top layer (yellow) with laser vias.
• Arrange a “quiet” path for output voltage sense, and
make it surrounded by a ground plane.
• SW connected to the Lout inductor with local mini
planes used on the top layer (green) and the layer just
below the top layer (yellow) with laser vias.
Thermal Rules
Good PCB layout improves the thermal performance and
thus allows for high power dissipation even with a small IC
package. Thermal layout guidelines are:
(See Figures 47 and 48 for examples)
4.3 mm
0603
22 uF
2.3 x 1.2 mm
FB
SCL
EN
AGND PGND
SW
SW
SW
SW
PGND
PG
PGND
PGND
PGND
INTB
PVIN
PVIN
PVIN
VSEL
SDA PGND AVIN
0603
4.7 uF
2.3 x 1.2 mm
S < 18.00 mm@
Figure 47. Placement Recommendation
Figure 48. Demo Board Example
Legend:
Green: top layer planes and wires
Yellow: layer1 plane and wires (just below top layer)
Big grey circles: normal vias
Small gray circles: top to layer1 vias
www.onsemi.com
29
NCP6356B
ORDERING INFORMATION
Device
†
Marking
Configuration
Package
Shipping
NCP6356BFCCT1G
6356B
5.0 A
1.15 V
ON
WLCSP20 2.02 x 1.62 mm
(Pb–Free)
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
NCP6356BSFCCT1G
NCP6356BSNFCCT1G
6356BS
6356BN
4.0 A
0.95 V
ON
WLCSP20 2.02 x 1.62 mm
(Pb–Free)
4.0 A
1.20 V
ON
WLCSP20 2.02 x 1.62 mm
(Pb–Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Demo Board Available:
The NCP6356BGEVB/D evaluation board that configures the device in typical application to supply constant voltage.
www.onsemi.com
30
NCP6356B
PACKAGE DIMENSIONS
WLCSP20, 1.62x2.02
CASE 568AG
ISSUE D
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
PIN A1
REFERENCE
MILLIMETERS
DIM
A
A1
A2
A3
b
MIN
−−−
0.17
0.33
0.02
0.24
MAX
0.60
0.23
0.39
0.04
0.28
E
A2
DIE COAT
(OPTIONAL)
A3
2X
0.10
0.10
C
D
1.62 BSC
E
e
2.02 BSC
0.40 BSC
2X
C
TOP VIEW
DETAIL A
A2
DETAIL A
0.10
C
A
RECOMMENDED
0.05
C
SOLDERING FOOTPRINT*
SEATING
PLANE
NOTE 3
C
A1
SIDE VIEW
A1
PACKAGE
OUTLINE
e/2
20X
b
e
0.05
0.03
C A B
E
C
e
0.40
PITCH
D
C
B
20X
0.25
0.40
PITCH
DIMENSIONS: MILLIMETERS
A
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1
2
3
4
BOTTOM VIEW
2
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