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NCP702SN31T1G [ONSEMI]

200 mA, Ultra-Low Quiescent Current, Ultra-Low Noise, LDO Linear Voltage Regulator;
NCP702SN31T1G
型号： NCP702SN31T1G
厂家： ONSEMI    ONSEMI
描述：

200 mA, Ultra-Low Quiescent Current, Ultra-Low Noise, LDO Linear Voltage Regulator
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NCP702  
200 mA, Ultra-Low Quiescent  
Current, Ultra-Low Noise, LDO  
Linear Voltage Regulator  
Noise sensitive applications such as Phase Locked Loops,  
Oscillators, Frequency Synthesizers, Low Noise Amplifiers and other  
Precision Instrumentation require very clean power supplies. The  
NCP702 is a 200 mA LDO that provides the engineer with a very  
stable, accurate voltage with ultra−low noise and very high Power  
Supply Rejection Ratio (PSRR), making it suitable for RF  
applications. The device doesn’t require an additional noise bypass  
capacitor to achieve ultra−low noise performance. In order to optimize  
performance for battery operated portable applications, the NCP702  
employs an Adaptive Ground Current feature for ultra−low ground  
current consumption during light−load conditions.  
http://onsemi.com  
5
1
1
TSOP−5  
XDFN−6  
MX SUFFIX  
CASE 711AE  
SN SUFFIX  
CASE 483  
MARKING DIAGRAMS  
Features  
• Operating Input Voltage Range: 2.0 V to 5.5 V  
5
1
1
• Available in Fixed Voltage Options: 0.8 to 3.5 V  
Contact Factory for Other Voltage Options  
• Output Voltage Trimming Step: 2.5 mV  
XXXAYW  
X M  
G
G
• Ultra−Low Quiescent Current of Typ. 10 mA  
X, XXX = Specific Device Code  
M
A
Y
W
G
= Date Code  
• Ultra−Low Noise: 11 mV  
from 100 Hz to 100 kHz  
• Very Low Dropout: 140 mV Typical at 200 mA  
2% Accuracy Over Full Load/Line/Temperature  
RMS  
= Assembly Location  
= Year  
= Work Week  
= Pb−Free Package  
•
• High PSRR: 68 dB at 1 kHz  
• Thermal Shutdown and Current Limit Protections  
• Internal Soft−Start to Limit the Turn−On Inrush Current  
• Stable with a 1 mF Ceramic Output Capacitor  
• Available in TSOP−5 and XDFN 1.5 x 1.5 mm Package  
• Active Output Discharge for Fast Output Turn−Off  
• These are Pb−Free Devices  
PIN CONNECTIONS  
1
IN  
OUT  
GND  
EN  
N/C  
5−Pin TSOP−5  
(Top View)  
Typical Applicaitons  
• PDAs, Mobile Phones, GPS, Smartphones  
• Wireless Handsets, Wireless LAN, Bluetooth, Zigbee  
• Portable Medical Equipment  
1
OUT  
IN  
N/C  
GND  
N/C  
EN  
• Other Battery Powered Applications  
6−Pin XDFN 1.5 x 1.5 mm  
NCP702  
(Top View)  
V
IN  
V
OUT  
IN  
OUT  
1 mF  
C
1 mF  
IN  
EN  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information in the  
package dimensions section on page 18 of this data sheet.  
C
OUT  
GND  
Figure 1. Typical Application Schematic  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
July, 2013 − Rev. 3  
NCP702/D  
NCP702  
IN  
ENABLE  
LOGIC  
THERMAL  
SHUTDOWN  
UVLO  
EN  
−
MOSFET  
DRIVER WITH  
CURRENT LIMIT  
BANDGAP  
REFERENCE  
INTEGRATED  
SOFT−START  
+
OUT  
AUTO LOW  
POWER MODE  
ACTIVE  
DISCHARGE  
EEPROM  
EN  
GND  
Figure 2. Simplified Schematic Block Diagram  
Table 1. PIN FUNCTION DESCRIPTION  
Pin No.  
XDFN 6  
Pin No.  
TSOP−5  
Pin  
Name  
Description  
1
5
OUT  
Regulated output voltage pin. A small 1 mF ceramic capacitor is needed from this pin to ground  
to assure stability.  
2
3
4
4
2
3
N/C  
GND  
EN  
Not connected. This pin can be tied to ground to improve thermal dissipation.  
Power supply ground.  
Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into  
shutdown mode.  
5
6
N/C  
IN  
Not connected. This pin can be tied to ground to improve thermal dissipation.  
1
Input pin. It is recommended to connect a 1 mF ceramic capacitor close to the device pin.  
Table 2. ABSOLUTE MAXIMUM RATINGS  
Rating  
Symbol  
Value  
Unit  
V
Input Voltage (Note 1)  
V
IN  
−0.3 V to 6 V  
Output Voltage  
V
OUT  
−0.3 V to V + 0.3 V  
V
IN  
Enable Input  
V
−0.3 V to V + 0.3 V  
V
EN  
SC  
IN  
Output Short Circuit Duration  
Maximum Junction Temperature  
Storage Temperature  
t
Indefinite  
150  
s
T
°C  
°C  
V
J(MAX)  
T
STG  
−55 to 150  
2000  
ESD Capability, Human Body Model (Note 2)  
ESD Capability, Machine Model (Note 2)  
ESD  
HBM  
ESD  
200  
V
MM  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.  
2. This device series incorporates ESD protection and is tested by the following methods:  
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)  
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)  
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.  
http://onsemi.com  
2
 
NCP702  
Table 3. THERMAL CHARACTERISTICS (Note 3)  
Rating  
Symbol  
Value  
Unit  
Thermal Characteristics, TSOP−5,  
Thermal Resistance, Junction−to−Air  
Thermal Characterization Parameter, Junction−to−Lead (Pin 2)  
°C/W  
q
y
224  
115  
JA  
JA  
Thermal Characteristics, XDFN6 1.5 x 1.5 mm  
Thermal Resistance, Junction−to−Air  
Thermal Characterization Parameter, Junction−to−Board  
°C/W  
q
y
149  
81  
JA  
JB  
2
3. Single component mounted on 1 oz, FR4 PCB with 645 mm Cu area.  
Table 4. ELECTRICAL CHARACTERISTICS  
−40°C ≤ T ≤ 125°C; V = V  
+ 0.3 V or 2.0 V, whichever is greater; V = 0.9 V, I  
= 10 mA, C = C  
= 1 mF.  
J
IN  
OUT(NOM)  
EN  
OUT  
IN  
OUT  
Typical values are at T = +25°C. Min/Max values are specified for T = −40°C and T = 125°C respectively. (Note 4)  
J
J
J
Parameter  
Test Conditions  
Symbol  
Min  
2.0  
1.2  
−2  
Typ  
Max  
Unit  
Operating Input Voltage  
Undervoltage lock−out  
Output Voltage Accuracy  
Line Regulation  
V
IN  
5.5  
1.9  
+2  
V
V
V
V
V
V
rising  
UVLO  
1.6  
IN  
+ 0.3 V ≤ V ≤ 5.5 V, I  
= 0 − 200 mA  
V
OUT  
%
OUT  
OUT  
OUT  
IN  
OUT  
OUT  
OUT  
+ 0.3 V ≤ V ≤ 4.5 V, I  
= 10 mA  
= 10 mA  
Reg  
Reg  
290  
440  
13  
mV/V  
mV/V  
mV/mA  
mV  
mA  
mA  
IN  
LINE  
LINE  
LOAD  
DO  
+ 0.3 V ≤ V ≤ 5.5 V, I  
IN  
Load Regulation  
I
I
= 0 mA to 200 mA  
Reg  
OUT  
OUT  
Dropout voltage (Note 5)  
Output Current Limit  
Quiescent current  
Ground current  
= 200 mA, V  
= 2.5 V  
V
140  
385  
10  
200  
550  
16  
OUT(nom)  
OUT(nom)  
V
OUT  
= 90% V  
I
CL  
220  
I
I
I
= 0 mA  
= 2 mA  
= 200 mA  
≤ 0.4 V  
I
Q
OUT  
OUT  
OUT  
I
I
60  
mA  
GND  
GND  
160  
0.005  
0.01  
mA  
Shutdown current (Note 6)  
V
V
I
I
mA  
EN  
DIS  
≤ 0.4 V, V = 4.5 V  
1
mA  
EN  
IN  
DIS  
EN Pin Threshold Voltage  
High Threshold  
Low Threshold  
V
V
V
Voltage increasing  
Voltage decreasing  
V
0.9  
EN  
EN_HI  
V
0.4  
EN  
EN_LO  
EN Pin Input Current  
V
= V = 5.5 V  
I
110  
300  
500  
nA  
ms  
%
EN  
IN  
EN  
Turn−On Time (Note 7)  
C
= 1.0 mF, I  
= 1 mA  
t
OUT  
OUT  
ON  
Output Voltage Overshoot on  
Start−up (Note 8)  
V
EN  
= 0 V to 0.9 V, 0 ≤ I  
≤ 200 mA  
DV  
2
OUT  
OUT  
OUT  
Load Transient  
I
I
= 1 mA to 200 mA or  
= 200 mA to 1 mA in 10 ms, C  
DV  
−30/+30  
mV  
dB  
OUT  
OUT  
= 1 mF  
OUT  
Power Supply Rejection Ratio  
V
IN  
= 3 V, V  
= 2.5 V  
f = 100 Hz  
f = 1 kHz  
f = 10 kHz  
PSRR  
70  
68  
53  
OUT  
I
= 150 mA  
OUT  
Output Noise Voltage  
V
= 2.5 V, V = 3 V, I  
= 200 mA  
V
N
11  
mV  
rms  
OUT  
IN  
OUT  
f = 100 Hz to 100 kHz  
Active Discharge Resistance  
Thermal Shutdown Temperature  
Thermal Shutdown Hysteresis  
V
< 0.4 V  
R
1
kW  
EN  
DIS  
Temperature increasing from T = +25°C  
T
160  
20  
°C  
°C  
J
SD  
Temperature falling from T  
T
SDH  
−
−
SD  
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T = T  
J
A
= 25_C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.  
5. Characterized when V  
falls 100 mV below the regulated voltage at V = V  
+ 0.3 V.  
OUT  
IN  
OUT(NOM)  
6. Shutdown Current is the current flowing into the IN pin when the device is in the disable state.  
7. Turn−On time is measured from the assertion of EN pin to the point when the output voltage reaches 0.98 V  
8. Guaranteed by design.  
OUT(NOM)  
http://onsemi.com  
3
 
NCP702  
TYPICAL CHARACTERISTICS  
10  
1
V
V
C
= 2.0 V  
IN  
= 0.8 V  
= C = 1 mF  
OUT  
IN  
OUT  
MLCC, X5R,  
0402 size  
RMS Output Noise  
I
OUT  
10 Hz − 100 kHz  
100 Hz − 100 kHz  
21.17  
I
= 1 mA  
OUT  
0.1  
1 mA  
10 mA  
200 mA  
21.74  
14.62  
10.74  
14.07  
I
= 200 mA  
10.02  
OUT  
0.01  
I
= 10 mA  
OUT  
0.001  
10  
10  
10  
100  
100  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
Figure 3. Output Voltage Noise Spectral Density for VOUT = 0.8 V, COUT = 1 mF  
10  
1
V
V
C
= 2.0 V  
IN  
= 0.8 V  
= C = 4.7 mF  
OUT  
IN  
OUT  
MLCC, X7R,  
1206 size  
RMS Output Noise  
I
OUT  
I
= 1 mA  
10 Hz − 100 kHz  
100 Hz − 100 kHz  
13.43  
OUT  
I
= 10 mA  
OUT  
0.1  
1 mA  
10 mA  
200 mA  
14.16  
14.20  
10.99  
13.70  
I
= 200 mA  
OUT  
10.48  
0.01  
0.001  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
Figure 4. Output Voltage Noise Spectral Density for VOUT = 0.8 V, COUT = 4.7 mF  
10  
1
V
V
C
= 2.0 V  
IN  
= 0.8 V  
= C = 10 mF  
OUT  
IN  
OUT  
MLCC, X7R,  
1206 size  
RMS Output Noise  
I
OUT  
I
= 1 mA  
OUT  
10 Hz − 100 kHz  
100 Hz − 100 kHz  
12.11  
I
= 10 mA  
0.1  
OUT  
1 mA  
10 mA  
200 mA  
12.94  
12.78  
11.33  
12.25  
I
= 200 mA  
OUT  
10.83  
0.01  
0.001  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
Figure 5. Output Voltage Noise Spectral Density for VOUT = 0.8 V, COUT = 10 mF  
http://onsemi.com  
4
 
NCP702  
TYPICAL CHARACTERISTICS  
10  
1
V
V
C
= 3.8 V  
IN  
= 3.3 V  
= C = 1 mF  
OUT  
IN  
OUT  
MLCC, X5R,  
0402 size  
RMS Output Noise  
I
OUT  
10 Hz − 100 kHz  
100 Hz − 100 kHz  
17.87  
I
= 1 mA  
OUT  
I
= 10 mA  
OUT  
0.1  
1 mA  
10 mA  
200 mA  
20.28  
16.73  
13.70  
13.90  
I
= 200 mA  
10.21  
OUT  
0.01  
0.001  
10  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
Figure 6. Output Voltage Noise Spectral Density for VOUT = 3.3 V, COUT = 1 mF  
10  
1
V
V
C
= 3.8 V  
IN  
= 3.3 V  
= C = 4.7 mF  
OUT  
IN  
OUT  
MLCC, X7R,  
1202 size  
RMS Output Noise  
I
OUT  
10 Hz − 100 kHz  
100 Hz − 100 kHz  
11.82  
I
= 1 mA  
OUT  
0.1  
I
= 10 mA  
1 mA  
10 mA  
200 mA  
15.76  
17.09  
14.51  
OUT  
13.88  
I
= 200 mA  
OUT  
11.47  
0.01  
0.001  
10  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
Figure 7. Output Voltage Noise Spectral Density for VOUT = 3.3 V, COUT = 4.7 mF  
10  
1
V
V
C
= 3.8 V  
IN  
= 3.3 V  
= C = 10 mF  
OUT  
IN  
OUT  
MLCC, X7R,  
1206 size  
RMS Output Noise  
I
OUT  
10 Hz − 100 kHz  
100 Hz − 100 kHz  
10.57  
I
= 1 mA  
OUT  
0.1  
I
= 10 mA  
1 mA  
10 mA  
200 mA  
14.87  
16.00  
14.89  
OUT  
12.65  
I
= 200 mA  
OUT  
11.84  
0.01  
0.001  
10  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
Figure 8. Output Voltage Noise Spectral Density for VOUT = 3.3 V, COUT = 10 mF  
http://onsemi.com  
5
 
NCP702  
TYPICAL CHARACTERISTICS  
100  
90  
80  
70  
60  
50  
40  
30  
20  
100  
V
V
C
C
= 2.0 V  
V
V
C
= 2.0 V  
C
= none  
IN  
IN  
IN  
90  
= 0.8 V  
= 0.8 V  
MLCC, X7R,  
1206 size  
OUT  
OUT  
= 1 mF  
80  
70  
60  
50  
40  
30  
20  
= 4.7 mF  
OUT  
OUT  
= none  
IN  
MLCC, X5R,  
0402 size  
I
I
I
I
I
= 1 mA  
I
I
I
I
= 1 mA  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
= 10 mA  
= 50 mA  
= 150 mA  
= 200 mA  
= 10 mA  
= 50 mA  
= 150 mA  
= 200 mA  
OUT  
OUT  
OUT  
10  
0
10  
10  
0
10  
I
OUT  
100  
1k  
10k  
100k  
1M  
10M  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 9. Power Supply Rejection Ratio,  
Figure 10. Power Supply Rejection Ratio,  
V
OUT = 0.8 V, COUT = 1 mF  
VOUT = 0.8 V, COUT = 4.7 mF  
90  
80  
70  
60  
50  
40  
30  
20  
110  
100  
V
V
C
C
= 3.8 V  
IN  
= 3.3 V  
OUT  
90  
80  
70  
60  
50  
40  
30  
20  
= 1 mF  
OUT  
= none  
IN  
MLCC, X5R,  
0402 size  
V
V
C
C
= 3.8 V  
IN  
= 3.3 V  
I
= 1 mA  
OUT  
OUT  
I
I
I
I
I
= 1 mA  
OUT  
OUT  
OUT  
OUT  
OUT  
= 4.7 mF  
I
I
I
I
= 10 mA  
= 50 mA  
= 150 mA  
= 200 mA  
OUT  
OUT  
OUT  
OUT  
OUT  
= 10 mA  
= 50 mA  
= 150 mA  
= 200 mA  
= none  
IN  
MLCC, X7R,  
1206 size  
10  
0
10  
10  
0
10  
100  
1k  
10k  
100k  
1M  
10M  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 11. Power Supply Rejection Ratio,  
OUT = 3.3 V, COUT = 1 mF  
Figure 12. Power Supply Rejection Ratio,  
V
VOUT = 3.3 V, COUT = 4.7 mF  
100  
90  
80  
70  
60  
50  
40  
30  
20  
90  
80  
70  
f = 100 Hz  
f = 1 kHz  
60  
50  
40  
30  
20  
f = 10 kHz  
f = 100 kHz  
V
V
C
C
= 3.8 V  
IN  
f = 1 MHz  
= 3.3 V  
I
I
I
I
I
= 1 mA  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
= 10 mF  
= 10 mA  
= 50 mA  
= 150 mA  
= 200 mA  
OUT  
V
C
C
= 3.3 V  
I
= 200 mA  
= 4.7 mF MLCC, X7R,  
OUT  
OUT  
= none  
IN  
MLCC, X7R,  
1206 size  
OUT  
IN  
10  
0
10  
0
10  
= none  
1206 size  
0
0.2  
0.4  
− V  
0.6  
0.8  
1.0 1.2  
1.4  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY (Hz)  
V
IN  
VOLTAGE DIFFERENTIAL (V)  
OUT  
Figure 13. Power Supply Rejection Ratio,  
OUT = 3.3 V, COUT = 10 mF  
Figure 14. PSRR vs. Voltage Differential,  
V
COUT = 4.7 mF, IOUT = 200 mA  
http://onsemi.com  
6
NCP702  
TYPICAL CHARACTERISTICS  
80  
70  
60  
50  
40  
30  
20  
12  
T = 125°C  
J
f = 1 kHz  
10  
T = 25°C  
J
f = 10 kHz  
8
f = 100 kHz  
T = −40°C  
J
f = 1 MHz  
6
4
V
C
C
= 3.3 V  
= 4.7 mF  
= none  
= 10 mA  
OUT  
OUT  
IN  
V
OUT  
= 3.3 V  
= 0 mA  
= 1 mF  
I
OUT  
2
0
I
OUT  
MLCC, X7R,  
1206 size  
10  
0
C
OUT  
0
0
0
0.2  
0.4  
− V  
0.6  
0.8  
1.0  
1.2  
1.4  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
, INPUT VOLTAGE (V)  
V
IN  
VOLTAGE DIFFERENTIAL (V)  
V
IN  
OUT  
Figure 15. PSRR vs. Voltage Differential,  
OUT = 4.7 mF, IOUT = 10 mA  
Figure 16. Quiescent Current vs. Input Voltage,  
OUT = 3.3 V  
C
V
12  
10  
8
140  
120  
100  
80  
T = 125°C  
J
T = 125°C  
J
T = 25°C  
J
T = 25°C  
J
T = −40°C  
J
6
60  
T = −40°C  
J
4
40  
V
OUT  
= 0.8 V  
= 0 mA  
= 1 mF  
2
V
= 3.3 V  
= 1 mF  
OUT(nom)  
I
OUT  
20  
0
C
= C  
IN  
OUT  
C
OUT  
0
1
2
3
4
5
6
0
20 40 60 80 100 120 140 160 180 200  
, OUTPUT CURRENT (mA)  
V
, INPUT VOLTAGE (V)  
I
OUT  
IN  
Figure 17. Quiescent Current vs. Input Voltage,  
OUT = 0.8 V  
Figure 18. Dropout Voltage vs. Output Current,  
VOUT = 3.3 V  
V
200  
180  
160  
0.817  
0.813  
0.809  
140  
120  
100  
80  
0.805  
0.801  
0.797  
0.793  
0.789  
T = 125°C  
J
T = 25°C  
J
V
V
I
= 2.0 V  
IN  
OUT(nom)  
60  
T = −40°C  
J
= 0.8 V  
= 10 mA  
40  
V
= 2.5 V  
OUT  
OUT(nom)  
C
= C  
= 1 mF  
C
= C  
= 1 mF  
0.785  
0.781  
OUT  
OUT  
IN  
OUT  
20  
0
20 40 60 80 100 120 140 160 180 200  
, OUTPUT CURRENT (mA)  
−40 −20  
0
20  
40  
60  
80 100 120 140  
I
T , JUNCTION TEMPERATURE (°C)  
OUT  
J
Figure 19. Dropout Voltage vs. Output Current,  
OUT = 2.5 V  
Figure 20. Output Voltage vs. Temperature,  
VOUT = 0.8 V  
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7
NCP702  
TYPICAL CHARACTERISTICS  
1.816  
1.812  
1.808  
1.804  
1.800  
1.796  
1.792  
3.317  
V
V
= 2.1 V  
IN  
V
V
I
= 3.8 V  
IN  
OUT  
3.313  
3.309  
3.305  
3.301  
3.297  
3.293  
= 1.8 V  
OUT  
= 3.3 V  
= 10 mA  
I
= 10 mA  
OUT  
OUT  
C
= C  
= 1 mF  
OUT  
OUT  
C
= C  
= 1 mF  
OUT  
OUT  
1.788  
3.289  
3.285  
1.784  
1.780  
−40 −20  
0
20  
40  
60  
80 100 120 140  
−40 −20  
0
20  
40  
60  
80 100 120 140  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 21. Output Voltage vs. Temperature,  
OUT = 1.8 V  
Figure 22. Output Voltage vs. Temperature,  
VOUT = 3.3 V  
V
10  
9
10  
9
V
V
= 2.0 V  
= 0.8 V  
= 0 mA … 200 mA  
V
V
= 2.1 V  
IN  
OUT  
IN  
= 1.8 V  
= 0 mA … 200 mA  
OUT  
8
8
I
I
OUT  
OUT  
7
7
C
= C  
= 1 mF  
C
= C = 1 mF  
OUT  
OUT  
OUT  
OUT  
6
6
5
5
4
4
3
3
2
2
1
0
1
0
−40 −20  
0
20  
40  
60  
80 100 120 140  
−40 −20  
0
20  
40  
60  
80 100 120 140  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 23. Load Regulation vs. Temperature,  
OUT = 0.8 V  
Figure 24. Load Regulation vs. Temperature,  
VOUT = 1.8 V  
V
10  
9
1000  
900  
800  
700  
600  
500  
400  
300  
200  
V
= 0.8 V  
= 10 mA  
OUT  
V
V
= 3.6 V  
= 3.3 V  
= 0 mA … 200 mA  
IN  
OUT  
I
OUT  
8
C
= C  
= 1 mF  
OUT  
OUT  
I
OUT  
7
C
= C  
= 1 mF  
OUT  
OUT  
6
5
V
= 2.0 V … 5.5 V  
= 2.0 V … 4.5 V  
IN  
4
3
V
IN  
2
1
0
100  
0
−40 −20  
0
20  
40  
60  
80 100 120 140  
−40 −20  
0
20  
40  
60  
80 100 120 140  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 25. Load Regulation vs. Temperature,  
OUT = 3.3 V  
Figure 26. Line Regulation vs. Temperature,  
VOUT = 0.8 V  
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8
NCP702  
TYPICAL CHARACTERISTICS  
1000  
900  
800  
700  
600  
500  
400  
300  
200  
1000  
V
= 1.8 V  
OUT  
900  
I
= 10 mA  
= C  
OUT  
800  
700  
600  
500  
400  
300  
200  
V
V
= 3.6 V … 5.5 V  
= 3.6 V … 4.5 V  
C
= 1 mF  
OUT  
IN  
OUT  
IN  
V
= 2.1 V … 5.5 V  
IN  
V
IN  
= 2.1 V … 4.5 V  
V
OUT  
= 3.3 V  
I
= 10 mA  
OUT  
100  
0
100  
0
C
= C  
= 1 mF  
OUT  
OUT  
−40 −20  
0
20  
40  
60  
80 100 120 140  
−40 −20  
0
20  
40  
60  
80 100 120 140  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 27. Line Regulation vs. Temperature,  
Figure 28. Line Regulation vs. Temperature,  
VOUT = 3.3 V  
V
OUT = 1.8 V  
0.50  
0.45  
0.40  
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0.50  
0.45  
0.40  
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
V
V
V
= 5.5 V  
V
V
V
= 5.5 V  
IN  
OUT  
IN  
OUT  
= 1.8 V  
= 0 V  
= 3.3 V  
= 0 V  
EN  
EN  
C
= C  
= 1 mF  
C
= C  
= 1 mF  
OUT  
OUT  
OUT  
OUT  
0
0
−0.05  
−0.05  
−40 −20  
0
20  
40  
60  
80 100 120 140  
−40 −20  
0
20  
40  
60  
80 100 120 140  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 29. Disable Current vs. Temperature,  
Figure 30. Disable Current vs. Temperature,  
VOUT = 3.3 V  
V
OUT = 1.8 V  
450  
430  
410  
390  
370  
350  
330  
310  
290  
270  
250  
0.50  
0.45  
0.40  
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
V
V
V
= 5.5 V  
IN  
OUT  
= 0.8 V  
= 0 V  
Output Short Circuit  
EN  
V
OUT  
= 0 V  
C
= C  
= 1 mF  
OUT  
OUT  
Output Current Limit  
V
OUT  
= V  
− 0.1 V  
OUT(nom)  
V
V
C
= V = 2 V  
EN  
IN  
= 0.8 V  
OUT(nom)  
= C  
= 1 mF  
0
IN  
OUT  
−0.05  
−40 −20  
0
20  
40  
60  
80 100 120 140  
−40 −20  
0
20  
40  
60  
80  
100 120 140  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 31. Disable Current vs. Temperature,  
OUT = 0.8 V  
Figure 32. Output Current Limit vs.  
Temperature, VOUT = 0.8 V  
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NCP702  
TYPICAL CHARACTERISTICS  
490  
470  
450  
430  
410  
390  
370  
350  
330  
310  
290  
1.0  
0.9  
V
V
I
= 3.3 V  
= 3.6 V  
= 10 mA  
OUT(nom)  
V
V
C
= V = 3.6 V  
EN  
IN  
IN  
= 3.3 V  
OUT(nom)  
Output Short Circuit  
= 0 V  
OUT  
= C  
= 1 mF  
IN  
OUT  
0.8  
0.7  
0.6  
0.5  
0.4  
V
OUT  
C
= C  
= 1 mF  
OUT  
OUT  
Output Current Limit  
V
= V  
− 0.1 V  
OUT  
OUT(nom)  
0.3  
0.2  
−40 −20  
0
20  
40  
60  
80  
100 120 140  
−40 −20  
0
20  
40  
60  
80 100 120 140  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 33. Output Current Limit vs.  
Temperature, VOUT = 3.3 V  
Figure 34. Enable Low Threshold Voltage  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
V
V
= 3.3 V  
= 3.6 V  
= 10 mA  
OUT(nom)  
IN  
V
V
C
C
= 3.6 V  
IN  
I
OUT  
= 3.3 V  
= 1 mF  
OUT(nom)  
C
= C  
= 1 mF  
OUT  
OUT  
OUT  
OUT  
= none  
= 1 mA  
= 25°C  
IN  
I
OUT  
T
A
I
I
= 60 mA  
INRUSH  
INRUSH  
EN  
0.3  
0.2  
−40 −20  
0
20  
40  
60  
80 100 120 140  
100 ms/div  
T , JUNCTION TEMPERATURE (°C)  
J
Figure 35. Enable High Threshold Voltage  
Figure 36. Enable Turn−On Response,  
OUT = 3.3 V, COUT = 1 mF  
V
V
V
C
C
= 3.6 V  
IN  
= 3.3 V  
= 3 mF  
OUT(nom)  
OUT  
V
V
C
C
= 2.0 V  
IN  
OUT  
= none  
IN  
= 0.8 V  
= 1 mF  
OUT(nom)  
I
T
= 1 mA  
= 25°C  
OUT  
OUT  
A
= none  
IN  
I
= 115 mA  
I
T
= 1 mA  
= 25°C  
INRUSH  
OUT  
I
INRUSH  
A
I
= 20 mA  
INRUSH  
EN  
100 ms/div  
100 ms/div  
Figure 37. Enable Turn−On Response,  
OUT = 3.3 V, COUT = 3 mF  
Figure 38. Enable Turn−On Response,  
VOUT = 0.8 V, COUT = 1 mF  
V
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10  
NCP702  
TYPICAL CHARACTERISTICS  
200  
V
IN  
= V  
+ 0.3 V or 2 V  
OUT  
whichever is greater  
= 0 V to 1 V  
160  
120  
80  
V
EN  
C
= none, T = 25°C  
IN  
J
V
V
= 2.0 V  
IN  
I
= 1 mA  
OUT  
= 0.8 V  
= 3 mF  
OUT(nom)  
C
C
I
OUT  
= none  
= 1 mA  
IN  
V
OUT  
= 3.3 V  
OUT  
T
A
= 25°C  
V
OUT  
= 0.8 V  
I
= 45 mA  
INRUSH  
40  
0
100 ms/div  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
C
, OUTPUT CAPACITANCE (mF)  
Figure 39. Enable Turn−On Response,  
OUT = 0.8 V, COUT = 3 mF  
OUT  
V
Figure 40. Turn−On Inrush Current vs. Output  
Capacitance  
Figure 41. Enable Turn−Off Response,  
OUT = 3.3 V, COUT = 1 mF  
Figure 42. Enable Turn−Off Response,  
VOUT = 3.3 V, COUT = 4.7 mF  
V
Figure 43. Enable Turn−Off Response,  
OUT = 3.3 V, COUT = 10 mF  
Figure 44. Slow Input Voltage  
Turn−On/Turn−Off, VOUT = 3.3 V  
V
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11  
 
NCP702  
TYPICAL CHARACTERISTICS  
Figure 45. Line Transient Response −  
Figure 46. Line Transient Response −  
Rising Edge, VOUT = 3.3 V  
Falling Edge, VOUT = 3.3 V  
Figure 47. Load Transient Response − Rising  
Edge, IOUT = 1 mA − 200 mA, VOUT = 0.8 V  
Figure 48. Load Transient Response − Falling  
Edge, IOUT = 1 mA − 200 mA, VOUT = 0.8 V  
Figure 49. Load Transient Response − Rising  
Edge, IOUT = 1 mA − 200 mA, COUT = 1.0 mF  
Figure 50. Load Transient Response − Falling  
Edge, IOUT = 1 mA − 200 mA, COUT = 1.0 mF  
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12  
NCP702  
TYPICAL CHARACTERISTICS  
Figure 51. Load Transient Response − Rising  
Edge, IOUT = 1 mA − 200 mA, COUT = 4.7 mF  
Figure 52. Load Transient Response − Falling  
Edge, IOUT = 1 mA − 200 mA, COUT = 4.7 mF  
Figure 53. Load Transient Response − Rising  
Edge, IOUT = 1 mA − 200 mA, COUT = 10 mF  
Figure 54. Load Transient Response − Falling  
Edge, IOUT = 1 mA − 200 mA, COUT = 10 mF  
Figure 55. Output Short Circuit Response  
Figure 56. Cycling between Output Short  
Circuit and Thermal Shutdown  
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13  
NCP702  
TYPICAL CHARACTERISTICS  
80  
70  
60  
50  
40  
30  
20  
10  
0
180  
T = 125°C  
J
T = 125°C  
J
T = 25°C  
J
160  
140  
120  
100  
80  
T = −40°C  
J
T = −40°C  
J
T = 25°C  
J
V
V
C
= 3.6 V  
IN  
V
V
C
= 3.6 V  
IN  
= 3.3 V  
= C = 1 mF  
OUT  
60  
= 3.3 V  
= C = 1 mF  
OUT  
IN  
OUT  
IN  
OUT  
40  
MLCC, X7R,  
1206 size  
MLCC, X7R,  
1206 size  
20  
0
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
0
20 40 60 80 100 120 140 160 180 200  
, OUTPUT CURRENT (mA)  
I
, OUTPUT CURRENT (mA)  
I
OUT  
OUT  
Figure 57. Ground Current vs. Output Current,  
OUT = 0 mA to 5 mA  
Figure 58. Ground Current vs. Output Current,  
IOUT = 0 mA to 200 mA  
I
0.12  
0.10  
0.08  
0.06  
0.04  
10  
1
Unstable Operation  
V
OUT  
= 0.8 V  
V
OUT  
= 3.3 V  
Stable Operation  
0.1  
V
V
= 5.5 V  
= 1.8 V  
= 10 mA  
IN  
OUT  
0.01  
I
OUT  
V
IN  
= V  
+ 0.3 V or 2 V  
OUT(nom)  
T = 25°C  
0.02  
0
J
C
= C = 1 mF  
OUT  
IN  
C
= C  
= 1 mF  
IN  
OUT  
T
A
= 25°C  
0.001  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
, ENABLE VOLTAGE (V)  
0
20 40 60 80 100 120 140 160 180 200  
, OUTPUT CURRENT (mA)  
V
EN  
I
OUT  
Figure 59. EN Pin Input Current vs. Enable Pin  
Voltage  
Figure 60. Output Capacitor ESR vs. Output  
Current  
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14  
NCP702  
APPLICATIONS INFORMATION  
General  
capacitor will limit the influence of input trace inductance  
The NCP702 is a high performance 200 mA Low Dropout  
Linear Regulator. This device delivers excellent noise and  
dynamic performance.  
and source resistance during sudden load current changes.  
Larger input capacitor may be necessary if fast and large  
load transients are encountered in the application.  
Thanks to its adaptive ground current feature the device  
consumes only 10 mA of quiescent current at no−load  
condition.  
Output Decoupling (COUT  
)
The NCP702 is designed to be stable with a small 1.0 mF  
ceramic capacitor on the output. To assure proper operation  
it is strongly recommended to use min. 1.0 mF capacitor with  
the initial tolerance of 10%, made of X7R or X5R dielectric  
material types.  
The regulator features ultra−low noise of 11 mV  
,
RMS  
PSRR of 68 dB at 1 kHz and very good load/line transient  
performance. Such excellent dynamic parameters and small  
package size make the device an ideal choice for powering  
the precision analog and noise sensitive circuitry in portable  
applications. The LDO achieves this ultra low noise level  
output without the need for a noise bypass capacitor.  
A logic EN input provides ON/OFF control of the output  
voltage. When the EN is low the device consumes as low as  
typ. 10 nA from the IN pin.  
There is no requirement for the minimum value of  
Equivalent Series Resistance (ESR) for the C  
but the  
OUT  
maximum value of ESR should be less than 700 mW.  
Larger output capacitors could be used to improve the load  
transient response or high frequency PSRR as shown in  
typical characteristics. The initial tolerance requirements  
can be wider than 10% when using capacitors larger than  
1 mF.  
The LDO achieves ultra−low output voltage noise without  
the need for additional noise bypass capacitor.  
It is not recommended to use tantalum capacitors on the  
output due to their large ESR. The equivalent series  
resistance of tantalum capacitors is also strongly dependent  
on the temperature, increasing at low temperature. The  
tantalum capacitors are generally more costly than ceramic  
capacitors.  
The device is fully protected in case of output overload,  
output short circuit condition and overheating, assuring a  
very robust design.  
Input Capacitor Selection (CIN)  
It is recommended to connect a minimum of 1 mF Ceramic  
X5R or X7R capacitor close to the IN pin of the device. This  
capacitor will provide a low impedance path for unwanted  
AC signals or noise modulated onto constant input voltage.  
There is no requirement for the min./max. ESR of the  
input capacitor but it is recommended to use ceramic  
capacitors for their low ESR and ESL. A good input  
The table on this page lists the capacitors which were used  
during the IC evaluation.  
No−load Operation  
The regulator remains stable and regulates the output  
voltage properly within the 2% tolerance limits even with  
no external load applied to the output.  
V
V
OUT  
IN  
OUT  
0 mA ... 200 mA  
2 V ... 5.5 V  
IN  
NCP702  
C2  
C1  
EN  
GND  
U1  
Figure 61. Typical Applications Schematics  
LIST OF CAPACITORS USED DURING THE NCP702 EVALUATION:  
Symbol  
Manufacturer  
Kemet  
Part Number  
C0402C105K8PACTU  
C1005X5R1A105K  
GRM155R61A105KE15D  
0402ZD105KAT2A  
MCCA000571  
Description  
1 mF Ceramic 10%, 10 V, 0402, X5R  
TDK  
−||−  
Murata  
−||−  
C1, C2  
AVX  
−||−  
Multicomp  
Panason − ECG  
1 mF Ceramic 10%, 50 V, 1206, X7R  
4.7 mF Ceramic 20%, 6.3 V, 0402, X5R  
ECJ−0EB0J475M  
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15  
NCP702  
APPLICATIONS INFORMATION  
Enable Operation  
the nominal V  
. If the Output Voltage is directly shorted  
= 0 V), the short circuit protection will  
OUT  
The NCP702 uses the EN pin to enable/disable its output  
and to deactivate/activate the active discharge function.  
If the EN pin voltage is <0.4 V the device is guaranteed to  
be disabled. The pass transistor is turned−off so that there is  
virtually no current flow between the IN and OUT. The  
active discharge transistor is active so that the output voltage  
to ground (V  
OUT  
limit the output current to 390 mA (typ). The current limit  
and short circuit protection will work properly up to V  
=
IN  
5.5 V at T = 25°C. There is no limitation for the short circuit  
A
duration.  
Thermal Shutdown  
When the die temperature exceeds the Thermal Shutdown  
V
OUT  
is pulled to GND through a 1 kW resistor. In the  
disable state the device consumes as low as typ. 10 nA from  
the V .  
threshold (T − 160°C typical), Thermal Shutdown event  
SD  
IN  
is detected and the device is disabled. The IC will remain in  
this state until the die temperature decreases below the  
If the EN pin voltage >0.9 V the device is guaranteed to  
be enabled. The NCP702 regulates the output voltage and  
the active discharge transistor is turned−off.  
Thermal Shutdown Reset threshold (T  
− 140°C typical).  
SDU  
Once the IC temperature falls below the 140°C the LDO is  
enabled again. The thermal shutdown feature provides  
protection from a catastrophic device failure due to  
accidental overheating. This protection is not intended to be  
used as a substitute for proper heat sinking.  
The EN pin has internal pull−down current source with  
typ. value of 110 nA which assures that the device is  
turned−off when the EN pin is not connected. A build in  
2 mV of hysteresis in the EN prevents from periodic on/off  
oscillations that can occur due to noise.  
In the case where the EN function isn’t required the EN  
pin should be tied directly to IN.  
Power Dissipation  
As power dissipated in the NCP702 increases, it might  
become necessary to provide some thermal relief. The  
maximum power dissipation supported by the device is  
dependent upon board design and layout. Mounting pad  
configuration on the PCB, the board material, and the  
ambient temperature affect the rate of junction temperature  
rise for the part. For reliable operation junction temperature  
should be limited to +125°C.  
Undervoltage Lockout  
The internal UVLO circuitry assures that the device  
becomes disabled when the V falls below typ. 1.5 V. When  
IN  
the V voltage ramps−up the NCP702 becomes enabled, if  
IN  
V
IN  
rises above typ. 1.6 V. The 100 mV hysteresis prevents  
on/off oscillations that can occur due to noise on V line.  
IN  
Reverse Current  
The PMOS pass transistor has an inherent body diode  
The maximum power dissipation the NCP702 can handle  
is given by:  
which will be forward biased in the case that V  
> V .  
ƪ
ƫ
OUT  
IN  
125 * TA  
(eq. 1)  
PD(MAX)  
+
Due to this fact in cases where the extended reverse current  
condition is anticipated the device may require additional  
external protection.  
qJA  
The power dissipated by the NCP702 for given  
application conditions can be calculated from the following  
equations:  
Output Current Limit  
Output Current is internally limited within the IC to a  
typical 380 mA. The NCP702 will source this amount of  
current measured with the output voltage 100 mV lower than  
ǒ
Ǔ
ǒV  
Ǔ
(eq. 2)  
P
D [ VIN IGND@IOUT ) IOUT IN * VOUT  
330  
310  
290  
0.65  
0.60  
0.55  
P
, T = 25°C, 2 OZ CU  
A
D(MAX)  
270  
250  
230  
210  
190  
0.50  
0.45  
0.40  
0.35  
0.30  
q
q
, 1 OZ CU  
, 2 OZ CU  
JA  
JA  
P
, T = 25°C, 1 OZ CU  
A
D(MAX)  
170  
150  
0.25  
0.20  
700  
0
100  
200  
300  
400  
500  
600  
2
PCB COPPER AREA (mm )  
Figure 62. qJA and PD(MAX) vs. Copper Area (TSOP5)  
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16  
 
NCP702  
400  
350  
300  
250  
200  
150  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
P
, T = 25°C, 2 OZ CU  
A
D(MAX)  
P
, T = 25°C, 1 OZ CU  
A
D(MAX)  
q
q
, 1 OZ CU  
, 2 OZ CU  
JA  
JA  
100  
50  
0.2  
0.1  
0
100  
200  
300  
400  
500  
600  
700  
800  
2
PCB COPPER AREA (mm )  
Figure 63. qJA and PD(MAX) vs. Copper Area (XDFN6)  
400  
Load Regulation  
V
= 3.3 V  
OUT  
The NCP702 features very good load regulation of  
maximum 2.6 mV in the 0 mA to 200 mA range. In order to  
achieve this very good load regulation a special attention to  
PCB design is necessary. The trace resistance from the OUT  
pin to the point of load can easily approach 100 mΩ which  
will cause a 20 mV voltage drop at full load current,  
deteriorating the excellent load regulation.  
360  
320  
280  
240  
200  
160  
120  
80  
V
= 0.8 V  
OUT  
V
OUT  
= 1.8 V  
V
IN  
= V  
+ 0.3 V or 2 V  
Line Regulation  
The IC features very good line regulation of 0.44 mV/V  
OUT  
I
= 10 mA  
OUT  
C
= C  
= 1 mF  
IN  
OUT  
measured from V = V  
operated applications it may be important that the line  
+ 0.3 V to 5.5 V. For battery  
IN  
OUT  
40  
V
EN  
= 0 V −> 0.9 V  
0
−40 −20  
0
20  
40  
60  
80  
100 120 140  
regulation from V = V  
+ 0.3 V up to 4.5 V is only  
IN  
OUT  
0.29 mV/V.  
T , JUNCTION TEMPERATURE (°C)  
J
Figure 64. Turn−On Time vs. Temperature  
Power Supply Rejection Ratio  
The NCP702 features very good Power Supply Rejection  
ratio. If desired the PSRR at higher frequencies in the range  
Internal Soft­Start  
The Internal Soft−Start circuitry will limit the inrush  
current during the LDO turn-on phase. Please refer to  
Figure 43 for typical inrush current values for given output  
capacitance.  
100 kHz – 10 MHz can be tuned by the selection of C  
capacitor and proper PCB layout.  
OUT  
Output Noise  
The soft−start function prevents from any output voltage  
overshoots and assures monotonic ramp-up of the output  
voltage.  
The IC is designed for ultra−low noise output voltage.  
Figures 3 – 8 illustrate the noise performance for different  
V
, I  
, C  
. Generally the noise performance in the  
OUT OUT OUT  
indicated frequency range improves with increasing output  
current, although even at I = 1 mA the noise levels are  
PCB Layout Recommendations  
To obtain good transient performance and good regulation  
OUT  
below 22 mV  
.
RMS  
characteristics place C and C  
capacitors close to the  
IN  
OUT  
device pins and make the PCB traces wide. In order to  
minimize the solution size use 0402 capacitors. Larger  
copper area connected to the pins will also improve the  
device thermal resistance. The actual power dissipation can  
be calculated by the formula given in Equation 2.  
Turn−On Time  
The turn−on time is defined as the time period from EN  
assertion to the point in which V will reach 98% of its  
OUT  
nominal value. This time is dependent on V  
,
OUT(NOM)  
C
OUT  
, T . The turn−on time temperature dependence is  
A
shown below:  
http://onsemi.com  
17  
NCP702  
ORDERING INFORMATION  
Device  
†
Voltage Option  
1.8 V  
Marking  
Package  
Shipping  
NCP702MX18TCG  
NCP702MX28TCG  
NCP702MX30TCG  
NCP702MX33TCG  
NCP702SN18T1G  
NCP702SN28T1G  
NCP702SN30T1G  
NCP702SN31T1G  
NCP702SN33T1G  
P
2
2.8 V  
XDFN6  
(Pb−Free)  
3000 / Tape & Reel  
3000 / Tape & Reel  
3.0 V  
3
3.3 V  
4
1.8 V  
A7J  
AD2  
A7R  
A7P  
A7T  
2.8 V  
TSOP5  
(Pb−Free)  
3.0 V  
3.1 V  
3.3 V  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
http://onsemi.com  
18  
NCP702  
PACKAGE DIMENSIONS  
XDFN6 1.5x1.5, 0.5P  
CASE 711AE  
ISSUE A  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. DIMENSION b APPLIES TO PLATED  
TERMINAL AND IS MEASURED BETWEEN  
0.10 AND 0.20mm FROM TERMINAL TIP.  
L
D
A
B
L1  
DETAIL A  
MILLIMETERS  
ALTERNATE TERMINAL  
CONSTRUCTIONS  
DIM  
A
MIN  
0.35  
0.00  
MAX  
0.45  
0.05  
E
PIN ONE  
REFERENCE  
A1  
A3  
b
0.13 REF  
EXPOSED Cu  
MOLD CMPD  
0.20  
0.30  
2X  
0.10  
C
1.50 BSC  
D
E
1.50 BSC  
0.50 BSC  
e
2X  
0.10  
C
L
0.40  
---  
0.60  
0.15  
0.70  
TOP VIEW  
L1  
L2  
DETAIL B  
0.50  
ALTERNATE  
A
DETAIL B  
CONSTRUCTIONS  
0.05  
0.05  
C
C
A3  
A1  
RECOMMENDED  
MOUNTING FOOTPRINT*  
5X  
0.73  
SEATING  
PLANE  
C
6X  
SIDE VIEW  
0.35  
DETAIL A  
1
e
5X  
L
1.80  
3
L2  
0.50  
PITCH  
0.83  
DIMENSIONS: MILLIMETERS  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
6
4
6X b  
0.10  
C
C
A
B
NOTE 3  
0.05  
BOTTOM VIEW  
http://onsemi.com  
19  
NCP702  
PACKAGE DIMENSIONS  
TSOP−5  
CASE 483−02  
ISSUE K  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ASME  
Y14.5M, 1994.  
NOTE 5  
5X  
D
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH  
THICKNESS. MINIMUM LEAD THICKNESS IS THE  
MINIMUM THICKNESS OF BASE MATERIAL.  
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD  
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD  
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT  
EXCEED 0.15 PER SIDE. DIMENSION A.  
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL  
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.  
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2  
FROM BODY.  
0.20 C A B  
2X  
0.10  
T
M
5
4
3
2X  
0.20  
T
B
S
1
2
K
B
A
DETAIL Z  
G
A
MILLIMETERS  
TOP VIEW  
DIM  
A
B
MIN  
3.00 BSC  
1.50 BSC  
MAX  
DETAIL Z  
C
D
0.90  
0.25  
1.10  
0.50  
J
G
H
J
K
M
0.95 BSC  
C
0.01  
0.10  
0.20  
0
0.10  
0.26  
0.60  
10  
3.00  
0.05  
H
SEATING  
PLANE  
END VIEW  
C
_
_
SIDE VIEW  
S
2.50  
SOLDERING FOOTPRINT*  
1.9  
0.074  
0.95  
0.037  
2.4  
0.094  
1.0  
0.039  
0.7  
0.028  
mm  
inches  
ǒ
Ǔ
SCALE 10:1  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,  
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC  
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any  
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without  
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications  
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC  
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for  
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where  
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and  
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,  
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture  
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81−3−5817−1050  
ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada  
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
NCP702/D  

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