NCP730BMT500TBG [ONSEMI]
LDO Regulator, 150 mA, 38V, 1 A IQ, with PG;
| 型号： | NCP730BMT500TBG |
| 厂家： | 
ONSEMI |
| 描述： | LDO Regulator, 150 mA, 38V, 1 A IQ, with PG |
| 文件： | 总30页 (文件大小：3625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LDO Regulator, 150 mA,
38ꢀV, 1 mA IQ, with PG
NCP730
The NCP730 device is based on unique combination of features −
very low quiescent current, fast transient response and high input and
output voltage ranges. The NCP730 is CMOS LDO regulator designed
for up to 38 V input voltage and 150 mA output current. Quiescent
current of only 1 mA makes this device ideal solution for battery−
powered, always−on systems. Several fixed output voltage versions
are available as well as the adjustable version.
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5
The device (version B) implements power good circuit (PG) which
indicates that output voltage is in regulation. This signal could be used
for power sequencing or as a microcontroller reset.
1
TSOP−5
CASE 483
WDFN6 (2x2)
CASE 511BR
Internal short circuit and over temperature protections saves the
device against overload conditions.
MARKING DIAGRAMS
5
Features
XX MG
• Operating Input Voltage Range: 2.7 V to 38 V
• Output Voltage: 1.2 V to 24 V
G
1
• Capable of Sourcing 200 mA Peak Output Current
• Low Shutdown Current: 100 nA typ.
XX= Specific Device
Code
M = Date Code
• Very Low Quiescent Current: 1 mA typ.
• Low Dropout: 290 mV typ. at 150 mA, 3.3 V Version
• Output Voltage Accuracy 1%
G
= Pb−Free Package
(Note: Microdot may be in either location)
1
• Power Good Output (Version B)
XX M
• Stable with Small 1 mF Ceramic Capacitors
• Built−in Soft Start Circuit to Suppress Inrush Current
• Over−Current and Thermal Shutdown Protections
• Available in Small TSOP−5 and WDFN6 (2x2) Packages
• These Devices are Pb−Free and are RoHS Compliant
XX = Specific Device Code
M
= Date Code
PIN ASSIGNMENTS
TSOP−5
Typical Applications
• Battery Power Tools and Equipment
• Home Automation
• RF Devices
IN
GND
EN
5
1
2
OUT
4
NC/ADJ/PG
3
• Metering
CASE 483
• Remote Control Devices
• White Goods
WDFN6 (2x2)
6
5
4
IN
OUT
1
2
3
EP
NC/ADJ
GND
NC/PG
EN
CASE511BR
(Top Views)
ORDERING INFORMATION
See detailed ordering and shipping information on page 27 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
March, 2020 − Rev. 0
NCP730/D
NCP730
TYPICAL APPLICATION SCHEMATICS
VOUT=5V
VIN=6−38V
VOUT=5.0V
VIN=6−38V
IN
OUT
NCP730AADJ
TSOP−5 / WDFN−6
EN
IN
OUT
NCP730A 5.0V
TSOP−5 / WDFN−6
EN NC
COUT
1mF
CIN
1mF
COUT
1mF
CIN
R1
CFF
1nF
1mF
2M4
ON
OFF
ON
OFF
1.2V
ADJ
GND
GND
R2
750k
Figure 1. Fixed Output Voltage Application (No PG)
Figure 2. Adjustable Output Voltage Application (No PG)
VIN=6−38V
VOUT=5V
VIN=6−38V
VOUT=5.0V
IN
IN
OUT
OUT
CIN
1mF
COUT
1mF
COUT
1mF
CIN
1mF
R1
CFF
1nF
NCP730B ADJ
Only WDFN−6
ADJ
NCP730B 5.0V
TSOP−5 / WDFN−6
2M4
RPG
100k
1.2V
NC
RPG
100k
ON
OFF
ON
OFF
EN
EN
PG
PG
PG
R2
750k
GND
GND
PG
Figure 3. Fixed Output Voltage Application with PG
Figure 4. Adjustable Output Voltage Application with PG
R1
R2
ǒ Ǔ
V
OUT + VADJ @ 1 )
) IADJ @ R1
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NCP730
SIMPLIFIED BLOCK DIAGRAMS
IN
OUT
UVLO Comparator
UVLO
1.95 V
V
V
REF
1.2V
CCEN
V−REFERENCE
EA
AND SOFT−START
R
R
ADJ1
ADJ2
V
=1.2V
FB
EN
ADJ
Enable
EN Comparator
GND
THERMAL
SHUTDOWN
0.9 V
PG
NC
PG Comparator
DEGLITCH
DELAY TMR
93% of V
REF
Blue objects are valid for ADJ version
Green objects are valid for FIX version
Brown objects are valid for B version (with PG)
Note:
Figure 5. Internal Block Diagram
PIN DESCRIPTION
Pin No. TSOP−5 Pin No. WDFN−6
Pin Name
Description
1
2
5
3
6
3
1
4
IN
Power supply input pin.
Ground pin.
GND
OUT
EN
LDO output pin.
Enable input pin (high − enabled, low − disabled). If this pin is connected to IN pin
or if it is left unconnected (pull−up resistor is not required) the device is enabled.
4 (Note 1)
4 (Note 1)
2
5
ADJ
PG
Adjust input pin, could be connected to the resistor divider to the OUT pin.
Power good output pin. Could be left unconnected or could be connected to GND
if not needed. High level for power ok, low level for fail.
4 (Note 1)
2, 5
NC
Not internally connected. This pin can be tied to the ground plane to improve
thermal dissipation.
NA
EP
EPAD
Connect the exposed pad to GND.
1. Pin function depends on device version.
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3
NCP730
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
VIN Voltage (Note 2)
VOUT Voltage
EN Voltage
V
IN
−0.3 to 40
V
−0.3 to [(V + 0.3) or 40 V; whichever is lower]
V
OUT
IN
V
−0.3 to (V + 0.3)
V
EN
IN
ADJ Voltage
V
−0.3 to 5.5
V
FB/ADJ
PG Voltage
V
PG
−0.3 to (V + 0.3)
V
IN
Output Current
PG Current
I
Internally limited
mA
mA
°C
°C
V
OUT
I
3
150
PG
Maximum Junction Temperature
T
J(MAX)
Storage Temperature
T
−55 to 150
2000
STG
ESD Capability, Human Body Model (Note 3)
ESD Capability, Charged Device Model (Note 3)
ESD
ESD
HBM
CDM
1000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001, EIA/JESD22−A114 (AEC−Q100−002)
ESD Charged Device Model tested per ANSI/ESDA/JEDEC JS−002, EIA/JESD22−C101 (AEC Q100−011D)
THERMAL CHARACTERISTICS (Note 4)
Characteristic
Thermal Resistance, Junction−to−Air
Symbol
WDFN6 2x2
TSOP−5
142
80
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
R
61
200
14
46
3
thJA
thJCt
thJCb
Thermal Resistance, Junction−to−Case (top)
R
Thermal Resistance, Junction−to−Case (bottom)
Thermal Resistance, Junction−to−Board (top)
R
N/A
110
R
thJBt
Thermal Characterization Parameter, Junction−to−Case (top)
Thermal Characterization Parameter, Junction−to−Board [FEM]
Psi
21
JCt
Psi
46
113
JB
2
4. Measured according to JEDEC board specification (board 1S2P, Cu layer thickness 1 oz, Cu area 650 mm , no airflow). Detailed description
of the board can be found in JESD51−7.
ELECTRICAL CHARACTERISTICS (V = V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C = C = 1.0 mF
OUT
IN
OUT−NOM
IN
EN
OUT
IN
(effective capacitance – Note 5), T = −40°C to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 6)
J
Parameter
Recommended Input Voltage
Output Voltage Accuracy
Test Conditions
Symbol
Min
2.7
−1
−1
−
Typ
Max
38
Unit
V
V
IN
−
−
T = −40°C to +85°C
V
OUT
1
%
J
T = −40°C to +125°C
−
2
J
ADJ Reference Voltage
ADJ Input Current
ADJ version only
V
ADJ
1.2
0.01
−
−
V
V
ADJ
= 1.2 V
I
−0.1
−
0.1
0.2
0.4
2.5
3.0
450
1.5
450
450
480
−
mA
ADJ
Line Regulation
V
IN
= V
+ 1 V to 38 V and V ≥ 2.7 V DV
%V
OUT−NOM
IN
O(DVI)
OUT
OUT
Load Regulation
I
= 0.1 mA to 150 mA
DV
−
−
%V
OUT
O(DIO)
Quiescent Current (version A)
Quiescent Current (version B)
Ground Current
V
IN
V
IN
= V
+ 1 V to 38 V, I
= 0 mA
= 0 mA
I
Q
−
1.3
1.8
325
0.35
280
280
290
80
mA
OUT−NOM
OUT−NOM
OUT
= V
+ 1 V to 38 V, I
−
OUT
I
= 150 mA
I
−
mA
mA
OUT
GND
Shutdown Current (Note 10)
Output Current Limit
V
V
V
= 0 V, I
= 0 mA, V = 38 V
I
SHDN
−
EN
OUT
IN
= V
− 100 mV
I
OLIM
200
200
−
mA
mA
mV
dB
OUT
OUT
OUT−NOM
Short Circuit Current
= 0 V
= 150 mA
I
OSC
Dropout Voltage (Note 7)
Power Supply Ripple Rejection
I
V
DO
OUT
V
= V
= 10 mA
+ 2 V
10 Hz
10 kHz
PSRR
−
IN
OUT−NOM
I
OUT
−
70
−
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NCP730
ELECTRICAL CHARACTERISTICS (V = V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C = C = 1.0 mF
OUT
IN
OUT−NOM
IN
EN
OUT
IN
(effective capacitance – Note 5), T = −40°C to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 6) (continued)
J
Parameter
Test Conditions
+ 2 V
OUT−NOM
Symbol
Min
−
Typ
42
Max
−
Unit
Power Supply Ripple Rejection
V
OUT
= V
100 kHz
1 MHz
PSRR
dB
IN
I
= 10 mA
−
48
−
Output Noise
f = 10 Hz to 100 kHz
V
N
−
100*
OUT
−
mV
RMS
V
EN Threshold
V
V
V
V
V
V
rising
falling
V
V
0.7
0.01
0.01
−1
0.9
0.1
0.3
0.05
250
600
1.95
0.2
93
1.05
0.2
1
V
V
EN
EN−TH
EN−HY
EN−PU
EN Hysteresis
EN
EN Internal Pull−up Current
EN Input Leakage Current
Start−up time (Note 8)
= 1 V, V = 5.5 V
I
mA
mA
ms
EN
IN
= 30 V, V = 30 V
I
t
1
EN
IN
EN−LK
≤ 3.3 V
100
300
1.6
0.05
90
500
1000
2.6
0.3
96
OUT−NOM
OUT−NOM
START
> 3.3 V
Internal UVLO Threshold
Ramp V up until output is turned on
V
V
V
V
IN
IUL−TH
Internal UVLO Hysteresis
Ramp V down until output is turned off
IN
IUL−HY
PG Threshold (Note 9)
V
OUT
V
OUT
falling
rising
V
%
%
ms
ms
V
PG−TH
PG−HY
PG−DG
PG Hysteresis (Note 9)
V
0.1
75
2
3.5
270
600
0.4
1
PG Deglitch Time (Note 9)
PG Delay Time (Note 9)
t
160
320
0.2
0.01
165
20
t
120
−
PG−DLY
PG Output Low Level Voltage (Note 9)
PG Output Leakage Current (Note 9)
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
I
= 1 mA
V
PG
PG−OL
V
PG
= 30 V
I
−
mA
°C
°C
PG−LK
Temperature rising from T = +25°C
T
SD
−
−
J
Temperature falling from T
T
−
−
SD
SDH
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Effective capacitance, including the effect of DC bias, tolerance and temperature. See the Application Information section for more
information.
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T = 25°C.
A
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
7. Dropout measured when the output voltage falls 100 mV below the nominal output voltage. Limits are valid for all voltage versions.
8. Startup time is the time from EN assertion to point when output voltage is equal to 95% of V
.
OUT−NOM
9. Applicable only to version B (device option with power good output). PG threshold and PG hysteresis are expressed in percentage of nominal
output voltage.
10.Shutdown current includes EN Internal Pull−up Current.
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NCP730
TYPICAL CHARACTERISTICS
V
IN
= V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C
= 1.0 mF, ADJ tied to OUT, T = 25°C, unless otherwise specified
OUT−NOM
IN
EN
OUT
OUT
J
2.0%
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
2.5
High limit
2.3
V
IN = (VOUT-NOM + 1 V) to 38 V, VIN ≥ 2.7 V
High limit
IOUT = 1 to 150 mA
Version-B
(with PG)
2.1
VOUT-NOM = 5 V
VOUT-NOM = 15 V
1.9
1.7
1.5
1.3
1.1
Version-A
(non PG)
VOUT-NOM = 1.2 V
Low limit
VIN = 38 V
-1.5%
-2.0%
0.9
0.7
IOUT = 0 mA
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE, T ( C)
°
JUNCTION TEMPERATURE, T ( C)
°
J
J
Figure 6. Output Voltage vs. Temperature
Figure 7. Quiescent Current vs. Temperature
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
High limit
High limit
Note:
Shutdown current is measured at IN pin
and includes EN pin pull-up current.
Low limit
V
IN = 38 V
VEN = 0 V
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE, TJ ( C)
°
JUNCTION TEMPERATURE, T ( C)
°
J
Figure 8. Shutdown Current vs. Temperature
Figure 9. Enable Threshold Voltage vs.
Temperature
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.10
0.08
0.06
0.04
High limit
High limit
0.02
0.00
VEN = 1 V
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE ( C)
°
TEMPERATURE (°C)
Figure 10. Enable Internal Pull−Up Current vs.
Figure 11. ADJ Input Current vs. Temperature
Temperature
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NCP730
TYPICAL CHARACTERISTICS
V
IN
= V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C
= 1.0 mF, ADJ tied to OUT, T = 25°C, unless otherwise specified
OUT−NOM
IN
EN
OUT
OUT
J
500
High limit
450
400
350
300
250
200
150
100
50
V
OUT = VOUT-NOM - 100 mV
IOUT = 150 mA
All output voltage versions
0
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE, T ( C)
°
J
Figure 12. Dropout Voltage vs. Temperature
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NCP730
TYPICAL CHARACTERISTICS
V
IN
= V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C = 1.0 mF, ADJ tied to OUT, T = 25°C, unless otherwise specified
OUT J
OUT−NOM
IN
EN
OUT
4.3V
1mA
VIN
VIN
8.3V
1mA
150mA
150mA
IOUT
IOUT
+55mV
+58mV
VOUT
3.3V
VOUT
3.3V
-115mV
-120mV
C1: V
C2: VOUT (ac)
C4: IOUT
1.0V/div
50mV/div
100mA/div
20.0ms/div
C1: V
C2: VOUT (ac)
C4: IOUT
2.0V/div
50mV/div
100mA/div
20.0ms/div
IN
IN
Figure 13. Load Transient − NCP730−3.3 V,
OUT = 1 mF
Figure 14. Load Transient − NCP730−3.3 V,
COUT = 1 mF
C
VIN
38.0V
1mA
3.3V
VIN
4.3V
1mA
150mA
150mA
IOUT
IOUT
+58mV
+37mV
VOUT
3.3V
VOUT
-60mV
-120mV
C1: V
C2: VOUT (ac)
C4: IOUT
10.0V/div
50mV/div
100mA/div
20.0ms/div
C1: V
C2: VOUT (ac)
C4: IOUT
1.0V/div
50mV/div
100mA/div
50.0ms/div
IN
IN
Figure 15. Load Transient − NCP730−3.3 V,
OUT = 1 mF
Figure 16. Load Transient − NCP730−3.3 V,
COUT = 10 mF
C
VIN
4.3V
1mA
150mA
VIN
6.0V
150mA
IOUT
1mA
5.0V
IOUT
+55mV
+30mV
VOUT
3.3V
VOUT
-50mV
-115mV
C1: V
C2: VOUT (ac)
C4: IOUT
1.0V/div
50mV/div
100mA/div
50.0ms/div
C1: V
C2: VOUT (ac)
C4: IOUT
5.0V/div
50mV/div
100mA/div
20.0ms/div
IN
IN
Figure 17. Load Transient − NCP730−3.3 V,
OUT = 22 mF
Figure 18. Load Transient − NCP730−5.0 V,
COUT = 1 mF
C
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NCP730
TYPICAL CHARACTERISTICS
V
IN
= V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C = 1.0 mF, ADJ tied to OUT, T = 25°C, unless otherwise specified
OUT J
OUT−NOM
IN
EN
OUT
VIN
38.0V
VIN
6.0V
150mA
150mA
1mA
5.0V
IOUT
1mA
5.0V
IOUT
+48mV
+36mV
VOUT
VOUT
-60mV
-112mV
C1: V
C2: VOUT (ac)
C4: IOUT
10.0V/div
50mV/div
100mA/div
20.0ms/div
C1: V
C2: VOUT (ac)
C4: IOUT
5.0V/div
50mV/div
100mA/div
50.0ms/div
IN
IN
Figure 19. Load Transient − NCP730−5.0 V,
Figure 20. Load Transient − NCP730−5.0 V,
COUT = 10 mF
C
OUT = 1 mF
VIN
15.5V
VIN
6.0V
150mA
150mA
1mA
IOUT
1mA
5.0V
IOUT
+34mV
+55mV
VOUT
15.0V
VOUT
-53mV
-120mV
C1: V
C2: VOUT (ac)
C4: IOUT
5.0V/div
50mV/div
100mA/div
50.0ms/div
C1: V
C2: VOUT (ac)
C4: IOUT
10.0V/div
100mV/div
100mA/div
20.0ms/div
IN
IN
Figure 21. Load Transient − NCP730−5.0 V,
COUT = 22 mF
Figure 22. Load Transient − NCP730−15.0 V,
COUT = 1 mF
VIN
38.0V
VIN
15.5V
150mA
150mA
1mA
IOUT
1mA
IOUT
+40mV
+50mV
VOUT
15.0V
15.0V
VOUT
-110mV
-105mV
C1: V
C2: VOUT (ac)
C4: IOUT
10.0V/div
100mV/div
100mA/div
20.0ms/div
C1: V
C2: VOUT (ac)
C4: IOUT
10.0V/div
50mV/div
100mA/div
50.0ms/div
IN
IN
Figure 23. Load Transient − NCP730−15.0 V,
COUT = 1 mF
Figure 24. Load Transient − NCP730−15.0 V,
COUT = 10 mF
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NCP730
TYPICAL CHARACTERISTICS
V
IN
= V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C = 1.0 mF, ADJ tied to OUT, T = 25°C, unless otherwise specified
OUT J
OUT−NOM
IN
EN
OUT
VIN
VIN
15.5V
15.5V
150mA
150mA
1mA
IOUT
1mA
IOUT
+45mV
+16mV
VOUT
15.0V
15.0V
VOUT
-98mV
-44mV
C1: V
C2: VOUT (ac)
C4: IOUT
10.0V/div
50mV/div
100mA/div
50.0ms/div
C1: V
C2: VOUT (ac)
C4: IOUT
10.0V/div
20mV/div
100mA/div
100.0ms/div
IN
IN
Figure 25. Load Transient − NCP730−15.0 V,
OUT = 22 mF
Figure 26. Load Transient − NCP730−15.0 V,
COUT = 50 mF
C
Figure 27. PSRR − NCP730−3.3 V, COUT = 1 mF,
Figure 28. PSRR − NCP730−3.3 V, COUT = 1 mF,
IOUT = 10 mA
IOUT = 100 mA
Figure 29. PSRR − NCP730−3.3 V, VIN = 4.3 V,
Figure 30. PSRR − NCP730−3.3 V, VIN = 8.3 V,
IOUT = 100 mA
IOUT = 100 mA
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NCP730
TYPICAL CHARACTERISTICS
V
IN
= V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C = 1.0 mF, ADJ tied to OUT, T = 25°C, unless otherwise specified
OUT J
OUT−NOM
IN
EN
OUT
Vi=6V
Vi=12V
Vi=36V
Io=1mA
Io=10mA Io=150mA
Rms Noise Value (10Hz - 100kHz)
Rms Noise Value (10Hz - 1MHz)
229.1
229.5
230.6
231.1
225.2
225.7
mVrms
mVrms
Rms Noise Value (10Hz - 100kHz)
Rms Noise Value (10Hz - 1MHz)
230.6
231.1
240.2
251.9
226.3
272.7
mVrms
mVrms
mVrms/V
mVrms/V
Rms Noise Value (10Hz - 100kHz)
45.8
45.9
46.1
46.2
45.0
45.1
Rms Noise Value (10Hz - 100kHz)
Rms Noise Value (10Hz - 1MHz)
46.1
46.2
48.0
50.4
45.3
54.5
mVrms/V
mVrms/V
Rms Noise Value (10Hz - 1MHz)
Figure 31. Noise – FIX − 5.0 V, IOUT = 1 mA,
Figure 32. Noise – FIX − 5.0 V, COUT = 1 mF,
C
OUT = 1 mF, Different VIN
Different IOUT
Io=1mA
Io=10mA Io=150mA
Io=1mA
Io=10mA Io=25mA Io=50mA Io=150mA
Rms Noise Value (10Hz - 100kHz)
Rms Noise Value (10Hz - 1MHz)
219.8
219.9
239.5
239.8
259.1
263.9
mVrms
mVrms
Rms Noise Value (10Hz - 100kHz)
Rms Noise Value (10Hz - 1MHz)
189.2
189.3
222.2
222.4
229.0
229.2
235.1
235.3
240.7
241.0
mVrms
mVrms
mVrms/V
mVrms/V
Rms Noise Value (10Hz - 100kHz)
44.0
44.0
47.9
48.0
51.8
52.8
Rms Noise Value (10Hz - 1MHz)
Rms Noise Value (10Hz - 100kHz)
Rms Noise Value (10Hz - 1MHz)
37.8
37.9
44.4
44.5
45.8
45.8
47.0
47.1
48.1
48.2
mVrms/V
mVrms/V
Figure 33. Noise – FIX − 5.0 V,
OUT = 1 mF + 10 mF, Different IOUT
Figure 34. Noise – FIX − 5.0 V,
COUT = 1 mF + 50 mF, Different IOUT
C
Co=1u
Co=1u+10u Co=1u+50u
Co=1u Co=1u+10u Co=1u+50u
Rms Noise Value (10Hz - 100kHz)
Rms Noise Value (10Hz - 1MHz)
240.2
251.9
239.5
239.8
222.2
222.4
Rms Noise Value (10Hz - 100kHz)
Rms Noise Value (10Hz - 1MHz)
226.3
272.7
259.1
263.9
240.7
241.0
mVrms
mVrms
mVrms
mVrms
mVrms/V
mVrms/V
Rms Noise Value (10Hz - 100kHz)
48.0
50.4
47.9
48.0
44.4
44.5
mVrms/V
mVrms/V
Rms Noise Value (10Hz - 100kHz)
45.3
54.5
51.8
52.8
48.1
48.2
Rms Noise Value (10Hz - 1MHz)
Rms Noise Value (10Hz - 1MHz)
Figure 35. Noise – FIX − 5.0 V, IOUT = 10 mA,
Figure 36. Noise – FIX − 5.0 V, IOUT = 150 mA,
Different COUT
Different COUT
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11
NCP730
TYPICAL CHARACTERISTICS
V
IN
= V
+ 1 V and V ≥ 2.7 V, V = 1.2 V, I
= 1 mA, C = 1.0 mF, ADJ tied to OUT, T = 25°C, unless otherwise specified
OUT J
OUT−NOM
IN
EN
OUT
NCP730ASNADJ-5V
BMT500
ASN330
BMT500 BMT1500
Cff=10p
Cff=100p
Cff=1nF
Cff=10nF
Cff=NA
mVrms
mVrms
Rms Noise Value (10Hz - 100kHz)
Rms Noise Value (10Hz - 1MHz)
203.0
214.2
240.2
251.9
457.0
463.9
mVrms
mVrms
Rms Noise Value (10Hz
-
-
100kHz)
1MHz)
199.3
208.9
132.3
150.9
99.0
80.5
240.2
251.9
Rms Noise Value (10Hz
124.9
111.2
Rms Noise Value (10Hz
-
-
100kHz)
1MHz)
39.9
41.8
26.5
30.2
19.8
25.0
16.1
22.2
48.0
50.4
mVrms/V
mVrms/V
Rms Noise Value (10Hz - 100kHz)
61.5
64.9
48.0
50.4
30.5
30.9
mVrms/V
mVrms/V
Rms Noise Value (10Hz
Rms Noise Value (10Hz - 1MHz)
Figure 37. Noise – ADJ−set−5.0 V with
Different CFF and FIX − 5.0 V
Figure 38. Noise – FIX, IOUT = 10 mA,
OUT = 1 mF, Different VOUT
C
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12
NCP730
APPLICATIONS INFORMATION
Input Capacitor Selection (CIN)
divider for adjustment. When it is connected to the OUT pin
the output voltage of the circuit is simply the same as the
nominal output voltage of the LDO. At this case, without
ADJ resistor divider, the LDO should be loaded by at least
200 nA (by the application or added pre−load resistor).
When connected to the resistor divider the output voltage
could be computed as the ADJ reference voltage (1.2 V)
multiplied by the resistors divider ratio, see following
equation.
Input capacitor connected as close as possible is necessary
to ensure device stability. The X7R or X5R capacitor should
be used for reliable performance over temperature range. The
value of the input capacitor should be 1 mF or greater (max.
value is not limited). This capacitor will provide a low
impedance path for unwanted AC signals or noise modulated
onto the input voltage. There is no requirement for the ESR
of the input capacitor but it is recommended to use ceramic
capacitor for its low ESR and ESL. A good input capacitor
will limit the influence of input trace inductance and source
resistance during load current changes. When a large load
transients (like 1 mA to 150 mA) happens in the application
the input power source of the LDO needs to provide enough
power and the input voltage must not go below the level
R1
R2
(eq. 1)
ǒ Ǔ
V
OUT + VADJ @ 1 )
) IADJ @ R1
Where:
V
V
ADJ
is output voltage of the circuit with resistor divider.
is the LDO’s ADJ reference voltage.
OUT
defined by this equation: V = V
+ V
I
is the LDO’s ADJ pin input current.
IN
OUT−NOM
DO
ADJ
otherwise the output voltage drop will be significantly
higher (because LDO will enter the dropout state). In some
cases when power supply powering the LDO has a poor load
transient response or when there is a long connection
between LDO and its power source then capacitance of input
capacitor needs to be high enough to cover the LDO’s input
voltage drop caused by load transient and maintains its value
R and R are resistors of output resistor divider.
1
2
At the classical “old style” regulators like LM317 etc. the
resistors where small (100 W − 10 kW) to make regulator
stable at light loads (divider was also a pre−load function).
On NCP730, which is very low quiescent current LDO
regulator (1 mA), we need to care about current consumption
of surrounding circuitry so we need to set the current through
above the V = V
+ V level (then C could be
IN
OUT−NOM
DO IN
resistor divider flowing from V
GND, as low as possible.
through R and R to
OUT
1 2
in range of hundreds of mF).
On the other hand, the parasitic leakage current flowing
into ADJ pin (I ) causes V voltage error (given by
Output Capacitor Selection (COUT
)
ADJ
OUT
The LDO requires the output capacitor connected as close
as possible to the output and ground pins. The LDO is
designed to remain stable with output capacitor’s effective
capacitance in range from 1 mF to 100 mF and ESR from
1 mW to 200 mW. The ceramic X7R or X5R type is
recommended due to its low capacitance variations over the
specified temperature range and low ESR. When selecting
the output capacitor the changes with temperature and DC
bias voltage needs to be taken into account. Especially for
small package size capacitors such as 0402 or smaller the
effective capacitance drops rapidly with the applied DC bias
voltage (refer the capacitor’s datasheet for details). Larger
capacitance and lower ESR improves the load transient
response and PSRR.
I
⋅ R ). The I
is temperature dependent so it is
ADJ
1
ADJ
changing and we cannot compensate it in application, we
just can minimize the influence by setting of R value low,
1
what is in opposite to maximizing its value because of
current consumption.
So when selecting the R and R values we need to find a
1
2
compromise between desired V
error (temperature
OUT
dependent) and total circuit quiescent current.
If we want to simplify this task, we can say the I should
R2
be 100−times higher than I
at expected T temperature
ADJ
J
range. If we chose the ratio “I to I ” higher (for example
R2
ADJ
more than 100 as stated before), the ΔV
ADJ
error caused by
change over temperature would be lower and opposite,
OUT
I
if the ratio “I to I ” is smaller, the error would be bigger.
R2
ADJ
In limited T temperature range −40°C to +85°C the I
Output Voltage
J
ADJ
is about 10−times smaller than in the full temperature range
NCP730 is available in two version from output voltage
point of view. One is fixed output voltage version (FIX
version) and the other one is adjustable output voltage
version (ADJ version).
−40°C to +125°C (see typical characteristics graph of I
ADJ
over temperatures), so we can use bigger R , R values, as
1
2
could be seen at next examples.
The ADJ version has ADJ pin, which could be connected
to the OUT pin directly, just to compensate voltage drop
across the internal bond wiring and PCB traces or could be
connected to the middle point of the output voltage resistor
Example 1:
Desired V
voltage is 5.0 V. Computed maximal T in
J
OUT
application (based on max. power dissipation and cooling)
is 85°C. Than I at 85°C is about: I = 10 nA.
ADJ
ADJ85
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13
NCP730
VOUT =5V
VOUT =5V
OUT
OUT
R
1
R
1
3.76 MW
376 kW
NCP730A ADJ
NCP730A ADJ
C
OUT
C
OUT
IR1
1.01uA
IR1
10.1uA
IADJ
10nA
IADJ
100nA
1mF
1mF
VOUT
5V
VOUT
5V
ADJ
ADJ
GND
GND
IR2
IR2
1uA
10uA
VR2=VADJ
1.2V
VR2=VADJ
1.2V
R
2
R
2
1.2 MW
120kW
Figure 39. ADJ Output Voltage Schematic − Example 1
Figure 40. ADJ Output Voltage Schematic − Example 2
We chose:
We chose:
I
R2 + 100 @ IADJ85 + 100 @ 10E−9 + 1 mA
I
R2 + 100 @ IADJ125 + 100 @ 100E−9 + 10 mA
Then:
Then:
VR2
IR2
VR2
IR2
1.2
1.2
R2 +
+
+
+ 1.2 MW
R2 +
+
+
+ 120 kW
1E−6
10E−6
V
OUT * VR2
VR1
IR1
V
OUT * VR2
VR1
IR1
5 * 1.2
5 * 1.2
100E−9 ) 10E−6
R1 +
+
R1 +
+
I
ADJ85 ) IR2
10E−9 ) 1E−6
I
ADJ125 ) IR2
3.8
1.01E−6
3.8
10.1E−6
+
+ 3.762 MW
+
+ 376.2 kW
Verification:
Verification:
For low temperature (T = 25°C) the I
= 1 nA:
For low temperature (T = 25°C) the I
= 1 nA:
J
ADJ25
J
ADJ25
R1
R2
RADJ1
RADJ2
ǒ Ǔ
V
OUT + VADJ @ 1 )
) IADJ @ R1
@ ǒ1 ) Ǔ) I
V
OUT + VADJ
ADJ @ RADJ1
3.762E6
376.2E3
ǒ
1.2E6 Ǔ) 1E−9 @ 3.762E6
V
OUT + 1.2 @ 1 )
ǒ
120E3 Ǔ) 1E−9 @ 376.2E3
V
OUT + 1.2 @ 1 )
+ 4.966 V
+ 4.962 V
For maximal temperature (T = 85°C) the I
= 10 nA:
J
ADJ85
For maximal temperature (T = 125°C) the I
= 100 nA:
J
ADJ125
3.762E6
376.2E3
ǒ
1.2E6 Ǔ) 10E−9 @ 3.762E6
V
OUT + 1.2 @ 1 )
ǒ
120E3 Ǔ) 100E−9 @ 376.2E3
V
OUT + 1.2 @ 1 )
+ 5.000 V
+ 5.000 V
Output voltage error for temperatures 85°C to 25°C is:
Output voltage error for temperatures 125°C to 25°C is:
V
OUT85 * V
V
OUT125 * V
OUT25 @ 100
DVOUT
+
OUT25 @ 100
DVOUT
+
VOUT85
VOUT125
5.000 * 4.966
5.000 * 4.962
+
@ 100 + 0.68%
+
@ 100 + 0.76%
5.000
5.000
Total circuit quiescent current at T = 25°C is:
J
Total circuit quiescent current at T = 25°C is:
J
I
Q(TOT) + IQ(LDO) ) IR1 + 1.3E−6 ) 1.01E−6 + 2.31 mA
I
Q(TOT) + IQ(LDO) ) IR1 + 1.3E−6 ) 10.1E−6 + 11.4 mA!!!
We can see that current consumption of external resistor
divider is almost the same as quiescent current of LDO.
We can see that error of V
in example 1 (because we have used the same “I to I
voltage is almost the same as
OUT
”
R2
ADJ
Example 2:
Desired V
ratio = 100x) but the application quiescent current is almost
10−times higher (because of 10−times higher divider
current).
voltage is 5.0 V. Computed maximal T in
J
OUT
application (based on max. power dissipation and cooling)
is in this case higher, 125°C, to show the difference. Than
CFF Capacitor
maximal I
at 125°C is I
= 100 nA (based on
ADJ
ADJ125
Even the NCP730 is very low quiescent current device,
both the load transients over/under shoots and settling times
are excellent. See the Typical characteristics graphs.
Electrical characteristics table).
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14
NCP730
At adjustable application, the external resistor divider
with input ADJ pin capacity and ADJ pin PCB trace capacity
to GND makes a low pass filter what negatively affects the
dynamic behavior of the LDO. On the next picture is shown
how this unwanted side effect could be compensated by
adding of feed−forward capacitor C across R resistor.
FF
1
VOUT=5V
OUT
C
OUT
R
1
C
FF
1mF
NCP730A ADJ
2M4
1nF
1.2V
ADJ
GND
R
2
750k
Figure 44. PSRR – Different CFF
Figure 41. ADJ Output Voltage Schematic − CFF
Capacitor
The value of the C depends on R and R resistor values.
FF
1
2
When R , R values are in hundreds of kiloohms, proposed
1
2
C
FF
value is 1 nF, as shown on picture above, for the best
dynamic performance. Generally, the value could be in
range from 0 to 10 nF.
On next three pictures is shown the C capacitor
FF
influence to dynamic parameters.
VIN =4.3V – 1V/div
IOUT =1−to−150mA – 100mA/div
CFF =0pF
VOUT =3.3V – 50mV/div
Figure 45.
Startup
In the NCP730 device there are two main internal signals
which triggers the startup process, the under−voltage
lockout (UVLO) signal and enable signal. The first one
comes from UVLO comparator, which monitors if the IN
pin voltages is high enough, while the second one comes
from EN pin comparator. Both comparators have embedded
hysteresis to be insensitive to input noise.
C
FF = 100p
N
CP730ASN−ADJ
set to 3.3V
C
FF =1nF
CFF =10pF
Figure 42. Load Transient – Different CFF
Time – 10ms/div
Not only the comparator but also the pull−up current
source is connected to EN pin. Current source is sourcing
CP730ASN−ADJ
set to 3.3V
N
I
= 300 nA current flowing out of the chip what
EN-PU
ensures the level on the pin is high enough when it is left
floating. The comparator compares the EN pin voltage with
internal reference level 0.9 V (typ.). Hysteresis is 100 mV
(typ.).
V
38V − 5V/div
IN = 0´
CFF =0pF
VOUT =3.3V – 1V/div
The UVLO comparator threshold voltage is 1.95 V (typ.)
and hysteresis is 200 mV (typ.).
CFF = 100pF
=1nF
CFF
Time – 2ms/div
Figure 43. Startup Timing – Different CFF
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15
NCP730
IN
OUT
V
IN
IN
OUT
V
OUT
UVLO Comparator
UVLO
C
IN
C
OUT
NCP730
1mF
1mF
1.95 V
VC CEN
VEN
VR EF
1.2V
EN
GND
V−REFERENCE
AND SOFT−START
EA
R
R
ADJ1
ADJ2
Figure 49. Circuit – EN Pin Connected to IN Pin
VFB =1.2V
EN
ADJ
Enable
VIN−TOP
VIUL−TH
VIUL−TH – VIUL−HY
300 nA
EN Comparator
VIN
THERMAL
SHUTDOWN
GND
0.9 V
VIN−TOP
= V
VEN
IN
VEN−TH
VEN−TH – VEN−HY
PG Comparator
PG
NC
VOUT−NOM
DEGLITCH
DELAY TMR
95% of V
OUT−NOM
93% of VR EF
VOUT
Time
tSTART
Figure 46. Internal Block Diagram – EN Pin
Startup by IN Pin Voltage
Figure 50. Startup Timing – EN Pin Connected to IN
Pin
When the LDO is started by IN pin voltage rise, it is turned
ON when the voltage is higher than UVLO threshold level.
This is the case of both following application circuits, the
first one with EN pin floating and the second one with EN
pin connected to IN pin.
Startup time in both cases above is measured from the
point where IN pin voltage reaches V
value to point
IUL−TH
when OUT pin voltage reaches 95% of its nominal value.
The reason why the LDO is started by the UVLO signal
and not by the enable signal is the fact that the UVLO signal
turns to valid state later then the enable. (EN pin voltage
When the EN pin is floating (left unconnected) its voltage,
after the LDO is powered, rises to V
level
reaches the V
level prior the IN pin voltage reaches the
CCEN
EN-TH
(2.5 V – 4.5 V, V dependent) as the internal current source
V
IUL-TH
level).
IN
pulls the pin voltage up. V
higher than EN comparator threshold so the LDO is turned
ON.
voltage level on EN pin is
CCEN
Startup by EN Pin Voltage
When V voltage in the application is settled above the
IN
V
IUL-TH
level and control voltage to the EN pin is applied,
V
IN
IN
OUT
V
OUT
the level higher than V
enables the LDO and the level
EN−TH
lower than (V
– V
) disables it.
EN-TH
EN-HY
C
IN
C
OUT
NCP730
1mF
Startup time is measured from point where V voltage
1mF
EN
VEN
reaches V
value to point when V
voltage reaches
EN−TH
OUT
EN
GND
95% of its nominal value.
Figure 47. Circuit – Floating EN Pin
V
IN
IN
OUT
V
OUT
VIN−TOP
C
OUT
C
IN
NCP730
VIUL−TH
VIUL−TH – VIUL−HY
1mF
1mF
VIN
VEN
EN
GND
VCCEN
VEN
VEN−TH
Figure 51. Circuit – LDO Controlled by VEN
VEN−TH – VEN−HY
VOUT−NOM
95% of VOUT−NOM
VOUT
VIUL−TH
VIUL−TH – VIUL−HY
Time
VIN
tSTART
Figure 48. Startup Timing – Floating EN Pin
VEN−TH
VEN
VEN−TH – VEN−HY
It is also possible to connect EN pin directly to IN pin in
the whole input voltage range. The startup sequence is very
similar to previous case, the only difference is that the EN
VOUT−NOM
95% of VOUT−NOM
VOUT
pin voltage is not clamped to V
level but it is the same
CCEN
Time
as V voltage.
tSTART
IN
Figure 52. Timing – VEN−Startup
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16
NCP730
Startup by IN Pin Voltage − Delayed
The startup time triggered by IN pin voltage rise could be
delayed by adding of EN pin capacitor (C ). The startup
signal makes it high because the transistor is connected as
signal invertor.
In this application we need to care about transistor’s
leakage current which must be negligible compared to the
EN
sequence is following − after the V voltage is applied, the
IN
charging of C
capacitor by internal pull−up current
internal pull−up current
additional pull−up resistor R
I
= 300 nA otherwise
will be needed. The
EN
EN−PU
(I
) is started. When the C capacitor voltage (V
)
EN-PU
EN
CEN
EN
reaches EN comparator’s threshold voltage (V
) the
CCEN
maximum value of the EN resistor R
is computed
EN−TH
EN-MAX
LDO is enabled. Charging of C continues up to the V
from maximal external transistor leakage current (over
EN
level (2.5 V – 4.5 V, V dependent) with no following effect.
desired temperature range) I
and minimal input
IN
T-LK-MAX
The steepness of the LDO’s output voltage rise (soft−start
time) is not affected by using of C
voltage V
:
IN−MIN
capacitor. The
EN
VIN−MIN
IT−LK−MAX
(eq. 4)
REN−MAX
+
additional delay time (t
) could be computed by:
CEN−DELAY
V
0.9 V
(eq. 2)
EN−TH + CEN
@
EN
For safe, select the EN resistor value R lower enough
t
CEN−DELAY + CEN
@
IEN−PU
300 nA
to computed R
.
EN-MAX
The total startup time (t
) with connected C
EN
When R
is used the overall application shutdown
START-CEN
EN
capacitor is a sum of normal startup time (t
) and
capacitor
current is increased because the current through R resistor
START
EN
additional delay time caused by
(t ):
C
EN
(I
(I
(I
) is added to input shutdown current of the LDO
). The total application shutdown current
REN
CEN-DELAY
SD(LDO)
) is:
SD(TOT)
t
START−CEN + tSTART ) tCEN−DELAY
(eq. 3)
(eq. 5)
I
SD(TOT) + ISD(LDO) ) IREN
Value of the C capacitor could be in range from 0 to
EN
several microfarads. Capacitor’s leakage current must be
negligible to internal pull−up current I , otherwise the
ǒV
Ǔ
IN * VT−DS
IREN
+
EN−PU
REN
charging will be affected and adding of R resistor from IN
EN
to EN pin will be needed.
Where V
is the drain to source voltage of the transistor
T−DS
(given by R
and I
).
DSON
REN
VOUT
V
IN
IN
OUT
The overall application quiescent current when R is
EN
used is influenced only by the transistor’s leakage current
C
OUT
C
IN
NCP730
1mF
1mF
I
.
T−LK
V EN
(eq. 6)
I
Q(TOT) + IQ(LDO) ) IT−LK
EN
GND
IEN−PU
C
EN
IQ(TOT)
IQ(LDO)
V
IN
IN
OUT
V
OUT
IREN
R
EN
C
IN
C
OUT
Figure 53. Circuit – CEN−Delayed VIN−Startup
NCP730
1mF
Opt.
1mF
VEN
IEN−PU
IT
EN
GND
VIN
VCTRL
VCCEN
(without CEN
)
VEN−TH
Figure 55. Circuit – EN Pin Controlled by Transistor
VEN
(with CEN
)
VOUT−NOM
95% of VOUT−NOM
(without CEN
)
(with CEN)
VOUT
VCTRL
Time
tCEN−DELAY
tSTART
VEN−TH
VEN−TH – VEN−HY
tSTART−CEN
VEN
Figure 54. Timing – CEN−Delayed VIN−Startup
VOUT−NOM
95% of VOUT−NOM
VOUT
Startup by Transistor at EN Pin
Time
tSTART
If the LDO needs to be controlled by transistor or
generally by open collector / open drain circuit as shown at
the next picture, the control behavior is inverted. High
control signal makes the EN pin voltage low and low control
Figure 56. Startup Timing – EN Pin Controlled by
Transistor
www.onsemi.com
17
NCP730
Startup by Transistor at EN Pin − Delayed
The startup time triggered by EN pin voltage rise, could
be delayed the same way as IN pin triggered startup, by
UVLO threshold value, the external resistor divider from IN
pin to EN pin, is needed.
Note that the specification of EN pin threshold voltage
(0.7 V to 1.05 V over full operating temperature range) is
not as precise as threshold voltage on dedicated UVLO
devices. The reason is the EN circuit has to have ultra−low
adding of C capacitor. The startup sequence is following
EN
– when the external NMOS control voltage (V
) is high
CTRL
the C capacitor connected to the EN pin is shorted to GND
EN
and LDO is disabled. After the V
is turned low the
current consumption (NCP730 I
is 350 nA typ. even
CTRL
SHDN
charging of C capacitor by the internal pull−up current
while I
is 300 nA typ. so EN comparator is powered
EN
EN−PU
source (I
) starts. When the C
capacitor voltage
by less than 50 nA typ.). We need to count with that when
thinking about the IN pin UVLO design. Below is the
application example to show what precision we can get.
EN-PU
EN
(V
, which is the V in fact) reaches EN comparator’s
CEN
EN
threshold voltage (V
) the LDO is enabled. Charging of
ENTH
C
EN
then continues up to the V
level (2.5 V – 4.5 V,
CCEN
IQ(TOT)
IQ(LDO)
V
IN
dependent) with no following effect. The steepness of
VIN
IN
OUT
V
OUT
the LDO’s output voltage rise (soft−start time) is not affected
by using of C capacitor. The additional delay time
IREN1
C
IN
C
1mOUFT
R
EN1
EN2
NCP730
1mF
EN
VEN
IEN−PU
IREN2
(t
) could be computed by eq. 2 and the total
CEN-DELAY
EN
GND
delayed startup time with C capacitor (t
) by eq.
EN
START-CEN
C
EN
R
100pF
3. What has been said about the C capacitor selection at
EN
Optional
previous paragraphs is applicable here as well.
Also in this application we need to care about transistor’s
leakage current which must be negligible compared to the
Figure 59. Circuit – IN Voltage UVLO by EN Pin
internal pull−up current
additional pull−up resistor R will be needed. Same rules
and computations as stated in previous paragraph about R
are applicable here. Note that R would influence the speed
I
EN
= 300 nA otherwise
EN−PU
The two main equations for IN pin threshold computation
are:
EN
V
IN−UVLO−TH * VEN−TH
(eq. 7)
EN
REN1
REN2
+
+
IREN1
of C capacitor charging.
EN
VEN−TH
IQ(TOT)
IQ(LDO)
VOUT
VIN
IN
OUT
I
REN1 ) IEN−PU
IREN
R
EN
C
OUT
C
IN
From that, we can get:
NCP730
1mF
Opt.
1mF
(eq. 8)
VEN
REN1
REN2
EN
GND
@ ǒ1 ) Ǔ* R
V
IN−UVLO−TH + VEN−TH
EN1 @ IEN−PU
IEN−PU
C
EN
VCTRL
We can see that IN pin UVLO threshold is EN pin
threshold multiplied by the resistor divider ratio as expected
Figure 57. Circuit – EN Pin with CEN Controlled by
Transistor
but it is unwillingly affected by I
pull−up current. As
current could vary up to the 1 mA max., we need
EN-PU
the I
EN-PU
to choose the I
current several times higher to make the
REN1
I
influence negligible. The good practice could be to
EN-PU
VCTRL
choose I
at least 10−times higher than I
(the
REN1
EN-PU
bigger the better for the accuracy).
An optional component in this application is C capacitor.
Its main function is filtering out the spurious signals coming
from IN power supply and the minor function is to delay the
startup as described in section before. The value of C for
VCCEN
(without C
)
EN
EN
VEN−TH
VEN
(with C
)
EN
VOUT−NOM
95% of V
OUT−NOM
(without C
)
(with C )
EN
EN
EN
VOUT
filtering purpose could be in range from 10 pF to 10 nF. The
time constant of this filter is given by:
Time
tCEN−DELAY
tSTART −CEN
tSTART
R
EN1 @ REN2
(eq. 9)
t
FILTER + CEN @
R
EN1 ) REN2
Figure 58. Startup Timing – EN Pin with CEN
Controlled by Transistor
The side effect of the UVLO divider is increased overall
power consumption. At no load state, the quiescent current
I
of the application is:
Q(TOT)
Enable Input as Inaccurate IN Pin UVLO
(eq. 10)
I
Q(TOT) + IQ(LDO) ) IREN1
The EN input pin on NCP730 device is specified by
threshold voltage and hysteresis both with minimum and
maximum value, what allows using EN comparator as
So if we select the I
value at least 10−times higher
REN1
than I
(1 mA), then the UVLO divider current is
EN-PU-MAX
adjustable input voltage UVLO function. To set the V
IN
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18
NCP730
Output Current Limit
almost 10-times higher than typical LDO’s quiescent
Output current is internally limited to 280 mA typ. The
LDO will source this current when the output voltage drops
down from the nominal output voltage (test condition is 90%
current (1.3 mA).
IN voltage UVLO application example:
Desired V
voltage is 5 V, the LDO’s input voltage in
OUT
of V ). If the output voltage is shorted to ground,
OUT−NOM
normal state is 12 V. We want to turn−off the LDO’s output
voltage when input voltage is below 10 V (max.).
First, choose the I
the device continues with current limitation at the same
current level. The current limit and short circuit protection
will work properly over the whole temperature and input
voltage ranges. There is no limitation for the short circuit
duration.
Minimal output current limit value is 200 mA what could
be used to cover current demand peaks, higher than the
LDO’s nominal output current (150 mA).
current as 10−times the maximum
REN1
I
current:
EN-PU
(eq. 11)
I
REN1 + 10 @ IEN−PU + 10 @ 1 mA + 10 mA
Then, to obtain R
and R
values for maximal
EN1
EN2
V
V
= 10 V, we need to put maximum value of
(1.05 V) and minimum value of I
IN-UVLO-TH
(0 mA) into
EN-TH
EN-PU
the equations for R
and R
:
EN1
EN2
Inrush Current
(eq. 12)
V
IN−UVLO−TH−VEN−TH
At every application, the startup sequence needs a special
care because during power−up the bypass capacitors
connected to the power rail are charged from zero to input
voltage level, what generates a current spike, so called
inrush current. The size of such current spike depends on the
voltage transient slope (the faster the bigger spike), on the
total impedance of the loop from the power source to bypass
capacitor (traces impedance, power source internal
impedance and capacitor impedance; the lower the bigger
spike) and on the capacitor value (the higher the bigger
spike).
10 V−1.05 V
10 mA
REN1
REN2
+
+
+
+ 895 kW
IREN1
VEN−TH
1.05
10 mA ) 0 mA
+
+ 105 kW
I
REN1 ) IEN−PU
The resulting V
limits will be:
IN-UVLO-TH
(eq. 13)
EN1 @ IEN−PU−MAX
REN1
REN2
@ ǒ1 ) Ǔ* R
V
IN−UVLO−TH−MIN + VEN−TH−MIN
895 kW
ǒ1 ) Ǔ* 895 kW @ 1 mA
V
IN−UVLO−TH−MIN + 0.7 @
105 kW
This inrush current during startup could cause power
source’s overcurrent event, damage of PCB traces, power
line fuses blowing or spurious signal generation in
surrounding application parts.
V
IN−UVLO−TH−MIN + 5.77 V
REN1
@ ǒ1 ) Ǔ* R
V
IN−UVLO−TH−MAX + VEN−TH−MAX
EN1 @ IEN−PU−MIN
REN2
For a simplified case when total impedance between input
power source and bypass capacitor is zero, we can use
following equation to compute the inrush current, based just
on voltage transient slope (dV/dt) and the capacitor value:
895 kW
ǒ1 ) Ǔ−895 kW @ 0 mA
V
IN−UVLO−TH−MAX + 1.05 @
105 kW
IN−UVLO−TH−MAX + 10.0 V
Q(TOT) + IQ(LDO) ) IREN1 + 1.3 mA ) 10 mA + 11.3 mA
V
I
dV
i
INRUSH + C @
(eq. 16)
dt
When higher I
is selected the V
IN-UVLO-TH-MIN
REN1
would be slightly near the target value, the
Example – when the voltage changes from 0 V to 24 V in
10 ms and bypass capacitor is 10 mF, the inrush current is:
V
would stay the same but the I
IN-UVLO-TH-MAX
Q(TOT)
would be significantly higher:
24 V * 0 V
i
INRUSH + 10 mF @
+ 24A (eq. 17)
(eq. 14)
I
REN1 + 100 @ IEN−PU + 100 @ 1 mA + 100 mA
10 ms
We would get:
Of course, this is the worst case when impedances in the
circuit are zero, but it shows why we need to care about
startup and what defines the inrush current value. We can see
the inrush current is lower when capacitance and voltage
change are smaller or transition time is longer.
(eq. 15)
R
R
EN1 + 89.5 kW
EN2 + 10.5 kW
V
IN−UVLO−TH−MIN + 6.58 V
In most cases, the capacitor value and the input voltage
change are defined by the application so then the only thing
we can do is to slow down the input voltage transition time.
We can do it directly by changing input voltage rise time by
soft−start circuit (related to Equation 16) or indirectly by
adding a current limit block, which in combination with the
capacitor will do the same (slower the input voltage rise), see
the following equation:
I
Q(TOT) + IQ(LDO) ) IREN1 + 1.3 mA ) 100 mA + 101.3 mA
We can see the IN pin UVLO threshold precision
computed above (5.77 V or 6.58 V min. / 10.0 V max.) is not
too high because the EN pin threshold and EN pin internal
pull−up current specifications are not so tight as on
dedicated UVLO devices but at some applications this
precision could fit the needs.
dV
ILIMIT
t
START + C @
(eq. 18)
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19
NCP730
We see that voltage transition time (t
) is given by
current limit value). While at the case of big output capacitor
(for example 47 mF), the soft−start time is not slow enough
and the input current needs to be limited by the current limit
function.
Next picture shows both startup cases – with small (1 mF)
and big (47 mF) output capacitors. Startup is caused by IN
voltage rise, EN pin is connected to IN pin and device
voltage version is 5.0 V.
START
bypass capacitor value (C), by the voltage change (dV) and
by current limit value (I ) of added current limit block.
LIMIT
Now back to LDO application. Here we can see two
different inrush current spikes. The first one is caused by the
LDO’s input capacitor (C ) charging from zero to the input
IN
voltage level. It happens when the previous power block (for
example DC/DC) starts providing the input voltage to the
LDO circuit. The maximum level of this inrush current is
given by Equation 16. It doesn’t matter if LDO is enabled or
(3)
47μF
(1)
disabled as this inrush current spike is related only to C
IIN
V
IN
1μF
1μF
(2)
and it can’t be suppressed by the LDO, it is matter of
previous power block. This inrush current spike is shown at
Figure 61, point (1).
IN
VOUT
The second inrush current spike is generated by the LDO’s
47μF
output capacitor (C ) charging from zero to nominal
OUT
output voltage level. It happens when the LDO is enabled by
any way (by driving EN pin or by internal UVLO when EN
pin is connected to IN pin). This inrush current is limited by
the LDO’s soft−start and current limit functions.
Soft−start function limits the speed of the output voltage
rise to avoid possible latch−up of application circuit caused
by high dV/dt what naturally suppresses input inrush current
(related to Equation 16).
The current limit function, used to guard the LDO and
application against the overcurrent, is also used during the
LDO’s startup to limit the input inrush current.
Now focus onto the NCP730 device. At the next picture
we can see both, soft−start and current limit functions have
been implemented, shown in red. At this device, the startup
current limit level is the same as the normal operation
current limit level (specified at the parametric table).
μ
200 s/div
C1: VIN
C2: VOUT
C4: IIN
1.0V/div
1.0V/div
200mA/div
Figure 61.
With the C
= 1 mF, the inrush current (seen at I
IN
signal at point−2) is almost zero, its level is defined by
soft−start time which is about 550 ms (from the picture).
OUT
DVOUT
tSTART
i
INRUSH + COUT @
(eq. 19)
5 V * 0 V
550 ms
i
INRUSH−1mF + 1 mF @
+ 9 mA
OUT
With the C
47−times higher than in case of 1 mF:
= 47 mF, the inrush current should be
OUT
IN
UVLO Comparator
UVLO
5 V * 0 V
500 ms
1.95 V
(eq. 20)
i
INRUSH−47mF + 47 mF @
+ 470 mA
VREF
VCCEN
1.2V
Therefore, in this case the current limit is activated and
limits the C charging current to about 280 mA (from the
picture, point−3). This leads to enlarging of startup time to:
V−REFERENCE
AND SOFT−START
EA
OUT
R
ADJ1
ADJ2
EN
ADJ
VFB =1.2V
Enable
DVOUT
ILIMIT
t
START + COUT @
EN Comparator
R
GND
(eq. 21)
THERMAL
SHUTDOWN
0.9 V
5 V * 0 V
270 mA
t
START + 47 mF @
+ 870 ms
PG Comparator
PG
NC
One additional thing could be seen at the picture above
and it is a small current spike highlighted as a point−1 at the
DEGLITCH
DELAY TMR
93% of V REF
I
curve. It is the inrush current caused by input voltage
IN
transient (from 0 V to 6 V in 10 ms) and input capacitor
= 100 nF. As stated before, for this current spike is
Figure 60.
C
IN
responsible the prior power source, not the LDO (in this case
the test equipment which generates the V transient). The
A few practical notes. If the LDO’s output capacitor value
is small (for example 1 mF), then soft−start limited output
voltage rise is slow enough to suppress the inrush current
IN
C
IN
inrush current amplitude is:
6 V * 0 V
10 ms
(output capacitor charging current, generated by dV
/dt,
OUT
(eq. 22)
+ 60 mA
i
INRUSH_POINT−1 + 100 nF @
based on Equation 16, is significantly smaller than the
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20
NCP730
Power Supply Rejection Ratio
different power supply voltage to the LDO’s V
Below are the connections examples.
level.
OUT
The LDO features high power supply rejection ratio even
it is very low quiescent current device. See the Typical
characteristics section for the graphs over different
conditions.
5.0V
IN
OUT
VCC
1OmUFT
C
The PSRR at higher frequencies (from about 100 kHz) can
NCP730B500
RPG
Application
be tuned by the selection of C
capacitor, applied input
OUT
voltage and proper PCB layout (minimizing impedance
EN
PG
PGI
GND
from load to C ).
OUT
CTRL
PG Output
Version B of the NCP730 device contains PG circuit for
the V voltage level monitoring. Internally it is combined
from PG comparator, deglitch/delay timer and output
NMOS transistor (highlighted by red color at picture
below). At both, ADJ and FIX versions, the PG comparator
Figure 63. Circuit Example – PG Connected to LDO’s
Output
OUT
5.0V
IN
OUT
VCCA
Appl.
Part 1
(analog)
COUT
compares internal feedback signal voltage (V ) with the
FB
1mF
NCP730B500
93% of V
(typ.) what makes the function independent to
REF
the output voltage absolute value (it always compares set
EN
PG
GND
3.3V
VCCD
V
OUT
with 93% of its nominal value).
Appl.
Part 2
(MCU)
R
PG
IN
OUT
PGI
CTRL
UVLO Comparator
UVLO
1.95 V
Figure 64. Circuit Example – PG Connected to
Application Power Supply
VR EF
1.2V
VCCEN
V−REFERENCE
AND SOFT−START
EA
Following timing diagrams show the situation when LDO
falls out of regulation 3 times (output voltage drops down
from nominal value) because of (for example) insufficient
IN pin voltage.
R
R
ADJ1
ADJ2
VFB =1.2V
EN
ADJ
Enable
EN Comparator
Note that the V voltage at “power ok state” follows the
PG
THERMAL
SHUTDOWN
GND
0.9 V
voltage where the R is connected because the PG output
PG
is in Hi−Z state and just R connection point defines the
PG
PG Comparator
PG
NC
V
PG
level. In the first example when R is connected to
PG
LDO’s output, the V follows the LDO’s V
including
DEGLITCH
PG
OUT
DELAY TMR
the drops. In the second example the R is connected to
PG
93% of VR EF
LDO independent power rail (3.3 V) so the V is not
following the LDO’s output voltage.
PG
Blue objects are valid for ADJ version
Green objects are valid for FIX version
Red objects are valid for B version (with PG)
Note:
tOUT−LOW < tPG−DG
tPG−DG
tPG−DLY
5V
Figure 62. Power Good Output Block Diagram
VPG−TH
VPG−TH – VPG−HY
The PG output is in high impedance state (Hi−Z) to show
“power ok state” when the V voltage is above the PG
VOUT
OUT
threshold level (V
“power fail state” when the V
) or is shorted to GND pin to show
PG-TH
~10kW (t~500ns)
RPG
falls below the level
OUT
5V
(V
– V
).
PG-TH
PG-HY
The PG threshold voltage is 93% of V
(typ.) and
~100kW (t~5ms)
RPG
VPG
OUT-NOM
the hysteresis is 2% of V
(typ.).
OUT-NOM
Because the PG output is open drain type it needs to be
connected by external pull resistor to a voltage level, which
defines the PG pin voltage at time when it is in Hi−Z state.
It allows connections of PG pin to circuit with the same or
Time
Time
region
1
2
3
4
Figure 65. Timing – PG Connected to LDO’s Output
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21
NCP730
tOUT−LOW < tPG−DG
tPG−DG
tPG−DLY
through the R to the grounded PG pin. This is just a case
PG
5V
of the power fail state so probably not a concern too.
At the electrical characteristics table we can find the
VPG−TH
VPG−TH – VPG−HY
VOUT
parameter “PG Output Low Level Voltage (V )” which
PG-OL
defines the drop across the PG internal transistor when it
sinks current 1 mA. We can take this current condition
~10kW (t~500ns)
RPG
3.3V
(1 mA) as a maximal PG current (I
) for the R
PG−MAX
PG−MIN
computation (as we know the PG drop at this level, 0.4 V
~100kW (t~5ms)
RPG
VPG
max.). If the application input current I
is negligible to
PGI
I
we can compute the R
by:
RPG
PGI−MIN
Time
VCC−RPG
IPG−MAX
RPG−MIN
+
(eq. 23)
Time
region
1
2
3
4
Figure 66. Timing – PG Connected to Application
Power Supply 3.3 V
And, for example, when R is connected to 3.3 V power
rail:
PG
The timing diagrams have been divided into 4 time
regions to show different situations:
VCC−RPG
IPG−MAX
3.3 V
1 mA
(eq. 24)
+ 3.3 kW
RPG−MIN
+
+
In region−1, the V
drop is not deep enough so the PG
OUT
output shows “power ok state”.
In region−2, the V drop is deeper and crosses the
VCC−RPG
OUT
V
threshold level but the duration of the drop is shorter
PG-TH
IRPG
R
PG
then PG deglitch time (t
= 160 ms typ.) so the PG
PG-DG
NCP730B
Application
output still shows “power ok state”. Note that the deglitch
time has been intentionally implemented to filter out
spurious output voltage drops (caused for example by fast
load transients etc.).
VPG
PG
PGI
IPGI
IPG
GND
In both two first regions the V is high and follows the
Note: IPG = I RPG when IPGI = 0mA
PG
voltage level where the R
resistor is connected to
PG
Figure 67. Circuit Example for RPG Value Selection
(V
or V
).
LDO(OUT)
CCD
In region−3, the V
drop is deep enough and the
From the opposite side, R is limited to its maximum
OUT
PG
duration is longer then t
time so the PG output is
value, based on: maximum PG leakage current
PG-DG
shorted to GND pin and shows power fail state.
In region−4, the V returns back to its nominal value.
I
, maximum threshold voltage of the application
PG−LK−MAX
input V
and maximum application input
OUT
PGI−TH−MAX
When it crosses the level (V
– V
) the PG output
leakage current I
. Then:
PG-TH
PG-HY
PGI−LK−MAX
turns from short to GND into Hi−Z state, not immediately,
but after the PG delay time (t = 320 ms typ.). The PG
V
CC−RPG * VPGI−TH−MAX
RPG−MAX
+
(eq. 25)
PG-DLY
I
PG−LK−MAX ) IPGI−LK−MAX
delay ensures that low PG pulse, showing “power fail state”,
is always longer than the t time and then could be
For example, when R is connected to 3.3 V power rail,
max. threshold voltage of the application input is 1.3 V and
application input leakage current is 3 mA max.:
PG
PG-DLY
caught by the application circuit (for example by MCU).
RPG Value Selection
As shown on the Figure 65 and Figure 66 in the time
region-4, the steepness of PG signal return to high level
V
CC−RPG * VPGI−TH−MAX
RPG−MAX
+
+
(eq. 26)
I
PG−LK−MAX ) IPGI−LK−MAX
3.3 V * 1.3 V
1 mA ) 3 mA
depends on the R pull−up resistance (with relation to
PG
+ 500 kW
capacitance of LDO’s PG output, parasitic capacitance of
PG signal PCB traces and the application circuit PGI input
capacitance. The lower R resistance the faster PG return
Based on results above, the R value could be selected
in range from 3.3 kW to 500 kW to fit the example
PG
PG
to high level.
application.
At the most applications, the PG return speed to high level
is not a concern, mainly because of the fact that the LDO
Thermal Shutdown
When the LDO’s die temperature exceeds the thermal
shutdown threshold value the device is internally disabled.
The IC will remain in this state until the die temperature
decreases by the thermal shutdown hysteresis value. Once
already delays the PG return by the t
time (320 ms
PG-DLY
typ.) intentionally so the returning speed itself is negligible.
The next view to the R value is the power consumption
PG
at “power fail state” when the current from the supply flows
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22
NCP730
the IC temperature falls this way, the LDO is back enabled.
Where: (T − T ) is the temperature difference between the
J A
The thermal shutdown feature provides the protection
against overheating due to some application failure and it is
not intended to be used as a normal working function.
junction and ambient temperatures and θ is the thermal
JA
resistance (dependent on the PCB as mentioned above).
For reliable operation junction temperature should be less
than +125°C.
Power Dissipation
The power dissipated by the LDO for given application
conditions can be calculated by the next equation:
Power dissipation caused by voltage drop across the LDO
and by the output current flowing through the device needs
to be dissipated out from the chip. The maximum power
dissipation is dependent on the PCB layout, number of used
Cu layers, Cu layers thickness and the ambient temperature.
The maximum power dissipation can be computed by
following equation:
ǒ Ǔ
D + VIN @ IGND ) VIN * VOUT @ IOUT [W]
(eq. 28)
P
Where: I
is the LDO’s ground current, dependent on the
GND
output load current.
Connecting the exposed pad and NC pin to a large ground
planes helps to dissipate the heat from the chip.
TJ * TA
qJA
125 * TA
The relation of θ and P
to PCB copper area and
Cu layer thickness could be seen on the Figures 68 and 69.
JA
D(MAX)
PD(MAX)
+
+
[W]
(eq. 27)
qJA
Figure 68. qJA and PD(MAX) vs. Copper Area
Figure 69. qJA and PD(MAX) vs. Copper Area
Figure 70. Maximum Output Current vs. Input
Voltage
Figure 71. Maximum Output Current vs. Input
Voltage
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23
NCP730
PCB Layout Recommendations
To obtain good LDO’s stability, transient performance
and good regulation characteristics place C and C
capacitors as close as possible to the device pins and make
the PCB traces wide, short and place capacitors to the same
layer as the LDO is (to avoid connection through vias). The
same rules should be applied to the connections between
Besides the LDO application circuit, each demo board
includes some supporting staff, the same at all boards:
• Positions for optional through hole SMB connectors at
IN, OUT and EN pins (Molex 73100−0258 or
compatible) mainly for line/load transients, PSRR,
noise and startup testing the demo board includes.
• Edge connector where all these signal leads too (the
appropriate receptacle type is SAMTEC
MECF−20−01−L−DV−WT).
IN
OUT
C
OUT
and the load – the less parasitic impedance the better
transients and regulation at the point of load.
To minimize the solution size, use 0402 or 0201 capacitor
sizes with appropriate effective capacitance in mind.
Regarding high impedance ADJ pin, prevent capacitive
coupling of the trace to any switching signals in the circuitry.
Adequate input power filtering is always a good practice.
For load transients the input capacitor value must be high
enough to cover the current demands especially if the power
source is connected by long traces/wires with high
impedance.
• Thermal management circuit (heating transistor and
diodes as temperature sensors).
Demo Boards
Below are the main part of the schematics and top/bottom
board layout pictures of the NCP730 demo boards for
various packages. These boards have been used during
evaluation to capture the data shown in this datasheet like:
transients, PSRR, startups etc. At some of these pictures are
shown details of PCB traces surrounding the LDO including
Figure 72. Edge Connector Pinout (All Demo Boards)
C , C
IN
, resistor divider R /R , feed forward capacitor
OUT
1 2
C
FF
and IN/OUT−FORCE/SENSE connections.
Generally, when testing LDOs dynamic performance on
demo board which is connected to laboratory power supply
typically by long cables, the device needs additional input
capacitor. This capacitor covers the voltage drop generated
by the load current transients at the impedance of long
connection cables (note this is very different to normal
application where the distance of the LDO to its power
source is short).
Figure 73. Thermal Circuit (All Demo Boards)
www.onsemi.com
24
NCP730
NCP730ASN/BSN (TSOP−5 package) Demo Board (2 layer PCB, rev. 1)
Figure 74. TSOP−5 Demo Board (2 layer, rev. 1) – Schematics (Main Part)
Figure 76. TSOP−5 Demo Board (2 layer, rev. 1) –
PCB Bottom Layer
Figure 75. NCP730 Demo Board (2 layer, rev. 1) –
PCB Top Layer
Figure 77. TSOP−5 Demo Board (2 layer, rev. 1) – PCB Top Layer, Zoomed, Added Signal Labels
www.onsemi.com
25
NCP730
NCP730AMT/BMT (WDFN−6 2x2 package) Demo Board (2 layer PCB, rev. 1)
Figure 78. WDFN−6 2x2 Demo Board (2 layer, rev. 1) – Schematics (Main Part)
Figure 79. WDFN−6 2x2 Demo Board (2 layer, rev. 1) –
Figure 80. WDFN−6 2x2 Demo Board (2 layer, rev. 1) –
PCB Top Layer
PCB Bottom Layer
Figure 81. WDFN−6 2x2 Demo Board (2 layer, rev. 1) – PCB Top Layer, Zoomed, Added Signal Labels
www.onsemi.com
26
NCP730
ORDERING INFORMATION
Part Number
Marking
HAA
HAC
HAD
HAF
HAE
HAG
MA
Voltage Option (V
)
Version
Package
Shipping
OUT−NOM
NCP730ASNADJT1G
NCP730ASN250T1G
NCP730ASN280T1G
NCP730ASN300T1G
NCP730ASN330T1G
NCP730ASN500T1G
NCP730BMTADJTBG
NCP730BMT250TBG
NCP730BMT280TBG
NCP730BMT300TBG
NCP730BMT330TBG
NCP730BMT500TBG
NCP730BMT1500TBG
ADJ
2.5 V
2.8 V
3.0 V
3.3 V
5.0 V
ADJ
TSOP−5
(Pb−Free)
Without PG
3000 / Tape & Reel
MC
2.5 V
2.8 V
3.0 V
3.3 V
5.0 V
15.0 V
MD
WDFN6 2x2
(Pb−Free)
ME
With PG
3000 / Tape & Reel
MF
MG
MH
*To order other package, voltage version or PG / non PG variant, please contact your ON Semiconductor sales representative.
www.onsemi.com
27
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
DATE 12 AUG 2020
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
2X
0.10
T
M
5
4
3
2X
0.20
T
B
S
1
2
K
B
A
DETAIL Z
G
A
MILLIMETERS
TOP VIEW
DIM
A
B
C
D
MIN
2.85
1.35
0.90
0.25
MAX
3.15
1.65
1.10
0.50
DETAIL Z
J
G
H
J
K
M
S
0.95 BSC
C
0.01
0.10
0.20
0
0.10
0.26
0.60
10
3.00
0.05
H
SEATING
PLANE
END VIEW
C
_
_
SIDE VIEW
2.50
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
1.9
5
1
5
0.074
0.95
XXXAYWG
XXX MG
0.037
G
G
1
Analog
Discrete/Logic
2.4
0.094
XXX = Specific Device Code XXX = Specific Device Code
A
Y
W
G
= Assembly Location
= Year
= Work Week
M
G
= Date Code
= Pb−Free Package
1.0
0.039
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511BR
ISSUE B
DATE 19 JAN 2016
SCALE 4:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND
IS MEASURED BETWEEN 0.15 AND 0.25 mm FROM
THE TERMINAL TIP.
A3
EXPOSED Cu
MOLD CMPD
D
A
B
A1
ALTERNATE B−1
ALTERNATE B−2
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICES CONTAINING WETTABLE FLANK
OPTION, DETAIL A ALTERNATE CONSTRUCTION
A-2 AND DETAIL B ALTERNATE CONSTRUCTION
B-2 ARE NOT APPLICABLE.
DETAIL B
PIN ONE
ALTERNATE
REFERENCE
E
CONSTRUCTIONS
0.10
C
L
L
MILLIMETERS
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
0.10
C
L1
TOP VIEW
A1
A3
b
ALTERNATE A−1
ALTERNATE A−2
0.20 REF
0.25
1.50
0.35
DETAIL A
A3
DETAIL B
D
2.00 BSC
0.05
C
C
ALTERNATE
D2
E
1.70
CONSTRUCTIONS
2.00 BSC
A
E2
e
0.90
1.10
0.65 BSC
L
0.20
---
0.40
0.15
0.05
6X
A1
L1
SEATING
PLANE
NOTE 4
C
SIDE VIEW
D2
GENERIC
MARKING DIAGRAM*
1
DETAIL A
L
1
XX M
3
XX = Specific Device Code
M
= Date Code
E2
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
6
4
6X b
M
M
0.10
0.05
C
C
A
B
e
RECOMMENDED
MOUNTING FOOTPRINT
NOTE 3
BOTTOM VIEW
6X
1.72
0.45
1.12
2.30
PACKAGE
OUTLINE
1
0.65
6X
0.40
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON55829E
WDFN6 2X2, 0.65P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
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Voice Mail: 1 800−282−9855 Toll Free USA/Canada
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◊
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