NCP81081MNTWG [ONSEMI]
带高压侧和低压侧 MOSFET 的集成驱动器;
| 型号： | NCP81081MNTWG |
| 厂家： | 
ONSEMI |
| 描述： | 带高压侧和低压侧 MOSFET 的集成驱动器 驱动 高压 驱动器 |
| 文件： | 总7页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP81081
Integrated Driver and
MOSFET
The NCP81081 integrates a MOSFET driver, high−side MOSFET
and low−side MOSFET into a 6 mm x 6 mm 40−pin QFN package.
The driver and MOSFETs have been optimized for high−current
DC−DC buck power conversion applications. The NCP81081
integrated solution greatly reduces package parasitics and board space
compared to a discrete component solution.
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MARKING
DIAGRAM
Features
1
• Capable of Switching Frequencies Up to 1 MHz
• Capable of Output Currents Up to 35 A
• PWM Input Capable of 3.3 V and 5 V
• Internal Bootstrap Diode
NCP81081
AWLYYWWG
1
40
QFN40
MN SUFFIX
CASE 485AZ
• Zero Current Detection
• Undervoltage Lockout
• Internal Thermal Warning / Thermal Shutdown
• These are Pb−Free Devices
A
= Assembly Location
= Wafer Lot
WL
YY
WW
G
= Year
= Work Week
= Pb−Free Package
5 V
12−20 V
Thermal
Warning
ORDERING INFORMATION
5V
†
Device
NCP81081MNR2G
Package
Shipping
THWN
VIN
BOOT
QFN40
2500/Tape & Reel
VCIN
(Pb−Free)
ZCD_EN#
DISB#
ZCD Enable
PHASE
VSWH
NCP81081MNTWG QFN40
2500/Tape & Reel
Output
Disable
(Pb−Free)
Vout
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
PWM
PWM
CGND
PGND
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
March, 2012 − Rev. 1
NCP81081/D
NCP81081
BOOT
GH
VIN
VCIN
PWM
PHASE
VSWH
Logic
ZCD_EN#
Anti−Cross
Conduction
VCIN
PGND
DISB#
UVLO
THWN/THDN
THWN
GL
Figure 2. Simplified Block Diagram
VIN 11
40
PWM
VIN
VIN
12
13
VIN
FLAG42
CGND
FLAG41
39 DISB#
38 THWN
VIN 14
37
CGND
VSWH
PGND
15
16
36 GL
35 VSWH
PGND 17
PGND
34
VSWH
VSWH
FLAG43
18
33 VSWH
PGND 19
PGND 20
32
31
VSWH
VSWH
Figure 3. Pin Connections (Top View)
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2
NCP81081
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
ZCD_EN#
VCIN
Description
1
Enable Zero Current Detection
2
Control Input Voltage
No Connect
3, 8
NC
4
BOOT
CGND
GH
Bootstrap Voltage
5, 37, FLAG 41
Control Signal Ground
High Side FET Gate Access
6
7
PHASE
Provides a return path for the high side driver of the internal IC. Place a high frequency ceram-
ic capacitor of 0.1 uF to 1.0 uF from this pin to BOOT pin.
9−14, FLAG 42
VIN
Input Voltage
15, 29−35,
FLAG 43
VSWH
Switch Node Output
16−28
36
PGND
GL
Power Ground
Low Side FET Gate Access
Thermal Warning
38
THWN
DISB#
PWM
39
Output Disable Pin
PWM Drive Logic
40
Table 2. ABSOLUTE MAXIMUM RATINGS
Pin Symbol
VCIN
Pin Name
Min
−0.3 V
Max
7 V
Control Input Voltage
Power Input Voltage
Bootstrap Voltage
VIN
−0.3 V
30 V
BOOT
−0.3 V wrt/VSWH
35 V wrt/PGND
40 V < 50 ns wrt/PGND
7 V wrt/VSWH
VSWH
ZCD_EN#
PWM
Switch Node Output
Zero Current Detection
PWM Drive Logic
Output Disable
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
30 V
6.5 V
6.5 V
6.5 V
6.5 V
DISB#
THWN
Thermal Warning
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. THERMAL CHARACTERISTICS
Rating
Thermal Resistance, High−Side FET
Thermal Resistance, Low−Side FET
Operating Junction Temperature
Storage Temperature
Symbol
Value
Unit
°C/W
°C/W
°C
R
13
Q
JPCB
R
5
0 to 150
−55 to 150
3
Q
JPCB
T
J
T
S
°C
Moisture Sensitivity Level
MSL
Table 4. OPERATING RANGES
Rating
Symbol
VCIN
VIN
Min
4.5
4.5
Typ
5
Max
5.5
25
Unit
Control Input Voltage
Input Voltage
V
V
12
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3
NCP81081
ELECTRICAL CHARACTERISTICS (Note 1) (VCIN = 5 V, VIN = 12 V, T = −10°C to +100°C, unless otherwise noted)
A
Parameter
SUPPLY CURRENT
Symbol
Condition
Min
Typ
Max
Unit
VCIN Current (normal mode)
−
−
DISB# = 5 V, PWM = OSC,
FSW = 400 kHz
14
15
20
30
mA
VCIN Current (shutdown mode)
UNDERVOLTAGE LOCKOUT
UVLO Startup
DISB# = GND
mA
−
−
3.8
4.35
200
4.5
V
UVLO Hysteresis
150
250
mV
BOOTSTRAP DIODE
Forward Voltage
−
VCIN = 5 V, forward bias current = 2 mA
0.1
0.4
0.6
V
PWM INPUT
PWM Input Voltage High
PWM Input Voltage Mid−State
PWM Input Voltage Low
Tri−State Shutdown Holdoff Time
PWM Input Resistance
V
2.65
1.4
−
−
−
−
V
V
PWM_HI
V
2.0
0.7
PWM_MID
V
−
V
PWM_LO
t
250
63
1.7
ns
kW
V
holdoff
PWM Input Bias Voltage
OUTPUT DISABLE
Output Disable Input Voltage High
Output Disable Input Voltage Low
Output Disable Hysteresis
Output Disable Propagation Delay
ZERO CROSS DETECT
Zero Cross Detect High
V
2.0
−
−
−
−
0.8
−
V
V
DISB#_HI
V
DISB#_LO
−
−
500
20
mV
ns
−
40
V
2.0
−
−
−
V
V
ZCD_EN#_HI
Zero Cross Detect Low
V
−
0.8
ZCD_EN#_LO
Zero Cross Detect Threshold
ZCD Blanking Timer
−6
250
mV
ns
THERMAL WARNING/SHUTDOWN
Thermal Warning Temperature
Thermal Warning Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
150
15
°C
°C
°C
°C
180
25
1. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C. Low
J
A
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
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4
NCP81081
APPLICATIONS INFORMATION
Theory of Operation
The NCP81081 prevents cross conduction by monitoring
the status of the MOSFETs and applying the appropriate
amount of “dead−time” or the time between the turn off of
one MOSFET and the turn on of the other MOSFET.
When the PWM input pin goes high, the gate of the
low−side MOSFET (GL pin) will go low after a propagation
delay (tpdlGL). The time it takes for the low−side MOSFET
to turn off (tfGL) is dependent on the total charge on the
low−side MOSFET gate. The NCP81081 monitors the gate
voltage of both MOSFETs and the switchnode voltage to
determine the conduction status of the MOSFETs. Once the
low−side MOSFET is turned off an internal timer will delay
(tpdhGH) the turn on of the high−side MOSFET.
Likewise, when the PWM input pin goes low, the gate of
the high−side MOSFET (GH pin) will go low after the
propagation delay (tpdlGH). The time to turn off the
high−side MOSFET (tfGH) is dependent on the total gate
charge of the high−side MOSFET. A timer will be triggered
once the high−side MOSFET has stopped conducting, to
delay (tpdhGL) the turn on of the low−side MOSFET.
The NCP81081 is an integrated driver and MOSFET
module designed for use in a synchronous buck converter
topology. A single PWM input signal is all that is required
to properly drive the high−side and low−side MOSFETs.
Low−Side Driver
The low−side driver is designed to drive
ground−referenced low R N−Channel MOSFET. The
voltage rail for the low−side driver is internally connected to
a
DS(on)
VCIN and PGND.
High−Side Driver
The high−side driver is designed to drive a floating low
RDS(on) N−channel MOSFET. The gate voltage for the
high side driver is developed by a bootstrap circuit
referenced to Switch Node (VSWH) pin.
The bootstrap circuit is comprised of the internal diode
and an external bootstrap capacitor. When the NCP81081 is
starting up, the VSWH pin is at ground, so the bootstrap
capacitor will charge up to VCIN through the bootstrap
diode See Figure 1. When the PWM input goes high, the
high−side driver will begin to turn on the high−side
MOSFET using the stored charge of the bootstrap capacitor.
As the high−side MOSFET turns on, the VSWH pin will
rise. When the high−side MOSFET is fully on, the switch
node will be at 12 V, and the BST pin will be at 5 V plus the
charge of the bootstrap capacitor (approaching 17 V).
The bootstrap capacitor is recharged when the switch
node goes low during the next cycle.
Thermal Warning / Thermal Shutdown
When the temperature of the driver reaches 150°C, the
THWN pin will be pulled low indicating a thermal warning.
At this point, the part continues to function normally. When
the temperature drops below 135°C, the THWN will go
high.
If the driver temperature exceeds 180°C, the part will
enter thermal shutdown and turn off both MOSFETs. Once
the temperature falls below 155°C, the part will resume
normal operation. The THWN pin has a maximum current
capability of 30 mA.
Zero Current Detect
When ZCD_EN# is set high, the NCP81081 will operate
in normal PWM mode.
Power Supply Decoupling
When ZCD_EN# is set low, zero current detect (ZCD)
will be enabled. If PWM goes high, GH will go high after the
non−overlap delay. If PWM goes low, GL will go high after
the non−overlap delay, and stay high for the duration of the
ZCD blanking timer. Once this timer has expired, VSWH
will be monitored for zero current detection, and will pull
GL low once detected. The threshold on VSWH to
determine zero current undergoes an auto-calibration cycle
every time DISB# is brought from low to high. This
auto-calibration cycle typically takes 25 ms to complete.
The NCP81081 can source and sink relatively large
current to the gate pins of the MOSFETs. In order to
maintain a constant and stable supply voltage (VCIN) a low
ESR capacitor should be placed near the power and ground
pins. A 1 mF to 4.7 mF multi layer ceramic capacitor
(MLCC) is usually sufficient.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(C ) and the internal diode. The bootstrap capacitor must
BST
have a voltage rating that is able to withstand twice the
maximum supply voltage. A minimum 50 V rating is
recommended. A bootstrap capacitance greater than 100 nF
and a minimum 50 V rating is recommended. A good quality
ceramic capacitor should be used.
Safety Timer and Overlap Protection Circuit
It is very important that MOSFETs in a synchronous buck
regulator do not both conduct at the same time. Excessive
shoot−through or cross conduction can damage the
MOSFETs, and even a small amount of cross conduction
will cause a decrease in the power conversion efficiency.
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5
NCP81081
ZCD_EN#
PWM
GH
GL
IL
Figure 4. Zero Current Detection
PWM
GH
GL
t
t
t
holdoff
holdoff
holdoff
Figure 5. Tri−State Operation
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6
NCP81081
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P
MN SUFFIX
CASE 485AZ
ISSUE O
D
A B
NOTES:
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
PIN ONE
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. POSITIONAL TOLERANCE APPLIES TO ALL
THREE EXPOSED PADS.
LOCATION
L1
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
2X
MILLIMETERS
0.15
C
DIM MIN
MAX
1.00
0.05
EXPOSED Cu
MOLD CMPD
A
A1
A3
b
0.80
−−−
0.20 REF
0.18
2X
TOP VIEW
0.15
C
0.30
DETAIL B
(A3)
D
6.00 BSC
0.10
C
C
DETAIL B
D2
D3
E
E2
E3
e
G
K
L
L1
2.30
1.40
2.50
1.60
ALTERNATE
A
43X
CONSTRUCTION
6.00 BSC
4.30
1.90
4.50
2.10
0.08
SIDE VIEW
D2
A1
SEATING
PLANE
NOTE 4
C
0.50 BSC
2.20 BSC
0.20
0.30
−−−
−−−
0.50
0.15
0.10
C A B
NOTE 5
40X L
D3
G
DETAIL A
SOLDERING FOOTPRINT
6.30
E3
4.56
2.56
40X
0.63
E2
1.66
E3
1
1
G
40
K
e
40X b
2.16
e/2
0.10
C
C
A
B
4.56
6.30
G
NOTE 3
0.05
BOTTOM VIEW
2.16
40X
0.30
PKG
OUTLINE
0.50
PITCH
DIMENSIONS: MILLIMETERS
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NCP81081/D
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