NCP81158D [ONSEMI]

Synchronous Buck MOSFET Driver;


型号：	NCP81158D
厂家：	ONSEMI
描述：	Synchronous Buck MOSFET Driver
文件：	总8页 (文件大小：81K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP81158D

Synchronous Buck MOSFET

Driver

The NCP81158D is a high−performance dual MOSFET gate driver

in a small 3 mm x 3 mm package, optimized to drive the gates of both

high−side and low−side power MOSFETs in a synchronous buck

converter. The driver outputs can be placed into a high−impedance

state via the tri−state PWM and EN inputs. The NCP81158D comes

packaged with an integrated boost diode to minimize external

components. A VCC UVLO function guarantees the outputs are low

when the supply voltage is low.

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MARKING

DIAGRAM

Features

1158D

ALYWG

DFN8

CASE 506BJ

• When Device is Powered, Fast PWM Response to EN Going High

• Space−efficient 3 mm x 3 mm DFN8 Thermally−Enhanced Package

• VCC Range of 4.5 V to 5.5 V

1158D = Specific Device Code

= Assembly Location

= Wafer Lot

• Internal Bootstrap Diode

• 5 V 3−stage PWM Input

= Year

• Diode Braking Capability via EN Mid−state

= Work Week

= Pb−Free Package

• Adaptive Anti−cross Conduction Circuit Protects Against

Cross−conduction during FET Turn−on and Turn−off

• Output Disable Control Turns Off Both MOSFETs via Enable Pin

• VCC Undervoltage Lockout

(Note: Microdot may be in either location)

PINOUT DIAGRAM

• These Devices are Pb−free, Halogen−free/BFR−free and are RoHS

Compliant

BST

PWM

DRVH

Typical Applications

FLAG

• Power Solutions for Notebook and Desktop Systems

GND

DRVL

VCC

ORDERING INFORMATION

†

Device

Package

Shipping

NCP81158DMNTXG

DFN8

(Pb−Free)

3000 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

Publication Order Number:

April, 2017 − Rev. 1

NCP81158D/D

NCP81158D

BST

VCC

DRVH

ZCD

Auto−cal

Logic

PWM

Anti−Cross

Conduction

VCC

DRVL

ZCD

Detection

UVLO

VCC

GND

Figure 1. Block Diagram

PIN DESCRIPTIONS

Pin No.

Symbol

Description

BST

Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and

the SW pin.

PWM

Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode

Emulation Enabled, High = High Side FET Enabled.

Logic input. A logic high to enable the part and a logic low to disable the part. Three states logic input:

EN = High to enable the gate driver;

EN = Low to disable the driver;

EN = Mid to go into diode mode (both high and low side gate drive signals are low)

VCC

DRVL

GND

Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground.

Low side gate drive output. Connect to the gate of low side MOSFET.

Bias and reference ground. All signals are referenced to this node.

Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET.

High side gate drive output. Connect to the gate of high side MOSFET.

DRVH

FLAG

Thermal flag. There is no electrical connection to the IC. Connect to ground plane.

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NCP81158D

APPLICATION CIRCUIT

5V_POWER

VIN

0.0

0.1 uF

4.7 uF 4.7 uF 4.7 uF 390 uF

0.0

NCP81158D

0.0

DRVH

BST

PWM

GND

PWM

VCCP

235 nH

2.2

DRON

2700 pF

DRVL

VCC

1 uF

PAD

Figure 2. Application Circuit

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NCP81158D

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL INFORMATION

Symbol

Pin Name

MAX

MIN

Main Supply Voltage Input

6.5 V

7.5 V < 80 ns

−0.3 V

BST

Bootstrap Supply Voltage

35 V wrt/ GND

40 V v 50 ns wrt/ GND

6.5 V wrt/ SW

−0.3 V wrt/SW

7.7 V < 50 ns wrt/ SW

Switching Node (Bootstrap Supply Return)

High Side Driver Output

35 V

40 V v 80 ns

−5 V

−10 V (200 ns)

DRVH

DRVL

BST + 0.3 V

SW + 7 V (< 80 ns)

−0.3 V wrt/SW

−2 V (< 200 ns) wrt/SW

Low Side Driver Output

+ 0.3 V

−0.3 V DC

7 V (< 80 ns)

−5 V (< 200 ns)

PWM

DRVH and DRVL Control Input

Enable Pin

6.5 V

−0.3 V

0 V

6.5 V

GND

Ground

0 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

*All signals referenced to AGND unless noted otherwise.

THERMAL INFORMATION

Symbol

Parameter

Thermal Characteristic QFN Package (Note 1)

Operating Junction Temperature Range (Note 2)

Operating Ambient Temperature Range

Maximum Storage Temperature Range

Value

119

Unit

°C/W

°C

−40 to 150

−40 to +100

−55 to +150

°C

STG

°C

MSL

Moisture Sensitivity Level − QFN Package

*The maximum package power dissipation must be observed.

1. 1 in Cu, 1 oz. thickness.

2. JESD 51−7 (1S2P Direct−Attach Method) with 1 LFM.

NCP81158D ELECTRICAL CHARACTERISTICS (−40°C < T < +100°C; 4.5 V < V < 5.5 V, 4.5 V < BST−SWN < 5.5 V,

4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted)

Parameter

Test Conditions

Min

Typ

Max

Unit

SUPPLY VOLTAGE

VCC Operation Voltage

4.5

5.5

UNDERVOLTAGE LOCKOUT

VCC Start Threshold

3.8

4.35

200

4.5

VCC UVLO Hysteresis

150

250

SUPPLY CURRENT

Shutdown Mode

Normal Mode

+ I , EN = GND

690

4.7

0.9

900

BST

+ I , EN = 5 V, PWM = OSC

BST

Standby Current

+ I , EN = HIGH, PWM = LOW,

BST

No loading on DRVH & DRVL

Standby Current

+ I , EN = HIGH, PWM = HIGH,

1.1

0.4

BST

No loading on DRVH & DRVL

BOOTSTRAP DIODE

Forward Voltage

= 5 V, forward bias current = 2 mA

0.1

0.6

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NCP81158D

NCP81158D ELECTRICAL CHARACTERISTICS (−40°C < T < +100°C; 4.5 V < V < 5.5 V, 4.5 V < BST−SWN < 5.5 V,

4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted)

Parameter

PWM INPUT

Test Conditions

Min

Typ

Max

Unit

PWM Input High

3.4

1.3

PWM Mid−State

2.7

0.7

PWM Input Low

ZCD Blanking Timer

HIGH SIDE DRIVER

350

Output Impedance, Sourcing Current

Output Impedance, Sinking Current

DRVH Rise Time trDRVH

−V

= 5 V

0.9

0.7

1.7

BST SW

−V

BST SW

= 5 V

= 5 V, 3 nF load, V

−V

BST SW

= 5 V

=5 V

DRVH Fall Time tfDRVH

= 5 V, 3 nF load, V

−V

BST SW

DRVH Turn−Off Propagation Delay tpdlDRVH

= 3 nF

LOAD

DRVH Turn−On Propagation Delay tpdhDRVH

SW Pulldown Resistance

SW to PGND

DRVH to SW, BST−SW = 0 V

DRVH Pulldown Resistance

LOW SIDE DRIVER

Output Impedance, Sourcing Current

Output Impedance, Sinking Current

DRVL Rise Time trDRVL

0.9

0.4

1.7

0.8

= 3 nF

LOAD

DRVL Fall Time tfDRVL

DRVL Turn−Off Propagation Delay tpdlDRVL

DRVL Turn−On Propagation Delay tpdhDRVL

5.0

DRVL Pulldown Resistance

EN INPUT

DRVL to PGND, V = PGND

Input Voltage High

3.3

Input Voltage Mid

1.35

1.8

0.6

1.0

Input Voltage Low

Input bias current

−1.0

Propagation Delay Time, Falling

Propagation Delay Time, Rising

SW NODE

EN falling past 0.6V to DRVL @ 90%, PWM = 0V

EN rising past 3.3V to DRVL @ 10%, PWM = 0V

SW Node Leakage Current

Zero Cross Detection Threshold Voltage

−6.0

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Table 1. DECODER TRUTH TABLE

Input

PWM High (Enable High)

PWM Mid (Enable High)

PWM Low (Enable High)

Enable at Mid

ZCD

DRVL

Low

DRVH

High

Low

ZCD Reset

Positive Current Through the Inductor

Zero Current Through the Inductor

ZCD Reset

High

Low

High

Low

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NCP81158D

PWM

DRVL

tpdl_DRVLtf_DRVL

90%

1 V

90%

10%

tpdl_DRVH

tr_DRVL

tf_DRVH

tpdh_DRVHtr_DRVH

90%

10%

tpdh_DRVL

10%

1 V

DRVH−SW

Figure 3. Gate Timing Diagram

PWM

DRVH−SW

DRVL

Figure 4. Timing Diagram

APPLICATION INFORMATION

High−Side Driver

The NCP81158D gate driver is a single−phase MOSFET

driver designed for driving N−channel MOSFETs in a

synchronous buck converter topology.

The high−side driver is designed to drive a floating

low−R N−channel MOSFET. The gate voltage for the

DS(on)

high−side driver is developed by a bootstrap circuit

referenced to the SW pin.

The bootstrap circuit is comprised of the integrated diode

and an external bootstrap capacitor. When the NCP81158D

is starting up, the SW pin is held at ground, allowing the

Low−Side Driver

The low−side driver is designed to drive

ground−referenced low−R N−channel MOSFET. The

voltage supply for the low−side driver is internally

connected to the VCC and GND pins.

DS(on)

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NCP81158D

Three−State PWM Input

bootstrap capacitor to charge up to VCC through the

bootstrap diode. When the PWM input is driven high, the

high−side driver will turn on the high−side MOSFET using

the stored charge of the bootstrap capacitor. As the high−side

MOSFET turns on, the SW pin rises. When the high−side

MOSFET is fully turned on, SW will settle to VIN and BST

will settle to VIN + VCC (excluding parasitic ringing).

Switching PWM between logic−high and logic−low states

will allow the driver to operate in continuous conduction

mode as long as VCC is greater than the UVLO threshold

and EN is high. The threshold limits are specified in the

electrical characteristics table in this datasheet. Refer to

Figure 21 for the gate timing diagrams and Table 1 for the

EN/PWM logic table.

Bootstrap Circuit

The bootstrap circuit relies on an external charge storage

When PWM is set above PWM , DRVL will first turn off

after a propagation delay of tpdl

. To ensure

DRVL

capacitor (C ) and an integrated diode to provide current to

BST

non−overlap between DRVL and DRVH, there is a delay of

tpdh from the time DRVL falls to 1 V, before DRVH is

the high−side driver. A multi−layer ceramic capacitor (MLCC)

DRVH

with a value greater than 100 nF should be used for C

BST

allowed to turn on.

When PWM falls below PWM , DRVH will first turn

off after a propagation delay of tpdl

Power Supply Decoupling

. To ensure

DRVH

The NCP81158D can source and sink relatively large

currents to the gate pins of the MOSFETs. In order to

maintain a constant and stable supply voltage, a low−ESR

capacitor should be placed near the VCC and GND pins. A

MLCC between 1 mF and 4.7 mF is typically used.

non−overlap between DRVH and DRVL, there is a delay of

tpdh from the time DRVH – SW falls to 1 V, before

DRVL

DRVL is allowed to turn on.

When PWM enters the mid−state voltage range, DRVL

goes high after the non−overlap delay, and stays high for the

duration of the ZCD blanking + debounce timers. Once these

timers expire, SW is monitored for zero current detection

and pulls DRVL low once zero current is detected.

Undervoltage Lockout

DRVH and DRVL are low until VCC reaches the VCC

UVLO threshold, typically 4.35 V. Once VCC reaches this

threshold, the PWM signal will control DRVH and DRVL.

There is a 200 mV hysteresis on VCC UVLO. There are

pull−down resistors on DRVH, DRVL and SW to prevent the

gates of the MOSFETs from accumulating enough charge to

turn on when the driver is powered off.

Whenever VCC rises above the VCC UVLO threshold, an

auto−calibration cycle of the ZCD threshold is conducted.

DRVH and DRVL outputs will be pulled low during this

auto−calibration cycle, thus not responding to the PWM

input. The auto−calibration cycle takes 30 ms, typically.

Thermal Considerations

As power in the NCP81158D increases, it might become

necessary to provide some thermal relief. The maximum

power dissipation supported by the device is dependent

upon board design and layout. Mounting pad configuration

on the PCB, the board material, and the ambient temperature

affect the rate of junction temperature rise for the part. When

the NCP81158D has good thermal conductivity through the

PCB, the junction temperature will be relatively low with

high power applications. The maximum dissipation the

NCP81158D can handle is given by:

Three−State EN Input

Placing EN into a logic−high and logic−low will turn the

driver on and off, respectively, as long as VCC is greater than

the UVLO threshold. The EN threshold limits are specified

in the electrical characteristics table in this datasheet. Setting

the voltage on EN to a mid−state level will pull both DRVH

and DRVL low.

ƪ_T

_J(MAX)* T_A

(eq. 1)

P_D(MAX)

R_qJA

Since T is not recommended to exceed 150°C, the

NCP81158D, soldered on to a 645 mm copper area, using

1 oz. copper and FR4, can dissipate up to 1.05 W when the

Setting EN to the mid−state level can be used for body

diode braking to quickly reduce the inductor current. By

turning the LS FET off and having the current conduct

through the LS FET body diode, the voltage at the switch

node will be at a greater negative potential compared to

having the LS FET on. This greater negative potential on

switch node allows there to be a greater voltage across the

output inductor, since the opposite terminal of the inductor

is connected to the converter output voltage. The larger

voltage across the inductor causes there to be a greater

inductor current slew rate, allowing the current to decrease

at a faster rate.

ambient temperature (T ) is 25°C. The power dissipated by

the NCP81158D can be calculated from the following

equation:

(eq. 2)

_{[ VCC @}ƪ

P_D

n_HS@ Qg_HS) n_LS@ Qg_LS@ f ) I_standby

Where n and n are the number of high−side and

low−side FETs, respectively, Qg and Qg are the gate

charges of the high−side and low−side FETs, respectively

and f is the switching frequency of the converter.

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NCP81158D

PACKAGE DIMENSIONS

DFN8 3x3, 0.5P

CASE 506BJ

ISSUE O

EDGE OF PACKAGE

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND 0.30

MM FROM TERMINAL.

PIN 1

REFERENCE

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

DETAIL A

MILLIMETERS

OPTIONAL

DIM MIN

0.80

A1 0.00

MAX

1.00

0.05

CONSTRUCTION

0.10

0.20 REF

0.18

0.30

3.00 BSC

0.10

D2 1.64

E2 1.35

1.84

1.55

TOP VIEW

3.00 BSC

DETAIL A

OPTIONAL

0.50 BSC

DETAIL B

0.05

CONSTRUCTION

0.20

0.30

−−−

0.50

0.03

L1 0.00

0.05

(A3)

SEATING

PLANE

NOTE 4

SOLDERMASK DEFINED

MOUNTING FOOTPRINT

SIDE VIEW

MOLD CMPD

EXPOSED Cu

1.85

DETAIL A

8X L

0.35

DETAIL B

OPTIONAL

8X K

CONSTRUCTION

3.30

1.55

8X b

0.10 C A B

0.05

NOTE 3

BOTTOM VIEW

0.50

PITCH

0.63

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

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NCP81158D/D

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NCP81158D [ONSEMI]

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