NCP81296_技术文档

Hot Swap Smart Fuse

NCP81295, NCP81296

The NCP81295 and NCP81296 are 50 A, electronically re−settable,

in−line fuses for use in 12 V, high current applications such as servers,

storage and base stations. The NCP81295/6 offers a very low 0.65 mW

integrated MOSFET to reduce solution size and minimize power loss.

It also integrates a highly accurate current sensor for monitoring and

overload protection.

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Power Features

MARKING

DIAGRAM

• Co−packaged Power Switch, Hotswap Controller and Current Sense

• Up to 60 A Peak Current Output, 50 A Continuous

• Vin Range: 4.5 V to 18 V

1

• 0.65 mW, no R

Required

SENSE

NCP8129x

AWLYYWWG

G

32

1

Control Features

• Enable Input

• Optional Enable−controlled Output Pulldown when Disabled

• Programmable Soft−Start

• Programmable, Multi−level Current Limit

Reporting Features

• Accurate Analog Load Current Monitor

• Programmable Over Current Alert Output

• Analog Temperature Output

• Status Fault OK Output

LQFN32 5x5, 0.5P

CASE 487AA

NCP8129x = Specific Device Code

x

A

WL

YY

WW

G

= 5 or 6

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

= (may or may not be present)

(Note: Microdot may be in either location)

Other Features

• 5 mm x 5 mm QFN32 Package

PINOUT

• Operating Temperature: −40°C to 125°C

• Can be Paralleled for Higher Current Applications

• Built−in Insertion Delay for Hotswap Applications

• NCP81295: Latch off for Following Protection Features

NCP81296: Auto−Retry Mode for Following Protection Features

♦ Current−limit after Delay

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

NCP81295/6

(TOP VIEW)

33

VIN

♦ Fast Short−circuit Protection

♦ Over−Temperature Shutdown

♦ Excessive Soft−start Duration

• Internal Switch Fault Diagnostics

• Low−power Auxiliary Output Voltage

For more details see Figure 1.

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of

this data sheet.

1

Publication Order Number:

April, 2020 − Rev. 12

NCP81295/D

NCP81295, NCP81296

CLREF

CS

NC4

1

2

3

4

5

6

7

8

24

23

NC5

D_OC

IMON

VDD

22

21

20

19

NCP81295 /6

(TOP VIEW)

ON

GOK

NC1

VINF

NC2

33

VIN

GND

SS

VTEMP

GATE

18

17

Figure 1. Pin Configuration

Ordering Information

Table 1. AVAILABLE DEVICES

Device

†

Package

QFN32

Shipping

NCP81295MNTXG

NCP81296MNTXG

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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2

NCP81295, NCP81296

System VIN

VIN

VINF

VDD

GOK

D_OC

Fuse−protected

System VIN

ON

VOUT

NCP81295/ 6

VTEMP

IMON

CS

SS

GATE

CLREF

GND

Figure 2. Typical Application

Main

System

Power

Main Efuse

Input

Voltage

Main System

Main Efuse

E−Fuse

Control/

Monitor

E−Fuse

Control/

Monitor

PMBSUS Control and

Monitor

mController

E−Fuse

IMON

Standby

System

Power

Standby

System

Standby Efuse

E−Fuse

Control/

Monitor

Figure 3. Typical Application Diagram

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3

NCP81295, NCP81296

System VIN

VIN

VINF

VDD

NCP81295

mController

FAULT IN

GOK

OVERCURRENT IN

ENABLE OUT

D_OC

Fuse−protected

System VIN

ON

VOUT

GATE

TEMP MONITOR A/D IN

VTEMP

CURRENT MONITOR A/D IN

CURRENT LIMIT D/A OUT

IMON

SS

CS

CLREF

GND

VIN

VINF

VDD

NCP81295

GOK

D_OC

ON

VOUT

GATE

VTEMP

IMON

SS

CS

CLREF

GND

VIN

VINF

VDD

NCP81295

GOK

D_OC

ON

VOUT

GATE

VTEMP

IMON

SS

CS

CLREF

GND

Figure 4. Application Schematic − Parallel Fuse Operation with Controller

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4

NCP81295, NCP81296

System VIN

VIN VINF

mController

FAULT IN

GOK

VDD

GATE

D_OC

OVERCURRENT IN

ENABLE OUT

ON NCP81295/6

Fuse Protected

System VIN

TEMP MONITOR A/D IN

VTEMP

VOUT

CS

SS

CLREF

IMON

CURRENT LIMIT D/A OUT

CURRENT MONITOR A/D IN

GND

Figure 5. Application Schematic − Single EFuse with Controller

System VIN

VIN VINF

GOK

VDD

GATE

D_OC

ON

NCP81295/6

Fuse Protected

System VIN

VOUT

VTEMP

CS

SS

CLREF

IMON

GND

Figure 6. Application Schematic − Stand−alone Single EFuse

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5

NCP81295, NCP81296

System VIN

VIN

VINF

VDD

NCP81295

GOK

D_OC

Fuse−protected

System VIN

ON

VOUT

GATE

VTEMP

IMON

SS

CS

CLREF

GND

VIN

VINF

VDD

NCP81295

GOK

D_OC

ON

VOUT

GATE

VTEMP

IMON

SS

CS

CLREF

GND

VIN

VINF

VDD

NCP81295

GOK

D_OC

ON

VOUT

GATE

VTEMP

IMON

SS

CS

CLREF

GND

Figure 7. Application Schematic − Stand−alone Parallel EFuse

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6

NCP81295, NCP81296

VIN

9−16

VOUT > 90 % VIN

VOUT > 80 % VIN

SENSEFET

1:5000

OUTPUT

MONITOR

VOUT > 70 % VIN

VOUT > 40 % VIN

VINF

VDD

7

CHARGE

PUMP

5V

LDO

VINF+2XVDD

VOUT

-32

25−32

21

500

EN

VDD

PD

VDD_UVR

5 mA

SS

19

ISC

A_IMON

A_CS

IMON

CS

22

23

VDD

VOUT>90%VIN

VOUT>70%VIN

DRAIN MON

GATE MON

5

mA

VDD

ON

4

10 mA

OVERCURRENT

TIMER

CLREF

24

3

V

SWON

D_OC

VCL_MAX

V

SWOFF

LOGIC

VCL_HI

VCL_LO

VDD

DIE TEMP

MONITOR

VOC_TH(85% CLREF)

VOUT>80%VIN

VOUT>40

%VIN

GOK

5

VTEMP

GND

18

20

50 mA

Figure 8. Block Diagram

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7

NCP81295, NCP81296

Table 2. PIN DESCRIPTION

Pin No.

Symbol

NC4

Description

1

2

3

No electrical connection internally. May connect to any potential

NC5

D_OC

Overcurrent indicator output (open drain). Low indicates the NCP81295 is limiting current. The D_OC

output does not report current limiting during soft−start.

4

5

ON

Enable input and output pulldown resistance control.

OK status indicator output (open drain). Low indicates that the NCP81295 was turned off by a fault.

Test pin. Do not connect to this pin. Leave floating

Control circuit power supply input. Connect to VIN pins through an RC filter. (1 W / 0.1 mF)

Internal FET sense pin. Do not connect to this pin. Leave floating

Input of high current output switch

GOK

6

NC1

7

VINF

8

NC2

9

VIN09

VIN10

VIN11

VIN12

VIN13

VIN14

VIN15

VIN16

GATE

10

11

12

13

14

15

16

17

Input of high current output switch

Internal FET gate pin. Connect to the cathode of an anode grounded diode such as BAS16P2T5G. A

4.7 nF ceramic capacitor is reserved between this pin and GND for NCP81295 to mitigate the oscilla-

tion risk when small amount of output capacitance (< 100 mF) or long input/output cable (large L

OUT

/

IN

L

) happens.

18

19

20

21

22

23

VTEMP

SS

Analog temperature monitor output.

Soft Start time programming pin. Connect a capacitor to this pin to set the softstart time.

GND

VDD

IMON

CS

Ground

Linear regulator output

Analog current monitor output

Current sense feedback output (current). Scaling the voltage developed at this pin with a resistor to

ground makes this also an input for several current limiting functions and overcurrent indicator D_OC.

24

25

26

27

28

29

30

31

32

33

CLREF

VOUT25

VOUT26

VOUT27

VOUT28

VOUT29

VOUT30

VOUT31

VOUT32

VIN33

Current limit setpoint input for normal operation (after soft−start).

Output of high current output switch

Input of high current output switch

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8

NCP81295, NCP81296

Table 3. MAXIMUM RATINGS

Rating

Symbol

VINx, VINF

VOUTx

Min

−0.3

Max

20

Unit

V

Pin Voltage Range (Note 1) Vout enabled

Pin Voltage Range (Note 1) Vout disabled (Note 2)

Pin Voltage Range (Note 1)

30

V

−0.3

−1(<500 ms)

20

V

Pin Voltage Range (Note 1)

Pin Voltage Range (Note 3)

Operating Junction Temperature

Storage Temperature Range

VDD

−0.3

6.0

VDD + 0.3

150

V

All Other Pins

V

T

°C

J(max)

T

STG

−55

150

Lead Temperature Soldering

Reflow (SMD Styles Only), Pb−Free Versions (Note 4)

T

SLD

260

Electrostatic Discharge − Charged Device Model

Electrostatic Discharge − Human Body Model

ESD

2.0

2.5

kV

CDM

HBM

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. All signals referenced to GND unless noted otherwise.

2. Vout disable is the state of output OFF when internal FET has turned off by disable ON or FAULTs protection.

3. Pin ratings referenced to VDD apply with VDD at any voltage within the VDD Pin Voltage Range.

4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

Table 4. THERMAL CHARACTERISTICS

Rating

Symbol

Value

30

Unit

°C/W

Thermal Resistance, Junction−to−Ambient (Note 5)

Thermal Resistance, Junction−to−Top−Case

Thermal Resistance, Junction−to−Bottom−Case

Thermal Resistance, Junction−to−Board (Note 6)

Thermal Resistance, Junction−to−Case (Note 7)

R

θ

JA

R

50

θ

JCT

R

1.5

θ

JCB

R

θ

JB

R

θ

JC

2

5. R

6. R

7. R

is obtained by simulating the device mounted on a 500 mm , 1−oz Cu pad on a 80 mm x 80 mm, 1.6 mm thick 8−layer FR4 board.

q

JA

JB

JC

value based on hottest board temperature within 1 mm of the package.

≈ R

// R

(Two−Resistor Compact Thermal Model, JESD15−3).

q

JCT

JCB

Table 5. RECOMMENDED OPERATING RANGES

Parameter

Symbol

Min

Max

18

Unit

V

VIN, VINF Pin Voltage Range

Maximum Continuous Output Current

Peak Output Current

4.5

I

50

A

AVE

I

60

A

PEAK

VDD Output Load Capacitance Range

VTEMP Output Load Capacitance Range

Softstart Duration

C

2.2

0.1

10

mF

ms

kW

V

VDD

C

VTEMP

T

100

4

SS

CS

CS Load Resistance Range

CLREF Voltage Range

R

1.8

0.2

−40

V

1.4

125

CLREF

Operating Junction Temperature

T

J(OP)

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

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9

NCP81295, NCP81296

Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, V = 3.3 V, C

= 0.1 mF, C

= 4.7 mF, C = 0.1 mF,

VTEMP

ON

VINF

VDD

R

= 1 kW, C = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ T = T ≤ 125°C

VTEMP

S

A

J

unless noted otherwise, and are guaranteed by design and characterization through statistical correlation.

Parameter

VINF INPUT

Symbol

Test Conditions

Min

Typ

3.23

2.38

Max

Units

Quiescent Current

V

ON

V

ON

V

ON

V

ON

> 1.4 V, no load

> 1.4 V, fault

5.0

4.0

mA

< 0.8 V

< 0.8 V, VINF = 16 V

VDD REGULATOR

VDD Output Voltage

VDD Load Capability

VDD Current Limit

VDD Dropout Voltage

UVLO threshold − rising

UVLO threshold − falling

ON INPUT

V

I

= 0 mA, VINF = 6 V

4.7

50

5.09

5.3

30

V

DD_NL

VDD

I

VINF = 5.5 V

mA

mV

V

DDLOAD

I

VINF = 12 V and VINF = 6 V

70

85

DD_CL

I

= 25 mA, VINF = 4.5 V

200

4.5

4.2

VDD

V

4.1

3.8

4.3

4.0

DD_UVR

V

DD_UVF

Bias Current

I

From pin into a 0 V or 1.5 V source

4.0

5.0

1.4

1.2

6.0

mA

V

ON

Switch ON Threshold

V

1.33

1.13

1.47

1.27

SWON

Switch OFF/ Pulldown Upper

Threshold

V

SWOFF

Pulldown Lower Threshold

Switch ON Delay Timer

V

0.8

1.0

V

PDOFF

t

From ON transitioning above V

start

to SS

0.6

2.5

ms

ON

SWON

Switch OFF Delay Time

(Note 8)

t

From ON transitioning below V

pulldown

to GATE

1.7

3.0

ms

V

OFF

SWOFF

ON Current Source Clamp

Voltage

V

t

Max pullup voltage of current source

ON_CLMP

PD_DEL

Load Pulldown Delay Timer

From ON transitioning into the range between

2.0

ms

kW

V

and V

PDOFF

SWOFF

Output Pulldown Resistance

SS PIN

R

= 12 V, PD mode = 1

OUT

0.77

PD

Bias Current

I

From pin into a 0 V or 1 V source

0.1 mA into pin during ON delay

4.62

9.6

5.15

10

5.62

10.4

mA

V/V

mV

SS

Gain to VOUT

AV

SS

SS Pulldown Voltage

GOK OUTPUT

V

22

OL_SS

Output Low Voltage

Off−state Leakage Current

V

I

= 1 mA

0.1

1.0

V

OL_GOK

GOK

I

V

= 5 V

mA

LK_GOK

GOK

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. Guaranteed by design or characterization data. Not tested in production.

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10

NCP81295, NCP81296

Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, V = 3.3 V, C

= 0.1 mF, C

= 4.7 mF, C = 0.1 mF,

VTEMP

ON

VINF

VDD

R

= 1 kW, C = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ T = T ≤ 125°C

VTEMP

S

A

J

unless noted otherwise, and are guaranteed by design and characterization through statistical correlation.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Units

IMON/CS OUTPUT

IMON or CS Current

(single EFuse)

I

/I

T = 0 to 85°C

IOUT = 5 A (Note 8)

IOUT = 10 A (Note 8)

IOUT = 25 A (Note 8)

IOUT = 50 A (Note 8)

IOUT = 5 A (Note 8)

IOUT = 10 A (Note 8)

IOUT = 25 A (Note 8)

IOUT = 50 A (Note 8)

55

mA

%

IMON CS

J

105

255

505

Based on 10 mA/A+5 mA

Accuracy (single EFuse)

T = 0 to 85°C

J

−6

−4

+6

+4

%

IMON or CS Current Source

Clamp Voltage

V

/

Max pullup voltage of current source

3.0

5.0

V

IM_CLMP

CS_CLMP

Pre−Biased Offset Current

Load for Auto−Zero Op−Amp

I

mA

AZ_BIAS

CURRENT LIMIT & CLREF PIN

Current Limit Voltage

V

If V > VCL_TH current limiting regulation

95

98

101

12

%V

CLREF

CL_TH

CS

occurs via gate

Current Limit Enact Offset

Voltage

V

0.2 V < V

< 1.4 V

−70

−24

mV

ENACT

CLREF

Current Limit Clamp Voltage

V

VOUT < 40% VIN, V

> 0.15 V

135

480

152

504

165

520

mV

CL_LO

CLREF

V

CL_HI

40% VIN < VOUT < 80% VIN

> 0.5 V

V

CLREF

Max Current Limit Reference

Voltage

V

VOUT > 80% VIN, V

> 1.6 V

1.55

9.6

1.6

1.65

10.4

V

CL_MX

CLREF

Response Time (Note 8)

CLREF Bias Current

t

V

CS

> V until current limiting

CLREF

200

10

ms

mA

V

CL_REG

I

From pin into a 1.2 V source

CL

CL_CLMP

CLREF Current Source

Clamp Voltage

V

Max pullup voltage of current source

3.0

FET Turn−off Timer

t

Delay between current limit detection and FET

turn−off (GOK = 0)

250

ms

CL_LA

D_OC OUTPUT

Overcurrent Threshold

Output Low Voltage

Off−state Leakage Current

Delay (rising) (Note 8)

Delay (falling) (Note 8)

VOC_TH

If V > VOC_TH D_OC pin pulls low

83

86

90

0.1

1.0

%V

CLREF

CS

V

I

= 1 mA

V

OL_DOC

LK_DOC

DOC

I

V

= 5 V

−

mA

ms

DOC

< limit until D_OC rising

> limit until D_OC falling

1.0

CS

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. Guaranteed by design or characterization data. Not tested in production.

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11

NCP81295, NCP81296

Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, V = 3.3 V, C

= 0.1 mF, C

= 4.7 mF, C = 0.1 mF,

VTEMP

ON

VINF

VDD

R

= 1 kW, C = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ T = T ≤ 125°C

VTEMP

S

A

J

unless noted otherwise, and are guaranteed by design and characterization through statistical correlation.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Units

SHORT CIRCUIT PROTECTION

Current Threshold (Note 8)

I

NCP81295

NCP81296

100

80

A

SC

Response Time (Note 8)

VTEMP OUTPUT

Bias Voltage

t

From I

> I

until gate pulldown

500

ns

OUT

LIMSC

V

At 25°C

450

10

1

mV

mV/°C

kW

VTEMP25

°

Gain (Note 8)

A TEMP

0 C ≤ T ≤ 125 C

V

J

Load Capability

R TEMP

At 25°C

V

Pulldown Current

THERMAL SHUTDOWN

I TEMP

50

mA

V

Temperature Shutdown

(Note 8)

T

TSD

GOK pulls dow

140

°C

OUTPUT SWITCH (FET)

On Resistance

R

T = 25°C

0.65

1.0

mW

mA

DSon

J

Off−state leakage current

FAULT detection

I

VIN = 16 V, V < 1.2 V, T = 25°C

ON J

DSoff

V

Short Threshold

VDS_TH

VDS_OK

VDG_TH

VDG_OK

VG_TH

Startup postponed if VOUT > VDS_TH at V

88.8

68.6

3.1

%VIN

V

DS

GD

ON

> V

transition

SWON

Short OK Threshold

Short Threshold

Startup resumed if VOUT < VDS_OK anytime

after postponed

Startup postponed if V > VDG_TH at V

SWON

>

G

ON

V

transition

Short OK Threshold

Startup resumed if V < VDG_OK anytime af-

3.0

V

G

ter postponed

Low Threshold

Latch/Restart if V < VG_TH after t

SSF_END

5.4

V

G

GD

or t

GATE_FLT

Low Threshold

V

Latch/Restart if V < VOUTL_TH after

OUT

90

%VIN

ms

OUT

OUTL_TH

t

SSF_END

Gate Fault Timer (Note 8)

t

Time from V < V

SSF_END

transition after

200

GATE_FLT

GD

G_TH

t

completed

Startup Timer Failsafe

(Note 8)

t

Time from V > V

transition,

ms

SSF_END

ON

SWON

Max programmable softstart time

AUTO−RETRY (NCP81296)

Auto−Retry Delay

t

Delay from power−down to retry of startup

1000

ms

DLY_RETRY

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. Guaranteed by design or characterization data. Not tested in production.

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NCP81295, NCP81296

TYPICAL CHARACTERISTICS

Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, R

= 121 kW, R

= 2 kW

CLREF

IMON

600

500

400

300

200

600

500

400

300

200

100

0

100

0

10

20

30

40

50

60

0

10

20

30

40

50

60

LOAD CURRENT (A)

Figure 9. Ics vs. Load Current

Figure 10. Imon vs. Load Current

600

500

600

500

50 A

30 A

50 A

400

300

200

400

300

200

30 A

100

0

100

0

−50 −25

0

25

50

75

100

125 150

−50 −25

0

25

50

75

100

125 150

TEMPERATURE (°C)

Figure 11. Ics vs. Temperature

Figure 12. Imon vs. Temperature

1.0

1600

0.9

0.8

0.7

1400

1200

1000

800

0.6

0.5

0.4

0.3

0.2

600

400

200

0

0.1

0

−60 −40 −20

0

20 40

60 80 100 120 140

−60 −40 −20

0

20 40 60

80 100 120 140

TEMPERATURE (°C)

Figure 13. Output Switch R_DS(on)@ 22 A vs.

Temperature

Figure 14. Vtemp vs. Temperature (no load)

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13

NCP81295, NCP81296

TYPICAL CHARACTERISTICS

Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, R

= 121 kW, R

= 2 kW

CLREF

IMON

0

−1

−2

−3

−4

2500

2000

1500

1000

Power Loss

500

0

−5

−6

−60 −40 −20

0

20 40 60 80 100 120 140

0

10

20

30

40

50

60

TEMPERATURE (°C)

OUTPUT CURRENT (A)

Figure 15. Output Switch Off−state Leakage

Figure 16. Power Loss vs. Load Current

vs. Temperature

1000

100

10

100 ms

250 ms

1 ms

10 ms

100 ms

1 s

1

R

Limit

DS(ON)

10 s

Single Pulse

= 24.8 °C/W

T = 25°C

A

0.1

Dotted Lines: Measured SOA

Solid Lines: Calculated SOA

R

q

JA

0.01

0.1

1

10

20

V

DS

, DRAIN−SOURCE VOLTAGE (V)

Figure 17. Internal FET’s Safe Operating Area (SOA)

100k

250

200

150

10k

1k

T = 25°C

A

100

50

0

100

10

1

T = 25°C

A

T = 85°C

A

T = 85°C

A

0.00001 0.0001 0.001 0.01

0.1

1.0

10

100

1k

0.01

0.2 0.3

0.4 0.5

0.6 0.7

0.8 0.9

0.1

PULSE WIDTH (s)

Figure 18. Single Pulse Power Rating (10 ms −

1000 s, Junction−to−Ambient, Note 4)

Figure 19. Single Pulse Power Rating (10 ms −

100 ms, Junction−to−Ambient, Note 4)

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14

NCP81295, NCP81296

TYPICAL CHARACTERISTICS

Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, R

= 121 kW, R

= 2 kW

CLREF

IMON

Figure 20. Start Up by VIN (Iout = 0 A)

Figure 21. Shut Down by VIN (Iout = 0 A)

Figure 22. Start Up by VIN (Iout = 15 A)

Figure 23. Shut Down by VIN (Iout = 15 A)

Figure 24. Start Up by EN (Iout = 0 A)

Figure 25. Shut Down by EN (Iout = 0 A)

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15

NCP81295, NCP81296

TYPICAL CHARACTERISTICS

Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, R

= 121 kW, R

= 2 kW

CLREF

IMON

Figure 26. Start Up by EN (Iout = 15 A)

Figure 27. Shut Down by EN (Iout = 15 A)

Figure 28. Short Circuit during Normal

Operation (Iout = 0 A)

Figure 29. Short Circuit during Normal

Operation (Iout = 50 A)

Figure 30. Short FET’s Gate During Normal

Operation (Iout = 2.5 A)

Figure 31. DOC Index for Current Limit during

Normal Operation (Iout = 51.8 A)

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16

NCP81295, NCP81296

TYPICAL CHARACTERISTICS

Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, R

= 121 kW, R

= 2 kW

CLREF

IMON

Figure 32. OCP during Normal

Operation(Iout=60.2A)

Figure 33. OCP during Power Up by Enable

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17

NCP81295, NCP81296

General Information

t

(ms)

C

(nF)

t

(ms)

C

(nF)

SS

The NCP81295/6 is an N−channel MOSFET

co−packaged with a smart hotswap controller. It is suited for

high−side current limiting and fusing in hot−swap

applications. It can be used either alone, or in a paralell

configuration for higher current applications.

10

47

60

270

20

30

40

50

82

70

80

330

470

120

180

220

90

100

VDD Output (Auxiliary Regulated Supply)

An internal linear regulator draws current from the VINF

pin to produce and regulate voltage at the VDD pin. This

The maximum load capacitor value NCP81295/6 can

power up depends on the device soft−start time. When

auxiliary output supply is current−limited to I

. A

DD_CL

V

= 12 V, R = 2 kW, R

= 2.4 W, their relationship

IN

CS

LOAD

ceramic capacitor in the range of 2.2 mF to 10 mF must be

placed between the VDD and GND pins, as close to the

NCP81295/6 as possible. The voltage difference between

VIN and VINF pin voltage should be within 0.4 V for better

CS/IMON performance. Small time constant R/C filter such

as 1 W/0.1 mF on the VINF pin is recommended.

for different paralleled operations are shown as below chart

(above line device shuts down safely due to protection,

below line device powers up successfully without trigger

protection):

ON Input (Device Enable)

When the ON pin voltage (V ) is higher than V

,

ON

SWON

and no undervoltage (UVLO) or output switch faults are

present, the output switch turns on. When V is lower than

ON

V

SWOFF

, the output switch is off. If V is between V

ON PDOFF

and V

for longer than t , the output switches

PD_DEL

SWOFF

off, and a pulldown resistance to ground, of R , is applied

PD

to VOUT. In other words, there is behavior as follows:

• When V < 0.8 V, FET turns off.

ON

• When 0.8 V < V < 1.2 V, VOUT will discharge with

ON

ꢀ 15 mA.

• When V > 1.2 V, FET turns on.

ON

For standalone applications, the ON pin sources current

I

, which can be used to delay output switch turn−on for

GOK Output (Gate OK)

ON

some time after the appearance of input voltage by

connecting a capacitor from the ON pin to ground.

A bi−level control signal driving to ground can be biased

up with a resistive divider to produce ON input levels

The GOK pin is an open−drain output that is pulled low to

report the fault under the following conditions:

• V voltage is below UVLO voltage at any time.

DD

• V disabled and V

is false

ON

DS_OK

between V

< V < V

and V > V

in

PDOFF

ON

SWON

ON

SWON

(indicates a short from VIN to VOUT).

• V disabled and V is false

order to always apply the output pulldown when the output

switch is off.

ON

DG_OK

(indicates a short from GATE to VIN).

is false at t

SSF_END

SS Output (Soft−Start)

When the output switch first turns on, it does so in a

controlled manner. The output voltage (VOUT) follows the

• V enabled and V

ON

SS_OK

(indicates VOUT < 90% after soft−start completes

− FET latches off for NCP81295/auto−retries for

NCP81296).

voltage at the SS pin, produced by current I into a capacitor

SS

from SS to ground. The duration of soft−start can be

programmed by selection of the capacitor value. In parallel

fuse applications, the SS pins of all fuses should be shorted

together to one shared SS capacitor. Internal soft−start load

balancing circuity will ensure the soft−start current is shared

between paralleled devices, so as not to stress one device

more than another or hit a soft start−current limit.

• V enabled and V is below V

at t

ON

G

G_TH

SSF_END

(indicates leakage on GATE in startup – FET latches off

for NCP81295/auto−retries for NCP81296).

• V enabled and V is below V

after t

ON

G

G_TH

GATE_FLT

(indicates leakage on GATE during normal operation

– FET latches off for NCP81295/auto−retries for

NCP81296).

The soft−start capacitor value can be calculated by:

• V enabled and a current−limiting condition lasts

ON

C

SS

= (t * I * AV )/VIN (where t is the target

SS SS SS SS

longer than t

OC_LA

soft−start time). The recommended range of t is 10 −

SS

(FET latches off for NCP81295/auto−retries for

NCP81296).

100 ms (see Table 5).

The typical C values for different t are listed below:

SS

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18

NCP81295, NCP81296

During startup (V > V

current limit reference voltage is clamped according to the

following:

for less than t

), the

• V enabled and device temperature is above T

SWON

SS_END

ON

TSD

(indicates an over−temperature is detected − FET

latches off for NCP81295/auto−retries for NCP81296).

• When VOUT < 40% of VIN, V

= V

or

CL_TH

CL_LO

Usually GOK can’t be used as power good to indicate the

output voltage is in the normal range. Bringing VDD below

the UVLO voltage is required to release a latching condition.

V

CLREF

(whichever is lower).

• When VOUT is between 40% and 80% of VIN,

= V or V (whichever is lower).

V

CL_TH

CL_HI

CLREF

IMON Output (Current Monitor)

The IMON pin sources a current that is A

times the VOUT output current and plus I

connected from the IMON pin to ground can be used to

monitor current information as a voltage up to V . A

capacitor of any value in parallel with the IMON resistor can

be used to low−pass filter the IMON signal without affecting

any internal operation of the device.

• When VOUT exceeds 80% of VIN, V

= V

CL_MX

CL_TH

(10 mA/A)

. A resistor

IMON

or V

(whichever is lower).

CLREF

AZ_BIAS

If a current limiting condition exists anytime for a

continuous duration > t , then the device latches off

CL_LA

IM_CLMP

(NCP81295) or restarts (NCP81296).

The CS pin must have no capacitive loading other than

parasitic device/board capacitance to function correctly. The

recommended range of R is 1.8 − 4 kW (see Table 5).

CS

CLREF Pin (Current Limit and Over−Current Reference)

The CLREF pin voltage determines the current−limit

regulation point and over−current indication point via its

interaction with the CS pin voltage. The CLREF voltage can

be applied by an external source, such as a hot−swap

controller or D−to−A converter, or developed across a

programming resistor to ground by the CLREF bias current,

CS AMP OFFSET BIAS

NCP81295/6 use an auto−zero Op−Amp with low input

offset to sense current in FET with high−accuracy, and an

pre−biased offset current load, I

is need for this

AZ_BIAS

Op−Amp to always keep it to maintain this low input offset

(<100 mV). The internal IMON and CS current source

follow below relationship:

I

. The recommended range of CLREF voltage is 0.2 −

CL

I_CS* I_{AZ_BIAS}

1.4 V (see Table 5).

I_OUT

+

(eq. 3)

10 m

CS Input/Output (Current Set)

and

The CS pin is both an input and an output. The CS pin

sources a current that is A (10 mA/A) times the VOUT

CS

I_MON* I_{AZ_BIAS}

+

(eq. 4)

I_OUT

current and plus I . This produces a voltage on the CS

AZ_BIAS

10 m

pin that is the product of the CS pin current and an external

CS pin resistance to ground.

For typical 5 mA I

, there has 0.5 A positive off−set

AZ_BIAS

in I

sense.

OUT

The voltage generated on V determines the D_OC

CS

over−current indicator trip point and the current−limit

regulation point, via its interaction with the voltage on

CLREF pin.

D_OC Output (Over−current Indicator)

The D_OC pin is an open−drain output that indicates

when an over−current condition exists after soft−start is

complete. When the voltage on the CS pin is higher than

When the voltage on the CS pin is higher than V

,

OC_TH

D_OC is pulled low. If the CS pin voltage drops below

, the D_OC pin is released to and gets pulled high by

V

, D_OC is pulled low. If output current drops below

, the D_OC pin is released and gets pulled high by

OC_TH

V

OC_TH

the external pullup resistor. D_OC transitions based on the

following formula:

an external pullup resistor.

VTEMP Output (Temperature Indicator)

V

)V

OC_TH

ENACT

* I_{AZ_BIAS}

VTEMP is a voltage output proportional to device

temperature, with an offset voltage. The VTEMP output can

source much more current than it can sink, so that if multiple

VTEMP outputs are connected together, the voltage of all

VTEMP outputs will be driven to the voltage produced by

the hottest NCP81295/6. A 100 nF capacitor or greater must

be connected from the VTEMP pin to ground.

R

CS

(eq. 1)

I_OUT

+

10 m

The V

trip point is based on a percentage of V

CLREF

OC_TH

(86%).

During normal operation (V > V

for longer than

SWON

ON

t

), if the voltage on the CS pin is above V

SS_END

CL_TH

(V

is clamped at V

if V

> V ), then

CL_MX

CL_TH

CL_MX

CL_TH

the gate voltage of the FET is modulated to limit current into

the output based on the following formula:

V

)V

CL_TH

ENACT

* I_{AZ_BIAS}

R

CS

(eq. 2)

I_OUT

+

10 m

The V

regulation point is equal to V

.

CL_TH

CLREF

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19

NCP81295, NCP81296

Auto−Retry Restart (NCP81296)

Under certain fault conditions, the FET is turned off and

another soft−start procedure takes place. Between the fault

and the new soft−start, there is a delay of t

• VIN to VOUT short, non−latching/non−auto−retry

condition. If the device is disabled and

VOUT > V

then GOK is pulled low and the

DS_TH

. The

DLY_RETRY

device is prevented from powering up. The device is

allowed to power up once VOUT < V

protection features that use this hiccup mode restart are:

.

DS_OK

• Over−Current

• Short−Circuit Detection

• Over−Temperature

• Excessive Soft−Start Duration

• Gate Leakage

• GATE to VIN short, non−latching/non−auto−retry

condition. If the device is disabled and

GATE (Pin 8) > V

, then GOK is pulled low and

DG_TH

device is prevented from powering up. The device

allowed to power up once GATE < V

DG_OK.

• GATE leakage − startup.

Protection Features

If (GATE – VINF) < V

at t

, then GOK is

G_TH

SSF_END

For the following protection features, the FET either

latches off (NCP81295) or the FET turns off and initiates a

restart (NCP81296), unless noted otherwise.

pulled low and FET latches/restarts.

• GATE leakage − normal operation.

If (GATE – VINF) < V

for t

time after

G_TH

GATE_FLT

the soft−start timer completes, then GOK is pulled low

and device latches/restarts.

Excessive Current Limiting

If a current limiting condition exists anytime for a

continuous duration > t

, then the FET latches/restarts.

CL_LA

FET SOA Limits

In−built timed current limits and fault−monitoring circuits

ensure the copackaged FET is always kept within SOA

limits.

Excessive Soft−Start Duration

If VOUT < V

when t

expires, then the

SSF_END

OUTL_TH

FET latches/restarts.

Multiple Fuse Power Up

Short Circuit Detection

When multiple NPC81295 are paralleled together as

shown in Figure 4, the NPC81295s will turn on together.

Keeping the current through each switch within 1 A (typical)

helps to prevent overstress on each switching during

soft−start.

If switch current exceeds I , the device reacts within t

,

SC

and the FET latches/restarts. The short−circuit current

monitor is independent of CS, CLREF, IMON and current

limit setting (cannot be changed externally).

Due to NCP81296 is featured by Auto−Retry Mode

protection, please follow the below reference schematic

of NCP81296 for paralleled operation.

Over−Temperature Shutdown

If the FET controller temperature > T

latches/restarts.

, then the FET

TSD

FET Fault Detection

The device contains various FET monitoring circuits:

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20

NCP81295, NCP81296

When paralleled multiple NPC81295 encounter fault, the system can recover the E−fuse by resetting their VDD with below

buffer and reset circuit.

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21

NCP81295, NCP81296

22nF

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22

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

LQFN32 5x5, 0.5P

CASE 487AA

ISSUE A

DATE 03 OCT 2017

32

SCALE 2:1

1

A

B

D

NOTES:

L

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

REFERENCE

DETAIL A

ALTERNATE

E

CONSTRUCTION

MILLIMETERS

DIM MIN

MAX

1.40

0.05

0.10

C

A

A1

A3

b

1.20

−−−

0.20 REF

0.18

A3

0.10

C

0.30

3.50

0.50

TOP VIEW

D

5.00 BSC

D2 3.30

A1

E

5.00 BSC

DETAIL B

(A3)

E2 3.30

DETAIL B

0.10

0.05

C

e

L

0.50 BSC

0.30

ALTERNATE

CONSTRUCTION

A

L2

0.13 REF

GENERIC

MARKING DIAGRAM*

SEATING

PLANE

A1

NOTE 4

L2

C

SIDE VIEW

1

D2

DETAIL A

L2

K

9

XXXXXXXX

AWLYYWWG

G

DETAIL C

17

24

4 PLACES

32X

L

E2

DETAIL C

XXXXX = Specific Device Code

1

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

32

25

WL

YY

WW

G

32X b

e

e/2

M

0.10

C A B

NOTE 3

0.05

C

BOTTOM VIEW

(Note: Microdot may be in either location)

RECOMMENDED

*This information is generic. Please refer

to device data sheet for actual part

marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present. Some prod-

ucts may not follow the Generic Marking.

SOLDERING FOOTPRINT*

5.30

32X

0.63

3.60

5.30

0.50

PITCH

32X

0.30

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON11454G

LQFN32, 5x5, 0.5P

PAGE 1 OF 1

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1


型号：	NCP81296
厂家：	ONSEMI
描述：	Hot Swap Smart Fuse
文件：	总24页 (文件大小：1232K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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