NCP81566MNTXG [ONSEMI]
8 + 1 Phase Output Controller with SVID Interface for Computer CPU Applications;
| 型号： | NCP81566MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | 8 + 1 Phase Output Controller with SVID Interface for Computer CPU Applications |
| 文件： | 总21页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
8 + 1 Phase Output
Controller with SVID
Interface for Computer CPU
Applications
1
52
QFN52 6x6, 0.4P
CASE 485BE
NCP81566
MARKING DIAGRAM
The NCP81566 is a dual rail, eight plus one phase buck solution
optimized for Intel’s IMVP9.2 CPUs. The multi−phase rail control
system is based on Dual−Edge pulse−width modulation (PWM)
combined with DCR current sensing. This provides an ultra−fast
initial response to dynamic load events and reduced system cost. The
NCP81566 has an ultra−low offset current monitor amplifier with
programmable offset compensation for high accuracy current
monitoring.
NCP81566
AWLYYWWG
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
Features
• Vin Range 4.5 V to 21 V
• Startup into Pre−Charged Loads While Avoiding False OVP
• Digital Soft Start Ramp
ORDERING INFORMATION
• Adjustable Vboot
†
Device
NCP81566MNTXG
Package
Shipping
• High Impedance Differential Output Voltage Amplifier
• Dual VID Table Support to Be Compatible with IMVP9.2
• Support High Current Extensions
• Dynamic Reference Injection
QFN52
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Programmable Output Voltage Slew Rates
• Dynamic VID Feed−Forward
• Differential Current Sense Amplifiers for Each Phase
• Programmable Adaptive Voltage Positioning (AVP)
• Adjustable Switching Frequency Range
• Digitally Stabilized Switching Frequency
• UltraSonic Operation
• Supports Acoustic Noise Mitigation Function
• PSYS Input Monitor
• Support for VCCIN_AUX IMON Input
• Meets Intel’s IMVP9.2 Specifications
• Current Mode Dual Edge Modulation for Fast Initial Response to
Transient Loading
• This is a Pb−Free Device
Typical Applications
• Computers
© Semiconductor Components Industries, LLC, 2023
1
Publication Order Number:
May, 2023 − Rev. 0
NCP81566/D
NCP81566
TSENSE
TSENSEA
VR_HOT#
Thermal
Monitor
UVLO
&
VSPA
VSNA
ENABLE
DACA
GND
DIFFAMP
VSP
VSN
DAC
GND
CSREFA
DIFFAMP
ENABLE
VSP
VSN
DAC
VSPA
VSNA
DACA
CSREF
VR Ready
DIFFA
Comparator
ERROR
AMP
DIFF
FBA
ERROR
AMP
COMPA
FB
VSP
VSN
OVP
OVP
Current
Measurement &
Limit
ILIMA
COMP
VSPA
VSNA
IOUTA
OVPA
OVPA
Current
Measurement &
Limit
ILIM
IOUT
CSSUMA
CSREFA
CSAMP
CSSUM
CSREF
CSAMP
CSCOMPA
ICC*2_MAIN_RAIL
CSCOMP
VSP‐VSN
VSPA‐VSNA
TSENSE
TSENSEA
IOUT
IOUTA
ROSC
ROSCA
VBOOT
SV_ADDR_SR
SDIO
ALERT#
SCLK
Data
SVID
ADC
Registers
Interface
MUX
DAC
DAC
DAC
DACA
PSYS
ICCMAX_AUXIN
AUX_IN
PH_CONFIG
RAMP8
IPH8
IPH7
IPH6
CSP8
CSP7
CSP6
CSP5
CSP4
CSP3
CSP2
CSP1
RAMP7
RAMP6
IPH5
RAMP5
PWM
Current
Balance
Ramp
IPH4
IPH3
IPH2
RAMP4
RAMP3
RAMP2
Generators
Generators
PWM
Current
Balance
IPH1A
RAMP1A
CSP1A
Generators
IPH1
RAMP1
Power State
Stage
Power State Stage
Figure 1. Internal Block Diagram
www.onsemi.com
2
NCP81566
APPLICATIONS INFORMATION
VIN
VCC
EN
+5V
VRMP
VIN
VCC
BST
VCC
DRVH
SW
SW1
VR_EN
DRON
DRON
VCCCORE
EN
Driver
PWM
PWM1/SV_ADDR_SR
DRVL
VCCIO
VCCIO
CSP1
CSREF
SDIO
ALERT
SCLK
CSREF
CPU_SDIO
CPU_ALERT
CPU_SCLK
SDIO
VIN
VCC
ALERT#
SCLK
BST
VCC
DRVH
SW
SW2
EN
DRON
Driver
PWM
DRVL
PWM2/VBOOT
VPULL-UP
CSP2
CSREF
VR_HOT#
VR_RDY
VR_HOT#
VR_RDY
VIN
VCC
BST
VCC
DRVH
SW
SW3
EN
DRON
PSYS
PSYS
Driver
(BATTERY CHARGER)
PWM
DRVL
PWM3/ICCMAX
AUX_IN
AUX_OUT
CSP3
(AUX Power)
CSREF
VIN
VCC
BST
VCC
DRVH
SW
SW4
EN
DRON
Driver
VCCCORE
PWM
PWM4/ROSC
DRVL
VCCCORE_SENSE
VSP
VSN
CSP4
VSSCORE_SENSE
GND
CSREF
VIN
VCC
DIFF
FB
BST
VCC
DRVH
SW
SW5
EN
DRON
Driver
PWM
DRVL
PWM5/ROSCA
COMP
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
CSSUM
CSP5
CSREF
VIN
VCC
NTC
BST
VCC
CSCOMP
ILIM
DRVH
SW
SW6
EN
DRON
Driver
PWM
DRVL
PWM6/ICCMAX_AUXIN
IOUT
CSP6
TSENSE
CSREF
VIN
NTC
VCC
VCCGT
BST
VCC
DRVH
SW
SW7
VCCGT_SENSE
VSPA
VSNA
EN
DRON
Driver
PWM7/
PWM
VSSGT_SENSE
GND
DRVL
ICC*2_MAIN_RAIL
CSP7
DIFFA
FBA
CSREF
VIN
VCC
BST
VCC
DRVH
SW
COMPA
SW8
EN
DRON
Driver
SW1A
CSSUMA
PWM
PWM8
DRVL
CSP8
CSREF
NTC
CSCOMPA
ILIMA
VIN
VCC
BST
VCC
DRVH
SW
SW1A
IOUTA
TSENSEA
GND
VCCGT
EN
DRON
Driver
PWM
PWM1A/ICCMAXA
DRVL
NTC
CSP1A
CSREFA
CSREFA
Figure 2. Typical Application Circuit
www.onsemi.com
3
NCP81566
Figure 3. Pinout
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
IOUT
Description
1
2
3
4
5
6
7
8
9
Total output current monitor for regulator 1
Enable. High enables both rails
Serial VID data interface
Serial VID ALERT#
EN
SDIO
ALERT#
SCLK
Serial VID clock
VR_RDY
VCC
VR_RDY indicates both rails are ready to accept SVID commands
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground
System power signal input. A resistor to ground scales this signal.
PSYS
VRMP
Feed−forward input of Vin for the ramp−slope compensation. The current fed into this pin is used to
control the ramp of the PWM slopes
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VR_HOT#
AUX_IN
NC
OD output. Indicates high VR temperature.
AUX IMON Input. A resistor to ground scales this signal.
Reserved.
IOUTA
Total output current monitor for regulator 2
VSNA
Differential output voltage negative sense for regulator 2
Differential output voltage positive sense for regulator 2
Output of the regulator 2’s differential remote sense amplifier
Error amplifier voltage feedback for regulator 2
VSPA
DIFFA
FBA
COMPA
CSCOMPA
ILIMA
Output of the error amplifier and the inverting inputs of the PWM comparators for regulator 2
Output of total−current−sense amplifier for regulator 2
Over−current threshold setting – programmed with a resistor to CSCOMPA for regulator 2
Inverting input of total−current−sense amplifier for regulator 2
Total−current−sense amplifier reference voltage input for regulator 2
Non−inverting input to current−balance amplifier for Phase 1 of regulator 2
Temperature sense input for regulator 2
CSSUMA
CSREFA
CSP1A
TSENSEA
PWM1A / ICCMAXA PWM1 output for regulator 2. Pulldown on this pin programs ICCMAX for regulator 2 during startup
www.onsemi.com
4
NCP81566
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
26
Pin Name
DRON
Description
External FET driver enable for discrete driver or onsemi DrMOS
PWM8 output for regulator 1
27
PWM8
28
PWM7 /
ICC*2_MAIN_RAIL
PWM7 output for regulator 1 / Pulldown on this pin programs ICCMAX on main rail from 255 to 511A
29
PWM6 /
ICCMAX_AUXIN
PWM6 output for regulator 1 / Pulldown resistor on this pin programs ICCMAX for the AUX_IN
monitoring rail
30
31
32
33
34
PWM5 / ROSCA
PWM4 / ROSC
PWM3 / ICCMAX
PWM2 / VBOOT
PWM5 output for regulator 1 / Pulldown on this pin programs RoscA value for regulator 2
PWM4 output for regulator 1 / Pulldown on this pin programs Rosc value for regulator 1
PWM3 output for regulator 1 / Pulldown on this pin programs ICCMAX for regulator 1 during startup
PWM2 output for regulator 1 / Pin−program for regulator 1 and regulator 2 Vboot.
PWM1 /
SV_ADDR_SR
PWM1 output for regulator 1 / Pulldown on this pin configures SVID address, slew rate and Intel
Proprietary Current Protection Feature
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
TSENSE
CSP1
CSP2
CSP3
CSP4
CSP5
CSP6
CSP7
CSP8
CSREF
CSSUM
ILIM
Temperature sense input for regulator 1
Differential current sense positive for Phase 1 of regulator 1
Differential current sense positive for Phase 2 of regulator 1
Differential current sense positive for Phase 3 of regulator 1
Differential current sense positive for Phase 4 of regulator 1
Differential current sense positive for Phase 5 of regulator 1
Differential current sense positive for Phase 6 of regulator 1
Differential current sense positive for Phase 7 of regulator 1
Differential current sense positive for Phase 8 of regulator 1
Total−current−sense amplifier reference voltage input for regulator 1
Inverting input of total−current−sense amplifier for regulator 1
Over−current threshold setting – programmed with a resistor to CSCOMP for regulator 1
Output of total−current−sense amplifier for regulator 1
Output of the error amplifier and the inverting inputs of the PWM comparators for regulator 1
Error amplifier voltage feedback for regulator 1
CSCOMP
COMP
FB
DIFF
Output of the regulator 1’s differential remote sense amplifier
Differential output voltage sense positive for regulator 1
Differential output voltage sense negative for regulator 1
GND
VSP
VSN
Flag
1. “Regulator 1” is referred to as “Main” rail throughout the datasheet. “Main” is the primary rail with the highest phase count.
2. “Regulator 2” is referred to as “A” rail throughout the datasheet.
www.onsemi.com
5
NCP81566
Table 2. MAXIMUM RATINGS (Note 3)
Pin Symbol
COMP, COMPA
CSCOMP, CSCOMPA
PWMX
V
V
I
I
SINK
MAX
MIN
SOURCE
VCC + 0.3 V
VCC + 0.3 V
VCC + 0.3 V
GND + 0.3 V
VCC + 0.3 V
VCC + 0.3 V
6.0 V
−0.3 V
−0.3 V
2 mA
2 mA
2 mA
1 mA
2 mA
2 mA
−
2 mA
−
−0.3 V
VSN, VSNA
DIFF, DIFFA
VR_RDY
GND – 0.3 V
−0.3 V
1 mA
2 mA
2 mA
−
−0.3 V
VCC
−0.3 V
−
VRMP
VCC + 0.3 V
3.6 V
−0.3 V
−
−
−
−
SCLK, SDIO
All Other Pins
−0.3 V
VCC + 0.3 V
−0.3 V
−
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. All signals referenced to GND unless noted otherwise
Table 3. ESD CAPABILITY
Description
ESD Capability, Human Body Model (Note 4)
ESD Capability, Charged Device Model (Note 4)
Symbol
Typ
2000
750
Unit
V
ESD
ESD
HBM
CDM
V
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charge Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)
Latch−up Current Maximum Rating: 200 mA per JEDEC standard: JESD78.
Table 4. RECOMMENDED OPERATING CONDITIONS
Description
Symbol
VCC
TJ
Min
4.75
−40
−40
Max
5.25
125
100
Unit
V
VCC Voltage Range
Operating Junction Temperature Range (Note 5)
Operating Ambient Temperature Range
°C
°C
TA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. JEDEC JESD 51−7 with 0 LFM.
Table 5. THERMAL CHARACTERISTICS
Description
Thermal Characteristic QFN Package
Symbol
Value
Unit
°C/W
°C
R
68
JA
Maximum Storage Temperature Range
T
STG
−40 to +150
Moisture Sensitivity Level QFN Package
MSL
1
Soldering Temperature
260
30
°C
Junction−to−Ambient, Thermal Resistance (Note 6)
Junction−to−Case (Top), Thermal Resistance (Note 6)
Junction−to−Board Heat Spreader, Thermal Resistance (Note 6)
Junction−to−Case (Top), Measurement Reference (Note 6)
6. JEDEC JESD 51−7 with 0 LFM
ꢀ
°C/W
°C/W
°C/W
°C/W
JA
ꢀ
18
JC(TOP)
ꢀ
1.0
1.1
JB
ꢁ
J−CT
www.onsemi.com
6
NCP81566
Table 6. ELECTRICAL CHARACTERISTICS (−40°C < T < 100°C; 4.75 V < V < 5.25 V; C
= 0.1 ꢂF unless otherwise noted)
A
CC
VCC
Parameter
BIAS SUPPLY
Test Conditions
Min
Typ
Max
Unit
VCC Voltage Range
Quiescent Current
4.75
−
−
29
25
21
14
−
5.25
−
V
PS0
mA
mA
mA
mA
ꢂ A
ꢂ A
V
PS1
−
−
PS2
−
−
PS3
−
−
PS4
−
79
64
4.5
−
Enable Low
VCC Rising
VCC Falling
−
−
UVLO Threshold
−
−
4.1
−
−
V
VCC UVLO Hysteresis
100
−
mV
VRMP
VIN Supply Range
VRMP range prior to external voltage divider
resistor network with 1/12 ratio
4.5
−
21
V
UVLO Threshold
VRMP Rising
VRMP Falling
−
−
−
0.355
V
V
0.250
−
ENABLE INPUT
Upper Threshold
Activation Level
0.8
−
−
−
V
V
Lower Threshold
Deactivation Level
−
0.3
PHASE DETECTION
CSP Pin Threshold Voltage
Phase Detect Timer
VCC − 0.4
−
−
−
V
−
1.5
ms
IMVP9.2 DAC (PROTOCOL 0Eh)
System Voltage Accuracy
0.25 V < DAC < 0.495 V (at 25°C only)
0.5 V < DAC < 0.745 V (at 25°C only)
0.75 V < DAC < 1.52 V (at 25°C only)
−10
−8
−
−
−
10
8
mV
mV
%
−0.5
0.5
DAC SLEW RATE
Soft Start Slew Rate
Slew Rate Slow
Slew Rate Fast
DRON
−
−
1/2 fast
1/2 fast
>10
−
−
mV/ꢂ s
mV/ꢂ s
mV/ꢂ s
Resistor Selectable (See Table 9)
Output High Voltage
Output Low Voltage
TSENSE
Sourcing 1 mA
Sinking 1 mA
3
−
−
−
V
V
−
0.1
TSENSE Bias Current
Alert#
115.5
120
556
595
517
556
124.5
ꢂ A
mV
mV
mV
mV
Assert Threshold
−
−
−
−
−
−
−
−
De−Assert Threshold
Assert Threshold
VR_HOT
De−Assert Threshold
www.onsemi.com
7
NCP81566
Table 6. ELECTRICAL CHARACTERISTICS (−40°C < T < 100°C; 4.75 V < V < 5.25 V; C
= 0.1 ꢂF unless otherwise noted)
A
CC
VCC
Parameter
VR_RDY OUTPUT
Test Conditions
Min
Typ
Max
Unit
Output Low Saturation Voltage
VR_RDY Rise Time
VR_RDY Fall Time
ALERT#
I
= −4 mA
−
−
−
0.1
110
20
0.3
150
150
V
VR_RDY
1 kꢃ pull−up to 3.3 V
= 45 pF
ns
ns
C
TOT
VOL (Output Low)
−
−
0.3
V
OVP AND UVP
Absolute Over Voltage Threshold
10 mV DAC step
3.3
2.8
3.44
2.9
3.6
3.05
475
V
V
During Soft Start − CSREF Rising
5 mV DAC step
During Soft Start − CSREF Rising
Over Voltage Threshold Above DAC
Over Voltage Delay
VSP−VSN−VID Rising
350
400
50
mV
ns
VSP−VSN Rising to PWM Low
VSP−VSN−VID Falling
Under Voltage Threshold Below
DAC−DROOP (VUVM)
−440
−400
−360
mV
Under Voltage Delay
PWM OUTPUT
−
5
−
ꢂ s
Output High Voltage
Output Mid Voltage
Output Low Voltage
DIFFERENTIAL AMPLIFIER
Input Bias Current
−3 dB Bandwidth
Closed Loop DC Gain
ERROR AMPLIFIER
Input Bias Current
DC Gain
Sourcing 500 ꢂ A
Vcc − 0.2
−
1.8
−
−
V
V
V
No Load, Power State 2
Sinking 500 ꢂ A
1.7
1.9
0.7
−
VSP = 1.3 V
300
−
−
22.5
1
600
−
nA
MHz
V/V
CL = 20 pF, RL = 10 kꢃ
VSP − VSN = 0.5 V to 1.3 V
−
−
Input = 1.3 V
−400
−
80
20
5
400
−
nA
dB
CL = 20 pF, RL = 10 kꢃ
CL = 20 pF, RL = 10 kꢃ
ꢄVin = 100 mV, G = −10 V/V,
−
−
−
−3 dB Bandwidth
Slew Rate
−
MHz
V/ꢂ s
−
ꢄ
V
o
u
t
=
1
.
5
V
t
o
2
.
5
V
,
C
L
=
2
0
p
F
,
R
L
=
1
0
k
ꢃ
OVER−CURRENT PROTECTION (ILIM)
ILim Threshold Current
PS0
8.5
−
10
10/N*
15
11.5
−
ꢂ A
ꢂ A
ꢂ A
ꢂ A
ꢂ s
(Delayed OCP shutdown)
PS1, PS2, PS3
PS0
ILim Threshold Current
(Immediate OCP shutdown)
13.5
−
16.5
−
PS1, PS2, PS3
Immediate
Delayed
15/N*
1.3
Shutdown Delay
−
−
−
50
−
ꢂ
s
IOUT OUTPUT
Current Gain
IOUT/ILIM
9.5
10
10.5
A/A
(RLIM = 20 kꢃ, RIOUT = 5 kꢃ, Vout = 0.8 V,
1.25 V, 1.52 V)
PWM GENERATOR
PWM Minimum Pulse Width
0% Duty Cycle
40
ns
V
Comp Voltage for PWM Held Low
1.3
www.onsemi.com
8
NCP81566
Table 6. ELECTRICAL CHARACTERISTICS (−40°C < T < 100°C; 4.75 V < V < 5.25 V; C
= 0.1 ꢂF unless otherwise noted)
A
CC
VCC
Parameter
100% Duty Cycle
100% Duty Cycle
Test Conditions
Min
Typ
1.75
3.4
Max
Unit
V
Comp Voltage for PWM Held High VIN at 4.5 V
Comp Voltage for PWM Held High VIN at 21 V
V
CURRENT SUMMING AMPLIFIER (CSAMP)
Offset Voltage
−500
−10
−
−
−
500
10
−
ꢂ V
ꢂ A
Input Bias Current
CSSUM = CSREF = 1.0 V
Open Loop Gain
80
10
dB
Open Loop Unity Gain Bandwidth
CURRENT BALANCE AMPLIFIER
CL = 20 pF to GND, RL = 10 kꢃ to GND
−
−
MHz
Differential Mode Input Voltage Range CSREF = 1.2 V
−100
−
100
mV
PSYS
Full Scale Input Voltage
Disable Threshold
−
−
2.5
−
−
V
V
VCC − 0.4
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
*N is the phase configuration number in PS0.
Start Up
Following the rise of VCC above the UVLO threshold,
externally programmed configuration data is collected, and
all PWM outputs are set to Mid−level to prepare the gate
drivers of the power stages for activation. When the
controller is enabled, DRON is asserted (high) to activate the
external gate drivers. A digital counter steps the DAC up
from zero to the target boot voltage based on the Soft Start
Slew Rate in the spec table. As the DAC ramps, the PWM
outputs of each rail will change from Mid−level to high
when the first PWM pulse for that rail is produced. When the
controller is disabled, the PWM signals return to Mid−level.
The VR_RDY signal is asserted when the controller is ready
to accept the first SVID command.
www.onsemi.com
9
NCP81566
DEVICE CONFIGURATION
ICCMAX
Phase and Rail Configuration
During start−up, the number of operational phases of the
multiphase rail is determined by the internal circuitry
monitoring the CSP inputs. If a reduced phase count is
required, the appropriate CSP pins should be externally
pulled to VCC with a resistor during startup. When used
with the NCP81568 controller, the PSYS input needs to be
connected to VCC so that it does not respond to any calls on
the SVID bus. PSYS functionality is enabled on the
NCP81568 only.
The SVID interface provides the platform ICCMAX
values at register 21h. Resistors to ground on the
PWM3/ICCMAX,
PWM1A/ICCMAXA
and
PWM6/ICCMAX_AUXIN pins programs these registers on
power up. 10 ꢂ A is sourced from this pin to generate a
voltage on the program resistor. The value of the register is
set by the equation below. The resistor value should be no
less than 10 kꢃ.
R @ 10 ꢂ A @ 255 A
(eq. 1)
ICCMAX
+
2.5 V
21h
Basic Configuration
The controller has four basic configuration features. On
power up a 10 ꢂ A current is sourced from these pins through
a resistor connected to this pin and the resulting voltage is
measured. The following features will be programmed:
ICCMAX Additional Capability
IMVP9.2 adds an option to extend the current range of the
main rail by scaling the LSB size of register ICCMAX by
21h
ICCMAX_ADD [1:0]
50h
2
amps (See Table 7). On the
NCP81566, these register bits can be configured to 2 A per
bit by enabling ICC*2_MAIN_RAIL mode. See Table 11
for details on how to enable this mode.
• SVID Address
• Slew Rate
• V
BOOT
• Output Voltage Step
Table 7. ICCMAX CAPABILITY SCALING
SVID address and slew rate options are shown in Table 9.
ICCMAX_ADD [4:0]
50h
Power
V
BOOT
and output voltage step options are shown in
Power [4:2]
010
011
Current [1:0]
00
01
Scaling
ICC Scaling
1 A / bit
Table 10.
4 W / bit
8 W / bit
Intel Proprietary Current Protection Feature
VR_HOT assertion for Intel Proprietary Current
Protection Feature on/off selection as shown in Table 9.
2 A / bit
When ICC*2_MAIN_RAIL mode is enabled, the bits
ICCMAX_ADD [1:0] are set to 01b to indicate a scaling
50h
Switching Frequency
of 2 A per bit. This scaling applies to both the ICCMAX
21h
Switching frequencies between 180 kHz and 1.17 MHz
are programmed at power up with pulldown resistors on
Rosc and RoscA pin. Switching frequency options are
shown in Table 12. IA rail follows phase configuration
number in PS0. GT rail follows 1−phase switching
frequency settings.
and the IOUT_H
SVID registers. The bits
15h
ICCMAX_ADD [4:2] are also set to 011b to indicate that
50h
the POUT_H18h register value is scaled to 8 W per bit.
Table
8
shows the rail configurations when
ICC*2_MAIN_RAIL mode is enabled and disabled.
www.onsemi.com
10
NCP81566
Table 8. RAIL SETTINGS FOR ICC*2_MAIN_RAIL MODE
ICC*2_MAIN_RAIL
Disabled
Enabled
2A
ICCMAX
LSB Size
1A
1A
21h
IOUT
LSB Size
LSB Size
2A
15h
POUT
4 W
00
8 W
18h
Main Rail
HIGHPOWER_ICCMAX_ADD [1:0]
01
50h
HIGHPOWER_ICCMAX_ADD [4:2]
010
011
50h
Loadline Weighting
93.75%
187.5%
ICCMAX
LSB Size
1A
1A
21h
IOUT
LSB Size
LSB Size
15h
POUT
4 W
00
18h
A Rail
HIGHPOWER_ICCMAX_ADD [1:0]
50h
HIGHPOWER_ICCMAX_ADD [4:2]
010
93.75%
1A
50h
Loadline Weighting
ICCMAX
LSB Size
21h
IOUT
LSB Size
LSB Size
1A
15h
POUT
4 W
00
VCCIN_AUX
18h
HIGHPOWER_ICCMAX_ADD [1:0]
50h
HIGHPOWER_ICCMAX_ADD [4:2]
010
50h
Ultrasonic Mode
Table 9. NCP81566 SVID ADDRESS, SLEW RATE AND
FAST V MODE
The switching frequency of a rail in DCM will decrease
at very light loads. Ultrasonic Mode forces the switching
frequency to stay above the audible range.
Intel
Proprietary
Current
Protection
Feature
Main Rail
SVID
Address
A Rail
SVID
Address
CCM/DCM Operation
Resistor
(kW)
SR
(mV/ms)
In PS0, all rails operate in Continuous Conduction Mode
(CCM) which uses the dual−edge control methodology.
However, if PS0 is configured as one−phase instead of
multi−phase, the control methodology changes to RPM
operation. RPM has great transient performance in
one−phase CCM operation. The RPM frequency average
DC value is targeted to be similar to the PS0 Dual Edge
frequency. However, the switching frequency of RPM
depends on input voltage, output voltage, load current,
inductor value, and output capacitor value. In PS1, all rails
operate in one−phase CCM RPM. In PS2 and PS3, all rails
operate in either CCM or Discontinuous Conduction Mode
(DCM). It depends on load current in order to prevent loss
of efficiency from negative inductor current.
10
10
30
48
10
30
48
10
30
48
10
30
48
00
00
00
01
01
01
00
00
00
01
01
01
01
01
01
00
00
00
02
02
02
02
02
02
ON
ON
14
18.7
24.3
30.9
38.3
47.5
59
ON
OFF
OFF
OFF
ON
ON
71.5
86.6
105
127
ON
OFF
OFF
OFF
www.onsemi.com
11
NCP81566
monitoring of the total platform system power. For more
information regarding PSYS please contact Intel, inc.
Table 10. VBOOT AND OUTPUT VOLTAGE STEP
Resistor
(kW)
V
(V)
V
BOOT
(V)
Output Voltage
Step
BOOT
Main Rail
A Rail
0 V
AUX_IN
10
0 V
Both rail
5 mV/step
The AUX_IMON current monitor input is a means of
measuring the VCCIN_AUX platform VR output current
using the IMVP9.2 ADC.
14
0 V
1.05 V
0 V
18.7
24.3
30.9
38.3
47.5
59
1.05 V
1.05 V
0 V
Programming Pin
1.05 V
0 V
This is a multifunction select pin used to set the operation
of multiple features and the combination of these features
enabled/disabled. Items programmed on this pin are
ICC*2_MAIN_RAIL which allows the user to select if the
ICCMAX and IOUT reporting for the main rail is a 1 A or
2 A LSB step size. When off, the resolution is 1 A per LSB.
When on, the resolution is set to 2 A per LSB which allows
reporting of over 255 A on the main rail only.
Automatic Power Management is used to add or remove
phases based on real time load current requirements sensed
by the controller. The phase configuration levels are defined
as:
Both rail
10 mV/step
0 V
1.8 V
0 V
1.8 V
1.8 V
0 V
1.8 V
0 V
71.5
86.6
105
127
154
187
221
280
Main rail
5 mV/step.
A rail
0 V
1.8 V
0 V
10 mV/step.
1.05 V
1.05 V
0 V
1.8 V
0 V
Main rail
10 mV/step.
A rail
1.8 V
0 V
0 V
<5A = DCM
<15A = CCM 1−phase
<25A = CCM 2−phase
>25A = CCM All phases on
5 mV/step.
1.05 V
1.05 V
1.8 V
The other options include dithering and acoustic noise
solution.
PSYS
The PSYS pin is an analog input to the VR controller.
PSYS is a system input power monitor that facilitates the
www.onsemi.com
12
NCP81566
Table 11. PIN OF ICC*2_MAIN_RAIL CONFIGURATION
Automatic Power
Management
Resistor (kW)
10
ICCMAX*2 Main Rail
Acoustic Noise Solution
Spread Spectrum
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
14
18.7
24.3
30.9
38.3
47.5
59
OFF
ON
ON
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON
ON
ON
71.5
86.6
105
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON
127
ON
ON
154
ON
OFF
OFF
ON
OFF
ON
187
ON
ON
221
ON
ON
OFF
ON
280
ON
ON
ON
Table 12. SWITCHING FREQUENCY
Switching Frequency (kHz)
1 Phase~6 Phase
7 Phase
180
215
250
285
320
355
390
425
460
495
530
600
700
800
900
1000
8 Phase
180
210
240
270
300
330
360
390
420
450
480
510
540
600
700
800
Control by Pin Resistor (kW)
10
180
225
270
315
360
405
450
495
540
630
720
810
900
990
1080
1170
14
18.7
24.3
30.9
38.3
47.5
59
71.5
86.6
105
127
154
187
221
280
www.onsemi.com
13
NCP81566
THEORY OF OPERATION
Input Voltage Feed−Forward (VRMP Pin)
signals are summed with the COMP or ramp signals at their
respective PWM comparator inputs in order to balance
phase currents via a current mode control approach.
Ramp generator circuits are provided for the dual−edge
modulator. The ramp generators implement input voltage
feed−forward control by varying the ramp slopes
proportional to the VRMP pin voltage. The VRMP pin also
has a UVLO function, which is active only after the
controller is enabled. The VRMP pin is high impedance
input when the controller is disabled. For multi−phase
operation, the dual−edge PWM ramp amplitude is changed
according to the following:
LPHASE
RCSN
+
(eq. 3)
CCSN DCR
DCR
SWx
L
PHASE
VOUT
C
CSN
R
CSN
VRMPPP + 0.1 VVRMP
(eq. 2)
CSPx
Figure 6. Per Phase Current Sense Network
Total Current Sense Amplifier
The multiphase rail uses a patented approach to sum the
phase currents into a single, temperature compensated, total
current signal. This signal is then used to generate the output
voltage droop, total current limit, and the output current
monitoring functions. The Rref(n) resistors average the
voltages at the output terminals of the inductors to create a
low impedance reference voltage at CSREF. The Rph
resistors sum currents from the switch nodes to the virtual
CSREF potential created at the CSSUM pin by the amplifier.
The total current signal is the difference between the
CSCOMP and CSREF voltages.
The amplifier filters, and amplifies, the voltage across the
inductors in order to extract only the voltage across the
inductor series resistances (DCR). An NTC thermistor (Rth)
in the feedback network placed near the Phase 1 inductor
senses the inductor temperature, and compensates both the
DC gain and the filter time constant for the change in DCR
with temperature. The Phase 1 inductor is chosen for the
thermistor location so that the temperature of the inductor
providing current in the PS1 power mode.
Figure 4. Ramp Feed Forward
An external voltage divider is required on this VRMP pin
in order to scale the voltage seen on the VRMP pin the
voltage divider on the pin needs to be setup to maintain a
ratio of 1/12. Typical resistor values may include 1 MOhm
Rup / 90.9 KOhm Rdown or 1.1 MOhm Rup / 100 KOhm
Rdown. UVLO on VRMP is inactive in PS4 power state and
PS3 when a VID to 0 V is received.
Input Voltage
Feed Forward
Control
Rup
VRMP
VIN
Rdown
Figure 5. Ramp Feed Forward Circuit
The DC gain equation for the DC total current signal is:
RCS1 Rth
Differential Current Feedback Amplifiers
RCS2
)
R
CS1)Rth
Each phase of the rail has a low offset, differential
amplifier to sense the current of that phase in order to
balance current. The CSREF and CSPx pins are high
impedance inputs, but it is recommended that any external
filter resistor RCSN does not exceed 10 kꢃ to avoid offset
due to leakage current.
It is also recommended that the voltage sense element be
no less than 0.5 mꢃ for best current balance.
The external filter RCSN and CCSN time constant should
match the inductor L/DCR time constant, but fine tuning of
this time constant is generally not required. Phase current
V
CSCOMP * VCSREF + *
DCR IOUT
(eq. 4)
Rph
Set the DC gain by adjusting the value of the Rph resistors
in order to make the ratio of total current signal to output
current equal the desired loadline. The values of Rcs1 and
Rcs2 are set based on the effect of temperature on both the
thermistor and inductor, and may need to be adjusted to
eliminate output voltage temperature drift with the final
product enclosure and cooling.
www.onsemi.com
14
NCP81566
Loadline Programming (VDROOP
)
An output loadline is a power supply characteristic
wherein the regulated (DC) output voltage decreases
proportional to load current. This characteristic can reduce
the output capacitance required to maintain output voltage
within limits during load transients faster than those to
which the regulation loop can respond.
Rcs1
Rcs2
Ccs2
Ccs1
SWN1
SWNX
Rph1
Rphx
CSSUM
CSREF
cscomp
CSN1
CSNX
Rref1
Rrefx
Rilim
A load line is produced by adding a signal proportional to
To remote sense
Cref
amplifier
output load current (V ) to the output voltage feedback
DROOP
buffer
signal – thereby satisfying the voltage regulator at an output
voltage reduced proportional to load current. The load line
is programmed by setting the gain of the Total Current Sense
Amplifier such that the total current signal is equal to the
desired output voltage droop.
ilim
Current Limit Current
Comparator Mirror
Ciout
Riout
RCS1 Rth
RCS2
)
R
CS1)Rth
VDROOP
+
DCR IOUT
Rph
(eq. 8)
Figure 7. Total Current Sense Amplifier
For the main rail, loadline programming is dependent on its
programmed ICCMAX value.
The pole frequency of the CSCOMP filter should be set
equal to the zero of the output inductor. This causes the total
current signal to contain only the component of inductor
voltage caused by the DCR voltage, and therefore to be
proportional to inductor current. Connecting Ccs2 in
parallel with Ccs1 allows fine tuning of the pole frequency
using commonly available capacitor values. It is best to
perform fine tuning during transient testing.
Rcs
Loadline + DCR
Weighting
(eq. 9)
Rph
For ICC*2_MAIN_RAIL configuration enabled, weighting
= 87.50%.
For ICC*2_MAIN_RAIL configuration disabled,
weighting = 43.75%.
For the A rail, load line weighting = 93.75%.
DCR25°C
FZ
+
(eq. 5)
Rail Remote Sense Amplifier
2ꢅ LPhase
A
high performance high input impedance true
1
FP
+
differential amplifier is provided to accurately sense
regulator output voltage. The VSP and VSN inputs should
be connected to the regulator’s output voltage sense points.
The remote sense amplifier takes the difference of the output
voltage with the DAC voltage and adds the droop voltage.
RCS1 Rth
ǒ
Ǔ
2ꢅ RCS2
)
(CCS1 ) CCS2)
R
CS1)Rth
(eq. 6)
This signal then goes through a standard error
compensation network and into the inverting input of the
error amplifier.
VDIFFOUT + (VVSP * VVSN) ) (1.3 V * vDAC
)
The value of the CREF capacitor (in nF) on the CSREF pin
should be:
(eq. 10)
) (VDROOP * VCSREF
)
Programming the Current Limit
0.02 Rph
Cref +
The current limit thresholds are programmed with a
resistor between the ILIM and CSCOMP pins. The
multiphase rails generates a replica of the CSREF pin
voltage at the ILIM pin, and compares ILIM pin current to
ICL0 and ICLM0 (ICL1 and ICLM1 in PS1, PS2 and PS3).
The controller latches off if ILIM pin current exceeds ICL0
(eq. 7)
Rref
High Performance Voltage Error Amplifier
The Remote Sense Amplifier output feeds a Type III
compensation network formed by the Error Amplifier and
external tuning components. The non−inverting input of the
error amplifier is connected to the same reference voltage
used to bias the Remote Sense Amplifier output.
(ICL1 for PS1, PS2, and PS3) for t
, and latches
OCP_DELAY
off immediately if ILIM pin current exceeds ICLM0
(ICLM1 for PS1, PS2 and PS3). Set the value of the current
limit resistor RLIMIT according to the desired current limit
Iout LIMIT.
C2
C3
R3
C1
R2
RCS1 Rth
RCS2
)
R1
R
CS1)Rth
DIFFOUT
FB
Vref
COMP
−
DCR IOUT
LIM
EA
Rph
+
RLIMIT
+
10 ꢂ
(eq. 11)
Figure 8. Error Amplifier
www.onsemi.com
15
NCP81566
Programming IOUT
TSENSE Network
The IOUT pin sources a current proportional to the ILIM
current. The voltage on the IOUT pin is monitored by the
internal A/D converter and should be scaled with an external
resistor to ground such that a load equal to ICCMAX
generates a 2.5 V signal on IOUT.
A temperature sense input is provided for each rail. A
precision current is sourced from the output of the TSENSE
pin to generate a voltage on the temperature sense networks.
The voltages on the temperature sense inputs are sampled by
the internal A/D converter. A 100k NTC similar to the
Murata NCP15WF104E03RC should be used. Rcomp1 in
the following Figure is optional, and can be used to slightly
change the hysteresis. See the specification table for the
thermal sensing voltage thresholds and source current.
2.5 V RLIMIT
RIOUT
+
RCS1 Rth
RCS2
)
R
CS1)Rth
Rph
10
DCR ICCMAX
(eq. 12)
TSENSE
Programming DAC Feed−Forward Filter
The multiphase rail outputs a pulse of current from the
VSN pin upon each increment of the internal DAC
following a DVID UP command. A parallel RC network
inserted into the path from VSN to the output voltage return
sense point, VSS_SENSE, causes these current pulses to
temporarily decrease the voltage between VSP and VSN.
This causes the output voltage during DVID to be regulated
slightly higher, in order to compensate for the response of
the DROOP function to current flowing into the charging
R
COMP1
C
FILTER
R
NTC
R
COMP2
Figure 10. TSENSE Network
PWM Comparators
output capacitors. In the following equations, C
total output capacitance of the system.
is the
OUT
The noninverting input of each comparator (one for each
phase) is connected to the summation of the error amplifier
output (COMP) and each phase current (IL x DCR x Phase
Balance Gain Factor). The inverting input is connected to
the triangle ramp voltage of that phase. The output of the
comparator generates the PWM output. During steady state
PS0 operation, the main rail PWM pulses are centered on the
valley of the triangle ramp waveforms and both edges of the
PWM signals are modulated. During a transient event, the
duty cycle can increase rapidly as the error amp signal
increases with respect to the ramps, to provide a highly
linear and proportional response to the step load.
RFF + Cout LL 453.6 106
(eq. 13)
(eq. 14)
LL Cout
CFF
+
RFF
Figure 9. DAC Feed Forward
www.onsemi.com
16
NCP81566
Table 13. PHASE CONFIGURATION
Phase
Configuration
Programming Pin in CSPx
Unused Pin
8 + 1
All CSP pins are connected normally
No unused Pin
Float PWM8.
7 + 1
CSP1 to CSP7 and CSP1A pins connected normally.
CSP8 connected to VCC through a 2 kꢃ resistor.
6 + 1
5 + 1
CSP1 to CSP6 and CSP1A pins connected normally.
Float PWM8 and CSP8.
CSP7 connected to VCC through a 2 kꢃ resistor.
Use PWM7 for programming ICC*2_MAIN_RAIL only.
CSP1 to CSP5 and CSP1A pins connected normally.
CSP6 connected to VCC through a 2 kꢃ resistor.
Float PWM8, CSP7, and CSP8.
Use PWM7 for programming ICC*2_MAIN_RAIL only.
Use PWM6 for programming ICCMAX_AUXIN only.
8 + 0
4 + 1
CSP1 to CSP8 pins connected normally.
Float PWM1A.
CSP1A connected to VCC through a 2 kꢃ resistor.
CSP1 to CSP4 and CSP1A pins connected normally.
CSP5 connected to VCC through a 2 kꢃ resistor.
Float PWM8, CSP6, CSP7, and CSP8.
Use PWM7 for programming ICC*2_MAIN_RAIL only.
Use PWM6 for programming ICCMAX_AUXIN only.
Use PWM5 for programming ROSCA only.
3 + 1
2 + 1
CSP1 to CSP3 and CSP1A pins connected normally.
Float PWM8, CSP5, CSP6, CSP7, and CSP8.
Use PWM7 for programming ICC*2_MAIN_RAIL only.
Use PWM6 for programming ICCMAX_AUXIN only.
Use PWM5 for programming ROSCA only.
CSP4 connected to VCC through a 2 kꢃ resistor.
Use PWM4 for programming ROSC only.
CSP1 to CSP2 and CSP1A pins connected normally.
CSP3 connected to VCC through a 2 kꢃ resistor.
Float PWM8, CSP4, CSP5, CSP6, CSP7, and CSP8.
Use PWM7 for programming ICC*2_MAIN_RAIL only.
Use PWM6 for programming ICCMAX_AUXIN only.
Use PWM5 for programming ROSCA only.
Use PWM4 for programming ROSC only.
Use PWM3 for programming ICCMAX only.
1 + 1
CSP1 and CSP1A pins connected normally.
CSP2 connected to VCC through a 2 kꢃ resistor.
Float PWM8, CSP3, CSP4, CSP5, CSP6, CSP7, and
CSP8
Use PWM7 for programming ICC*2_MAIN_RAIL only.
Use PWM6 for programming ICCMAX_AUXIN only.
Use PWM5 for programming ROSCA only.
Use PWM4 for programming ROSC only.
Use PWM3 for programming ICCMAX only.
Use PWM2 for programming VBOOT only.
www.onsemi.com
17
NCP81566
FAULT PROTECTION
Over Current Protection (OCP)
multiphase−phase rail output falls more than VUVM2
below the DAC−DROOP voltage, the UVM comparator
will trip – sending the VR_RDY signal low.
A programmable total phase current limit is provided that
is decreased when not operating in PS0 mode. This limit is
programmed with a resistor between the CSCOMP and
ILIM pins. The current from the ILIM pin to this resistor is
compared to the ILIM Threshold Currents (ICL0, ICLM0,
ICL1, and ICLM1). When the A rail is operating in PS0, if
the ILIM pin current exceeds ICL0, an internal latch−off
timer starts.
If the fault is not removed, the controller shuts down when
the timer expires. If the current into the pin exceeds ICLM0,
the controller shuts down immediately. When operating in
PS1, PS2, or PS3, the ILIM pin current limits are ICL1 and
ICLM1. To recover from an OCP fault, the EN pin or VCC
voltage must be cycled low.
Output Over Voltage Protection
The multiphase phase output voltage is monitored for
OVP at the VSP pin. During normal operation, if an output
voltage exceeds the DAC voltage by VOVP, the VR_RDY
flag goes low, and the DAC voltage of the overvoltage rail
will be slowly ramped down to 0 V to avoid producing a
negative output voltage. At the same time, the PWM outputs
of the overvoltage rail are sent low. The PWM output will
pulse to mid−level during the DAC ramp down period if the
output decreases below the DAC + OVP threshold as DAC
decreases. When the DAC gets to zero, the PWMs will be
held low, and the VR will stay in this mode until the VCC
voltage or EN is toggled.
Input Under−voltage Lockouts (UVLO)
The VR monitors the 5 V VCC supply as well as the
VRMP pin voltage. Hysteresis is incorporated within these
monitors.
Absolute OVP
During start up, the OVP threshold is set to the absolute
over voltage threshold. This allows the controller to start up
without false triggering OVP.
Output Under Voltage Monitor
The multiphase phase rail output voltage is monitored for
under voltage at the output of the differential amplifier. If the
Figure 11. OVP Threshold Behavior
www.onsemi.com
18
NCP81566
Figure 12. OVP Behavior at Start−up
Figure 13. OVP During Normal Operation Mode
Serial VID Interface (SVID)
For Intel proprietary interface communication details
please contact Intel, inc.
www.onsemi.com
19
NCP81566
PACKAGE DIMENSIONS
QFN52 6x6, 0.4P
CASE 485BE
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L
L
D
A B
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL TIP
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
LOCATION
L1
DETAIL A
MILLIMETERS
ALTERNATE TERMINAL
CONSTRUCTIONS
E
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
0.10
C
EXPOSED Cu
MOLD CMPD
0.15
0.25
D
D2
E
6.00 BSC
4.60
4.80
TOP VIEW
0.10
C
6.00 BSC
E2
e
K
L
L1
L2
4.60
0.40 BSC
0.30 REF
0.25
0.00
0.15 REF
4.80
A
(A3)
DETAIL B
DETAIL B
0.10
C
C
ALTERNATE
0.45
0.15
CONSTRUCTION
0.08
A1
NOTE 4
SEATING
PLANE
SIDE VIEW
D2
C
K
DETAIL C
14
DETAIL A
L2
27
L2
DETAIL C
8 PLACES
E2
52X
L
SOLDERING FOOTPRINT*
1
52
40
6.40
4.80
52X
0.63
52X b
e
0.07
C
C
A B
BOTTOM VIEW
0.05
NOTE 3
4.80
6.40
0.11
0.49
DETAIL D
PKG
8 PLACES
OUTLINE
DETAIL D
52X
0.25
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
20
NCP81566
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
onsemi Website: www.onsemi.com
◊
www.onsemi.com
相关型号：
NCP81599MNTXG
I2C Configurable, 4-Switch Buck Boost Controller for USB-PD Power Delivery and Type-C Applications
ONSEMI
NCP9001
1.5 MHz, 600 mA, High−Efficiency, Low Quiescent Current, Adjustable Output Voltage Step−Down Converter
ONSEMI
NCP9001SNT1G
1.5 MHz, 600 mA, High−Efficiency, Low Quiescent Current, Adjustable Output Voltage Step−Down Converter
ONSEMI
NCQ1004
Small Signal Field-Effect Transistor, 0.46A I(D), 60V, 4-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, CERAMIC, LCC-20
MICROSEMI
©2020 ICPDF网 联系我们和版权申明