NCS2002/D [ONSEMI]
NCS2002/D ;
| 型号： | NCS2002/D |
| 厂家： | 
ONSEMI |
| 描述： | NCS2002/D |
| 文件： | 总16页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCS2002, NCV2002
Sub−One Volt Rail−to−Rail
Operational Amplifier with
Enable Feature
The NCS2002 is an industry first sub−one volt operational amplifier
that features a rail−to−rail common mode input voltage range, along
with rail−to−rail output drive capability. This amplifier is guaranteed
to be fully operational down to 0.9 V, providing an ideal solution for
powering applications from a single cell Nickel Cadmium (NiCd) or
Nickel Metal Hydride (NiMH) battery. Additional features include no
output phase reversal with overdriven inputs, trimmed input offset
voltage of 0.5 mV, extremely low input bias current of 40 pA, and a
unity gain bandwidth of 1.1 MHz at 5.0 V.
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MARKING
DIAGRAM
6
4
5
TSOP
SN SUFFIX
CASE 318G
6
AAxYW
1
3
2
1
The NCS2002 also has an active high enable pin that allows external
shutdown of the device. In the standby mode, the supply current is
typically 1.9 mA at 1.0 V. Because of its small size and enable feature,
this amplifier represents the ideal solution for small portable
electronic applications. The NCS2002 is available in the space saving
SOT23−6 (TSOP−6) package with two industry standard pinouts.
x
= P for NCS2002SN1T1
Q for NCS2002SN2T1
AA = Assembly Location
Y
W
= Year
= Work Week
PIN CONNECTIONS
Features
• 0.9 V Guaranteed Operation
1
2
3
6
5
V
V
EE
OUT
• Standby Mode: I = 1.9 mA at 1.0 V, Typical
D
Enable
V
CC
+ −
• Rail−to−Rail Common Mode Input Voltage Range
• Rail−to−Rail Output Drive Capability
Non−Inverting
Input
Inverting
Input
4
Style 1 Pinout (SN1T1)
• No Output Phase Reversal for Over−Driven Input Signals
• 0.5 mV Trimmed Input Offset
• 10 pA Input Bias Current
• 1.1 MHz Unity Gain Bandwidth at $2.5 V, 1.0 MHz at $0.5 V
• Tiny SOT23−6 (TSOP−6) Package
1
2
3
6
5
V
V
CC
OUT
Enable
V
EE
+ −
Non−Inverting
Input
Inverting
Input
4
Style 2 Pinout (SN2T1)
Typical Applications
• Single Cell NiCd / NiMH Battery Powered Applications
• Cellular Telephones
• Pagers
• Personal Digital Assistants
• Electronic Games
• Digital Cameras
• Camcorders
• Hand Held Instruments
ORDERING INFORMATION
†
Device
Package
TSOP
TSOP
TSOP
TSOP
Shipping
NCS2002SN1T1
NCS2002SN2T1
NCV2002SN1T1*
NCV2002SN2T1*
3000/Tape & Reel
3000/Tape & Reel
3000/Tape & Reel
3000/Tape & Reel
Rail to Rail Input
Rail to Rail Output
*NCV2002: T = −40°C, T
= +125°C.
low
high
Guaranteed by design. NCV prefix is for automotive
and other applications requiring site and change
control.
0.8 V
to
7.0 V
+
−
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
This device contains 81 active transistors.
Figure 1. Typical Application
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
January, 2004 − Rev. 2
NCS2002/D
NCS2002, NCV2002
MAXIMUM RATINGS
Rating
Symbol
Value
7.0
Unit
V
Supply Voltage (V to V
)
V
S
CC
EE
Input Differential Voltage Range (Note 1)
Input Common Mode Voltage Range (Note 1)
Output Short Circuit Duration (Note 2)
Junction Temperature
V
V
t
V
V
– 300 mV to 7.0 V
– 300 mV to 7.0 V
Indefinite
V
IDR
ICR
Sc
EE
V
EE
sec
°C
T
150
J
Power Dissipation and Thermal Characteristics
SOT23−6 Package
Thermal Resistance, Junction to Air
Power Dissipation @ T = 70°C
R
P
235
340
°C/W
mW
q
JA
A
D
Operating Ambient Temperature Range
T
A
°C
NCS2002
NCV2002 (Note 3)
−40 to 105
−40 to 125
Storage Temperature Range
ESD Protection at any Pin Human Body Model (Note 4)
T
−65 to 150
2000
°C
stg
V
ESD
V
1. Either or both inputs should not exceed the range of V – 300 mV to V + 7.0 V.
EE
EE
2. Maximum package power dissipation limits must be observed to ensure that the maximum junction temperature is not exceeded.
T T + (P
R )
q
JA
J
A
D
3. NCV prefix is for automotive and other applications requiring site and change control.
4. ESD data available upon request.
DC ELECTRICAL CHARACTERISTICS (V = 2.5 V, V = −2.5 V, V = V = 0 V, R to Gnd, T = 25°C, unless otherwise noted)
CC
EE
CM
O
L
A
Rating
Symbol
Min
Typ
Max
Unit
Input Offset Voltage
V
IO
mV
V
CC
V
CC
V
CC
= 0.45 V, V = −0.45 V
EE
T = 25°C
−6.0
−8.5
−9.5
0.5
−
−
6.0
8.5
9.5
A
T = 0°C to 70°C
A
T = T
A
to T
low
high
= 1.5 V, V = −1.5 V
EE
T = 25°C
−6.0
−7.0
−7.5
0.5
−
−
6.0
7.0
7.5
A
T = 0°C to 70°C
A
T = T
A
to T
low
high
= 2.5 V, V = −2.5 V
EE
T = 25°C
−6.0
−7.5
−7.5
0.5
−
−
6.0
7.5
7.5
A
T = 0°C to 70°C
A
T = T
A
to T
low
high
Input Offset Voltage Temperature Coefficient (R = 50)
DV / DT
−
8.0
−
mV/°C
S
IO
T = T
to T
A
low
high
Input Bias Current (V = 1.0 V to 5.0 V)
I
−
−
10
−
−
pA
V
CC
IB
Input Common Mode Voltage Range
Large Signal Voltage Gain
V
ICR
V
EE
to V
CC
A
VOL
kV/V
V
CC
V
CC
V
CC
= 0.45 V, V = −0.45 V
EE
R = 10 k
−
−
40
40
40
−
−
−
L
= 1.5 V, V = −1.5 V
EE
R = 10 k
L
= 2.5 V, V = −2.5 V
EE
R = 10 k
L
10
Output Voltage Swing, High State Output (V = + 0.5 V)
V
OH
V
ID
T = T
to T
A
low
high
V
CC
V
CC
V
CC
= 0.45 V, V = −0.45 V
EE
R = 10 k
0.40
0.35
0.442
0.409
−
−
L
R = 2.0 k
L
= 1.5 V, V = −1.5 V
EE
R = 10 k
L
1.45
1.40
1.494
1.473
−
−
R = 2.0 k
L
= 2.5 V, V = −2.5 V
EE
R = 10 k
L
2.45
2.40
2.493
2.469
−
−
R = 2.0 k
L
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NCS2002, NCV2002
DC ELECTRICAL CHARACTERISTICS (V = 2.5 V, V = −2.5 V, V = V = 0 V, R to Gnd, T = 25°C, unless otherwise noted)
CC
EE
CM
O
L
A
Rating
Symbol
Min
Typ
Max
Unit
Output Voltage Swing, Low State Output (V = − 0.5 V)
V
OL
V
ID
T = T
to T
high
A
low
V
CC
V
CC
V
CC
= 0.45 V, V = −0.45 V
EE
R = 10 k
−
−
−0.446
−0.432
−0.40
−0.35
L
R = 2.0 k
L
= 1.5 V, V = −1.5 V
EE
R = 10 k
L
−
−
−1.497
−1.484
−1.45
−1.40
R = 2.0 k
L
= 2.5 V, V = −2.5 V
EE
R = 10 k
L
−
−
−2.496
−2.481
−2.45
−2.40
R = 2.0 k
L
Common Mode Rejection Ratio (V = 0 to 5.0 V)
CMRR
PSRR
60
82
−
dB
dB
in
T = T
to T
A
low
high
Power Supply Rejection Ratio (V = 0.5 V to 2.5 V, V = −2.5 V)
60
85
−
CC
EE
T = T
to T
A
low
high
Output Short Circuit Current
I
mA
SC
V
CC
V
CC
V
CC
= 0.45 V, V = −0.45 V, V = $0.4 V
EE ID
Source Current High Output State
Sink Current Low Output State
0.5
−
1.0
−3.0
−
−2.0
= 1.5 V, V = −1.5 V, V = $0.5 V
EE
ID
Source Current High Output State
Sink Current Low Output State
25
−
32
−58
−
−45
= 2.5 V, V = −2.5 V, V = $0.5 V
EE
ID
Source Current High Output State
Sink Current Low Output State
65
−
86
−128
−
−100
Power Supply Current (Per Amplifier, V = 0 V)
I
D
mA
O
T = T
to T
A
low
high
V
CC
V
CC
V
CC
= 0.5 V to V = −0.5 V
EE
Venable = V
Venable = V
−
−
480
1.5
600
3.0
CC
EE
= 1.5 V to V = −1.5 V
EE
Venable = V
Venable = V
−
−
720
2.2
900
5.0
CC
EE
= 2.5 V to V = −2.5 V
EE
Venable = V
−
−
820
2.5
1000
5.0
CC
EE
Venable = V
Enable Input Threshold Voltage (V = 2.5 V, V = −2.5 V)
V
th(EN)
V
CC
EE
Operating
Disabled
−
2.7 V + V
1.9
2.8 V + V
−
EE
EE
1.7 V + V
EE
Enable Input Current (V = 5.0 V, V = 0)
I
mA
CC
EE
Enable
Enable = 5.0 V
Enable = Gnd
−
−
1.1
1.1
2.0
2.0
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NCS2002, NCV2002
AC ELECTRICAL CHARACTERISTICS(V = 2.5 V, V = −2.5 V, V = V = 0 V, R to Gnd, T = 25°C, unless otherwise noted)
CC
EE
CM
O
L
A
Rating
= 0 V)
Symbol
Min
Typ
Max
−
Unit
tera W
pf
Differential Input Resistance (V
R
in
C
in
e
n
−
−
−
>1.0
3.0
CM
Differential Input Capacitance (V
= 0 V)
−
CM
Equivalent Input Noise Voltage (f = 1.0 kHz)
Gain Bandwidth Product (f = 100 kHz)
100
−
nV/ǠHz
MHz
GBW
V
CC
V
CC
V
CC
= 0.45 V, V = −0.45 V
−
−
0.6
0.8
0.8
0.9
−
−
−
EE
= 1.5 V, V = −1.5 V
EE
= 2.5 V, V = −2.5 V
EE
Gain Margin (R = 10 k, C = 5.0 pf)
Am
−
−
−
6.5
60
80
−
−
−
dB
Deg
kHz
%
L
L
Phase Margin (R = 10 k, C = 5.0 pf)
fm
L
L
Power Bandwidth (V = 4.0 Vpp, R = 2.0 k, THD = 1.0 %, A = 1.0)
BW
P
O
L
V
Total Harmonic Distortion (V = 4.0 Vpp, R = 2.0 k, A = 1.0)
THD
SR
O
L
V
f = 1.0 kHz
f = 10 kHz
−
−
0.008
0.08
−
−
Slew Rate (V = $2.5 V, V = −2.0 V to 2.0 V, R = 2.0 k, A = 1.0)
V/ms
S
O
L
V
Positive Slope
Negative Slope
0.85
0.85
1.2
1.3
−
−
Time Delay for Device to Turn On (R = 10 k)
t
t
−
−
5.5
2.5
7.5
3.0
ms
ms
L
on
Time Delay for Device to Turn Off (R = 10 k)
L
off
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4
NCS2002, NCV2002
0
0
−200
−400
−600
600
V
CC
−0.1
−0.2
−0.3
−0.4
−0.5
0.4
V
= ±2.5 V
S
V
CC
R to Gnd
T = 25°C
A
High State Output
Sourcing Current
L
V
S
= $2.5 V
R to Gnd
T = 25°C
A
L
High State Output
Sourcing Current
Low State Output
Sinking Current
0.3
400
Low State Output
Sinking Current
0.2
200
0
0.1
0
V
EE
V
EE
0
4.0
8.0
12
16
20
100
1.0 k
10 k
100 k
1.0 M
R , Load Resistance (W)
L
I , Load Current (mA)
L
Figure 2. Output Saturation Voltage versus
Load Resistance
Figure 3. Output Saturation Voltage versus
Load Current
10,000
1000
100
100
V
= $2.5 V
0
S
Gain
R = 100 k
L
80
60
40
20
0
20
T = 25°C
A
Amp = 0.8 mV
Phase
60
100
140
180
10
V
= ±2.5 V
S
R = ∞
C = 0
A = 1.0
V
L
1.0
0
L
1.0
10
100
1.0 k
10 k
100 k 1.0 M 10 M
0
25
50
75
100
125
T , Ambient Temperature (°C)
A
f, Frequency (Hz)
Figure 4. Input Bias Current versus
Temperature
Figure 5. Gain and Phase versus Frequency
V
= $2.5 V
S
V
= $2.5 V
S
R = 10 k
C = 10 pF
L
R = 10 k
C = 10 pF
L
L
L
A = 1.0
V
A = 1.0
V
T = 25°C
A
T = 25°C
A
t, Time (500 ns/Div)
t, Time (1.0 ms/Div)
Figure 6. Transient Response
Figure 7. Slew Rate
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5
NCS2002, NCV2002
10
8.0
6.0
4.0
2.0
90
A = 1.0
V
80
70
60
50
40
30
20
V
= ±2.5 V
R = 10 k
S
L
V
V
= ±3.5 V
= ±2.5 V
R = ∞
T = 25°C
A
S
L
A = 1.0
V
T = 25°C
A
S
V
S
= ±0.45 V
10
0
0
1.0 k
10 k
100 k
1.0 M
10
100
1.0 k
10 k
100 k 1.0 M
10 M
f, Frequency (Hz)
f, Frequency (Hz)
Figure 8. Output Voltage versus Frequency
Figure 9. Common Mode Rejection Ratio
versus Frequency
120
280
240
200
160
120
80
V
= ±2.5 V
S
Output Pulsed Test
at 3% Duty Cycle
−40°C
R = ∞
100
80
L
25°C
A = 1.0
V
PSR +
T = 25°C
A
PSR −
60
85°C
40
20
0
40
0
0
±0.5
±1.0
±1.5
±2.0
±2.5
±3.0 ±3.5
10
100
1.0 k
10 k
100 k
1.0 M
10 M
f, Frequency (Hz)
V , Supply Voltage (V)
S
Figure 10. Power Supply Rejection Ratio
versus Frequency
Figure 11. Output Short Circuit Sinking
Current versus Supply Voltage
200
160
120
80
1.0
0.8
0.6
0.4
Output Pulsed Test
at 3% Duty Cycle
−40°C
85°C
25°C
25°C
−40°C
85°C
0.2
0
40
0
R = ∞
A = 1.0
V
L
0
±0.5
±1.0
±1.5
±2.0
±2.5
±3.0
±3.5
0
±0.5
±1.0
±1.5
±2.0
±2.5
±3.0
±3.5
V
S,
Supply Voltage (V)
V , Supply Voltage (V)
S
Figure 12. Output Short Circuit Sourcing
Current versus Supply Voltage
Figure 13. Supply Current versus Supply
Voltage with No Load
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NCS2002, NCV2002
10
10
A = 1000
V
A = 1000
V
1.0
0.1
1.0
A = 100
A = 100
V
V
V
V
= ±0.5 V
V
V
= ±0.5 V
S
S
A = 10
V
A = 10
V
= 0.4 V
= 0.4 V
out
pp
out
pp
R = 2.0 k
T = 25°C
A
R = 10 k
T = 25°C
A
L
L
0.1
A = 1.0
V
A = 1.0
V
0.01
0.01
10
100
1.0 k
10 k
100 k
10
100
1.0 k
10 k
100 k
f, Frequency (Hz)
f, Frequency (Hz)
Figure 14. Total Harmonic Distortion versus
Frequency with 1.0 V Supply
Figure 15. Total Harmonic Distortion versus
Frequency with 1.0 V Supply
10
1.0
0.1
10
A = 1000
A = 1000
V
V
1.0
0.1
A = 100
V
A = 100
V
A = 10
V
A = 10
V
V
V
= ±2.5 V
V
V
= ±2.5 V
S
S
0.01
0.01
= 4.0 V
= 4.0 V
out
pp
out
pp
A = 1.0
V
R = 10 k
T = 25°C
A
R = 2.0 k
T = 25°C
A
L
L
A = 1.0
V
0.001
0.001
10
100
1.0 k
10 k
100 k
10
100
1.0 k
10 k
100 k
f, Frequency (Hz)
f, Frequency (Hz)
Figure 16. Total Harmonic Distortion versus
Frequency with 5.0 V Supply
Figure 17. Total Harmonic Distortion versus
Frequency with 5.0 V Supply
3.0
2.0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
+Slew Rate, V = ±2.5 V
S
V
= ±2.5 V
S
R = 10 k
C = 10 pF
L
L
−Slew Rate, V = ±2.5 V
S
+Slew Rate, V = ±0.5 V
S
−Slew Rate, V = ±0.5 V
S
1.0
0
R = 10 k
L
C = 10 pF
L
A = 1.0
V
0.6
0.5
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T , Ambient Temperature (°C)
A
T , Ambient Temperature (°C)
A
Figure 18. Slew Rate versus Temperature
Figure 19. Gain Bandwidth Product versus
Temperature
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NCS2002, NCV2002
100
60
100
60
Phase Margin
V
= ±2.5 V
S
100
140
180
220
260
40
20
0
80
60
40
80
60
40
V
= ±0.5 V
S
V
= ±2.5 V
S
R = 10 k
C = 10 pF
L
V
S
= ±2.5 V
L
V
= ±0.5 V
S
Gain Margin
R = 100 k
T = 25°C
L
20
0
−20
−40
20
0
A
Amp = 0.8 mV
100 k
−50 −25
0
25
50
75
100
125
10 k
1.0 M
10 M
100 M
f, Frequency (Hz)
T , Ambient Temperature (°C)
A
Figure 20. Voltage Gain and Phase versus
Frequency
Figure 21. Gain and Phase Margin versus
Temperature
100
100
100
100
Phase Margin
Phase Margin
80
60
40
80
60
40
80
60
80
60
V
= ±2.5 V
V
= ±2.5 V
S
S
R = 10 k
R = 10 k
C = 10 pF
T = 25°C
A
L
L
A = 100
V
L
T = 25°C
A
40
20
0
40
20
0
Gain Margin
Gain Margin
20
0
20
0
1.0
10
100
1.0 k
10 k
100 k
1.0
10
100
1000
C , CapacitIve Load (pF)
L
R , Differential Source Resistance (W)
t
Figure 22. Gain and Phase Margin versus
Differential Source Resistance
Figure 23. Gain and Phase Margin versus
Output Load Capacitance
100
80
100
80
60
40
20
8.0
6.0
Phase Margin
60
4.0
2.0
40
Gain Margin
R = 10 k
L
20
0
A = 100
V
T = 25°C
A
0
0
0
±0.5 ±1.0
±1.5
±2.0
±2.5
±3.0
±3.5
0
±0.5 ±1.0
±1.5
±2.0
±2.5
±3.0 ±3.5
V , Supply Voltage (V)
S
V , Supply Voltage (V)
S
Figure 24. Output Voltage Swing versus
Supply Voltage
Figure 25. Gain and Phase Margin versus
Supply Voltage
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NCS2002, NCV2002
100
80
60
40
20
0
20
V
= ±2.5 V
S
15
10
5
R = ∞
C = 0
L
L
A = 1.0
V
T = 25°C
A
0
−5
−10
R = 10 k
T = 25°C
A
L
−15
−20
0
±0.5
±1.0
±1.5
±2.0
±2.5
±3.0
±3.5
−3.0
−2.0
−1.0
, Common Voltage Range (V)
CM
0
1.0
2.0
3.0
V , Supply Voltage (V)
V
S
Figure 26. Open Loop Voltage Gain versus
Supply Voltage
Figure 27. Input Offset Voltage versus Common
Mode Input Voltage Range, VS = + 2.5 V
20
15
10
5
3.0
2.0
1.0
0
V
= ±0.9 V
S
R = ∞
C = 0
L
L
A = 1.0
V
T = 25°C
A
D V = 5.0 mV
IO
R = ∞
L
0
C = 0
L
A = 1.0
T = 25°C
A
V
−5
−10
−1.0
−2.0
−3.0
−15
−20
−1.0 −0.8 −0.6 −0.4 −0.2
0
0.2 0.4 0.6 0.8 1.0
0
±0.5
±1.0
±1.5
±2.0
±2.5
±3.0
V
CM
, Common Mode Input Voltage (V)
V , Supply Voltage (V)
S
Figure 28. Input Offset Voltage versus Common
Figure 29. Common−Mode Input Voltage Range
versus Power Supply Voltage
Mode Input Voltage Range, VS = + 0.9 V
3.0
2.5
2.0
1.5
1.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
EN(on)
V
EN(off)
R = ∞
L
A = 1.0
T = 25°C
A
A = ∞
T = 25°C
A
0.5
0
V
V
0.5
0
±3.5
0
±0.5
±1.0
±1.5
±2.0
±2.5
±3.0
±3.5
0
±0.5
±1.0
±1.5
±2.0
±2.5
±3.0
V , Supply Voltage (V)
S
V , Supply Voltage (V)
S
Figure 30. Supply Current versus
Supply Voltage (Disabled)
Figure 31. Enable Input Voltage versus
Supply Voltage
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NCS2002, NCV2002
16
14
12
10
8.0
6.0
4.0
2.0
0
R = 10 k
T = 25°C
A
L
t
t
on
off
0
±0.5
±1.0
±1.5
±2.0
±2.5
±3.0
±3.5
V , SUPPLY VOLTAGE (V)
S
Figure 32. Propagation Delay versus Supply Voltage
APPLICATION INFORMATION AND OPERATING DESCRIPTION
GENERAL INFORMATION
The ultra low input bias current of the NCS2002 allows
the use of extremely high value source and feedback resistor
without reducing the amplifier’s gain accuracy. These high
value resistors, in conjunction with the device input and
The NCS2002 is an industry first rail−to−rail input,
rail−to−rail output amplifier that features guaranteed sub
one volt operation. This unique feature set is achieved with
the use of a modified analog CMOS process that allows the
implementation of depletion MOSFET devices. The
amplifier has a 1.0 MHz gain bandwidth product, 1.2 V/ms
slew rate and is operational over a power supply range less
than 0.9 V to as high as 7.0 V.
printed circuit board parasitic capacitances C , will add an
in
additional pole to the single pole amplifier in Figure 33. If
low enough in frequency, this additional pole can reduce the
phase margin and significantly increase the output settling
time. The effects of C , can be canceled by placing a zero
in
into the feedback loop. This is accomplished with the
Inputs
addition of capacitor C . An approximate value for C can
fb
fb
The input topology chosen for this device series is
unconventional when compared to most low voltage
operational amplifiers. It consists of an N−channel depletion
mode differential transistor pair that drives a folded cascade
stage and current mirror. This configuration extends the
be calculated by:
R
+
C
in
in
C
fb
R
fb
C
fb
input common mode voltage range to encompass the V
EE
and V power supply rails, even when powered from a
CC
R
fb
combined total of less than 0.9 volts. Figures 27, 28 and 29
show the input common mode voltage range versus power
supply voltage.
The differential input stage is laser trimmed in order to
minimize offset voltage. The N−channel depletion mode
MOSFET input stage exhibits an extremely low input bias
current of less than 10 pA. The input bias current versus
temperature is shown in Figure 4. Either one or both inputs
R
in
−
+
Input
Output
C
in
C
= Input and printed circuit board capacitance
in
Figure 33. Input Capacitance Pole Cancellation
can be biased as low as V minus 300 mV to as high as
EE
7.0 V without causing damage to the device. If the input
common mode voltage range is exceeded, the output will not
display a phase reversal. If the maximum input positive or
negative voltage ratings are to be exceeded, a series resistor
must be used to limit the input current to less than 2.0 mA.
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10
NCS2002, NCV2002
Output
The output stage consists of complimentary P and N
large signal rise and fall time and reduce the output
amplitude. Depending upon the capacitor characteristics,
the isolation resistor value will typically be between 50 to
500 W. The output drive capability for resistive and
capacitive loads is shown in Figures 2, 3, and 23.
channel devices connected to provide rail−to−rail output
drive. With a 2.0 k load, the output can swing within 50 mV
of either rail. It is also capable of supplying over 75 mA
when powered from 5.0 V and 1.0 mA when powered from
0.9 V.
R
+
−
Input
Output
When connected as a unity gain follower, the NCS2002
can directly drive capacitive loads in excess of 820 pF at
room temperature without oscillating but with significantly
reduced phase margin. The unity gain follower
configuration exhibits the highest bandwidth and is most
prone to oscillations when driving a high value capacitive
load. The capacitive load in combination with the
amplifier’s output impedance, creates a phase lag that can
result in an under−damped pulse response or a continuous
oscillation. Figure 35 shows the effect of driving a large
capacitive load in a voltage follower type of setup. When
driving capacitive loads exceeding 820 pF, it is
recommended to place a low value isolation resistor
between the output of the op amp and the load, as shown in
Figure 34. The series resistor isolates the capacitive load
from the output and enhances the phase margin. Refer to
Figure 36. Larger values of R will result in a cleaner output
waveform but excessively large values will degrade the
C
L
Isolation resistor R = 50 to 500
Figure 34. Capacitance Load Isolation
Note that the lowest phase margin is observed at cold
temperature and low supply voltage.
Enable Pin
The enable pin allows the user to externally control the
device. if the enable pin is pulled below the input disable
threshold voltage (V
< 45% V ), the amplifier is
EN
CC
disabled. Once the enable pin is taken above the threshold
voltage (V = 60% V ), the amplifier will turn on. In the
EN
CC
event the enable pin is not connected, the amplifier will
remain on by default
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11
NCS2002, NCV2002
V
in
V
V
= ±0.45 V
= 0.8 Vpp
S
in
R = 0
C = 820 pF
L
A = 1.0
V
T = 25°C
A
V
out
Figure 35. Small Signal Transient Response with Large Capacitive Load
V
in
V
V
= ±0.45 V
= 0.8 Vpp
S
in
R = 51
C = 820 pF
L
A = 1.0
V
T = 25°C
A
V
out
Figure 36. Small Signal Transient Response with Large
Capacitive Load and Isolation Resistor.
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12
NCS2002, NCV2002
R
T
470 k
V
CC
Output Voltage
0
0.9 V
0.67 V
C
1.0 nF
CC
CC
Timing Capacitor
Voltage
T
0.33 V
−
+
f
O
= 1.5 kHz
The non−inverting input threshold levels are set so that
the capacitor voltage oscillates between 1/3 and 2/3 of
R
470 k
1a
V
CC
. This requires the resistors R , R and R to be of
1a 1b 2
equal value. The following formula can be used to
approximate the output frequency.
0.9 V
R
470 k
2
R
1b
470 k
1
f
+
O
1.39 RTCT
Figure 37. 0.9 V Square Wave Oscillator
D
1
1N4148
V
10 k
CC
cww
cw
Output Voltage
0
CC
CC
1.0 M
D
2
0.67 V
0.33 V
Timing Capacitor
Voltage
1N4148
10 k
Clock−wise, Low Duty Cycle
V
CC
C
T
V
CC
1.0 nF
Output Voltage
−
+
0
CC
CC
f
O
Timing Capacitor
Voltage
0.67 V
0.33 V
R
1a
470 k
Counter−Clock−wise, High Duty Cycle
V
CC
R
470 k
2
The timing capacitor C will charge through diode D and discharge
T
2
R
through diode D , allowing a variable duty cycle. The pulse width of the
1b
1
470 k
signal can be programmed by adjusting the value of the trimpot. The ca-
pacitor voltage will oscillate between 1/3 and 2/3 of V , since all the
CC
resistors at the non−inverting input are of equal value.
Figure 38. Variable Duty Cycle Pulse Generator
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13
NCS2002, NCV2002
R
1
1.0 M
2.5 V
R
3
1.0 k
+
−
≈
10,000 µF
C
in
10 mF
−2.5 V
R
R
1
3
C
+
C
in
eff.
R
2
1.0 M
Figure 39. Positive Capacitance Multiplier
A
f
C
f
400 pF
R
f
100 k
f
L
f
H
0.5 V
1
R
10 k
2
f +
[ 200 Hz
[ 4.0 kHz
L
2 p R C
1 1
+
V
O
1
f
+
V
in
−
H
2 p R C
f f
C
1
R
10 k
1
80 nF
−0.5 V
R
f
R
A + 1 )
+ 11
f
2
Figure 40. 1.0 V Voiceband Filter
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14
NCS2002, NCV2002
V
supply
V
CC
V
in
V
+
−
in
I
+
sink
R
sense
R
sense
Figure 41. High Compliance Current Sink
I
s
V
L
1.0 V
R
sense
R
3
1.0 k
R
R
1
4
I
V
O
R
s
L
1.0 k
1.0 k
R
+
−
5
435 mA
212 mA
34.7 mV
36.9 mV
V
O
2.4 k
75
R
6
For best performance, use low
tolerance resistors.
R
2
3.3 k
Figure 42. High Side Current Sense
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15
NCS2002, NCV2002
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE I
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
L
6
5
2
4
B
S
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
1
3
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
D
A
B
C
D
G
H
J
2.90
1.30
0.90
0.25
0.85
0.013
0.10
0.20
1.25
0
3.10 0.1142 0.1220
1.70 0.0512 0.0669
1.10 0.0354 0.0433
0.50 0.0098 0.0197
1.05 0.0335 0.0413
0.100 0.0005 0.0040
0.26 0.0040 0.0102
0.60 0.0079 0.0236
1.55 0.0493 0.0610
G
M
J
C
0.05 (0.002)
K
L
K
M
S
10
0
3.00 0.0985 0.1181
10
_
_
_
_
H
2.50
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NCS2002/D
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