NCS333SQ3T2G [ONSEMI]
Zero-Drift Operational Amplifier;
| 型号： | NCS333SQ3T2G |
| 厂家： | 
ONSEMI |
| 描述： | Zero-Drift Operational Amplifier |
| 文件： | 总27页 (文件大小：931K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCS333A, NCV333A,
NCS2333, NCV2333,
NCS4333, NCV4333,
NCS333
10 mV Offset, 0.07 mV/5C,
Zero-Drift Operational
Amplifier
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5
The NCS333/2333/4333 family of zero−drift op amps feature offset
voltage as low as 10 mV over the 1.8 V to 5.5 V supply voltage range.
The zero−drift architecture reduces the offset drift to as low as
0.07 mV/°C and enables high precision measurements over both time
and temperature. This family has low power consumption over a wide
dynamic range and is available in space saving packages. These
features make it well suited for signal conditioning circuits in portable,
industrial, automotive, medical and consumer markets.
5
1
1
SOT23−5
SN SUFFIX
CASE 483
SC70−5
SQ SUFFIX
CASE 419A
1
Features
UDFN8
MU SUFFIX
CASE 517AW
MSOP−8
DM SUFFIX
CASE 846A−02
• Gain−Bandwidth Product:
♦ 270 kHz (NCx2333)
♦ 350 kHz (NCx333, NCx333A, NCx4333)
• Low Supply Current: 17 mA (typ at 3.3 V)
8
14
1
• Low Offset Voltage:
1
♦ 10 mV max for NCS333, NCS333A
♦ 30 mV max for NCV333A, NCx2333 and NCx4333
• Low Offset Drift: 0.07 mV/°C max for NCS333/A
SOIC−8
D SUFFIX
CASE 751
SOIC−14
D SUFFIX
CASE 751A
• Wide Supply Range: 1.8 V to 5.5 V
• Wide Temperature Range: −40°C to +125°C
• Rail−to−Rail Input and Output
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 2 of this data sheet.
• Available in Single, Dual and Quad Packages
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
Applications
• Automotive
• Battery Powered/ Portable Application
• Sensor Signal Conditioning
• Low Voltage Current Sensing
• Filter Circuits
• Bridge Circuits
• Medical Instrumentation
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
June, 2018 − Rev. 18
NCS333/D
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
DEVICE MARKING INFORMATION
Single Channel Configuration
NCS333, NCS333A, NCV333A
33XAYWG
33XMG
G
G
TSOP−5/SOT23−5
SC70−5
CASE 483
CASE 419A
Dual Channel Configuration
NCS2333, NCV2333
8
8
1
2333
AYWG
G
N2333
ALYW
G
33A
YM
1
1
UDFN8, 2x2, 0.5P
CASE 517AW
Micro8/MSOP8
CASE 846A−02
SOIC−8
CASE 751
Quad Channel Configuration
NCS4333, NCV4333
14
NCS4333G
AWLYWW
1
SOIC−14
CASE 751A
X
= Specific Device Code
= E = NCS333 (SOT23−5)
= H = NCS333 (SC70−5)
= G = NCS333A (SOT23−5)
= K = NCS333A (SC70−5)
= M = NCV333A (SOT23−5)
= N = NCV333A (SC70−5)
= Assembly Location
= Year
A
Y
W
M
= Work Week
= Date Code
G or G = Pb−Free Package
(Note: Microdot may be in either location)
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2
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
PIN CONNECTIONS
Single Channel Configuration
NCS333, NCS333A, NCV333A
1
2
3
5
4
OUT
VSS
IN+
IN+
VSS
IN−
VDD
OUT
1
2
3
VDD
5
4
IN−
SC70−5 / SC−88−5 / SOT−353−5
SOT23−5 / TSOP−5
Dual Channel Configuration
NCS2333, NCV2333
Quad Channel Configuration
NCS4333, NCV4333
1
OUT 1
IN− 1
IN+ 1
VDD
14
13
12
11
10
9
OUT 4
IN− 4
IN+ 4
OUT 1
IN− 1
IN+ 1
VSS
1
2
3
4
8
7
6
5
VDD
2
−
−
−
OUT 2
IN− 2
IN+ 2
+
+
+
3
4
5
6
7
−
+
VSS
IN+ 3
IN− 3
OUT 3
IN+ 2
IN− 2
+
+
UDFN8* / Micro8 / SOIC−8
−
−
*The exposed pad of the UDFN8 package
can be floated or connected to VSS.
8
OUT 2
SOIC−14
ORDERING INFORMATION
†
Configuration
Automotive
Device
Package
SOT23−5 / TSOP−5
Shipping
Single
No
NCS333SN2T1G
NCS333ASN2T1G
NCS333SQ3T2G
NCS333ASQ3T2G
NCV333ASQ3T2G
NCV333ASN2T1G
NCS2333MUTBG
NCS2333DR2G
NCS2333DMR2G
NCV2333DR2G
NCV2333DMR2G
NCS4333DR2G
NCV4333DR2G
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
4000 / Tape & Reel
3000 / Tape & Reel
4000 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
SC70−5 / SC−88−5 / SOT−353−5
Yes
No
SOT23−5 / TSOP−5
UDFN8
Dual
SOIC−8
MICRO−8
SOIC−8
Yes
MICRO−8
SOIC−14
Quad
No
Yes
SOIC−14
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
ABSOLUTE MAXIMUM RATINGS
Over operating free−air temperature, unless otherwise stated.
Parameter
Rating
Unit
Supply Voltage
7
V
INPUT AND OUTPUT PINS
Input Voltage (Note 1)
(VSS) − 0.3 to (VDD) + 0.3
V
Input Current (Note 1)
10
mA
Output Short Circuit Current (Note 2)
TEMPERATURE
Continuous
Operating Temperature Range
Storage Temperature Range
Junction Temperature
−40 to +125
−65 to +150
+150
°C
°C
°C
ESD RATINGS (Note 3)
Human Body Model (HBM)
Machine Model (MM)
4000
200
V
V
V
Charged Device Model (CDM)
OTHER RATINGS
2000
Latch−up Current (Note 4)
MSL
100
mA
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Input terminals are diode−clamped to the power−supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less
2. Short−circuit to ground.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard JS−001 (AEC−Q100−002)
ESD Machine Model tested per JEDEC standard JESD22−A115 (AEC−Q100−003)
ESD Charged Device Model tested per JEDEC standard JESD22−C101 (AEC−Q100−011)
4. Latch−up Current tested per JEDEC standard: JESD78.
THERMAL INFORMATION (Note 5)
Parameter
Symbol
Package
SOT23−5 / TSOP5
SC70−5 / SC−88−5 / SOT−353−5
Micro8 / MSOP8
SOIC−8
Value
290
425
298
250
228
216
Unit
Thermal Resistance,
Junction to Ambient
q
°C/W
JA
UDFN8
SOIC−14
2
5. As mounted on an 80x80x1.5 mm FR4 PCB with 650 mm and 2 oz (0.07 mm) thick copper heat spreader. Following JEDEC JESD/EIA 51.1,
51.2, 51.3 test guidelines
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Range
Unit
V
Supply Voltage (V − V
)
V
S
1.8 to 5.5
−40 to 105
−40 to 125
DD
SS
Specified Operating Temperature Range
NCS333
T
A
°C
NCx333A, NCx2333, NCx4333
Input Common Mode Voltage Range
V
ICMR
V
SS
−0.1 to V +0.1
V
DD
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
ELECTRICAL CHARACTERISTICS: V = 1.8 V to 5.5 V
S
At T = +25°C, R = 10 kW connected to midsupply, V
= V
= midsupply, unless otherwise noted.
A
L
CM
OUT
Boldface limits apply over the specified operating temperature range, guaranteed by characterization and/or design.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
Min
Typ
Max
Unit
V
OS
V
S
= +5 V
NCS333, NCS333A
3.5
6.0
10
30
mV
NCV333A,
NCx2333, NCx4333
Offset Voltage Drift vs Temp
Offset Voltage Drift vs Supply
DV /DT
NCS333, NCS333A
NCV333A, V = 5 V
0.03
0.03
0.04
0.095
0.32
0.40
0.07
0.14
0.07
0.19
5
mV/°C
mV/V
OS
S
NCx2333, V = 5 V
S
NCx4333, V = 5 V
S
DV /DV
NCS333, NCS333A Full temperature range
OS
S
NCV333A
T = +25°C
A
5
Full temperature range
8
NCx2333, NCx4333
T = +25°C
A
0.32
5
Full temperature range
NCS333, NCx333A
NCx2333, NCx4333
12.6
200
400
Input Bias Current
(Note 6)
I
IB
T = +25°C
A
60
60
pA
Full temperature range
+400
50
Input Offset Current
(Note 6)
I
T = +25°C
NCS333, NCx333A
NCx2333, NCx4333
400
800
pA
dB
OS
A
50
Common Mode Rejection Ratio
(Note 7)
CMRR
V
V
= 1.8 V
111
118
123
S
= 3.3 V
NCS333, NCS333A,
S
V
= 5.0 V
106
103
S
NCx2333, NCx4333
NCV333A
123
127
180
90
V
S
= 5.5 V
Input Resistance
Input Capacitance
R
C
Differential
Common Mode
Differential
GW
IN
IN
NCS333
2.3
4.6
4.1
7.9
pF
Common Mode
Differential
NCx2333, NCx4333,
NCx333A
Common Mode
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain
(Note 6)
A
VOL
V
SS
+ 100 mV < V < V − 100 mV
106
145
dB
O
DD
Open Loop Output Impedance
Output Voltage High,
Z
f = UGBW, I = 0 mA
300
10
W
out−OL
O
V
OH
T = +25°C
A
50
70
50
70
mV
Referenced to V
DD
Full temperature range
Output Voltage Low,
Referenced to V
V
OL
T = +25°C
A
10
mV
SS
Full temperature range
6. Guaranteed by characterization and/or design
7. Specified over the full common mode range: V − 0.1 < V
< V + 0.1
SS
CM
DD
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5
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
ELECTRICAL CHARACTERISTICS: V = 1.8 V to 5.5 V
S
At T = +25°C, R = 10 kW connected to midsupply, V
= V
= midsupply, unless otherwise noted.
A
L
CM
OUT
Boldface limits apply over the specified operating temperature range, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS
Output Current Capability
I
O
Sinking Current
NCS333
25
11
mA
NCx333A,
NCx2333, NCx4333
Sourcing Current
5.0
Capacitive Load Drive
NOISE PERFORMANCE
Voltage Noise Density
Voltage Noise
C
See Figure 13
L
e
N
f
= 1 kHz
62
1.1
0.5
350
135
nV / √Hz
IN
e
P−P
f
f
= 0.1 Hz to 10 Hz
= 0.01 Hz to 1 Hz
mV
PP
IN
IN
Current Noise Density
Channel Separation
i
N
f
IN
= 10 Hz
fA / √Hz
NCx2333, NCx4333
dB
DYNAMIC PERFORMANCE
Gain Bandwidth Product
GBWP
C = 100 pF
L
NCS333, NCx333A,
NCx4333
350
kHz
NCx2333
270
18
Gain Margin
A
C = 100 pF
dB
°
M
L
Phase Margin
f
M
C = 100 pF
L
55
Slew Rate
SR
G = +1
0.15
V/ms
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
NCS333, NCS333A
Full temperature
range
106
130
130
dB
NCx2333, NCx4333,
NCV333A
T = +25°C
A
106
Full temperature range
98
Turn−on Time
t
V
= 5 V
100
17
ms
ON
S
Quiescent Current
(Note 8)
I
Q
NCS333, NCS333A,
NCx2333, NCx4333
1.8 V ≤ V ≤ 3.3 V
25
27
33
35
30
35
40
45
mA
S
3.3 V < V ≤ 5.5 V
21
20
28
S
NCV333A
1.8 V ≤ V ≤ 3.3 V
S
3.3 V < V ≤ 5.5 V
S
8. No load, per channel
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
TYPICAL CHARACTERISTICS
120
100
80
60
40
20
0
120
105
90
120
110
100
90
T = 25°C
A
Phase Margin
80
75
70
60
Gain
60
50
45
40
C = 100 pF
R = 10 kW
T = 25°C
L
30
30
L
20
A
−20
−40
15
0
10
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 1. Open Loop Gain and Phase Margin
vs. Frequency
Figure 2. CMRR vs. Frequency
120
3
2
1
0
T = 25°C
A
T = 25°C
A
V
V
= 5.5 V, V
= 1.8 V, V
S
OH
100
80
S
OH
+PSRR
60
−PSRR
V
= 1.8 V, V
S
S
OL
40
−1
20
0
−2
−3
V
= 5.5 V, V
3
OL
10
100
1k
10k
100k
1M
0
1
2
4
5
6
7
8
9
10
FREQUENCY (Hz)
OUTPUT CURRENT (mA)
Figure 3. PSRR vs. Frequency
Figure 4. Output Voltage Swing vs. Output
Current
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NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
TYPICAL CHARACTERISTICS
200
150
100
50
200
T = 25°C
S
A
V
150
100
50
= 1.8 V
I
I
IB+
I
I
IB+
IB−
0
0
IB−
−50
−100
−50
−100
T = 25°C
S
A
V
= 5 V
−150
−200
−150
−200
−0.2
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
COMMON MODE VOLTAGE (V)
−40 −20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 5. Input Bias Current vs. Common
Mode Voltage
Figure 6. Input Bias Current vs. Temperature
5
4
30
25
20
15
4
3
V
= 5.5 V
S
Input
V
V
= 5.0 V
= 3.3 V
3
2
1
S
S
2
Output
0
1
0
V
S
= 1.8 V
−1
−2
10
V
= 5.0 V
A = +1
R = 10 kW
S
−1
V
5
0
−3
−4
−2
−3
L
Per Channel
−40 −20
0
20
40
60
80
100
−100
0
100
200
TIME (ms)
300
400
TEMPERATURE (°C)
Figure 7. Quiescent Current vs. Temperature
Figure 8. Large Signal Step Response
0.20
0.15
0.10
0.05
0
1.0
3.0
0.5
0
2.5
2.0
Input
Input
−0.5
−1.0
−1.5
−2.0
1.5
1.0
0.5
0
V
= 5.0 V
S
A = −10
V
= 5.0 V
V
S
R = 10 kW
A = −1
L
V
Output
R = 10 kW
L
−0.05
Output
10
−0.10
−0.15
−2.5
−3.0
−0.5
−1.0
−10
0
20
30
TIME (ms)
TIME (50 ms/div)
Figure 9. Small Signal Step Response
Figure 10. Positive Overvoltage Recovery
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NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
TYPICAL CHARACTERISTICS
3.0
2.5
2.0
1.5
1.0
0.5
0
500
400
300
200
1.0
T = 25°C
R = 10 kW
L
A
0.5
0
Output
Input
−0.5
−1.0
−1.5
−2.0
V
= 5.0 V
S
A = −10
V
R = 10 kW
L
100
0
−0.5
−1.0
−2.5
−3.0
1
0
1
10
100
TIME (50 ms/div)
GAIN (V/V)
Figure 11. Negative Overvoltage Recovery
Figure 12. Setting Time to 0.1% vs.
Closed−Loop Gain
65
60
55
50
45
40
35
30
25
20
15
10
2000
1500
1000
500
V
= V /2
S
CM
R = 10 kW
T = 25°C
A
L
T = 25°C
A
0
−500
−1000
−1500
−2000
5
0
10
100
LOAD CAPACITANCE (pF)
1000
1
2
3
4
5
6
7
8
9
10
TIME (s)
Figure 13. Small−Signal Overshoot vs. Load
Figure 14. 0.1 Hz to 10 Hz Noise
Capacitance
1000
1000
T = 25°C
A
T = 25°C
A
100
10
100
10
1
10
100
1000
10,000
10
100
1000
10,000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. Voltage Noise Density vs.
Frequency
Figure 16. Current Noise Density vs.
Frequency
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NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
APPLICATIONS INFORMATION
OVERVIEW
NCS333 series of precision op amps uses
a
The NCS333, NCS333A, NCS2333, and NCS4333
precision op amps provide low offset voltage and zero drift
over temperature. The input common mode voltage range
extends 100 mV beyond the supply rails to allow for sensing
near ground or VDD. These features make the NCS333
series well−suited for applications where precision is
required, such as current sensing and interfacing with
sensors.
chopper−stabilized architecture, which provides the
advantage of minimizing offset voltage drift over
temperature and time. The simplified block diagram is
shown in Figure 17. Unlike the classical chopper
architecture, the chopper stabilized architecture has two
signal paths.
Main amp
+
IN+
O
−
IN−
−
+
+
−
+
−
Chopper
Chopper
RC notch filter
RC notch filter
Figure 17. Simplified NCS333 Block Diagram
In Figure 17, the lower signal path is where the chopper
samples the input offset voltage, which is then used to
correct the offset at the output. The offset correction occurs
at a frequency of 125 kHz. The chopper−stabilized
architecture is optimized for best performance at
frequencies up to the related Nyquist frequency (1/2 of the
offset correction frequency). As the signal frequency
exceeds the Nyquist frequency, 62.5 kHz, aliasing may
occur at the output. This is an inherent limitation of all
cascaded, symmetrical, RC notch filters tuned to the
chopper frequency and its fifth harmonic to reduce aliasing
effects.
The chopper−stabilized architecture also benefits from
the feed−forward path, which is shown as the upper signal
path of the block diagram in Figure 17. This is the high speed
signal path that extends the gain bandwidth up to 350 kHz.
Not only does this help retain high frequency components of
the input signal, but it also improves the loop gain at low
frequencies. This is especially useful for low−side current
sensing and sensor interface applications where the signal is
low frequency and the differential voltage is relatively
small.
chopper
and
chopper−stabilized
architectures.
Nevertheless, the NCS333 op amps have minimal aliasing
up to 125 kHz and low aliasing up to 190 kHz when
compared to competitor parts from other manufacturers.
ON Semiconductor’s patented approach utilizes two
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10
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
APPLICATION CIRCUITS
Low−Side Current Sensing
Low−side current sensing is used to monitor the current
through a load. This method can be used to detect
over−current conditions and is often used in feedback
control, as shown in Figure 18. A sense resistor is placed in
series with the load to ground. Typically, the value of the
sense resistor is less than 100 mW to reduce power loss
across the resistor. The op amp amplifies the voltage drop
across the sense resistor with a gain set by external resistors
R1, R2, R3, and R4 (where R1 = R2, R3 = R4). Precision
resistors are required for high accuracy, and the gain is set
to utilize the full scale of the ADC for the highest resolution.
R3
VLOAD
VDD
VDD
VDD
Load
R1
Microcontroller
+
RSENSE
ADC
control
−
R2
R4
Figure 18. Low−Side Current Sensing
Differential Amplifier for Bridged Circuits
produced is relatively small and needs to be amplified before
going into an ADC. Precision amplifiers are recommended
in these types of applications due to their high gain, low
noise, and low offset voltage.
Sensors to measure strain, pressure, and temperature are
often configured in a Wheatstone bridge circuit as shown in
Figure 19. In the measurement, the voltage change that is
VDD
VDD
−
+
Figure 19. Bridge Circuit Amplification
EMI Susceptibility and Input Filtering
General Layout Guidelines
Op amps have varying amounts of EMI susceptibility.
Semiconductor junctions can pick up and rectify EMI
signals, creating an EMI−induced voltage offset at the
output, adding another component to the total error. Input
pins are the most sensitive to EMI. The NCS333 op amp
family integrates low−pass filters to decrease sensitivity to
EMI.
To ensure optimum device performance, it is important to
follow good PCB design practices. Place 0.1 mF decoupling
capacitors as close as possible to the supply pins. Keep traces
short, utilize a ground plane, choose surface−mount
components, and place components as close as possible to
the device pins. These techniques will reduce susceptibility
to electromagnetic interference (EMI). Thermoelectric
effects can create an additional temperature dependent
offset voltage at the input pins. To reduce these effects, use
metals with low thermoelectric−coefficients and prevent
temperature gradients from heat sources or cooling fans.
www.onsemi.com
11
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
UDFN8 Package Guidelines
center pad can be electrically connected to VSS or it may be
left floating. When connected to VSS, the center pad acts as
a heat sink, improving the thermal resistance of the part.
The UDFN8 package has an exposed leadframe die pad on
the underside of the package. This pad should be soldered to
the PCB, as shown in the recommended soldering footprint
in the Package Dimensions section of this datasheet. The
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
DATE 17 JAN 2013
SCALE 2:1
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
G
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
---
0.004
0.004
0.004
0.010
0.012
---
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
GENERIC MARKING
DIAGRAM*
C
K
H
XXXMG
G
SOLDER FOOTPRINT
0.50
0.0197
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This infomration is generic. Please refer
to device data sheet for actual part
marking.
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
mm
inches
ǒ
Ǔ
SCALE 20:1
STYLE 3:
STYLE 1:
PIN 1. BASE
STYLE 2:
STYLE 4:
STYLE 5:
PIN 1. ANODE
2. EMITTER
3. BASE
PIN 1. ANODE 1
2. N/C
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
4. COLLECTOR
5. CATHODE
4. CATHODE 3
5. CATHODE 4
5. GATE 2
STYLE 9:
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
STYLE 7:
STYLE 8:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
PIN 1. BASE
2. EMITTER
3. BASE
PIN 1. CATHODE
2. COLLECTOR
3. N/C
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
4. COLLECTOR
5. COLLECTOR
4. BASE
5. EMITTER
98ASB42984B
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
DESCRIPTION: SC−88A (SC−70−5/SOT−353)
PAGE 1 OF2
DOCUMENT NUMBER:
98ASB42984B
PAGE 2 OF 2
ISSUE
REVISION
DATE
C
CONVERTED FROM PAPER DOCUMENT TO ELECTRONIC. REQ. BY N LAFEB-
RE.
20 JUN 1998
D
CONVERTED FROM MOTOROLA TO ON SEMICONDUCTOR. ADDED STYLE 5.
REQ. BY E. KIM.
24 JUL 2000
E
F
ADDED STYLES 6 & 7. REQ. BY S. BACHMAN.
03 AUG 2000
14 JUN 2001
25 JUN 2003
DELETED DIMENSION V, WAS 0.3−0.44MM/0.012−0.016IN. REQ. BY G. KWONG.
G
ADDED STYLE 8, REQ. BY S. CHANG; ADDED STYLE 9, REQ. BY S. BACHMAN;
ADDED NOTE 4, REQ. BY S. RIGGS
H
J
CHANGED STYLE 6. REQ. BY C. LIM
28 APR 2005
31 AUG 2005
13 JUL 2010
CHANGED TITLE DESCRIPTION. REQ. BY B. LOFTS.
K
CORRECTED TITLE AND DESCRIPTION TO SC−88A (SC−70−5/SOT−353). COR-
RECTED MARKING DIAGRAM. REQ. BY D. TRUHITTE.
L
ADDED SOLDER FOOTPRINT. REQ. BY I. MARIANO.
17 JAN 2013
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2013
Case Outline Number:
January, 2013 − Rev. L
419A
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE M
5
1
DATE 17 MAY 2016
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
2X
0.10
T
M
5
4
3
2X
0.20
T
B
S
1
2
K
B
A
DETAIL Z
G
A
MILLIMETERS
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
MIN
2.85
1.35
0.90
0.25
MAX
3.15
1.65
1.10
0.50
DETAIL Z
J
0.95 BSC
C
0.01
0.10
0.20
0
0.10
0.26
0.60
0.05
H
SEATING
PLANE
END VIEW
C
10
3.00
_
_
SIDE VIEW
2.50
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
1.9
0.074
5
1
5
0.95
0.037
XXXAYWG
XX MG
G
G
1
Analog
Discrete/Logic
2.4
XXX = Specific Device Code XX = Specific Device Code
0.094
A
Y
W
G
= Assembly Location
= Year
= Work Week
M
G
= Date Code
= Pb−Free Package
1.0
0.039
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
98ARB18753C
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
DESCRIPTION: TSOP−5
PAGE 1 OF2
DOCUMENT NUMBER:
98ARB18753C
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
A
INITIATED NEW MECHANICAL OUTLINE #483. REQ BY WL CHIN/L. RENNICK.
28 OCT 1998
13 NOV 1998
UPDATE OUTLINE DRAWING TO CORRECT DIN “C” (SHOULD BE FROM TIP OF
LID TO TOP OF PKG). DIM IN TABLE INCORRECTLY LISTED TO G, F TO H,
H TO J, N TO L & R TO M. REQ BY F. PADILLA
B
CHANGE OF LEGAL ONWERSHIP FROM MOTOROLA TO ON SEMICONDUC-
TOR. REQ BY A. GARLINGTON
20 APR 2001
C
D
E
F
ADDED NOTE “4”. REQ BY S. RIGGS
27 JUN 2003
07 APR 2005
14 SEP 2005
07 JUN 2006
ADDED FOOTPRINT INFORMATION. UPDATED MARKING. REQ. BY D. JOERSZ
CHANGED DEVICE MARKING FROM AWW TO AYW. REQ. BY J. MANES.
UPDATED DRAWINGS TO LATEST JEDEC STANDARDS. ADDED NOTE 5. REQ.
BY T. GURNETT.
G
H
ADDED MARKING DIAGRAM FOR IC OPTION. REQ. BY J. MILLER.
21 FEB 2007
18 MAY 2007
CORRECTED MARKING DIAGRAM ERROR BY REVERSING ANALOG AND
DISCRETE LABELS. REQ. BY GK SUA.
J
CHANGED NOTE 4. REQ. BY A. GARLINGTON.
13 MAR 2013
19 APR 2013
K
REMOVED DIMENSION L AND ADDED DATUMS A AND B TO TOP VIEW. REQ.
BY A. GARLINGTON.
L
REMOVED −02 FROM CASE CODE VARIANT. REQ. BY N. CALZADA.
23 SEP 2015
17 MAY 2016
M
CHANGED DIMENSIONS A & B FROM BASIC TO MIN AND MAX VALUES. REQ.
BY A. GARLINGTON.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2016
Case Outline Number:
May, 2016 − Rev. M
483
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN8, 2x2
CASE 517AW
ISSUE A
1
SCALE 2:1
DATE 13 NOV 2015
B
E
A
NOTES:
D
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMI-
NALS AND IS MEASURED BETWEEN 0.15
AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
L1
PIN ONE
REFERENCE
DETAIL A
ALTERNATE
CONSTRUCTIONS
2X
0.10 C
2X
0.10
C
TOP VIEW
MILLIMETERS
MOLD CMPD
DIM MIN
MAX
0.55
0.05
EXPOSED Cu
A
A1
A3
b
D
D2
E
E2
e
L
0.45
0.00
DETAIL B
A
0.13 REF
0.10
C
A3
C
0.18
2.00 BSC
1.50
0.30
1.70
A3
A1
0.08
C
DETAIL B
ALTERNATE
CONSTRUCTION
2.00 BSC
A1
SIDE VIEW
0.80
1.00
NOTE 4
SEATING
PLANE
0.50 BSC
0.20
−−−
0.45
0.15
L1
D2
DETAIL A
8X L
1
4
GENERIC
MARKING DIAGRAM*
E2
b
1
XX MG
G
5
8
8X
e
e/2
XX = Specific Device Code
0.10
C
C
A
B
M
= Date Code
0.05
NOTE 3
G
= Pb−Free Package
BOTTOM VIEW
(Note: Microdot may be in either location)
RECOMMENDED
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
8X
1.73
0.50
PACKAGE
OUTLINE
2.30
1.00
1
8X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
98AON34462E
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
REFERENCE:
DESCRIPTION: UDFN8, 2X2
PAGE 1 OF2
DOCUMENT NUMBER:
98AON34462E
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION FROM POD #UDFN8−033−01 TO ON SEMICON-
DUCTOR. REQ. BY B. BERGMAN.
19 DEC 2008
A
REDREW TO JEDEC STANDARDS. REQ. BY I. HYLAND.
13 NOV 2015
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2015
Case Outline Number:
November, 2015 − Rev. A
517AW
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
98ASB42564B
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
DESCRIPTION: SOIC−8, NB
PAGE 1 OF3
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
98ASB42564B
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
DESCRIPTION: SOIC−8, NB
PAGE 2 OF3
DOCUMENT NUMBER:
98ASB42564B
PAGE 3 OF 3
ISSUE
AB
REVISION
ADDED STYLE 25. REQ. BY S. CHANG.
DATE
15 MAR 2004
13 AUG 2004
18 NOV 2004
31 JAN 2005
14 APR 2005
AC
ADDED CORRECTED MARKING DIAGRAMS. REQ. BY S. FARRETTA.
CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY S. FARRETTA.
UPDATED SCALE ON FOOTPRINT. REQ. BY S. WEST.
AD
AE
AF
UPDATED MARKING DIAGRAMS. REQ. BY S. WEST. ADDED STYLE 26. REQ. BY
S. CHANG.
AG
AH
AJ
ADDED STYLE 27. REQ. BY S. CHANG.
ADDED STYLE 28. REQ. BY S. CHANG.
ADDED STYLE 29. REQ. BY D. HELZER.
ADDED STYLE 30. REQ. BY I. CAMBALIZA.
30 JUN 2005
09 MAR 2006
19 SEP 2007
16 FEB 2011
AK
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2011
Case Outline Number:
February, 2011 − Rev. 07AK
751
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
DATE 03 FEB 2016
SCALE 1:1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
1.27
PITCH
WW
G
= Work Week
= Pb−Free Package
14X
0.58
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
98ASB42565B
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
DESCRIPTION: SOIC−14 NB
PAGE 1 OF3
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 5:
STYLE 6:
STYLE 7:
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
98ASB42565B
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
DESCRIPTION: SOIC−14 NB
PAGE 2 OF3
DOCUMENT NUMBER:
98ASB42565B
PAGE 3 OF 3
ISSUE
REVISION
DATE
G
H
J
ADDED MARKING DIAGRAM. REQ. BY S. FARRETTA
ADDED SOLDERING FOOTPRINT. REQ. BY S. RIGGS.
30 APR 2004
04 OCT 2006
13 FEB 2008
CORRECTED MARKING DIAGRAM. MOVED PB−FREE INDICATOR “G” TO TOP
LINE. REQ. BY C. BIAS.
K
L
UPDATED DRAWING TO JEDEC STANDARDS. REQ. BY I. CAMBALIZA.
31 MAY 2011
03 FEB 2016
ADDED COPLANARITY TOLERANCE BOX TO SIDE VIEW. REQ. BY F. ESTRADA.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2016
Case Outline Number:
February, 2016 − Rev. L
751A
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8t
CASE 846A−02
ISSUE J
DATE 02 JUL 2013
SCALE 2:1
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
H
E
E
MILLIMETERS
INCHES
NOM
−−
0.003
0.013
0.007
0.118
DIM
A
A1
b
c
D
MIN
−−
0.05
0.25
0.13
2.90
2.90
NOM
−−
MAX
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
PIN 1 ID
e
1.10
0.15
0.40
0.23
3.10
3.10
b 8 PL
0.08
0.33
M
S
S
0.08 (0.003)
T B
A
0.18
3.00
E
3.00
0.118
e
L
0.65 BSC
0.55
4.90
0.026 BSC
0.021
0.193
SEATING
PLANE
0.40
4.75
0.70
5.05
0.016
0.187
0.028
0.199
−T−
H
E
A
0.038 (0.0015)
GENERIC
MARKING DIAGRAM*
L
A1
c
8
XXXX
AYWG
G
RECOMMENDED
SOLDERING FOOTPRINT*
8X
1
8X
0.48
0.80
XXXX = Specific Device Code
A
Y
W
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
5.25
(Note: Microdot may be in either location)
*This information is generic. Please refer to device data
sheet for actual part marking. Pb−Free indicator, “G”
or microdot “ G”, may or may not be present.
STYLE 1:
PIN 1. SOURCE
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
STYLE 3:
PIN 1. N-SOURCE
0.65
PITCH
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
2. N-GATE
3. P-SOURCE
4. P-GATE
5. P-DRAIN
6. P-DRAIN
7. N-DRAIN
8. N-DRAIN
DIMENSION: MILLIMETERS
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
STATUS:
98ASB14087C
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
DESCRIPTION:
PAGE 1 OF 2
MICRO8
DOCUMENT NUMBER:
98ASB14087C
PAGE 2 OF 2
ISSUE
REVISION
DATE
G
ADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ.
BY HONG XIAO
18 JUL 2005
H
J
CORRECTED GENERIC MARKING INFORMATION. REQ. BY T. GURNETT.
CORRECTED SOLDERING FOOTPRINT. REQ. BY J. LIU.
12 NOV 2007
02 JUL 2013
Micro8 is a trademark of International Rectifier.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2013
Case Outline Number:
July, 2013 − Rev. J
846A
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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