NCS37014MNTWG [ONSEMI]
Self Test GFCI controller compliant with UL943;
| 型号： | NCS37014MNTWG |
| 厂家： | 
ONSEMI |
| 描述： | Self Test GFCI controller compliant with UL943 |
| 文件： | 总9页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Self Test Ground Fault
Circuit Interrupter (GFCI)
QFN16
CASE 485FQ
NCS37014
The NCS37014 is a UL943 compliant signal processor for GFCI
applications with self test. The device integrates a flexible power
supply (including a 12 V shunt and two 3.3 V internal series
regulators), differential fault, and grounded−neutral detection circuits.
Self test is monitored at start up and then every 17 minutes.
PIN ASSIGNMENT
Features
CTG
GFT
CTB
CTS
LED
MLD
SUP
RES
• Meets UL943 Self−test GFCI Requirements
• 4.0 – 12 Volt Operation (120−480 V AC mains with the appropriate
series impedance)
o
o
• −40 C to 95 C
• Typical 575 mA Quiescent Current @ 11 V
• 16 Pin QFN
(Top View)
• Self Syncing Internal Oscillator adjusts to AC Mains Frequency to
Guarantee Full Resolution on 60 Hz Distribution Systems
• Optimized Solenoid Deployment (coil is not energized near the AC
mains zero crossings).
MARKING DIAGRAM
• Power Supply Monitor that Verifies Full Diode Bridge Operation
• Tiered Trip Times that Increase Immunity to Noise
37014
ALYWG
G
• Under−voltage Detection that Allows for Increased Operation at
Lower AC Input Voltages
37014 = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Typical Applications
• GFCI Receptacles
• Load Panel GFCI Breakers
• In−line GFCI Circuits (power cords)
(Note: Device NCS37014MNTWG includes
Pb−Free micro dot below assembly information text;
Device NCS37014MNATWG includes Pb−Free
micro dot to the right of assembly information text)
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
July, 2022 − Rev. 4
NCS37014/D
NCS37014
SUP
12V Shunt
Regulator
3.3V Analog
Regulator
3.3V Digital
Regulator
1.65V
CTB
IDF
−
VDA
RES
Bandgap
Reference
1.2V
3.3V Analog Regulator
Voltage Divider
2 MHz
Oscillator
POR
+
+0.2V
+
NCS37014
SCR
GFT
PTT
− + /
−0.2V
−
Digital
Filter
data[7:0]
SAR
done
ADC
Saturation
Clamp/
Detection
adc_start
clk
TE
CTO
CTG
+
CONTROL LOGIC
GROUND FAULT
LED
−
DYNAMIC OSC TRIM
gnComp
chop
saturated
CTS
MLD
OFFSET CORRECTION
GNE
GND
3.3V Shunt
Regulator
UVD
Figure 1. Simplified Block Diagram
Table 1. QFN PIN DESCRIPTION
Pin #
1
Name
CTG
GFT
CTB
CTS
CTO
IDF
Pad Description
Ground Neutral current transformer stimulus
2
Differential self test output signal
Differential current transformer bias voltage
Differential current input
3
4
5
Differential current to voltage output
Differential low pass filter/ADC input
Analog 3.3 V regulator output/ ADC reference voltage
Electronics ground
6
7
VDA
GND
RES
SUP
MLD
LED
PTT
SCR
TE
8
9
Reference current bias input
Power supply input
10
11
12
13
14
15
16
Mains level/under voltage detector
End of life LED drive
Push to test input
SCR gate drive signal
Test enable
GNE
Ground−neutral enable input
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2
NCS37014
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
13.5
Unit
V
Supply Voltage Range
Supply Current
Vs
Is
10
mA
V
Input Voltage Range (Note 3)
Output Voltage Range
V
in
−0.3 to 3.6
V
out
−0.3 to 3.6 V or (V + 0.3),
V
in
whichever is lower
Maximum Junction Temperature
T
140
−65 to 150
2
°C
°C
kV
V
J(max)
Storage Temperature Range
TSTG
ESD Capability, Human Body Model (Note 4)
ESD Capability, Charge Device Model (Note 4)
Lead Temperature Soldering
ESD
HBM
CDM
ESD
500
T
260
°C
SLD
Reflow (SMD Styles Only), Pb−Free Versions (Note 5)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Functional operation above the Recommended Operating Conditions is not implied. Extended
2. Exposure to stresses above the Recommended Operating Conditions may affect device reliability.
3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JS−001−2012
ESD Charge Device Model tested per JESD22−C101−F
Latchup Current Maximum Rating: v100 mA per JEDEC standard: JESD78D
5. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 3. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, QFN16, 3x3.3 mm (Note 6)
R
64
°C/W
θJA
Thermal Resistance, Junction−to−Air (Note 7)
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2
2
7. Values based on copper area of 645 mm (or 1 in ) of 1 oz copper thickness and FR4 PCB substrate.
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3
NCS37014
Table 4. OPERATING RANGES (Unless otherwise noted, I
= 3 mA, MLD input = 60 Hz, Refer to Figure 2)
SUP
Parameter
Operating Temperature
Conditions
Min
Typ
Max
95
Units
C
Ambient
−40
Shunt Regulator Voltage
Shunt Regulator Current
Quiescent Current
SUP to GND, I
= 1 mA
12
13
V
SUP
SUP
I
10
mA
mA
I , SUP = 10.5 V
SUP
575
203
750
215
RMS Trip Threshold Voltage
SCR Trigger Current
IDF to CTB, R8 = 32 kW, R
= 500 W
191
4
mV
mA
V
CTO
I
, SCR = 1 V, I
< 6 mA
SCR
SHUNT
SCR Trigger Output Voltage
LED Output Voltage
SCR to GND, SUP < 4 V
LED to GND, SUP < 4 V
CTB to GND, VDA = 3.3 V
CTS−CTB
3
3.6
3.6
3
V
CTB Bias Voltage
1.65
V
CTS−CTB Absolute Offset Voltage
Fault Response Time
−250
250
125
95
75
60
50
40
35
25
20
mV
6 mA ≤ I
< 10 mA
< 15 mA
ms
DIFF
Fault Response Time
10 mA ≤ I
ms
DIFF
Fault Response Time
15 mA ≤ I
< 17.5 mA
ms
DIFF
Fault Response Time
17.5 mA ≤ I
< 20 mA
ms
DIFF
Fault Response Time
20 mA ≤ I
< 22.5 mA
ms
DIFF
Fault Response Time
22.5 mA ≤ I
< 26.5 mA
ms
DIFF
Fault Response Time
26.5 mA ≤ I
< 29 mA
ms
DIFF
Fault Response Time
29 mA ≤ I
< 33 mA
ms
DIFF
Fault Response Time
I
≥ 33 mA
ms
DIFF
CTG Comparator Threshold
CTG Timer
CTG to GND, VDA = 3.3 V
CTG > Threshold
1.95
45
V
ms
CTG GN Trip Frequency
GN Response Time
CTG to GND
2
7
kHz
ms
Continuous GN Fault
350
2.2
95
Internal Oscillator Frequency
Under Voltage Detect
F
= 60 Hz +/−0.1
1.8
80
2
MHz
Vrms
mA
AC
V
AC
to GND, R7 = 1 MW, +/−1%
87
MLD Max Clamp Current
MLD Pull Down Current
First ST Timer
I
Max Sink Current
MLD = 1 V
400
MLD
500
2
nA
VDA > 3 V
1.7
15
2.3
20
seconds
minutes
minutes
Periodic ST Timer, Pass
Periodic ST Timer, Fail
Consecutive ST Failure Timer
LED Blink Frequency
Steady State, ST Pass
ST Fail
17
1
0.8
1.2
ST Fail Counter, Enable SCR
First ST Failure
7
1.8
6
2
2.2
14
Hz
mA
ST Cycle GF Pass Window
MLD Pin Check Wait Time to Enable LED
MLD Pin Continuity Pass
LED Blink Frequency
I
Ground Fault
DIFF
No MLD signal
Input Frequency
No MLD signal
No MLD signal
500
ms
25
Hz
1.5
2
6
2.5
Hz
MLD Pin Check Wait Time to Enable SCR
minutes
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
8. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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4
NCS37014
APPLICATIONS INFORMATION
R7
LINE
S1
Q1
R6
DB
R5
C3
TEST
C4
R12
C6
Rctg
CTG
GFT
CTB
CTS
LED
MLD
SUP
RES
C5
CT2
CT1
C7
F1
Ferrite
Bead
C1
R4
D4
F2
Ferrite
Bead
R1
C9
R8
Q2
D1
R10
C2
Rcto
R2
R3
R11
C8
D2
RESET
LOAD
Figure 2. GFCI Receptacle Application Diagram
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5
NCS37014
Table 5. RECOMMENDED EXTERNAL COMPONENTS
Component Type
SCR
Instance
Q1
Value
−
Note
ON−MCR08
NPN
Q2
−
MMBT6517LT1−D
Diode Bridge
Diode
DB
−
D1, D2
D3
−
1N4007
Diode
−
1N4007, auxiliary supply
LED for self test failure
Differential current filter capacitor
LED
D4
−
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Resistor
C1
33 nF
56 nF
10 nF
1 mF
C2
Anti−aliasing filter (1 kHz corner frequency)
SCR gate filter capacitor
C3
C4
SUP pin holding capacitor
C5
22−220 pF
4.7−47 nF
1 nF
Ground Neutral CT resonance capacitor
Ground Neutral CT AC coupler
C6
C7
CTB bias filter
C8
1 mF
Analog 3.3 V regulator filter
C9
1 nF
High frequency filter
R1
243 W
15 kW
10 kW
6.8 kW
0.47−4.7 kW
72 kW
1 MW
32 kW
72 kW
10−20 kW
120 kW
10 kW
0.47−1.5 kW
0 – 200 W
800
Precision resistor (1%), Differential burden/CT low pass filter
Controls the self test current in the Q2
Sets the current in the base of Q2
Limits current to the LED D3
Resistor
R2
Resistor
R3
Resistor
R4
Resistor
R5
Sets allowable gate current in Q1
Power supply current limit
Resistor
R6
Resistor
R7
MLD current limit/under voltage attenuator
Precision resistor (1%), Sets the differential trip level at 5 mA
Power supply current limit
Resistor
R8
RMS
Resistor
R9
Resistor
R10
R11
R12
Rcto
Rctg
CT1
CT2
Differential filter resistor
Resistor
Precision resistor (1%), Current reference bias resistor
Test button pull−up resistor
Resistor
Resistor
Precision resistor (1%), Sets the differential trip level at 5 mA
Sets the GN sensitivity
RMS
Resistor
Current Transformer
Current Transformer
Differential current transformer
250
GN current transformer
Functional Description (refer to application circuit)
The NCS37014 provides for a single IC controller
solution for ground fault, grounded neutral and self−test
protection per UL standard UL943.
The key internal blocks include: 12 V shunt regulator,
precision bandgap reference, two 3.3 V linear regulators
(one for the digital and one for the analog circuit) sense
(vda) and digital (vdd) internal circuitry via two 3.3 V linear
regulators.
At POR detection (vda>2.475) the logic is reset and the
bias circuitry is enabled, the LED pin will blink once for
250 ms. The MLD pin is continually checked for an input
signal greater than 25 Hz. If the MLD signal is greater than
25 Hz, this test passes. If it fails, the LED blinking logic will
be enabled. A six minute timer will start and if no MLD
signal is detected, the SCR will be enabled. If a MLD signal
occurs before the six minute timer and is longer than one
minute, the timer will be reset.
amplifier with V cancellation, 1.65 V reference for the
OS
CT, 2 MHz oscillator dynamically trimmed to the AC line
frequency, 8 bit SAR ADC, comparators, digital filters and
digital control logic.
The internal shunt regulator clamps the SUP pin voltage
at 12 volts. This provides the bias voltage for the analog
The first self test (ST) cycle will occur at two seconds and
thereafter every 17 minutes. During the ST cycle the GFT
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6
NCS37014
pin will be enabled and the CT current (set at 8 mA, R2 ) will
and vda. When the pin is clamped at vda, the current is
compared to a threshold so if the VAC voltage is below
87VRMS, the ST GF threshold will be reduced by 50%. This
function provides for an AC under voltage detection which
allows for the ST cycle to pass with a lower GF threshold.
The AC UVD threshold can be user programmable by
changing R7.
be verified for two half cycles. If a ST cycle fails due to a low
GF detection or a GF signal greater than 30 mA, the LED
blinking logic will be enabled. Another ST cycle will occur
in one minute. If seven consecutive ST cycles fail the SCR
will be enabled. If a ST cycle passes before the 7 consecutive
cycle counter, the ST logic will be reset and a ST cycle will
occur in 17 minutes.
Grounded Neutral detection is accomplished by the
addition of a GN coil to generate a “dormant oscillator”
circuit. When a GN condition occurs, both the sense coil and
GN coils are mutually coupled and the GN amplifier will
oscillate. This oscillation can be observed at the CTG pin.
When the oscillation at the CTG pin is above 1.95 volts for
greater than 45 us, and if this condition (oscillation) lasts for
longer than 64 ms, the internal NCS37014 logic will disable
the GN amplifier to stop the CTG oscillation for
approximately 90 ms. The amplifier will be enabled again
and if the oscillation on the CTG pin returns, the GN fault
will be detected and the SCR will be enabled
(NCS37014MNATWG device GN fault requires the GN
amplifier enabling and disability to go through two cycles).
This total sequence cycle takes a maximum of 175 ms (350
ms for NCS37014MNATWG). During power up, an
additional maximum of 80 ms is required. The maximum
time required during power up is 350 ms. The sensitivity of
the GN detection can be changed by capacitor C6 and
resistor Rctg. The frequency of this CTG oscillation needs
to be in the 2 kHz to 7 kHz.
The internal oscillator is trimmed to 2 MHz when the AC
frequency is 60 Hz. If the AC frequency is lower, the GF trip
threshold response time will be slower and the GN
sensitivity will be lower.
When the IC logic enables the SCR gate driver circuit, the
SCR pin will go high at approximately 26 degree phase
angle (for AC Mains at 60 Hz) for the duration of the MLD
half cycle and disable at the zero cross. The LED blinking
logic will be enabled.
The CT is biased at 1.65 volts. The sense amplifier
monitors the ground fault current. This current is converted
to a voltage level at the CTO pin which is the input to the
ADC (IDF pin). The resistor R8 sets the GF threshold per the
following equation:
ǒ
Ǔ
0.203 CT1 RCT1 ) R1 ) 2pfACLCT1
Idiff
+
(eq. 1)
ǒ
Ǔ
R8 RCT1 ) 2pfACLCT1
CT = Turns ratio of differential CT
1
R
CT1
= DC winding resistance of differential CT
f
= AC mains frequency
AC
L
= Inductance of differential CT
CT1
The ground fault detection circuit has different levels of
time delay before the SCR is enabled:
6 mA to 10 mA
10 mA to 15 mA
15 mA to 17.5 mA
17.5 mA to 20 mA
20 mA to 22.5 mA
22.5 mA to 26.5 mA
26.5 mA to 29 mA
29 mA to 33 mA
>33 mA
≤ 125 ms
≤ 95 ms
≤ 75 ms
≤ 60 ms
≤ 50 ms
≤ 40 ms
≤ 35 ms
≤ 25 ms
≤ 20 ms
If a very high GF occurs and a greater than 200 mV signal
occurs across the CT for greater than 1.4 ms, the SCR will
be enabled immediately.
Note that the above equation is for an ideal CT. In practice,
the GF threshold can be +/−30% different and should be
empirically set.
When the PTT pin is enabled for greater than 64 ms and
if the GNE PIN is high (16 ms when GNE PIN is low), a ST
cycle will be enabled. If the ST cycle passes, the SCR will
be enabled. If the ST cycle fails, the LED will be enabled and
blink. A PTT ST passing cycle will generate a POR reset.
The PTT pin has a 50 kW pull down resistor. This pin is a
CMOS input with hysteresis. To enable the PTT function,
the input voltage should go above 2.4 volts.
The RES pin is biased at 1.2 volts and should have an
external precision 120 kW resistor connected to the GND
pin. This resistor sets up an internal precision current source.
The TE pin is used for internal production testing only. A
50 kW pull down resistor is connected to this pin. This pin
should be open or connected to the GND pin (preferred).
The GNE pin has an internal 50 kW pull up resistor
connected to the internal 3.3 V supply. If this pin is pulled
low, the GN function will be disabled.
Contact ON Semiconductor for self−test requirement
details and noise filtering recommendations.
The MLD pin monitors the phase and zero cross for the
AC supply. The MLD circuit clamps the pin voltage to gnd
ORDERING INFORMATION
Device
Package
Shipping †
NCS37014MNTWG
QFN16
(Pb−Free)
3000 / Tape & Reel
NCS37014MNATWG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: NCS37014MNATWG is the improved version of NCS37014MNTWG with better frequency noise immunity.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485FQ
ISSUE B
DATE 12 JUL 2022
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
*This information is generic. Please refer to
XXXXX
XXXXX
ALYWG
G
Y
W
G
= Year
= Work Week
= Pb−Free Package
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”,
may or may not be present. Some products
may not follow the Generic Marking.
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON84763G
QFN16 3x3, 0.5P
PAGE 1 OF 1
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the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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