NCS37020DTBR2G [ONSEMI]

Self-Test Appliance Leakage Circuit Interrupter (ALCI);


型号：	NCS37020DTBR2G
厂家：	ONSEMI
描述：	Self-Test Appliance Leakage Circuit Interrupter (ALCI) 外围集成电路
文件：	总13页 (文件大小：361K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

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Self-Test Appliance

Leakage Circuit Interrupter

(ALCI)

MARKING

DIAGRAM

NCS

37020

ALYWG

NCS37020

TSSOP−14

CASE 948G

The NCS37020 is an UL943B compliant signal processor for ALCI

applications with self−test. The device integrates a 12 V shunt power

supply, tiered differential fault detection and self−test per the UL943B

standard. Self−test is monitored at start up and every 12 minutes.

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Features

• Meets UL943B Self−test ALCI Requirements

• 12 V Shunt Regulator

• Precision Bandgap

PIN CONNECTIONS

• 3.3 V LDO Linear Regulator

SCR Test

CTB

• CT Sense Amplifier V Dynamic Cancellation

SCR

Fault Test

• Oscillator Frequency Trimmed to AC Input

• Tiered GF Trip Times

CTS

CTO

IDF

LED

AUX

SUP

Phase

• Built−In Noise Filter

REF

GND

• LED EOL Indicator

• SCR Gate Driver

(Top View)

• Adjustable Sensitivity

• Minimum External Components

• Low Quiescent Current

• 14 Pin TSSOP Package

ORDERING INFORMATION

†

Device

NCS37020DTBR2G TSSOP−14 2500 / Tape &

(Pb−Free) Reel

Package

Shipping

Typical Applications

• Personal Care Products

†For information on tape and reel specifications, in-

cluding part orientation and tape sizes, please refer

to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

• Non Grounded Neutral Electrical Outlets, Circuit Breakers and

Power Cords Requiring Ground Fault Safety Features

• ALCI and RCCB Circuits

Publication Order Number:

September, 2022 − Rev. 3

NCS37020/D

NCS37020

SUP

AUX

12V Shunt

Regulator

3.3V Analog

Regulator

3.3V Digital

Regulator

1.65V

CTB

IDF

−

REF

Bandgap

Reference

1.2V

3.3V Analog Regulator

Voltage Divider

2MHz

Oscillator

POR

NCS37020

+0.25V

SCR

− + /

−0.25V

−

data[7:0]

SAR

Digital

Filter

Fault Test

ADC

done

Saturation

Clamp/

adc_start

clk

Detection

CTO

−

CONTROL LOGIC

GROUND FAULT

LED

DYNAMIC OSC TRIM

SCR Test

GND

CTS

Phase

chop

saturated

OFFSET CORRECTION

3.3V Shunt

Regulator

Figure 1. Simplified Block Diagram

Pad Description

Table 1. TSSOP PIN DESCRIPTION

Pin #

Name

SCR Test

CTB

SCR test input for SCR functionality

Differential current transformer bias voltage

Differential current signal input

Differential current to voltage output

Differential low pass filter/ADC input

3.3 V Internal reference voltage

Electronics ground

CTS

CTO

IDF

REF

GND

Phase

SUP

Zero cross input for V frequency

Power supply input

AUX

Auxiliary power supply input

End of life LED drive

LED

Test enable, Connect to GND

Differential self−test output signal

SCR gate drive signal

Fault Test

SCR

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NCS37020

Table 2. ABSOLUTE MAXIMUM RATINGS

Rating

Symbol

Value

13.5

Unit

Supply Voltage Range

Supply Current

Input Voltage Range (Note 3)

Output Voltage Range

−0.3 to 3.6

out

−0.3 to 3.6 V or (V + 0.3),

whichever is lower

Maximum Junction Temperature

140

−65 to 150

°C

J(max)

Storage Temperature Range

STG

ESD Capability, Human Body Model (Note 4)

ESD Capability, Charge Device Model (Note 4)

Lead Temperature Soldering

ESD

HBM

CDM

500

260

°C

SLD

Reflow (SMD Styles Only), Pb−Free Versions (Note 5)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Functional operation above the Recommended Operating Conditions is not implied. Extended

2. Exposure to stresses above the Recommended Operating Conditions may affect device reliability.

3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

4. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (JEDEC JS−001−2010)

ESD Charge Device Model tested per AEC−Q100−003 (JESD22−C101−A)

Latchup Current Maximum Rating: ≤100 mA, 20 ms pulse per JEDEC standard: JESD78

5. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM.D

Table 3. THERMAL CHARACTERISTICS

Rating

Symbol

Value

Unit

Thermal Characteristics, TSSOP14

Thermal Resistance, Junction−to−Air (Note 6)

115

°C/W

θJA

6. Values based on copper area of 645 mm (or 1 in ) of 1 oz copper thickness and FR4 PCB substrate.

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NCS37020

Table 4. OPERATING RANGES (Unless otherwise noted, ISUP = 3 mA, Phase input = 60 Hz, Refer to Figure 2)

Parameter

Operating Temperature

Conditions

Min

Typ

Max

Units

°C

Ambient

Shunt Regulator Voltage

Shunt Regulator Current

Quiescent Current

SUP to GND, I

= 1 mA

SUP

I , SUP = 10.5 V

SUP

575

203

800

215

RMS Trip Threshold Voltage

SCR Trigger Current

IDF to CTB, R5 = 32 kW

191

SCR

SCR Trigger Output Voltage

LED Output Voltage

SCR to GND, SUP > 4 V

LED to GND, SUP > 4 V

CTB to GND, REF = 3.3 V

CTS−CTB

3.6

CTB Bias Voltage

1.65

CTS−CTB Absolute Offset Voltage

Ground Fault Response Time

Internal Oscillator Frequency

Phase Pin Max Clamp Current

Phase Pin Pull Down Current

First ST Timer

−300

300

150

100

6 mA ≤ I

<15 mA

<30 mA

<100 mA

DIFF

15 mA ≤ I

DIFF

30 mA ≤ I

DIFF

≥ 100 mA

DIFF

= 60 Hz +/−0.1

1.8

2.2

400

MHz

Max Sink Current

Phase

Phase = 1 V

SUP > 4 V

0.75

1.25

seconds

minutes

seconds

Periodic ST Timer, Pass

Periodic ST Timer, Fail

Steady State, ST Pass

ST Fail

4.5

Consecutive ST Failure Timer

LED Blink Frequency

ST Fail Counter, Enable SCR

ST Failure, EOL

3.6

4.4

ST Cycle GF Pass Window

Phase Pin Check Wait Time to Enable EOL

Ground Fault

DIFF

No Phase signal

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

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NCS37020

APPLICATIONS INFORMATION

TEST

R11

RESET

MOV

Sense Coil 1:800

Line Hot

Load Hot

Load Neutral

Line Neutral

Q1B

Q1A

R12A

SCR Test

CTB

SCR

Fault Test

R10

R13

R12B

CTS

CTO

IDF

LED

AUX

R1B

D1−4

R1A

REF

SUP

GND

Phase

Figure 2. ALCI Application Diagram*

*Contact onsemi for additional filtering information

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NCS37020

Table 5. RECOMMENDED EXTERNAL COMPONENTS

Component Type

Controller

SCR

Instance

Value

−

Note

NCS37020DTBR2G

Q1A, Q1B

−

0.8 A, 400 V

MMBTA42

NPN

−

Diode Bridge

Diode

D1−D4

−

MB4S

−

1 A, 300 V

Diode

D6, D8, D9

−

15 mA, 300 V

LED for EOL Indicator

LED

−

Capacitor

Resistor

2.2 mF

1 mF

SUP pin holding capacitor, Ceramic 25 V

REF filter capacitor, 6.3 V

100 nF

1 nF

SCR gate filter capacitor

Dynamic V filter capacitor

33 nF

CT filter capacitor

2.2 nF

22 to 56 nF

49.9kW

1 MW

CTB bias capacitor

IDF filter capacitor

R1A

R1B

Shunt regulator current limit resistor, ¼W

AC zero cross current limit resistor

IDF filter resistor

Resistor

4.7 to 20 kW

31.6 kW

243 W

10 kW

3.3 kW

4.7 kW

15 kW

4.7 kW

3.3 kW

4.7 kW

1 kW @ 100 MHz

800 turns

Resistor

Precision resistor (1%), Sets the differential trip level at 5 mA

Precision resistor (1%), Differential burden/CT low pass filter

Sets the self−test GF current

Current limit resistor for LED bias

Current limit resistor for Q2 bias

Sets the manual GF test current

Current limit resistor for Q1A bias

Current limit resistor for Q1B bias

SCR gate bleeder resistor

RMS

Resistor

R10

R11

Resistor

R12A

R12B

R13

Resistor

Ferrite Bead

Current Transformer

CIM05U102, CT RF filter

Sense Coil

C5029−01C

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NCS37020

Functional Description (refer to application circuit, Figure 2)

The NCS37020 provides for a single IC controller

solution for ground fault protection and self−test auto

monitoring per UL standard UL943B.

The key internal blocks include: 12 V shunt regulator,

precision bandgap reference, two 3.3 V linear regulators

(one for the digital and one for the analog circuit), CT sense

The first self−test (ST) cycle will occur at one second and

thereafter every 12 minutes. During the ST cycle, the Fault

Test pin will be enabled during the positive half cycle and the

CT current (set at 12 mA, R8) will be verified. During the

next negative half cycle, the SCR’s anode voltage will be

pre−biased by the SCR Test pin to 3.3 volts. The SCR will

then be enabled and the SCR’s anode voltage will be

monitored by the SCR Test pin. If the anode voltage goes

below 2.1 volts, the SCR will be disabled after a 400 ms

verification check and the ST logic will register a passing ST

cycle. Figure 2 shows two SCRs in series. A redundant SCR

is required during the SCR anode to cathode short test to

prevent the solenoid from burn out damage. The SCR

self–test cycle will fail if either SCR Q1A or Q1B are open.

If either Q1A or Q1B are shorted (anode to cathode) the ST

cycle will pass, however, the GF function will also function

correctly. The next ST cycle will occur in 12 minutes. Note

that when the SCR is enabled, the blocking diode D5 will

prevent the solenoid from being energized and opening the

load contacts. If either the GF (ground fault) or SCR

self−test cycles fail, these self−test cycles will be repeated

for up to three more consecutive cycles. If any consecutive

GF and SCR tests pass, the ST logic will register a passing

self−test cycle. If all four ST consecutive cycles fail, a ST

cycle will be repeated at 2, 3 and 4 seconds for a total of 16

self−test cycles. If all 16 ST cycles fail, a ST EOL fault will

occur. The SCR will be enabled for four consecutive positive

half cycles, then the LED will blink at 4 Hz. The LED will

only be biased during the positive AC half wave cycle. The

SCR will be enabled for one positive half cycle every 4.5

seconds. A self−test cycle will occur every second. If a

self−test cycle passes, the ST EOL logic will be reset (power

on reset state). If a ground fault is detected during a ST EOL

state, the EOL logic will be reset. This allows for resetting

the ST EOL state by pressing the manual test button when

the load contacts are closed.

amplifier with V dynamic cancellation, 1.65 V reference

for the CT, 2 MHz oscillator dynamically trimmed to the AC

line frequency, 8 bit SAR ADC, comparators, digital filters

and digital control logic.

The internal shunt regulator clamps the SUP pin voltage

at 12 volts. This provides the bias voltage for the analog and

digital internal circuitry via two 3.3 V linear regulators. The

NCS37020 controller can be biased full wave or half wave.

Figure 2 shows a half wave bias application. Half wave bias

allows for lower wattage bias resistors (R1A and R1B) and

less redundant bias diodes. The D1−4 diodes are biased so

that only during the positive half cycle the capacitor C1 will

be charged to 12 volts. During the negative half cycle, C1

will supply the bias current for the NCS37020. To minimize

the NCS37020 bias current during the negative half cycle,

the SCR and LED outputs will only be enabled during the

positive half cycle. The D1−4 diodes and R1A−R1B

resistors include redundant components to pass the UL943B

standard.

At POR (power on reset) detection (SUP>4 V) the logic

is reset and the bias circuitry is enabled. The Phase pin

continually checks for an input signal. There is a 1 mA pull

down internal current source connected to this pin so a

floating or open pin will be biased low. If there is no

50/60 Hz signal detected on this pin for greater than 32 ms

due to an open solenoid or open R2 resistor, a “no clock” End

of Life (EOL) fault will occur. After ~150 ms, the LED

indicator logic will be enabled and blink at 4 Hz. The SCR

will be enabled for one positive half cycle every 4 seconds.

The “no clock” EOL logic state will continue until a POR

occurs or a 50/60 Hz signal is detected on the Phase pin.

When a 50/60 Hz signal is detected, the no clock EOL state

will be reset and a ST (self−test) cycle will occur after 75 ms.

If this ST cycle passes, the next ST cycle will occur in 12

minutes. If four consecutive no clock ST cycles fail, a ST

EOL fault will occur. During a no clock EOL state, the phase

information will be detected by the shunt regulator’s bias

circuitry. The shunt regulator will detect an AC zero cross by

monitoring the Shunt regulator’s clamp current. When the

VAC voltage crosses ~80 volts, a zero cross is registered by

the shunt regulator’s circuitry.

The above no clock and GF/SCR self−test functions

provide for full UL943B (3 Edition) compliance for the

auto monitoring requirement. The NCS37020 IC controller

tests for the CT, solenoid, clock input, SCR and bias

circuitry.

The CT is biased at 1.65 volts. The CT sense amplifier

monitors the ground fault current. This current is converted

to a voltage level at the CTO pin which is the input to the

ADC (IDF pin). The resistor R5 sets the GF threshold per the

following equation:

0.203 CT₁ R_CT1) R₇) 2pf_ACL_CT1

Note, the “no clock” EOL logic can be used in production

testing for generation of an EOL state and enabling the LED

indicator. If a DC voltage greater than ~75 volts is applied

to the Line Hot input, the NCS37020 will be biased correctly

but will not see a zero cross signal and a “no clock” ST EOL

failure will occur. The LED will be enabled within 150 ms.

I_diff

(eq. 1)

R₅ R_CT1) 2pf_ACL_CT1

CT = Turns ratio of differential CT

CT1

= DC winding resistance of differential CT

= AC mains frequency

= Inductance of differential CT

CT1

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NCS37020

The ground fault detection circuit has different levels of

time delay before the SCR is enabled:

Figure 5 shows a passing self−test SCR test. This test

checks for the SCR and bias circuitry. Channel 1 shows the

VAC 120 V

, 60 Hz Line Voltage. Channel 2 shows the

RMS

6 mA to 15 mA

15 mA to 30 mA

30 mA to 100 mA

>100 mA

If a very high GF occurs and a greater than 250 mV signal

occurs across the CT for greater than 1.4 ms, the saturation

fault comparator will enable the SCR during the positive

half cycle.

During a self−test, the GF detection circuit is active.

However, for the 6 mA to 15 mA GF range, an additional

~100ms trip delay will be added before the SCR is enabled.

Note that the above equation is for an ideal CT. In practice,

the GF threshold can be 30% different and should be

empirically set.

The internal oscillator is trimmed to 2 MHz when the AC

frequency is 60 Hz. If the AC frequency is lower, the GF trip

threshold response time will be slower.

≤150 ms

≤100 ms

≤40 ms

≤25 ms

positive and negative phase half wave cycles. Channel 3

shows the SCR signal and channel 4 shows the SCR Test

signal. At the end of the positive half cycle, the SCR Test pin

is biased high. Approximately 3 ms into the negative half

wave cycle, the SCR is enabled high. This causes the SCR

Test pin to go low. When it goes below ~2.1 volts, a passing

SCR test is recorded and the SCR signal is disabled.

After a passing self−test cycle per Figures 4 and5, the next

ST cycle will occur in 720 seconds.

Figure 6 shows a failing ST cycle for an open CT. Channel

1 shows the NCS37020 supply voltage. Channel 2 shows the

phase pin. Channel 3 shows the Fault Test signal and channel

4 shows the LED (End of Life) signal. The first four

consecutive ST cycles occur at about 1.1 seconds, then at

2.2, 3.3 and 4.4 seconds. After the 16 consecutive cycle

failure, the SCR is enabled for four positive half cycles and

then the LED is enabled.

The CT sense amplifier has an internal dynamic V

cancelation circuit which allows for direct coupling to the

CT transformer.

The TE pin is used for internal production testing only.

This pin should be connected to the GND pin.

Contact onsemi for self−test requirement details and

noise filtering recommendations.

Figure 7 also shows a failing ST cycle for an open CT. It

is a zoom figure for the first four consecutive ST cycles. It

shows the same waveforms as Figure 6 but channel 4 shows

the SCR pin. Comparing Figure 7 with Figure 4, it can be

observed that the Fault Test pin is enabled for the complete

positive half wave cycle because no GF signal is detected by

the NCS37020.

Figure 8 shows a failing ST cycle for an open SCR.

Channel 1 shows the supply voltage, channel 2 shows the

Phase pin, channel 3 shows the SCR pin and channel 4 shows

the SCR Test pin. The SCR is enabled inside the negative

half wave cycle. The SCR Test pin does not detect the SCR

going low so the cycle is recorded as a SCR failure test.

Figure 9 shows a failing “no clock” test. The Phase pin is

floating for this test. Channel 1 shows the supply voltage,

channel 2 shows the Phase pin and channel 3 shows the LED

pin. No signal is present on the Phase pin after POR. At

~114 ms, the LED End of Life signal is enabled during the

positive half wave cycle. The LED EOL signal blinks at

4 Hz.

Figure Description

Figure 3 shows the typical SCR enable delay time versus

the GF current level. Shown is a typical 85 ms delay time for

a 6 mA GF. The typical delay time for a 25 mA GF is 28 ms

and 14 ms for a 500 W 240 mA GF.

Figure 4 shows a passing self−test ground fault test. This

test checks for the CT and bias circuitry. Channel 1 shows

the VAC 120 V , 60 Hz Line Voltage. Channel 2 shows

RMS

the positive and negative phase half wave cycles. Channel 3

shows the Fault Test signal and channel 4 shows the IDF

signal (CTO output). The self−test cycle starts in the positive

half wave cycle. The Fault Test pin goes high and Q2

(Figure 2) is enabled. Enabling Q2 generates a GF signal via

R8. The IDF signal is the CTO amplifier output which is a

GF current to voltage signal per the equation on the previous

page. When a 5 to 15 mA GF signal is detected, a “passing

GF test” is recorded and the Fault Test signal is disabled.

Figure 10 also shows a failing “no clock” test. This figure

is the same as Figure 9 except for the time scale and the SCR

signal is added (channel 4). The first SCR pulse occurs at

~3.8 seconds.

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NCS37020

Figure 3. Typical GF Current vs. Trip Time

Passing Self Test

GF Test

Ch1: VAC 120V

RMS

Ch2: Phase (Pin 8)

Ch3: Fault Test (Pin 13)

Ch4: IDF (Pin 5)

Figure 4. Passing Self Test − GF

Passing Self Test

SCR Test

Ch1: VAC 120V

RMS

Ch2: Phase (Pin 8)

Ch3: SCR (Pin 14)

Ch4: SCR Test (Pin 1)

Figure 5. Passing Self Test − SCR

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NCS37020

Failing Self Test

CT Open

Ch1: Supply (Pin 9)

Ch2: Phase (Pin 8)

Ch3: Fault Test (Pin 13)

Ch4: LED (Pin 14)

Figure 6. Failing Self Test − CT Open

Failing Self Test

CT Open

Ch1: Supply (Pin 9)

Ch2: Phase (Pin 8)

Ch3: Fault Test (Pin 13)

Ch4: SCR (Pin 14)

Figure 7. Failing Self Test − CT Open

Failing Self Test

SCR Open

Ch1: Supply (Pin 9)

Ch2: Phase (Pin 8)

Ch3: SCR (Pin 14)

Ch4: SCR Test (Pin 1)

Figure 8. Failing Self Test − SCR Open

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NCS37020

Failing Self Test

No Clock

Ch1: Supply (Pin 9)

Ch2: Phase (Pin 8)

Ch3: LED (Pin 11) @ 114 ms

Figure 9. Failing Self Test − No Clock

Failing Self Test

No Clock

Ch1: Supply (Pin 9)

Ch2: Phase (Pin 8)

Ch3: LED (Pin 11)

Ch4: SCR (Pin 14) @ 3.8 seconds

Figure 10. Failing Self Test − No Clock

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

TSSOP−14 WB

CASE 948G

ISSUE C

DATE 17 FEB 2016

SCALE 2:1

NOTES:

14X K REF

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

0.10 (0.004)

T U

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL

IN EXCESS OF THE K DIMENSION AT

MAXIMUM MATERIAL CONDITION.

0.15 (0.006) T U

0.25 (0.010)

2X L/2

−U−

PIN 1

IDENT.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

DETAIL E

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

0.15 (0.006) T U

−V−

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

4.90

4.30

−−−

0.05

0.50

5.10 0.193 0.200

4.50 0.169 0.177

J J1

1.20

−−− 0.047

0.15 0.002 0.006

0.75 0.020 0.030

SECTION N−N

0.65 BSC

0.026 BSC

0.60 0.020 0.024

0.20 0.004 0.008

0.16 0.004 0.006

0.30 0.007 0.012

0.25 0.007 0.010

0.50

0.09

0.19

−W−

K1 0.19

6.40 BSC

0.252 BSC

0.10 (0.004)

SEATING

PLANE

−T−

DETAIL E

GENERIC

MARKING DIAGRAM*

SOLDERING FOOTPRINT

XXXX

ALYWG

7.06

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

0.65

PITCH

(Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

0¹.3^4X6

14X

1.26

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASH70246A

TSSOP−14 WB

PAGE 1 OF 1

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NCS37020DTBR2G [ONSEMI]

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