NCS5021MNR2 [ONSEMI]
NCS5021MNR2;
| 型号： | NCS5021MNR2 |
| 厂家： | 
ONSEMI |
| 描述： | NCS5021MNR2 |
| 文件： | 总13页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCS5021
Product Preview
Dual Band EDGE
Compatible PA Controller
The NCS5021 circuit is dedicated to RF Power amplifier control for
GSM and DCS standards. It significantly reduces the number of
external passive devices while giving the RF designer the capability to
perfectly tune the control loop. This device is compatible with both
constant and non−constant envelope modulations, which are used with
GSM and GSM/EDGE.
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MARKING
DIAGRAM
1
12
1
Features
xxx
QFN 3x3−12 LEAD
SQL SUFFIX
ALYW
• Integrated Two 50 W Matched RF Power Detectors
• Direct Supply from Battery Voltage
CASE 485N
• Low Bandwidth Mode (EDGE)
• High Gain Integrator Requesting only One External Capacitor
• PA Control Buffer Compatible with Gate Controlled Amplifiers
• Generation of Pre−bias Level for PA at Start of Burst
• 12 Pins QFN 3 x 3
xxx
Code
A
L
Y
= Specific Device
= Assembly Location
= Wafer Lot
= Year
Typical Applications
W
= Work Week
• Global System for Mobile Communication (GSM/DCS)
• Personal Communication Network (PCN)
9
1
8
2
7
3
RF GSM
V
APC
10
11
12
6
5
4
EDGE
V
CC
SELECT
ENABLE
GND
RF GND
RF DCS
100 kHz
8
3
RAMP
CTRL
9
+
V
APC
6
1/1
G = 2
Clamp
+
1/100
−
CMOS DETECTOR
RF GSM
RF GND
RF DCS
10
11
12
50 W
+
QFN3x3−12 (Top View)
−
50 W
75 mV
4
Calibration
Timer
250 k
ORDERING INFORMATION
Device
NCS5021MN
NCS5021MNR2
Package
Shipping
2
1
7
5
BAND SELECT
GND
CEXT
QFN3x3−12 Bulk/Railed/Tray
V
ENABLE
MIN
PRESET
Tape & Reel
QFN3x3−12
Figure 1. Functional Block Diagram
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 6
NCS5021/D
NCS5021
V
BAT
Power Amplifier
Two Couplers
GSM
DCS
GSM
DCS
Pin GSM
Pin DCS
Pout GSM
Pout DCS
−18 dB
−14 dB
V
EDGE
SELECT
3
BAT
NCS5021
V
CC
100 kHz
8
RAMP
CTRL
9
+
V
APC
6
1/1
1/100
G = 2
Clamp
+
−
CMOS DETECTOR
RF GSM
RF GND
RF DCS
10
11
50 W
+
−
50 W
75 mV
4
12
Calibration
Timer
250 k
2
1
7
5
BAND
SELECT
GND
CEXT
ENABLE
V
PRESET
MIN
V
REF
From DSP
Figure 2. Typical Application Circuit with Two Couplers
V
BAT
Power Amplifier
Dual Couplers
GSM
DCS
GSM
DCS
Pin GSM
Pin DCS
Pout GSM
−18 dB
−14 dB
Pout DCS
V
EDGE
SELECT
3
BAT
NCS5021
V
CC
100 kHz
8
RAMP
CTRL
9
+
V
APC
6
1/1
1/100
G = 2
Clamp
+
−
CMOS DETECTOR
RF GSM
RF GND
RF DCS
10
11
+
50 W
50 W
−
75 mV
4
12
Calibration
Timer
250 k
2
1
7
5
BAND
SELECT
GND
CEXT
ENABLE
V
PRESET
MIN
V
REF
From DSP
Figure 3. Typical Application Circuit with Dual Couplers
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2
NCS5021
PIN DESCRIPTION
Pin
Name
Pin Description
1
CEXT
Integrator’s external capacitor: The external capacitor is determining the integrator’s frequency response
and has a direct impact over the loop stability and its transient response.
2
3
BAND SELECT GSM/DCS band selection: A logical “0” on this input pin select the GSM RF input and a logical “1” selects
DCS RF input.
EDGE SELECT EDGE mode selection: When the EDGE pin is switched to a logical “1”, the integrator’s bandwidth is divided
by a factor of one hundred. The control loop becomes too slow to compensate the amplitude modulation
created by EDGE. This mode is not activated during power ramp−up and ramp−down to allow the control
loop to fit into the GSM time and frequency masks.
4
5
GND
Digital ground: To be connected to a digital ground.
ENABLE
Shutdown mode: A zero on this input pin switches off the output buffer V
. Also the Integrator’s CEXT
APC
capacitor is Reset (shot circuited) and all other functions are in low power mode. This input must be high
typically 25 ms before RAMP CONTROL raises. During this time the device is in calibration mode to cancel
internal offset. Before each first burst, the device must be set from disable to enable in order to perform the
calibration, excepted for a series of burst (GPRS).
6
7
V
Power Amplifier Control signal: This output pin controls the power amplifier. It remains at zero if ENABLE pin
APC
is low. When ENABLE pins high, V
rises to the voltage level on VMIN PRESET with a gain of 2 only if
APC
RAMP CTRL is over than 75 mV. Then it remains at VMIN PRESET level until RAMP CTRL goes over 100
mV, then the loop is closed and V
has a clamp at 2.8 V.
controls the PA power. So in order to protect the PA, the output buffer
APC
VMIN PRESET Output voltage minimum value: This analog input pin defines the V
minimum voltage. This level amplified
APC
by two should be slightly below the power amplifier amplification threshold. It helps the loop to quickly con-
verge without overshoot when the output power begins to rise.
8
9
V
Power supply.
CC
RAMP CTRL
Power control loop reference voltage: Due to the output detector offset voltage fixed at 100 mV in GSM and
DCS a voltage higher than 100 mV must be applied to raise V
. The ramp control voltage does not give a
APC
direct power value. It indicates the voltage, which should be present at the power detector output.
10
RF GSM
GSM band: RF signal input: The RF signal may vary from 200 MHz to 2.5 GHz. The input power may reach
+18 dBm.
When no RF is applied, the internal output detector offset is fixed at 100 mV.
11
12
RF GND
RF DCS
Ground Pin to be connected to the RF ground. So each internal 50 W required for matching is connected
between RF input and this ground pin.
DCS band : RF input signal: The RF signal may vary from 200 MHz to 2.5 GHz. The input power may reach
+18 dBm.
When no RF is applied, the internal output detector offset is fixed at 100 mV.
MAXIMUM RATINGS
Rating
Symbol
Value
23
Unit
dBm
V
Maximum Input Power on RF Pins
Maximum Power Supply
P
MAX
V
5.5
CCMAX
Human Body Model (HBM) ESD Rating for RF GSM and RF DCS Pin.
All Other Pins are (Note 4)
1000
2000
V
ESD HBM
ESD MM
Machine Model (MM) ESD Rating for RF GSM and RF DCS Pin.
All Other Pins are (Note 5)
100
200
V
Operating Ambient Temperature
Storage Temperature
TA
−30 to +85
°C
°C
V
T
stg
−65 to +150
Maximum Input DC Voltage on Pins
Minimum Input DC Voltage on Pins
V
V
+ 0.3
CC
IMAX
V
−0.3
15
V
IMIN
Maximum Current on Pin V
IO
mA
APC
MAX
1. Guaranteed by design.
2. Tested.
3. Guaranteed by design and characterized.
4. Human Body Model, 100 pF discharged through a 1.5 kΩ resistor following specification JESD22/A114.
5. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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3
NCS5021
ELECTRICAL CHARACTERISTICS Limits apply for TA between −30°C to +85°C (unless otherwise noted).
Input Specifications
Pin
8
Rating
Operating Power Supply (Note 6)
Symbol
Min
2.9
−
Typ
−
Max
4.8
Unit
V
V
CC
CC
8
Active Mode Current Consumption (Unloaded) (Note 6)
Power Down Current Consumption (Note 6)
Wake Up Time (Notes 8 and 9)
I
4.7
0.1
25
−
7.0
mA
mA
8
I
−
1.0
pdn
5
W
ut
TBD
200
50
ms
10
12
Operating Frequency Range Max (Note 8)
F_in
2500
MHz
9
Operating Voltage Range on Ramp CTRL (Note 8)
V Ramp
CTRL
−
−
−
1800
0.8
mV
V
7
Operating voltage range on VMIN PRESET. Below 100 mV with 0 V
from integrator, the transfer function is not guaranteed linear but low-
er than the straight line defined by GOP. (Note 6)
V
0.1
MIL
Detector
10
12
Linear Detection Range (Note 8)
Range Linear
−20
−25
−
−
18
20
dBm
With a "1.0 dB Linearity in Nominal Conditions at +25°C
With a "2.0 dB Linearity at −30°C < T < +85°C
10
12
Not Linear Detection Range (Note 8)
Range Not
Linear
dBm
mV
10
12
Detector Sensitivity (Note 8)
Det_Sens
Fin = 2.0 GHz, R = –15 dBm
10
−
−
−
−
1800
fin
Fin = 800 MHz, R = 20 dBm
fin
10
12
Input Impedance on RF GSM and RF DCS Pin
R_in
−
50
−
W
10
12
Harmonic Return Loss by RF_IN up to 20 dBm @ 900 MHz (Note 8)
H_Return
dBc
H2
H3
−
−
−38
−52
−
−
10
12
Voltage Standing Wave Ratio @ 25°C (Note 8)
VSWR
DD
−
−
2:1
−
10
12
Internal Output Detector Delay to 90% Detected of RF Power Step
(Note 7)
−
100
300
ns
Filter and Comparator
9
Ramp CTRL Threshold Offset Voltage to Close Loop @ 25°C and
= 3.6 V (Note 8)
O Ramp
CTRL
90
100
110
5.0
mV
mV
V
CC
9
Ramp CTRL Drifting Threshold Voltage versus V and Temperature
D Ramp
CTRL
−
−
CC
(Note 8)
9
9
9
Smoothing Filter Corner Frequency @ 25°C (Note 7)
Smoothing Filter Attenuation @ 1.0 MHz @ 25°C (Note 7)
FCS
ATT
100
45
−
−
−
−
kHz
dB
Comparator Threshold to Switch on VMIN PRESET versus O Ramp
CTRL. Due to hysteresis, add 5 mV for going up and remove 5 mV
for going down (Note 6)
V THRD
50
70
90
mV
9
Comparator Hysteresis @ 25°C and 3.6 V (Note 8)
H THRD
−
10
−
mV
6. Tested.
7. Guaranteed by design.
8. Guaranteed by design and characterized.
9. Time necessary for internal calibration, see “t1” on Figure 20. Typical Timing Chart for GSM and EDGE Application.
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4
NCS5021
ELECTRICAL CHARACTERISTICS Limits apply for TA between −30°C to +85°C (unless otherwise noted).
Integrator Section
Pin
Rating
Symbol
GDC
Min
Typ
Max
Unit
dB
−
DC Gain (Note 11)
Open Loop Band−Width from the Detector (RF GSM or RF DCS) to
55
70
−
INT_BW
kHz
Output Buffer (V
) @ 25 °C and CEXT = 1 nF (Note 12)
EDGE SELECT = 0 (not active)
EDGE SELECT = 1 (active)
APC
−
−
160
1.6
−
−
Phase Margin (Note 12)
Step Level on V
P_MARG
S EDGE
60
75
°
5
7
when EDGE is Switch in Close Loop with RAMP
−
2.5
−
mV
APC
CTRL constant in operating range. Typical Value @ V = 3.6 V and
CC
25°C (Note 11)
Output Buffers and Logic Section
6
Buffer Available Output Current (Note 10)
I
mA
out
V
= (V
= (V
unloaded −100 mV)
10
–1.0
–0.1
−
−
−
−
−
−
APC
APC
V
APC
APC
V
unloaded + 100 mV))
= 50 mV
APC
6
Output Buffers Voltage Clamp (Note 10)
V
2.65
8.0
2.8
10
3.0
V
high
−
Simulate Bandwidth With Out the Integrator Through Close Loop Way
(Detector, Comparator, Adder and Output Buffer) (Note 11)
BW
−
MHz
7
6
From 0.1 to 0.8 Apply on VMIN PRESET and no voltage from
GOP
−10
−
+10
%
Integrator. V
(Note 10)
is equal at Two Times VMIN PRESET
APC
Ripple Rejection, (Ripple 0.2 Vp−p) @ 25°C in Close Loop.
(Note 12)
PSRR
dB
60
58
50
35
70
68
60
45
−
−
−
= 1.0 kHz EDGE = 0
= 10 kHz EDGE = 0
= 1.0 kHz EDGE = 1
= 10 kHz EDGE = 1
2, 3, Voltage Input Logic Low (Note 10)
5
V
−
−
−
0.3
V
V
IL
2, 3, Voltage Input Logic High (Note 10)
5
V
1.5
IH
−
2, 3 Current Input Logic (Note 11)
Lin
−
0.01
250
0.1
mA
kW
5
Pull down on ENABLE logic input to keep level low when the driver is
in high impedance condition. (Note 12)
PDE
150
400
10.Tested.
11. Guaranteed by design.
12.Guaranteed by design and characterized.
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5
NCS5021
TYPICAL PERFORMANCE CHARACTERISTICS
80
60
80
60
EDGE = 0
40
40
EDGE = 0
20
20
0
0
−20
−40
−60
−20
EDGE = 1
1.0 k
EDGE = 1
−40
−60
10
100
10 k
100 k
1.0 M
10 M
10
100
1.0 k
10 k
100 k
1.0 M
10 M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4. Open−Loop Gain at CEXT = 1.0 nF
Figure 5. Open−Loop Gain at CEXT = 4.7 nF
180
135
90
180
EDGE = 0
EDGE = 0
135
90
45
45
0
0
−45
−90
−135
−180
−45
−90
−135
−180
EDGE = 1
EDGE = 1
10
100
1.0 k
10 k
100 k
1.0 M
10 M
10
100
1.0 k
10 k
100 k
1.0 M
10 M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Open−Loop Phase at CEXT = 1.0 nF
−30°C
Figure 7. Open−Loop Phase at CEXT = 4.7 nF
10000
1000
100
10
35
30
25
20
15
10
5
+85°C
+25°C
900 MHz
0
1800 MHz
−5
−10
1
90
290
490
690
890 1090 1290 1490
−25 −20 −15 −10 −5
0
5
10
15
20
RAMP CTRL (mV)
RF INPUT POWER (dBm)
Figure 8. Transfer Function with 18 dB
Coupler at 900 MHz
Figure 9. Detector Characteristic
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NCS5021
TYPICAL PERFORMANCE CHARACTERISTICS
2
1
0
−10
−30°C
−20
−30
−40
−50
−60
−70
−80
EDGE = 1
0
−1
−2
+85°C
EDGE = 0
100 k 1.0 M
100
1.0 k
10 k
FREQUENCY (Hz)
−5
0
5
10
15
20
25
30
35
PA OUTPUT (dBm)
Figure 11. PSRR at V = 3.6 V and Ripple 0.2 Vp−p
Figure 10. PA Output Drift vs. Temperature with
18 dB Coupler at 900 MHz
CC
0.5
40
35
30
25
20
15
10
5
High Power
0.25
0
Low Power
High Power
Medium Power
Medium Power
Low Power
−0.25
0
880
−0.5
885
890
895
900
905
910
915
880
885
890
895
900
905
910
915
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. PA Output vs. EGSM Frequency Range
with 18 dB Coupler
Figure 13. Power Variation vs.
EGSM Frequency Range
35
30
25
20
15
10
5
0.5
0.25
0
High Power
Medium Power
DCS Range
1760
PCS Range
−0.25
Low Power
0
−5
−0.5
1710 1730 1750 1770 1790 1810 1830 1850 1870 1890 1910
1710
1810
1860
1910
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. PA Output vs. DCS/PCS Frequency
Range with 14 dB Coupler
Figure 15. Power Variation vs. DCS/PCS
Frequency Range
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NCS5021
TYPICAL PERFORMANCE CHARACTERISTICS
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
H2
H2
H3
H3
−20
−10
0
INPUT POWER (dBm)
10
20
−20
−10
0
INPUT POWER (dBm)
10
20
Figure 16. Return Harmonic by Input RF GSM or
RF DCS at 900 MHz
Figure 17. Return Harmonic by Input RF GSM or
RF DCS at 1.8 GHz
1: 22.687 Ω 4.3623 Ω 277.71 pH
S
1 U FS
11
2.4
2.2
2
2 500.000 000 MHz
hp
2: 51.27 Ω
−4.0469 Ω
200 Ω
Cor
MARKER 1
2.5 GHz
1.8
1.6
1.4
1.2
1
1
2
200
700
1200
1700
2200
2700
FREQUENCY (MHz)
CH1 START 200.000 000 MHz STOP 2 500.000 000 MHz
Figure 18. VSWR for Input RF GSM or RF DCS
Figure 19. S11 Parameter in Smith Chart for Input
RF GSM or RF DCS
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8
NCS5021
V
ENABLE
Pin 4
V
BAND
SELECT
Pin 3
V
RAMP
CTRL
Pin 11
100 mV
t1
V
EDGE
SELECT
Pin 2
Only for EDGE (8−PSK) modulation
V
VAPC
Pin 7
dBc
+2.4
+4
+1
−1
0
−6
Nominal Level
Time mask for EDGE (8−PSK) modulation
−15
−30 dBc
Time mask for GMSK modulation
RF
Power
Level
7056/13 (542,8 ms)
10
8
10 22
22 10
8
10
Time (ms)
Figure 20. Typical Timing Chart for GSM and EDGE Application
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NCS5021
DETAILED OPERATING DESCRIPTION
Integrator
RF Power Detector
It performs the amplitude demodulation of applied RF
input signal. Its dynamic range fully covers the different
GSM power levels. The requested biasing signals are
internally generated. The power detector is designed to
fulfill the GSM 05.05 standard providing good peak power
control over a 40 dB linear range. The 43 dB detection range
allows the Figure 20 template to be respected during
ramp−up and ramp down. The very low out−of−burst noise
floor can be achieved by apply level from DAC lower than
75 mV to RAMP CTRL. The detector is designed to operate
with a RF coupler providing a 18 dB attenuation in GSM
mode and a 14 dB attenuation in DCS/PCS is recommended
by Murata, for example. 8 bits DAC may be used as
Reference signal generator. Nevertheless such low
resolution DAC may result in a loss of accuracy at very low
power levels (beginning of the ramp). The RF GSM and RF
DCS inputs are both 50 W matched with DC coupling
capacitor and provide a very good Voltage Standing Wave
Radio (VSWR). Linearity detection versus frequency is
The integrator performs two different functions. Due to its
very high gain, it minimizes the error signal resulting from
detector’s output and reference signal comparison,
contributing to power control accuracy. Then, by the correct
bandwidth setting, it guarantees the system stability and fits
GSM time mask. Due to the system constraint, a fine
frequency tuning is often requested. The NCS5021 circuit
provides this flexibility by keeping the integrator capacitor
external. To limit power consumption, the external capacitor
charge and discharge current does not exceed 100 mA
(typical). The minimal external capacitor should not be
lower than 47 pF to guarantee loop stability and should not
exceed 4.7 nF.
Minimum Voltage Adder
The power amplifier control input needs to reach a certain
threshold before the output power begins to rise. Due to the
integrator’s low bandwidth which has been chosen for
stability reasons, an important delay may be present before
the power begins to rise. Furthermore, some ringing may
occur when the control loop switches from its inactive state,
to normal, regulated state. An efficient way to solve these
there by excellent and could allow use of
a
frequency−correcting table. Nevertheless the coupler may a
have coupling factor variation and downgraded the linearity.
problems is to raise the PA control voltage to a V
voltage, very close to the emission threshold. V
Preset
Preset
MIN
Reference Signal Filter
MIN
If we consider a close loop operation and an infinite
integrator gain, the reference voltage will be equal to the
internal detector output voltage. So, knowing the transfer
function characteristics (see Figure 8), it defines the PA
output power. The reference signal varies during the burst to
reach the requested Tx power, to stand at the nominal power
level, and then return to the specified out−of−burst level.
This signal is generated with a clocked DAC, whose steps
have to be smoothed to minimize switching transients. The
third order Bessel filter’s transfer function is defined to
comply with GSM requirements in terms of switching
transients and time and frequency masks. A systematic
offset has been created on REF input to ensure that the loop
remains closed even at very low output power whatever the
internal offset voltages.
signal is added to the integrator’s output signal through the
output buffer amplified by two.
Output Buffer
The output buffer is providing the current capability to
drive the PA control input. With Enable pin low, V
APC
remains low to make that sure RF power will not be supplied
by the PA. So the device may be switched on typically by
25 ms before the burst to ramp−up, to allow the internal
calibration sequence.
Power−down Mode
During the unused time slots in Time Division Multiple
Access (TDMA) systems, the NCS5021 must be in low
power mode by applying a zero logic level on pin ENABLE.
This function saves power from battery and put PA in low
power by supplying very low level to output buffer V
.
APC
Also when power−down mode is active, the external
capacitor is discharged to initial conditions for next burst.
This input must be high typically by 25 ms before Ramp
Control goes high.
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10
NCS5021
DEMO BOARD
J5
V
S1
V
2
1
APC
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
P
MIN
STRAP
RAMP C
ENABLE
EDGE S
SYNCHRO
BAND S
PRESET
TP8 V
APC
V
APCD
V
APCG
J7
SMB M
V CONTROL
+5V
HEADER 8X2
TP3 V
P
MIN
U1
NCS5021QFN12
10
11
12
RF GSM
AGND
J8
V
P
7
MIN
SMB F
V
P
MIN
C2
10 n
RF DCS
TP5 CEXT
1
TP1V
CC
V CONTROL
J9
SMB F
8
V
CC
CEXT
3
C5
C4
C3
1 n
*pF
1 nF
2
5
9
4
TP7 EDGE
TP2 RAMP C
RAMP C
TP4 ENABLE
TP6 BAND S
V CONTROL
V CONTROL
BAND S
ENABLE
J1
1
1
R1
100 k
V CONTROL
1
2
2
2
3
C1
100 n
3
Power
J4
J3
Figure 21. Demo Board Schematic
Figure 22. Silkscreen
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11
NCS5021
DEMO BOARD
Figure 23. PCB Top View
Figure 24. PCB Bottom View
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12
NCS5021
PACKAGE DIMENSIONS
12 PIN, 3X3 QFN
CASE 485N−01
ISSUE O
A
D
B
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN
MAX
1.00
0.05
0.75
A
A1
A2
A3
b
0.80
0.00
0.65
0.20 REF
0.20
0.15
C
0.15
C
0.30
D
D2
E
3.00 BSC
1.50
1.80
3.00 BSC
0.10
0.08
C
E2
e
K
1.50
0.50 BSC
0.20
0.35
1.80
A2
A
−−−
0.45
SEATING
PLANE
L
C
A3
A1
REF
C
D2
12 X L
e
4
6
3
1
7
E2
9
12 X b
0.10 C A B
0.05
12
10
12 X K
C
NOTE 3
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