NCS7041D3G050R2G_技术文档

DATA SHEET

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Current Sense Amplifier,

80ꢀV Common-Mode

Voltage, Bidirectional

8

1

SOIC−8 NB

CASE 751−07

Micro8 / MSOP−8

CASE 846A−02

NCS7041, NCV7041

MARKING DIAGRAMS

8

The NCS7041 and NCV7041 are high voltage, high resolution,

current sense amplifiers. They feature gain options of 14, 20, 50, and

100 V/V, with a maximum 0.3% gain error over the entire

temperature range. Each part consists of a preamplifier and buffer with

access to output and input via A1 and A2 pins for an intermediate filter

network or modified gain. These parts have a wide common mode

input voltage range from −6 V to 80 V. The NCS7041 can perform

unidirectional or bidirectional current measurements across a sense

resistor in a variety of applications. Automotive qualified options are

available under NCV prefix. All versions are specified over the

extended operating temperature range from −40°C to 150°C.

8

7041XXX

41XX

AYWG

G

ALYWX G

G

1

SOIC−8 NB

Micro8 / MSOP−8

XXXXX = Specific Device Code

A

L

Y

W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

Features

• Gain Bandwidth: 100 kHz

• Input Offset Voltage: 300 mV Max

• Input Offset Drift over Temperature: 3 mV/°C Max

• Gain Error: 0.3% Max

• Quiescent Current: 1.5 mA Typ

• Supply Voltage: 3 V to 5.5 V

• Common−Mode Input Voltage Range: −6 V to 80 V

• CMRR: 85 dB Min

• PSRR: 75 dB Min

• Low−pass Filter (1−pole or 2−pole)

PIN ASSIGNMENT

−IN

1

8

+IN

V

NCS7041

GND

A1

2

3

7

6

REF

V

S

A2

4

5

OUT

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

ORDERING INFORMATION

See detailed ordering and shipping information on page 15 of

this data sheet.

• These are Pb−Free Devices

Typical Applications

• Telecom Equipment

• Power Supply Designs

• Diesel Injection Control

• Automotive

• Solenoids / Actuators

This document contains information on some products that are still under development.

onsemi reserves the right to change or discontinue these products without notice.

1

Publication Order Number:

May, 2023 − Rev. 2

NCS7041/D

NCS7041, NCV7041

V_S

A1

A2

NCS7041

EMI Filter

R

100k

PRE

1.4M

G = 2

−

−IN

+

OUT

+

+IN

−

G = 7, 10, 25, or 50

1.4M

10k

GND

V_REF

Figure 1. Simplified Representative Block Diagram

V

S

= 5 V

NCS7041

high−side

switch

V_S

OUT

A1

V

= 5 V

S

+IN

NCS7041

sense

resistor

load

V_S

OUT

A1

A2

−IN

+

+IN

−

load

GND

V_REF

sense

resistor

A2

−IN

V

2.5 V

=

REF

low−side

switch

optional

filtering

V

2.5 V

=

GND

V_REF

REF

optional

filtering

Low−Side Current Sensing

High−Side Current Sensing

Figure 2. Application Schematics

PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

−IN

Description

1

2

3

4

5

6

7

8

Inverting input. Connect to sense resistor

Device ground

GND

A1

Pre−amp output connection

Buffer amp input connection

Device output

A2

OUT

V

S

Power supply connection. Connect a bypass capacitor of 0.1 mF as close as possible to this pin

Voltage reference connection to offset output

V

REF

+IN

Non−inverting input. Connect to sense resistor

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2

NCS7041, NCV7041

ABSOLUTE MAXIMUM RATINGS

Symbol

Rating

Value

Unit

V

S

Input Voltage Range (Note 1)

Reference Pin Voltage

−0.3 to 7

V

REF

−0.3 to (V + 0.3)

V

S

V

Input Common−Mode Voltage Range

Differential Input Voltage

−14 to 85

V

CM

V

S

V

ID

I

Maximum Input Current

10

50

mA

mW

°C

V

I

O

Maximum Output Current

P

Continuous Total Power Dissipation

Maximum Junction Temperature

Storage Temperature Range

200

D

T

150

J(max)

T

−65 to 150

STG

ESD

ESD Capability (Note 2)

HBM

Human Body Model, Input pins

Human Body Model, All other pins

Charged Device Model

7000

4000

1000

Latch−Up Current (Note 3)

Moisture Sensitivity Level

Lead Temperature Soldering

100

1

mA

−

MSL

T

SLD

260

°C

Reflow (SMD Styles Only), Pb−Free Versions (Note 4)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

2. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per JS−001−2017 (AEC−Q100−002)

ESD Charged Device Model tested per JS−002−2014 (AEC−Q100−004)

3. Latch−up current maximum rating: 100 mA per JEDEC standard JESD78E

4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

THERMAL CHARACTERISTICS (Note 5)

Symbol

Parameter

Thermal Resistance, Junction−to−Air

Package

Micro8

Value (Note 6)

163

Unit

°C/W

q

JA

SOIC−8

Micro8

128

Y

JT

Thermal Characteristic, Junction−to−Case Top

Thermal Characteristic, Junction−to− Board

24.4

SOIC−8

Micro8

28.5

Y

JB

137.3

103.5

SOIC−8

5. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.

2

6. Values based on copper area of 645 mm (or 1 in ) of 1 oz copper thickness and FR4 PCB substrate.

OPERATING RANGES (Note 7)

Symbol

Parameter

Min

3

Max

Unit

V

S

Supply Voltage

5.5

V

REF

Reference Voltage

0

V

S

V

Input Common−Mode Range

Ambient Temperature

−6

−40

80

V

CM

T

150 (Note 8)

°C

A

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

7. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

8. Operation up to T = 150°C is permitted, provided the total power dissipation is limited to prevent the junction temperature from exceeding

A

the 150°C absolute maximum limit.

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3

NCS7041, NCV7041

ELECTRICAL CHARACTERISTICS (At V = 5 V, T = +25°C, V = 12 V, V

= 2.5 V, R ≥ 10 kW, unless otherwise noted.

L

Limits in bold apply over the specified temperature range, guaranteed by characterization and/or design.)

S

A

CM

REF

Symbol

GAIN

Parameter

Conditions

Temp (5C)

Min

Typ

Max

Unit

G

Total Gain, Preamplifier and

Buffer

G = 14 V//V

25

−

14

20

−

V/V

G = 20 V/V

G = 50 V/V

G = 100 V/V

50

100

−40 to 125

−40 to 150

−40 to 125

−

+0.3

+0.5

+20

G

Gain Error

Gain Drift

%

e

G = 14 V//V

G = 20 V//V

G = 50 V//V

DG/DT

ppm / °C

G = 100 V//V

−

+35

VOLTAGE OFFSET

Input Offset Voltage

25

−

100

−

300

+300

+400

+3

V

OS

mV

−40 to 125

−40 to 150

−40 to 125

DV /DT Input Offset Voltage Drift

−

mV / °C

OS

INPUT

V

CM

Common−Mode Input Voltage

Range

−40 to 150

−6

−

80

V

= −6 to 80 V

−40 to 150

85

105

−

CMRR

Common−Mode Rejection

Ratio (see Graphs and Appli-

cation Information sections)

dB

CM

f = 10 kHz

= 12 V,

G = 14

G = 20

G = 50

G = 100

65

70

75

80

83

90

−

V

CM

1 V

PP

PREAMPLIFIER

G

Gain

G = 14 V//V

G = 20 V/V

G = 50 V/V

G = 100 V/V

25

−

7

−

V/V

PRE

10

25

50

G

Gain Error

−40 to 125

−40 to 150

25

−40 to 150

−40 to 125

−

+0.3

%

V

e

V

OH

Output Voltage Swing to V

V − 0.05 V − 0.002

S

−

S

V

OL

Output Voltage Swing to GND

Output Resistance

−

98

94

−

1.5

100

−

25

mV

kW

102

106

500

R

PRE

I

IB

Input Bias Current

200

mA

OUTPUT BUFFER

G

Gain

25

−

2

−

+0.3

−

V/V

%

OUT

G

Gain Error

−40 to 125

−40 to 150

−40 to 125

−

e

V

Output Voltage Swing to V

V

S

− 0.05 V − 0.003

V

OH

S

V

I

Output Voltage Swing to GND

Input Bias Current

−

0.5

5

25

mV

nA

OL

IB

+20

DYNAMIC PERFORMANCE

BW

SR

Bandwidth

Slew Rate

25

−

100

1

−

kHz

V / ms

NOISE

V

Voltage Noise, Peak−to−Peak

f = 0.1 Hz to 10 Hz

f = 1 kHz

25

−

10

−

mV

p−p

n

e

N

Voltage Noise Density (RTI)

120

nV / √Hz

POWER SUPPLY

V

Operating Voltage Range

Quiescent Current

−40 to 150

25

−40 to 125

−40 to 150

3

−

75

−

1.5

−

90

5.5

2.4

2.7

2.8

−

V

S

I

mA

DD

PSRR

Power Supply Rejection Ratio

dB

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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4

NCS7041, NCV7041

TYPICAL CHARACTERISTICS

At T = 25°C, V = 5 V, V

= 12 V, V

= 2.5 V, R = 10 kW, unless otherwise noted

A

S

CM

REF

L

45

30

25

120 Units

40

35

30

25

20

15

10

5

20

15

10

5

0

−75 −50 −25

0

25 50 75 100 125 150 175

−0.6 −0.4 −0.2

0

0.2 0.4 0.6 0.8

1

1.2

INPUT OFFSET VOLTAGE (mV)

INPUT OFFSET VOLTAGE DRIFT (mV/°C)

Figure 3. Input Offset Voltage Distribution

Figure 4. Input Offset Voltage Drift Distribution

150

100

50

1200

1000

800

600

5 Units

6 Units

400

200

0

−200

−400

−600

−50

−100

−50

−25

0

25

50

75

100

125

150

−10

0

10

20

30

40

50

60

70

80

TEMPERATURE (°C)

COMMON MODE VOLTAGE (V)

Figure 5. Input Offset Voltage vs. Temperature

Figure 6. Input Offset Voltage vs. Common

Mode Input Voltage

130

110

90

V

CM

= 1 Vpp

70

50

30

G = 14

G = 20

G = 50

G = 100

10

−10

−30

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 7. CMRR vs. Frequency

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5

NCS7041, NCV7041

TYPICAL CHARACTERISTICS

At T = 25°C, V = 5 V, V

= 12 V, V

= 2.5 V, R = 10 kW, unless otherwise noted

A

S

CM

REF

L

100

90

80

70

60

50

40

30

20

2.80

100

4.2

4.0

3.8

3.6

3.4

3.2

3.0

2.8

2.6

4 typical units

output

4 typical units

90

80

70

60

2.72

2.64

2.56

output

50

40

30

20

2.48

2.40

input

2.4

2.2

10

0

10

0

input

TIME (20 ms/div)

TIME (500 ms/div)

Figure 8. Common Mode Step Response with

1 ms Rising Edge

Figure 9. Common Mode Step Response with

10 ms Rising Edge

100

90

80

70

60

50

40

30

20

2.80

100

90

80

70

60

50

40

30

20

2.6

2.4

2.2

4 typical units

2.72

2.64

2.56

input

2.0

1.8

1.6

1.4

1.2

1.0

output

2.48

2.40

10

0

0.8

0.6

10

0

4 typical units

TIME (500 ms/div)

TIME (10 ms/div)

Figure 10. Common Mode Step Response with

1 ms Falling Edge

Figure 11. Common Mode Step Response with

10 ms Falling Edge

300

I

−

IB

250

200

150

100

50

I +

IB

0

−50

0

50

TEMPERATURE (°C)

100

150

Figure 12. Preamplifier Input Bias Current vs.

Temperature

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6

NCS7041, NCV7041

TYPICAL CHARACTERISTICS

At T = 25°C, V = 5 V, V

= 12 V, V

= 2.5 V, R = 10 kW, unless otherwise noted

A

S

CM

REF

L

0.1

0.08

0.06

0.04

0.02

0

101.0

100.5

100.0

99.5

99.0

−0.02

−0.04

−0.06

98.5

98.0

−50

0

50

TEMPERATURE (°C)

100

150

−50

0

50

100

150

TEMPERATURE (°C)

Figure 13. Preamplifier Gain Error vs.

Temperature

Figure 14. Preamplifier Output Resistance vs.

Temperature

300

250

200

150

100

50

180

160

140

120

100

80

T = −40°C

A

T = −40°C

A

T = 25°C

A

T = 25°C

A

T = 125°C

A

T = 125°C

A

60

40

20

0

10

20

30

40

50

60

0

5

10

15

20

OUTPUT CURRENT (mA)

Figure 15. Buffer Output Voltage Swing to

GND vs. Output Current

Figure 16. Buffer Output Voltage Swing from

Supply Rail vs. Output Current

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7

NCS7041, NCV7041

TYPICAL CHARACTERISTICS

At T = 25°C, V = 5 V, V

= 12 V, V

= 2.5 V, R = 10 kW, unless otherwise noted

A

S

CM

REF

L

1000

100

10

8

7

6

5

4

3

2

1

V

A2

= 1 V

= 2 V

A2

1

0.1

0.01

0

−50

0

50

TEMPERATURE (°C)

100

150

1

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 17. Buffer, Input Bias Current vs.

Temperature

Figure 18. Buffer Output Impedance vs.

Frequency

0.02

0

50

40

30

20

10

−0.02

−0.04

−0.06

−0.08

−0.1

G = 14

G = 20

G = 50

G = 100

0

−0.12

−10

10

100

1k

10k

100k

1M

10M

−50

0

50

100

150

TEMPERATURE (°C)

FREQUENCY (Hz)

Figure 19. Total Gain Error vs. Temperature

Figure 20. Gain vs. Frequency

140

120

100

80

PSRR+

PSRR−

60

40

20

0

−20

−40

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 21. PSRR vs. Frequency

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8

NCS7041, NCV7041

TYPICAL CHARACTERISTICS

At T = 25°C, V = 5 V, V

= 12 V, V

= 2.5 V, R = 10 kW, unless otherwise noted

A

S

CM

REF

L

12.2

12.15

12.1

4.5

4

12.2

12.15

12.1

4.5

4

3.5

3

3.5

3

12.05

12

12.05

12

2.5

2

2.5

2

11.95

11.9

11.95

1.5

1

11.9

1.5

1

Input

Output

11.85

Input

Output

11.85

11.8

0.5

11.8

0.5

TIME (5 ms/div)

Figure 22. Transient Response

Figure 23. Transient Response

1k

100

10

1.5

1.25

1

0.75

0.5

0.25

0

−0.25

−0.5

−0.75

−1

−1.25

−1.5

100

1k

10k

100k

TIME (1 s/div)

FREQUENCY (Hz)

Figure 25. Noise, 0.1 Hz to 10 Hz, Referred to

Input

Figure 24. Voltage Noise Density

2

1.8

1.6

1.4

1.2

1

−50

0

50

TEMPERATURE (°C)

100

150

Figure 26. Quiescent Current

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9

NCS7041, NCV7041

APPLICATION INFORMATION

The NCS7041 and NCV7041 are current sense amplifiers

For switching applications, Figures 27 and 28 show the

suggested placement of the switch and sense resistor to

minimize noise and common mode artifacts.

featuring a wide common mode voltage up to 80 V

independent of the supply voltage. The NCS7041 series

current−sense amplifiers can be configured for both

low−side and high−side current sensing.

Unidirectional and Bidirectional Operation

The NCS7041 is capable of both unidirectional and

bidirectional current sensing. In unidirectional current

sensing, the measured load current always flows in the same

direction. Common applications for unidirectional

operation include power supplies and load current

monitoring. In bidirectional current sensing, the measured

load current can flow in either the positive or negative

direction. Common applications for bidirectional operation

include battery charging and discharging.

Current Sensing Techniques

Low−side sensing gives the impression of having

the advantage of being straightforward to implement with a

simple op amp circuit. However, a current sense amplifier

such as NCS7041 provides the full differential input

necessary to get accurate shunt connections, while also

providing a built−in gain network with precision difficult to

obtain with external resistors. The NCS7041 is shown in a

low−side configuration in Figure 27 below.

The internal circuitry of the NCS7041 is referenced to the

V

REF

pin, allowing the user to set the reference voltage by

setting this voltage with a DC voltage source or other low

impedance voltage source as described in the “Connecting

high−side

switch

the V

Pin” section.

V

S

= 5 V

REF

For unidirectional sensing, the IN+ pin of the NCS7041

should be connected to the high side of the sense resistor,

while the IN− pin should be connected to the low side of the

sense resistor. When no current is flowing though the

NCS7041

load

V_S

OUT

A1

+

+IN

−

sense

resistor

R , the NCS7041 output is expected to be close to

SHUNT

A2

−IN

ground. When current is flowing through R

the

SHUNT,

V

REF

=

output will swing positive, up to within the specified voltage

GND

V _REF

2.5 V

optional

filtering

drop from the applied supply voltage, V .

S

For bidirectional current sensing, typically V

is set to

REF

mid−supply. The shunt resistor can be connected to the IN+

and IN− pins in direction depending on the preferred polarity

of the output. When there no current being measured, the

Figure 27. Low−side Current Sensing

output voltage will be at the V

voltage.

REF

Although certain applications require low−side sensing,

only high−side sensing can detect a short from the positive

supply line to ground. Furthermore, high−side sensing

avoids adding resistance to the ground path of the load being

measured. The sections below focus primarily on high−side

current sensing. Figure 28 shows the NCS7041 configured

for high−side current sensing.

V_OUT+ (V_)IN* V_*IN) G ) V_REF

(eq. 1)

In bidirectional current sensing with V

mid−supply, the output will be at the V

set to

REF

voltage when no

REF

current is flowing through R

. When current flows

SHUNT

from the IN+ to IN− terminal, the output will swing towards

the V supply. When current flows in the other direction

S

from IN− to IN+, the output will swing towards GND.

V

S

= 5 V

NCS7041

Power Supplies

V_S

OUT

A1

The NCS7041 can be connected to the same power supply

that it is monitoring current from, or it can be connected to

a separate power supply. If it is necessary to detect short

circuit current on the load power supply, which may cause

the load power supply to sag to near zero volts, a separate

power supply must be used on the NCS7041. When using

multiple supplies, there are no restrictions on power supply

sequencing.

+IN

sense

resistor

A2

−IN

+

−

load

GND

V_REF

V

=

REF

2.5 V

low−side

switch

optional

filtering

Connecting the V_REFPin

In bidirectional current sensing, the current measurements

are taken when current is flowing in both directions. For

example, in fuel gauging, the current is measured when the

Figure 28. High−side Current Sensing

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10

NCS7041, NCV7041

battery is being charged or discharged. Bidirectional

operation requires the output to swing both positive and

negative around a bias voltage applied to the V pin. The

pin to provide a voltage reference to the NCS7041. The

pin must always be connected to a low impedance

circuit. If a resistor divider network is used to provide the

reference voltage, a unity gain buffer circuit must be used,

V

REF

voltage applied to the V

pin depends on the application.

REF

However, most often it is biased to either half of the supply

voltage or to half the value of the measurement system

reference.

as shown in Figure 29 (a). The V

directly to any voltage supply or voltage reference (shunt or

series).

pin can be connected

REF

Figure 29 shows bidirectional operation with two

different circuit choices that can be connected to the V

REF

V_REF

+

V_REF

−

(a)

(b)

Figure 29. Voltage sources for V_REFmust be low impedance. If using a resistor divider, the output must be

buffered as shown in (a). Alternatively, a Zener diode or voltage reference may be used to set the V_REFvoltage as

shown in (b).

In bidirectional applications, any voltage that exceeds V

S

Preamplifier

Gain = 7, 10, 20, 50

Buffer

Gain = 2

+ 0.3 V applied to the V

pin will forward bias an ESD

REF

diode between the V

pin and the V pin. Note that this

REF

S

exceeds the Absolute Maximum Ratings for the device.

+IN

+

OUT

A1 and A2 Pins

−IN

−

A1 is the preamplifier output and the A2 is the buffer

input. These pins can be used to make adjustments to the

gain or to create a low−pass filter. The output of the

preamplifier integrates a precision resistor of 100 kW 2%,

which can be utilized for either of these purposes.

The high impedances at the A1 and A2 pins make this

connection particularly sensitive, and a careful layout is

necessary if the high frequency response is required. Trace

lengths should be kept at a minimum and test points should

be avoided when possible at these pins. Even a small

capacitance of 20 pF from the PCB can lower the −3dB

signal bandwidth to 80 kHz. This filtering effect is useful for

decreasing noise, and is further discussed in the upcoming

”Filtering with A1 and A2” section.

100 kW

A2

A1

V

REF

R

EXT

Figure 30. Lowering the Gain Using an External

Resistor

The adjusted overall decreased gain, G

factor of the total gain, G, and the external resistor, R

, becomes a

ADJ−

EXT.

G R_EXT

G_ADJ

+

(eq. 2)

R

_EXT) 100 kW

Lowering the Gain with A1 and A2

This equation can be rearranged to calculate the external

resistor value for the desired gain value.

The gain can be lowered by using the A1 and A2 pins.

Connecting A1 to A2 and adding a resistor from this net to

REF creates a resistor divider network in combination with

the internal 100 kW resistor, as shown by Figure 30. For

example, adding an external 100 kW resistor, reduces the

voltage going into A2 by half, reducing the overall gain by

half.

100 kW G_ADJ*

+

R_EXT

(eq. 3)

G * G_ADJ*

www.onsemi.com

11

NCS7041, NCV7041

Increasing the Gain with A1 and A2

The gain can be increased by adding an external resistor

in positive feedback as shown in Figure 31.

Preamplifier

Gain = 7, 10, 20, 50

Buffer

Gain = 2

+IN

+

OUT

Preamplifier

Gain = 7, 10, 20, 50

Buffer

Gain = 2

−IN

−

100 kW

+

+IN

OUT

A2

A1

−IN

−

R_EXT

100 kW

C₁

A2

A1

C₂

R_EXT

Figure 33. Implementing a Two−pole, Low−pass

Filter Using the Sallen−Key Topology

Figure 31. Increasing the Gain Using an External

Resistor in Positive Feedback

G R_EXT

Input Filtering

G_ADJ

+

(eq. 4)

R

_EXT* 100 kW

Some applications may require filtering at the input of the

current sense amplifier. Figure 34 shows the recommended

schematic for input filtering. Possible reasons for adding

input filtering include the elimination of noise before it

enters the current sense signal path or counteracting shunt

inductance effects.

Filtering with A1 and A2

In some applications, the current being measured may be

inherently noisy. A low−pass filter can be created by

connecting A1 and A2 together and adding a capacitor from

the net to GND as shown in Figure 32. This creates a simple

RC filter with the internal 100 kW resistor. This single pole

filter has a 20 dB/decade attenuation.

V_S

NCS7041

R

FILT

V_S

10 W

OUT

Preamplifier

Gain = 7, 10, 20, 50

Buffer

Gain = 2

+IN

A1

R

C

FILT

0.25 mF

SHUNT

A2

−IN

200 mW

1 nH

+IN

+

V_REF

GND

OUT

−IN

−

R

FILT

10 W

V_REF

100 kW

Figure 34. Input Filtering Compensates for Shunt

Inductance on Shunts Less than 1 mW, as Well as

High Frequency Noise in Any Application

A2

A1

C _FILT

Input filtering is complicated by the fact that the added

resistance of the filter resistors and the associated resistance

mismatch between them can adversely affect gain, CMRR,

Figure 32. Implementing a Single−pole, Low−pass

and V . The effect on V is partly due to input bias

RC Filter

OS

currents as well. As a result, the value of the input resistors

should be limited to 10 W or less.

1

f_FILT

+

As the shunt resistors decrease in value, shunt inductance

can significantly affect frequency response. At values below

1 mW, the shunt inductance causes a zero in the transfer

function that often results in corner frequencies in the low

100’s of kHz. This inductance increases the amplitude of

high frequency spike transient events on the current sensing

line that can overload the front end of any shunt current

sensing IC. This problem must be solved by filtering at the

(eq. 5)

2 p (100 kW) C_FILT

A two−pole filter with 40 dB/decade attenuation can be

created with a Sallen−Key topology as shown in Figure 33.

www.onsemi.com

12

NCS7041, NCV7041

input of the amplifier. Note that all current sensing IC’s are

common−mode noise often present even in low−side current

sensing. Providing all of this in a tiny package makes it very

competitive when compared to discrete op amp solutions.

vulnerable to this problem, regardless of manufacturer

claims. Filtering is required at the input of the device to

resolve this problem, even if the spike frequencies are above

the rated bandwidth of the device.

Ideally, select the capacitor to exactly match the time

constant of the shunt resistor and its inductance;

alternatively, select the capacitor to provide a pole below

that point. Make the input filter time constant equal to or

larger than the shunt and its inductance time constant:

Selecting the Shunt Resistor

The desired accuracy of the current measurement

determines the precision, shunt size, and the resistor value.

The larger the resistor value, the more accurate the

measurement possible, but a large resistor value also results

in greater current loss.

For the most accurate measurements, use four terminal

current sense resistors. It provides two terminals for the

current path in the application circuit, and a second pair for

the voltage detection path of the sense amplifier. This

technique is also known as Kelvin Sensing. This insures that

the voltage measured by the sense amplifier is the actual

voltage across the resistor and does not include the small

resistance of a combined connection. When using

non−Kelvin shunts, follow manufacturer recommendations

on how to lay out the sensing traces closely.

L_SHUNT

≤ 2 R_FILTC_FILT

(eq. 6)

R_SHUNT

To determine the value of C

based on using 10 W

FILT

resistors for each R , the equation simplifies to:

FILT

L_SHUNT

C_FILT

≥

(eq. 7)

20 R_SHUNT

If the main purpose is to filter high frequency noise, the

capacitor should be increased to a value that provides the

desired filtering. The capacitor can have a low voltage

rating, but should have good high frequency characteristics.

As an example, a filtering frequency of 10 kHz would

require a 0.8 mF capacitor.

Shutting Down the NCS7041

While the NCS7041 does not provide a shutdown pin, a

simple MOSFET, power switch, or logic gate can be used to

switch off the power to the NCS7041 and eliminate the

quiescent current. Note that the shunt input pins will always

have a current flow via the input and feedback resistors. The

input pins support the rated common mode voltage even

when the NCS7041 does not have power applied. If the

1

f_FILT

+

(eq. 8)

2 p (2 R_FILT) C_FILT

Common Mode Voltage Step Response

Common mode voltage steps can induce a change in the

output voltage. Large common mode voltage steps with fast

slew rates can invoke transient voltage spikes on the output.

Note: Large common mode voltage steps with slow slew

rates can induce unwanted voltages on the output as well; see

Figures 8 to 11. Slower slew rate signals will have longer

settling times but smaller voltage spikes. Certain

applications that operate with large common mode input

voltage steps, including solenoid applications, require a

thorough evaluation of the output response during such

events.

There are a couple of methods to address this. The first is

to add a time delay to the measurement after a common

mode voltage step occurs, allowing the output to settle to the

final value. The measurement can also be filtered or

averaged; this can be done by adding a low−pass filter using

the A1 and A2 pins as described in the previous ”Filtering

with A1 and A2” section.

V

REF

pin is powered by a separate voltage source, the power

should be disconnected from V

as well.

REF

Layout

PCB layout is an important part of getting accurate

measurements in current sensing applications. Figure 35

shows an example recommended layout for the NCS7041.

External resistors are shown in dark blue, while external

capacitors are shown in yellow. Bypass capacitors are shown

on the V and V

pins.

S

REF

The large component shown at the top is the sense resistor.

Note how the traces are routed from the center of each

resistor pad, and symmetry is maintained between the +IN

and −IN paths. This is the typical connection recommended

for a sense resistor, but refer to the sense resistor

manufacturer’s guidelines. Maintaining symmetric input

traces reduces PCB−induced offsets. The optional common

mode input filter is shown here, and these components are

placed symmetrically also.

At the A1 and A2 pins, an optional filter capacitor and gain

decreasing resistor are shown. Due to the sensitivity of the

high impedance A1 and A2 pins, a keep−out area around

these pins and surrounding components will reduce parasitic

capacitance. For more details, refer to the previous sections

for filtering and adjusting the gain at the A1 and A2 pins.

The ac response to disturbances in the common mode

voltage is quantified to a certain degree in the CMRR vs.

Frequency graph in Figure 7.

Advantages When Used For Low−Side Current Sensing

The NCS7041 series offers many advantages for low−side

current sensing. The true differential input is ideal for

connection to either Kelvin Sensing shunts or conventional

shunts. Additionally, the true differential input rejects the

www.onsemi.com

13

NCS7041, NCV7041

LOAD

SUPPLY

GND

VIA

GND

VIA

GND

VIA

Input Filter

RC

1

2

3

4

+IN

V^REF

8

7

6

5

−IN

(Optional)

GND

VIA

GND

VS

A1

A2

Gain

Adjust

OUT

Resistor

GND

VIA

(Optional)

Filter

Capacitor

VREF

(Optional)

L2

Ground

Plane

Clear

Ground

Plane

GND

VIA

Figure 35. Example Layout for Filtering and Gain Adjustment

www.onsemi.com

14

NCS7041, NCV7041

ORDERING INFORMATION

Device

†

Marking

Package

Gain

Shipping

INDUSTRIAL AND COMMERCIAL

NCS7041D3G014R2G*

NCS7041DM3G014R2G

NCS7041D3G020R2G

NCS7041DM3G020R2G

NCS7041D3G050R2G

NCS7041DM3G050R2G

NCS7041D3G100R2G

NCS7041DM3G100R2G

7041014

SOIC−8

14

2500 / Tape & Reel

4000 / Tape & Reel

2500 / Tape & Reel

4000 / Tape & Reel

2500 / Tape & Reel

4000 / Tape & Reel

2500 / Tape & Reel

4000 / Tape & Reel

(Pb−Free)

4114

7041020

4120

Micro8

(Pb−Free)

SOIC−8

(Pb−Free)

20

50

Micro8

(Pb−Free)

7041050

4150

SOIC−8

(Pb−Free)

Micro8

(Pb−Free)

7041100

4100

SOIC−8

(Pb−Free)

100

Micro8

(Pb−Free)

AUTOMOTIVE

NCV7041D3G014R2G*

704014

4114

SOIC−8

14

20

2500 / Tape & Reel

4000 / Tape & Reel

2500 / Tape & Reel

4000 / Tape & Reel

2500 / Tape & Reel

4000 / Tape & Reel

2500 / Tape & Reel

4000 / Tape & Reel

(Pb−Free)

NCV7041DM3G014R2G

NCV7041D3G020R2G

NCV7041DM3G020R2G

NCV7041D3G050R2G

NCV7041DM3G050R2G

NCV7041D3G100R2G

NCV7041DM3G100R2G

Micro8

(Pb−Free)

7041020

4120

SOIC−8

(Pb−Free)

Micro8

(Pb−Free)

7041050

4150

SOIC−8

(Pb−Free)

50

Micro8

(Pb−Free)

7041100

4100

SOIC−8

(Pb−Free)

100

Micro8

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*In development. Contact local sales office for more information.

www.onsemi.com

15

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AK

8

1

DATE 16 FEB 2011

SCALE 1:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

−X−

A

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

8

5

4

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

S

M

Y

B

0.25 (0.010)

1

K

−Y−

MILLIMETERS

DIM MIN MAX

INCHES

G

MIN

MAX

0.197

0.157

0.069

0.020

A

B

C

D

G

H

J

K

M

N

S

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

C

N X 45

_

SEATING

PLANE

1.27 BSC

0.050 BSC

−Z−

0.10

0.19

0.40

0

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

8

0.020

0.244

0.10 (0.004)

M

J

H

D

8

0

_

0.25

5.80

0.50 0.010

6.20 0.228

M

S

X

0.25 (0.010)

Z

Y

GENERIC

MARKING DIAGRAM*

SOLDERING FOOTPRINT*

8

1

8

1

8

XXXXX

ALYWX

XXXXXX

AYWW

G

XXXXX

ALYWX

XXXXXX

AYWW

1.52

0.060

G

1

Discrete

(Pb−Free)

IC

(Pb−Free)

7.0

0.275

4.0

0.155

XXXXX = Specific Device Code

XXXXXX = Specific Device Code

A

L

= Assembly Location

= Wafer Lot

A

= Assembly Location

= Year

Y

W

G

= Year

= Work Week

= Pb−Free Package

WW

G

= Work Week

= Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

0.6

0.024

1.270

0.050

mm

inches

ǒ

Ǔ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASB42564B

SOIC−8 NB

PAGE 1 OF 2

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

STYLE 1:

STYLE 2:

STYLE 3:

STYLE 4:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

6. EMITTER, #2

7. BASE, #1

6. SOURCE, #2

7. GATE, #1

7. BASE

8. EMITTER

8. EMITTER, #1

8. SOURCE, #1

8. COMMON CATHODE

STYLE 5:

STYLE 6:

PIN 1. SOURCE

2. DRAIN

STYLE 7:

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

3. DRAIN

3. BASE, #2

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

6. GATE

7. SOURCE

8. SOURCE

STYLE 9:

STYLE 10:

PIN 1. GROUND

2. BIAS 1

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

STYLE 12:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

STYLE 15:

PIN 1. ANODE 1

2. ANODE 1

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

STYLE 18:

STYLE 19:

PIN 1. SOURCE 1

2. GATE 1

STYLE 20:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

5. RXE

6. VEE

7. GND

8. ACC

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 21:

STYLE 22:

STYLE 23:

STYLE 24:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

PIN 1. I/O LINE 1

PIN 1. LINE 1 IN

PIN 1. BASE

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 25:

PIN 1. VIN

2. N/C

STYLE 26:

PIN 1. GND

2. dv/dt

STYLE 27:

PIN 1. ILIMIT

2. OVLO

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

5. V_MON

6. VBULK

7. VBULK

8. VIN

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASB42564B

SOIC−8 NB

PAGE 2 OF 2

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

Micro8

CASE 846A−02

ISSUE K

DATE 16 JUL 2020

SCALE 2:1

GENERIC

MARKING DIAGRAM*

8

XXXX

AYWG

G

1

XXXX = Specific Device Code

A

Y

W

G

= Assembly Location

= Year

= Work Week

= Pb−Free Package

STYLE 1:

STYLE 2:

PIN 1. SOURCE 1

STYLE 3:

PIN 1. SOURCE

PIN 1. N-SOURCE

2. N-GATE

(Note: Microdot may be in either location)

2. SOURCE

3. SOURCE

4. GATE

2. GATE 1

3. SOURCE 2

4. GATE 2

3. P-SOURCE

4. P-GATE

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

5. P-DRAIN

6. P-DRAIN

7. N-DRAIN

8. N-DRAIN

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASB14087C

MICRO8

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	NCS7041D3G050R2G
厂家：	ONSEMI
描述：	Current Sense Amplifier, 80V Common-Mode Voltage, Bidirectional
文件：	总19页 (文件大小：716K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCS7041D3G050R2G [ONSEMI]

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