NCV-RSL10-101Q48-AVG

DATA SHEET

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Bluetooth⁾5.2 Radio

System-on-Chip (SoC) for

Automotive

1

48

QFNW48

CASE 512AD

NCV-RSL10

Introduction

A member of the RSL10 product family, NCV−RSL10 brings the

industry’s lowest power Bluetooth Low Energy technology to the

automotive industry. NCV−RSL10 helps enable advanced new

functionality including keyless entry using a fob or smartphone, active

safety and diagnostic alerts, and enhanced infotainment controls while

maximizing energy efficiency.

MARKING DIAGRAM

RSL10

AWLYYWWG

The Bluetooth 5.2 certified radio SoC supports 2 Mbps data rates,

twice the speed possible with previous Bluetooth generations.

Specially designed and qualified for the unique needs of automotive,

NCV−RSL10 features built−in data encryption, wettable flank−plated

packaging, and a higher operating temperature range.

(QFNW48)

A

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G

= Pb−Free Package

Key Features

• Automotive Ready

♦ AEC−Q100 Grade 2, ETSI, FCC Qualified

♦ Operating Temperature Range (−40°C to +105°C)

• Advanced Wireless Functionality

ORDERING INFORMATION

†

Device

Package

Shipping

♦ Bluetooth 5.2 certified with LE 2−Mbit PHY (High Speed), as

well as backwards compatibility and support for earlier Bluetooth

Low Energy specifications

NCV−RSL10−

101Q48−AVG

QFNW48

(Pb−Free)

3000 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

♦ Transmitting Power: −17 dBm to +6 dBm

♦ Rx Sensitivity (Bluetooth Low Energy Mode, 1 Mbps): −94 dBm

• Enhanced Security

♦ Built−in AES128 encryption accelerator

• Industry’s Lowest Power Consumption

♦ Tx peak (PHY) @ 0 dBm: 4.3 mA (3.3 V Supply)

♦ Rx peak (PHY): 2.7 mA (3.3 V Supply)

♦ Deep Sleep, I/O Wake−up (3.3 V Supply): 25 nA

♦ Deep Sleep, Active External 32 kHz oscillator (3.3 V Supply): 40 nA

• Reliable Assembly

♦ Wettable flank−plated QFNW48, 7x7 mm package

• Highly−Integrated System−on−Chip (SoC)

♦ 384 kB of Flash Memory

♦ Flexible Dual−Core architecture (Arm(R) Cortex−M3 processor,

32−bit DSP)

Other Specifications

• Data Rate: 62.5 to 2000 kpbs

• Flexible Supply Voltage Range (1.1−3.3 V)

• Supports Firmware Over−The−Air (FOTA) updates

1

Publication Order Number:

January, 2022 − Rev. 2

NCV−RSL10/D

NCV−RSL10

FEATURES

• Arm Cortex−M3 Processor: A 32−bit core for

• Standby Mode: Can be used to reduce the average

power consumption for off−duty cycle operation,

ranging typically from a few ms to a few hundreds of

ms. The typical chip power consumption is 30 mA in

Standby Mode.

real−time applications, specifically developed to enable

high−performance low−cost platforms for a broad range

of low−power applications.

• LPDSP32: A 32−bit Dual Harvard DSP core that

efficiently supports custom crypto graphic algorithms

or other signal processing that require significant

number crunching.

• Radio Frequency Front−End: Based on a 2.4 GHz RF

transceiver, the RFFE implements the physical layer of

the Bluetooth Low Energy technology standard and

other proprietary or custom protocols.

• Multi−Protocol Support: Using the flexibility

provided by LPDSP32, the Arm Cortex−M3 processor,

and the RF front−end; proprietary protocols and other

custom protocols are supported.

• Flexible Supply Voltage: RSL10 integrates high−

efficiency power regulators and has a VBAT range of

1.1 to 3.3 V.

2

• Protocol Baseband Hardware: Bluetooth 5.2 certified

and includes support for a 2 Mbps RF link and custom

protocol options. The RSL10 baseband stack is

supplemented by support structures that enable

implementation of onsemi and customer designed

custom protocols.

• Highly Configurable Interfaces: I C, UART, two SPI

interfaces, PCM interface, multiple GPIOs.

• Flexible Clocking Scheme: RSL10 must be clocked

from the XTAL/PLL of the radio front−end at 48 MHz

when transmitting or receiving RF traffic. When RSL10

is not transmitting/receiving RF traffic, it can run off

the 48 MHz XTAL, the internal RC oscillators, the

32 kHz oscillator, or an external clock. A low

• Highly−Integrated SoC: The dual−core architecture is

complemented by high−efficiency power management

units, oscillators, flash and RAM memories, a DMA

controller, along with a full complement of peripherals

and interfaces.

frequency RTC clock at 32 kHz can also be used in

Deep Sleep Mode. It can be sourced from either the

internal XTAL, the RC oscillator, or a digital input pad.

• Deep Sleep Mode: RSL10 can be put into a Deep

Sleep Mode when no operations are required. Various

Deep Sleep Mode configurations are available,

including:

• Diverse Memory Architecture: 76 kB of SRAM

program memory (4 kB of which is PROM containing

the chip boot−up program, and is thus unavailable to

the user) and 88 kB of SRAM data memory are

available. A total of 384 kB of flash is available to store

the Bluetooth stack and other applications. The Arm

Cortex−M3 processor can execute from SRAM and/or

flash.

♦ “IO wake−up” configuration. The power

consumption in deep sleep mode is 25 nA (3.3 V

VBAT).

♦ Embedded 32 kHz oscillator running with interrupts

from timer or external pin. The total current drain is

40 nA (3.3 V VBAT).

♦ As above with 8 kB RAM data retention. The total

current drain is 150 nA (3.3 V VBAT).

♦ The DC−DC converter can be used in either buck

mode or LDO mode during Sleep Mode, depending

on VBAT voltage.

• Security: AES128 encryption hardware block for

custom secure algorithms and code protection with

authenticated debug port access (JTAG ‘lock’)

• RoHS Compliant device

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2

NCV−RSL10

RSL10 INTERNAL BLOCK DIAGRAM

The block diagram of the RSL10 chip is shown in Figure 1.

Figure 1. RSL10 Block Diagram

Table 1. ABSOLUTE MAXIMUM RATINGS

Symbol

VBAT

Parameter

Min

Max

3.63

Unit

V

Power supply voltage

I/O supply voltage

VDDO

VSSRF

VSSA

V

RF front−end ground

−0.3

V

Analog ground

V

VSSD

Vin

Digital core and I/O ground

Voltage at any input pin

Storage temperature range (Note 2)

−0.3

V

VSSD−0.3

−40

VDDC + 0.3 (Note 1)

150

V

T storage

°C

Caution: ESD Classification Class C3 per AEC−Q100−011 Rev−C1.

The QFN package meets 250 V CDM level

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Up to a maximum of 3.63 V.

2. Applies after soldering to PCB.

Table 2. RECOMMENDED OPERATING CONDITIONS

Description

Symbol

VBAT

Conditions

Min

1.18

−40

Typ

Max

Units

V

Supply voltage operating range

Functional temperature range

Input supply voltage on VBAT pin (Note 4)

1.25

3.3

T functional

105

(Note 3)

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

3. For functional operation at greater than 85°C, the following trimming parameters must be used:

− VDDMRET_VTRIM = 0x3

− VDDTRET_VTRIM = 0x3

− VDDCRET_VTRIM = 0x3

4. In order to be able to use a VBAT Min of 1.1 V, the following reduced operating conditions should be observed:

− Maximum Tx power 0 dBm.

− SYSCLK ≤ 24 MHz.

− Functional temperature range limited to 0−50 °C

The following trimming parameters should be used:

− VCC = 1.10 V

− VDDC = 0.92 V

− VDDM = 1.05 V, will be limited by VCC at end of battery life

− VDDRF = 1.05 V, will be limited by VCC at end of battery life. VDDPA should be disabled

RSL10 should enter in end−of−battery−life operating mode if VCC falls below 1.03 V. VCC will remain above 1.03 V if VBAT ≥ 1.10 V under

the restricted operating conditions described above.

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3

NCV−RSL10

Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 3 V in DC−DC (buck) mode.

Description

Symbol

Conditions

Min

Typ

Max

Units

OVERALL

Current consumption RX,

I

0.9

25

mA

nA

VBAT

V

BAT

= 3 V

Current consumption TX,

= 3 V

VBAT

V

BAT

Deep sleep current,

example 1, V = 3 V

Ids1

Ids2

Wake up from wake up pin or DIO

wake up.

BAT

Deep sleep current,

example 2, V = 3 V

Embedded 32 kHz oscillator running

with interrupts from timer or external

pin.

40

nA

BAT

Deep sleep current,

example 3, V = 3 V

Ids3

Istb

As Ids2 but with 8 kB RAM data

retention.

100

17

nA

BAT

Standby Mode current,

= 3 V

Digital blocks and memories are not

clocked and are powered at a reduced

voltage.

mA

V

BAT

EEMBC ULPMark BENCHMARK, CORE PROFILE

ULPMark CP 3.0 V

Arm Cortex−M3 processor running

from RAM, VBAT= 3.0 V, IAR C/C++

Compiler for ARM 8.20.1.14183

1090

1260

ULP

Mark

ULPMark CP 2.1 V

Arm Cortex−M3 processor running

from RAM, VBAT= 2.1 V, IAR C/C++

Compiler for ARM 8.20.1.14183

ULP

Mark

EEMBC CoreMark BENCHMARK for the Arm Cortex−M3 Processor and the LPDSP32 DSP

Arm Cortex−M3 processor

running from RAM

At 48 MHz SYSCLK. Using the IAR

8.10.1 C compiler, certified

159

174

Core

Mark

LPDSP32 running from RAM

At 48 MHz SYSCLK

Using the 2020.03 release of

the Synopsys LPDSP32 C compiler

Core

Mark

Arm Cortex−M3 processor and

LPDSP32 running from RAM,

VBAT = 3 V

At 48 MHz SYSCLK

284

12.3

14.6

8.2

Core

Mark/

mA

Arm Cortex−M3 processor

running CoreMark from RAM,

VBAT = 3 V

At 48 MHz SYSCLK (processor

consumption only)

mA/MHz

Arm Cortex−M3 processor

running CoreMark from Flash,

VBAT = 3 V

At 48 MHz SYSCLK (processor

consumption only)

LPDSP32 running CoreMark

from RAM, VBAT = 3 V

At 48 MHz SYSCLK (processor

consumption only)

INTERNALLY GENERATED VDDC: Digital Block Supply Voltage

Supply voltage: operating range

VDDC

0.92

0.75

1.15

1.32

(Note 5)

V

Supply voltage: trimming range

Supply voltage: trimming step

VDDC

1.38

V

RANGE

VDDC

10

mV

STEP

INTERNALLY GENERATED VDDM: Memories Supply Voltage

Supply voltage: operating range

VDDM

1.05

0.75

1.15

1.32

(Note 6)

V

Supply voltage: trimming range

Supply voltage: trimming step

VDDM

1.38

V

RANGE

VDDM

10

mV

STEP

INTERNALLY GENERATED VDDRF: Radio Front end supply voltage

Supply voltage: operating range

VDDRF

1.00

0.75

1.10

1.32 (Notes

7 and 8)

V

Supply voltage: trimming range

VDDRF

1.38

RANGE

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4

NCV−RSL10

Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 3 V in DC−DC (buck) mode.

Description

INTERNALLY GENERATED VDDRF: Radio Front end supply voltage

Supply voltage: trimming step VDDRF

INTERNALLY GENERATED VDDPA: Optional Radio Power Amplifier Supply Voltage

Symbol

Conditions

Min

Typ

Max

Units

10

mV

STEP

Supply voltage: operating range

Supply voltage: trimming range

Supply voltage: trimming step

VDDPA

1.05

1.3

1.68

V

RANGE

VDDPA

10

mV

STEP

DCDC

VDDO PAD SUPPLY VOLTAGE: Digital Level High Voltage

Digital I/O supply VDDO

INDUCTIVE BUCK DC−DC CONVERTER

1.1

3.3

V

VBAT range when the DC−DC

converter is active (Note 9)

DCDC

IN_RANGE

1.4

1.1

3.3

V

VBAT range when the LDO is

active

LDO

IN_RANGE

Output voltage: trimming range

DCDC

OUT_RANGE

1.2

10

1.32

V

Supply voltage: trimming step

POWER−ON RESET

POR voltage

DCDC

mV

STEP

POR

VBAT

0.4

0.8

50

1.0

V

RADIO FRONT−END: General Specifications

RF input impedance

Input reflection coefficient

Data rate FSK / MSK / GFSK

Data rate 4−FSK

Z

in

Single ended

All channels

W

S

11

−8

dB

R

OQPSK as MSK

62.5

250

1000

3000

4000

2000

kbps

FSK

On−air data rate

bps

GFSK

RADIO FRONT−END: Crystal and Clock Specifications

Xtal frequency

F

XTAL

Fundamental

48

MHz

Equiv. series Res.

ESR

RSL10 has internal load capacitors,

additional external capacitors are not

required

20

6

80

10

W

XTAL

Differential equivalent load

capacitance

CL

Internal load capacitors

(NO EXTERNAL LOAD

CAPACITORS REQUIRED)

8

pF

XTAL

Settling time

0.5

1.5

ms

RADIO FRONT−END: Synthesizer Specifications

Frequency range

RX frequency step

F

RF

Supported carrier frequencies

2360

2500

100

MHz

Hz

RX Mode frequency synthesizer

resolution

TX frequency step

TX Mode frequency synthesizer

resolution

600

Hz

PLL Settling time, RX

PLL Settling time, TX

t

RX Mode

15

5

25

10

ms

PLL_RX

t

TX mode, BLE modulation

PLL_TX

RADIO FRONT−END: Receive Mode Specifications

Current consumption at 1 Mbps,

= 3 V, DC−DC

IBAT

VDDRF = 1.1 V, 100% duty cycle

0.1% BER (Notes 10, 11)

3.0

3.4

−97

mA

RFRX

V

BAT

Current consumption at 2 Mbps,

= 3 V, DC−DC

IBAT

RFRX

V

BAT

RX Sensitivity, 0.25 Mbps

dBm

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NCV−RSL10

Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 3 V in DC−DC (buck) mode.

Description

Symbol

Conditions

Min

Typ

Max

Units

RADIO FRONT−END: Receive Mode Specifications

RX Sensitivity, 0.5 Mbps

0.1% BER (Notes 10, 11)

−96

−94

dBm

RX Sensitivity, 1 Mbps, BLE

0.1% BER (Notes 10, 11) Single−end-

ed on chip antenna match to 50 W

RX Sensitivity, 2 Mbps, BLE

RSSI effective range

0.1% BER (Notes 10, 11)

Without AGC

−92

60

dBm

dB

RSSI step size

2.4

48

dB

RX AGC range

dB

RX AGC step size

Programmable

0.1% BER

6

dB

Max usable signal level

RADIO FRONT−END: Transmit Mode Specifications

−10

dBm

Tx peak power consumption at

VBAT = 3 V (Note 12)

IBAT

Tx power 0 dBm, VDDRF = 1.07 V,

VDDPA: off, DC−DC mode

4.6

8.6

12

mA

RFTX

Tx power 3 dBm, VDDRF = 1.1 V,

VDDPA = 1.26 V, DC−DC mode

Tx power 6 dBm, VDDRF = 1.1 V,

VDDPA = 1.60 V, DC−DC mode

mA

Transmit power range

BLE

−17

+6

(Note 15)

dBm

Transmit power step size

Transmit power accuracy

Full band.

1

dB

Tx power 3 dBm. Full band. Relative

to the typical value.

−1.5

+1

Tx power 0 dBm. Full band. Relative

to the typical value.

1.5

dB

nd

Power in 2 harmonic

0 dBm mode. 50 W for “Typ” value.

(Note 14)

−31

−40

−49

−18

−31

−42

dBm

rd

Power in 3 harmonic

0 dBm mode. 50 W for “Typ” value.

(Note 14)

th

Power in 4 harmonic

0 dBm mode. 50 W for “Typ” value.

(Note 14)

ADC

Resolution

ADC

8

0

12

14

2

bits

V

RES

Input voltage range

ADC

RANGE

INL

ADC

−2

+2

mV

kHz

INL

DNL

ADC

−1

+1

Channel sampling frequency

ADC

For the 8 channels sequentially,

SLOWCLK = 1 MHz

0.0195

6.25

CH_SF

32 kHz ON−CHIP RC OSCILLATOR

Untrimmed Frequency

Trimming steps

Freq

20

2

32

50

5

kHz

%

UNTR

Steps

1.5

3 MHz ON−CHIP RC OSCILLATOR

Untrimmed Frequency

Trimming steps

Freq

3

MHz

%

UNTR

Steps

Fhi

1.5

10

Hi Speed mode

MHz

32 kHz ON−CHIP CRYSTAL OSCILLATOR (Note 16)

Output Frequency

Startup time

Freq

Depends on xtal parameters

Steps of 0.4 pF

32768

1

Hz

s

32k

3

Internal load trimming range

0

25.2

pF

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NCV−RSL10

Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 3 V in DC−DC (buck) mode.

Description

Symbol

Conditions

Min

Typ

Max

Units

32 kHz ON−CHIP CRYSTAL OSCILLATOR (Note 16)

Load Capacitance

No external load capacitors required.

Maximum external parasitic capacity

allowed (package, routing, etc.)

3.5

pF

ESR

100

60

kW

Duty Cycle

40

50

%

DC INPUT CHARACTERISTICS OF THE DIGITAL PADS − With VDDO = 2.97 V – 3.3 V, nominal: 3.0 V Logic

Voltage level for high input

Voltage level for low input

V

2

VDDO+0.3

0.8

V

IH

V

VSSD−

0.3

IL

DC OUTPUT CHARACTERISTICS OF THE DIGITAL PADS

Voltage level for high input

V

I

= 2 mA to 12 mA

VDDO−

0.4

V

OH

Voltage level for low input

DIO DRIVE STRENGTH

DIO drive strength

V

I

= 2 mA to 12 mA

0.4

12

OL

OH

IDIO

2

12

mA

FLASH SPECIFICATIONS

Endurance of the 384 kB of flash

40,000

write/

erase

cycles

Endurance for sections NVR1,

NVR2, and NVR3 (6 kB in total)

1000

25

write/

erase

cycles

Retention

years

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. The maximum VDDC voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.

6. The maximum VDDM voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.

7. The maximum VDDRF voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.

8. The VDDRF calibrated targets are:

− 1.10 V (TX power > 0 dBm, with optimal RX sensitivity)

− 1.07 V (TX power = 0 dBm)

− 1.20 V (TX power = 2 dBm)

The VDDPA calibrated targets are:

− 1.30 V

− 1.26 V (TX power = 3 dBm, assumes VDDRF = 1.10 V)

− 1.60 V (TX power = 6 dBm, assumes VDDRF = 1.10 V)

9. The LDO can be used to regulate down from VBAT and generate VCC. For VBAT values higher than 1.5 V, the LDO is less efficient and it

is possible to save power by activating the DC−DC converter to generate VCC.

10.Signal generated by RF tester.

11. 0.5 to 1.0 dB degradation in the RX sensitivity is present on the QFN package. This is attributed to the presence of the metal slug of the QFN

package which is in close proximity to on−chip inductors.

12.All values are based on evaluation board performance at the antenna connector, including the harmonic filter loss

13.At +6 dBm Tx power, an antenna gain of +2.2 dBi or less must be used to ensure out−of−band regulatory emissions compliance

14.The values shown here are without RF filter. Harmonics need to be filtered with an external filter (See “RF Filter” on Table 6).

15.For optimal performance, charge pump frequency of 125 kHz should be avoided when VDDPA supply is enabled.

16.These specifications have been validated with the Epson Toyocom MC – 306 crystal

Table 4. VDDM Target Trimming Voltage as a Function of VDDO Voltage

VDDM Voltage (V)

DIO_PAD_CFG DRIVE

Maximum VDDO Voltage (V)

1.05

1.10

1

0

2.7

3.2

3.3

NOTE: These are trimming targets at room/ATE temperature 25X30°C.

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NCV−RSL10

Table 5. VDDC Target Trimming Voltage as a Function of SYSCLK Frequency

VDDC Voltage (V)

Maximum SYSCLK Frequency (MHz)

Restriction

0.92

≤ 24

The ADC will be functional in low frequency

mode and between 0 and 85°C only.

1.00

1.05

≤ 24

Fully functional

48

NOTE: These are trimming targets at room/ATE temperature 25X30°C.

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NCV−RSL10

Table 6. RECOMMENDED EXTERNAL COMPONENTS:

Components

Cap (VBAT−VSSA)

Cap (VDDO−VSSD)

Cap (VDDRF−VSSRF)

Cap (VCC−VSSA)

Cap (VDDA−VSSA)

Cap (CAP0−CAP1)

Inductor (DC−DC)

Xtal_32 kHz

Function

VBAT decoupling

Recommended typical value

Tolerance

20%

4.7 mF + 100 pF (Note 17)

VDDO decoupling

1 mF

20%

VDDRF decoupling

2.2 mF

20%

VCC decoupling

Low ESR 2.2 mF (Note 18) or 4.7 mF

20%

VDDA decoupling

1 mF

20%

Pump capacitor for the charge pump

DC−DC converter inductance

Xtal for 32 kHz oscillator

20%

Low ESR 2.2 mH (See Table 7 below)

20%

− MC – 306, Epson

− CM8V−T1A, Micro Crystal Switzerland

WMRAG32K76CS1C00R0, Murata

Xtal_48 MHz

Xtal for 48 MHz oscillator

External harmonic filter

8Q−48.000MEEV−T, TXC Corporation, Taiwan

XRCTD48M000NXQ2ER0, Murata

RF filter (Note 19)

1.5 pF / 3 nH / 1.5 pF / 1.8 nH

20%

NOTE: All capacitors used must have good RF performance.

17.The recommended decoupling capacitance uses 2 capacitors with the values specified.

18.Example: AMK105BJ225_P, Taiyo Yuden.

19.For improved harmonic performance in environments where RSL10 is operating in close proximity to smartphones or base stations, FBAR

filters such as the Broadcom ACPFP−7924 can be applied instead of the suggested discrete harmonic filter.

Table 7. RECOMMENDED DC−DC CONVERTER INDUCTANCE TABLE

Manufacturer

Part Number

Case Size

Comments

Taiyo Yuden

CKP2012N_2R2

0805 SMD with

A degradation of 1 dB in the RX sensitivity is expected in DC−DC mode

(Vbat = 3.3 V) versus LDO mode operation.

T

max

= 1.0 mm

Taiyo Yuden

CBMF1608T2R2M

0603 SMD with

= 1.0 mm

A degradation of <1 dB in RX sensitivity is expected in DC−DC mode

(Vbat = 3.3 V) versus LDO mode operation. Also, the current drawn from

the battery will be 4−10% higher than when the CKP2012N_2R2 is used

depending on operation mode and settings.

T

max

NOTE: Values have been measured on the QFN version of the RSL10 development board.

PCB Design Guidelines

1. Decoupling capacitors should be placed as close to the related pins as possible.

2. Differential output signals should be routed as symmetrically as possible.

3. Analog input signals should be shielded as well as possible.

4. Pay close attention to the parasitic coupling capacitors.

5. Special care should be made for PCB design in order to obtain good RF performance.

6. Multi−layer PCB should be used with a keep−out area on the inner layers directly below the antenna matching

circuitry in order to reduce the stray capacitances that influence RF performance.

7. All the supply voltages should be decoupled as close as possible to their respective pin with high performance RF

capacitors. These supplies should be routed separately from each other and if possible on different layers with short

lines on the PCB from the chip’s pin to the supply source.

8. Digital signals shouldn’t be routed close to the crystal or the power supply lines.

9. Proper DC−DC component placement and layout is critical to RX sensitivity performance in DC−DC mode.

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NCV−RSL10

2.2 uH

2.2 uF

1.4 - 3.6 V

4.7uF

100 pF

1uF

4.7uF

VSSD

VSSA

VSSD

Cpump

1uF

cap1

cap0

RF

3 nH

1.8 nH

1.5 pF

XTAL48_P

XTAL48_N

XTAL32k_IN

XTAL32k_OUT

RSL10

Figure 2. RSL10 Application Diagram in Buck Mode

1.25 V

4.7uF

100 pF

1uF

4.7uF

2.2 uF

1uF

VSSA

VSSD

VSSA

Cpump

1uF

cap1

cap0

RF

3 nH

1.8 nH

1.5 pF

XTAL48_P

XTAL48_N

XTAL32k_IN

XTAL32k_OUT

RSL10

NOTE: DC−DC inductance is not needed. RSL10

should be configured in LDO mode and the

DC−DC converter should not be used.

Figure 3. RSL10 Application Diagram in LDO Mode

www.onsemi.com

10

NCV−RSL10

Table 8. CHIP INTERFACE SPECIFICATIONS

Power

Domain

Pad #,

QFN48

Pad Name

VBAT

Description

I/O

I

A/D

P

Pull

Battery input voltage

VBAT

9

10

12

14

13

8

VDC

DC−DC output voltage to external LC filter

DC−DC filtered output

O

A

VCC

I

P/A

A

XTAL32_IN

XTAL32_OUT

VSSA

Xtal input pin for 32 kHz xtal

Xtal output pin for 32 kHz xtal

Analog ground

I/O

I

A

P

RES

RESERVED

D

11

5

VDDA

Charge pump output for analog and flash supplies

LDO’s output for radio voltage supply

Pump capacitor connection

Analog test pin

VDDA

VDDRF_SW

VDDPA

I/O

O

P/A

A

VDDRF

CAP0

48

7

CAP1

O

A

6

AOUT

O

A

4

VDDRF_SW

VDDSYN_SW

VSSRF

XTAL48_N

XTAL48_P

VDDPA

VSSPA

RF

Supply pin for the RF

P/A

P

47

45

46

43

44

2

Supply pin for the radio synthesizer

RF analog ground

I/O

Negative input for the 48 MHz xtal block

Positive input for the 48 MHz xtal block

Radio power amplifier voltage supply

Radio power amplifier ground

RF signal input/output (Antenna)

Flash high voltage access

A

P/A

P

3

RF

A

1

VPP

A

17

www.onsemi.com

11

NCV−RSL10

Table 8. CHIP INTERFACE SPECIFICATIONS

Power

Domain

Pad #,

QFN48

Pad Name

NRESET

WAKEUP

VDDC

Description

I/O

I

A/D

D

Pull

Reset pin

VDDO

U1

16

15

19

21

36

28, 35

42

31

18

20

23

25

24

27

29

30

26

22

32

38

37

39

41

40

33

34

Wake−up pin for power modes

LDO output for Core logic voltage supply

LDO output for memories voltage supply

Digital I/O voltage supply

I

A

I/O

I

P

VDDM

VDDO

P

VSSD

Digital ground pad for I/O

I/O

I

P

VSS (*)

EXTCLK

DIO[0]

Substrate connection for the RF part

External clock input

P

D

U

Digital input output / ADC 0 / Wakeup 0 / STANDBYCLK input

Digital input output / ADC 1 / Wakeup 1 / STANDBYCLK input

Digital input output / ADC 2 / Wakeup 2 / STANDBYCLK input

Digital input output / ADC 3 / Wakeup 3 / STANDBYCLK input

Digital input output 4

I/O

A/D

D

U/D

U

DIO[1]

DIO[2]

DIO[3]

DIO[4]

DIO[5]

Digital input output 5

D

DIO[6]

Digital input output 6

D

DIO[7]

Digital input output 7

D

DIO[8]

Digital input output 8

D

DIO[9]

Digital input output 9

D

DIO[10]

DIO[11]

DIO[12]

DIO[13]

DIO[14]

DIO[15]

JTCK

Digital input output 10

D

Digital input output 11

D

Digital input output 12

D

Digital input output / CM3−JTAG Test Reset

Digital input output / CM3−JTAG Test Data In

Digital input output / CM3−JTAG Test Data Out

CM3−JTAG Test Clock

D

JTMS

CM3−JTAG Test Mode State

D

U

*VSS should be connected to VSSRF at the PCB level.

NOTE: It is recommended that the QFN package metal slug be left open/floating for optimal Rx sensitivity performance

Legend:

Type: A = analog; D = digital; I = input; O = output; P = power

Pull: U = pull up; D = pull down

Pull up: selectable between 10 kW and 250 kW

Pull down: 250 kW

Pull resistor tolerance of 15%

All digital pads have a Schmitt trigger input.

2

All DIO pads have a programmable I C low pass filter.

www.onsemi.com

12

NCV−RSL10

ARCHITECTURE OVERVIEW

The architecture of the RSL10 chip is shown in Figure 4.

BB_DRAM0

8 KB

BB_DRAM1

8 KB

SPI interface

PBus

DSP_DRAM0

8 KB

DSP_DRAM1

8 KB

DSP_DRAM2

8 KB

DSP_DRAM3

8 KB

DSP_DRAM4

8 KB

DSP_DRAM5

8 KB

DSP_PRAM0

10 KB

DRAM0

8 KB

DSP_PRAM1

10 KB

DSP_PRAM2

10 KB

DRAM1

8 KB

DSP_PRAM3

10 KB

DRAM2

8 KB

DBus

CBus

IBus

Figure 4. RSL10 Architecture

www.onsemi.com

13

NCV−RSL10

Power Management Unit

Every clock generated in the system can be disabled when

they are not needed. Also, every clock has an associated

configurable prescaler to minimize the power dissipated on

the clock tree.

A clock detector unit can be used to monitor the system

clock and/or the RTC clock in sleep and standby modes. In

the event the clock frequency goes below a certain threshold,

the RSL10 IC will be reset. The clock detector threshold is

nominally 2 kHz. This block and the reset it triggers is

enabled by default, but both can be disabled.

The RSL10 power management unit allows for operation

across wide temperature and voltages ranges at low power

consumption and monitors the battery voltage to ensure

reliable operation. If the battery voltage dips below the

POWER−ON RESET (POR) voltage, a POR is asserted to

the system. This also prevents possible damage to RSL10

when the battery is inserted or removed.

RSL10 allows the use of either the DC−DC converter for

a better efficiency when the battery voltage is higher than

1.4 V or the internal LDO when VBAT is lower than 1.4 V.

The output of the DC−DC converter or the LDO regulator is

used to supply other voltage regulator blocks of RSL10.

These blocks are:

Radio Front−End

RSL10 2.4 GHz radio front−end implements the physical

layer for the Bluetooth Low Energy technology standard and

other standard, proprietary, and custom protocols. It

operates in the worldwide deployable 2.4 GHz ISM band

(2.4000 to 2.4835 GHz) and supports:

• Bluetooth 5.2 certified with LE 2M PHY support

The 2.4 GHz radio front−end is based on a low−IF

• A programmable voltage regulator to supply the digital

cores (VDDC)

• A programmable voltage regulator to supply the

memories (VDDM)

• A charge pump supplying the analog blocks and the

flash memory (VDDA)

• A programmable voltage regulator to supply the radio

front−end (VDDRF)

• A programmable voltage regulator to supply the power

amplifier of the radio (VDDPA): This regulator is used

only for the +6 dBm output power case or if we want to

transmit at +3 dBm output power with a battery level

less than 1.4 V. The VDDPA regulator can be disabled

if RSL10 doesn’t have to transmit at high power, and

VDDRF only should be used.

architecture and comprises the following building blocks:

• High performance single−ended RF port

• On−chip matching network with 50 ohm RF input

• High gain, low power LNA (low noise amplifier), and

mixer

• PA (Power Amplifier) with +3 dBm output power for

Bluetooth applications, and up to +6 dBm with

dedicated PA voltage supply

• ADC converter

• RSSI (Received Signal Strength Indication) with 60 dB

nominal range with 2.4 dB steps (not considering AGC)

• Fully integrated ultra−low power frequency synthesis

with fast settling time, with direct digital modulation in

transmission (pulse shape programmable)

Clock and Clocking Options

RSL10’s system clock (SYSCLK) can come from various

sources:

• A 48 MHz crystal oscillator, used in normal operation

mode

• 48 MHz XTAL reference (finely trimmable)

• Fully−integrated FSK−based modem with

programmable pulse shape, data rate, and modulation

index

• An internal trimmable RC oscillator that supplies a

3 MHz – 12 MHz clock used at system startup

• A Real Time Clock, used in stand−by mode, generated

• Digital baseband (DBB) with Link layer functionalities,

including automatic packet handling with preamble &

sync, CRC, and separate Rx and Tx 128−bytes FIFOs

• Serial and parallel digital interfaces

The 2.4 GHz radio front−end contains a full transceiver with

the following features:

from one of:

♦ A 32 kHz RC oscillator

♦ A 32 kHz crystal oscillator

♦ An external input on one of DIO0 to DIO3

• A JTAG clock, used in debug mode, coming from the

JTCK pad

• An external clock source, coming from the EXTCLK

• Manchester encoding

• Data whitening

pad

www.onsemi.com

14

NCV−RSL10

The 2.4 GHz radio front−end contains also a highly−flexible

digital baseband−in terms of modulations, configurability

and programmability – in order to support Bluetooth Low

Energy technology, and DSSS, and proprietary protocols. It

allows for programmable data rates from 62.5 kbps up to 2

Mbps, FSK with programmable pulse shape and modulation

index.

Application

The 2.4 GHz radio front−end also include Manchester

encoding and Data whitening. Its packet handling includes:

• Automatic preamble and sync word insertion

• Automatic packet length handler

• Basic address check

• Automatic CRC calculation and verification with a

GAP, GATT

programmable CRC polynomial

• Multi−frame support

• 2x128 byte FIFOs

SMP

ATT

Baseband Controller and Software Stack

L2CAP

The RSL10 Bluetooth baseband controller is connected to

the radio front−end. It configures the physical layer of the

RSL10 for use as a Bluetooth Low Energy technology

device. It provides access and support for the Direct−Test

Mode (DTM) layer for RF testing, and it implements

portions of the link layer and other controller level

components from the Bluetooth stack. It is dedicated to low

level bitwise operations and data packet processing.

RSL10 is Bluetooth 5.2 certified and includes LE 2 Mbps

support and all optional features from earlier versions of

Bluetooth Low Energy technology.

Link layer

Baseband

+ RF Front-End

Figure 5. Bluetooth Protocol Implementation

The following is a sample of the Bluetooth Low Energy

profiles supported by RSL10. For more information and a

complete list of the profiles offered, please download the

RSL10 SDK.

Also, the coexistence between Bluetooth and a custom

protocol is supported.

The software stack, including the profiles and the

application, handles the protocol functions and is executed

on the Arm Cortex−M3 processor. The Bluetooth IP

implementation is split among software and hardware as

shown in Figure 5.

• Find Me

• Proximity

• HID over GATT (HOG)

• Alert Notification

• Phone Alert Status

• Location and Navigation

• Rezence (custom protocol defined by AirFuelt

Alliance to support wireless battery charging)

www.onsemi.com

15

NCV−RSL10

Arm Cortex−M3 Processor Subsystem

• Two PWM (Pulse Width Modulation) drivers that can

generate a single bit output signal at a given frequency

• SWJ−DP interface for the Arm Cortex−M3 processor

The Arm Cortex−M3 processor subsystem includes the

Arm Cortex−M3 processor, which is the master processor of

the RSL10 chip. It also contains the Bluetooth baseband

controller, and all interfaces and other peripherals.

• JTAG interface for the Arm Cortex−M3 processor,

internal Flash memory, and the LPDSP32

Arm Cortex−M3 Processor

RSL10 includes 16 DIO pads (Digital Input/Output) that all

can be assigned to any of the interfaces above, or used as

general purpose DIOs.

The Arm Cortex−M3 processor is a state−of−the−art

32−bit core with embedded multiplier and ALU for handling

typical control functions. Software development is done

in C.

Peripherals

It features a low gate count, low interrupt latency, and

low−cost debug functionality. It is primarily intended for

deeply embedded applications that require low power

consumption with fast interrupt response. The processor

implements the Arm architecture v7−M. For power

management, the processor can be placed under firmware

control, into a Standby mode, in which the processor clock

is disabled. The Nested Vectored Interrupt Controller

(NVIC) will continue to run to enable exiting Standby mode

on an interrupt.

RSL10 includes:

• Four general purpose timers

• A DMA (Direct Memory Access) controller to transfer

data between peripherals and memories without any

core intervention

• A flash copier to initialize SRAM memories and that

can be used with the CRC blocks to validate flash

memory contents

• An Analog to Digital converter (ADC), accessed by the

Arm Cortex−M3 processor. The ADC can read 4

external values (DIO[0]−DIO[3]), AOUT, VDDC,

VBAT/2 and the ADC offset value.

• Two standard Cyclic Redundancy Code (CRC) blocks

to ensure data integrity of the user application code and

data

LPDSP32

LPDSP32 is a C−programmable, 32−bit DSP developed

byonsemi. LPDSP32 is a high efficiency, dual Harvard DSP

that supports both single (32−bit) and double precision

(64−bit) arithmetic.

LPDSP32’s dual MAC unit, load store architecture is

specifically optimized to support audio processing tasks.

The advanced architecture also provides:

• A Watchdog timer to detect and recover from RSL10

malfunctions.

• Four autonomous 32−bit Activity Counters. These

counters help analyze how long the system has been

running and how much the Arm Cortex−M3 processor,

LPDSP32, and the flash memory have been used by the

application. This is useful information to estimate and

optimize the power consumption of the application.

• Two 72−bit ALUs capable of doing single and double

precision arithmetic and logical operations

• Two 32−bit integer/fractional multipliers

• Four 64−bit accumulators with 8−bit overflow

(extension bits)

Communications to the Arm Cortex−M3 processor are

completed via interrupts and shared memories. Software

development is done in C, and the development tools are

provided upon request from Synopsys.

• An IP protection system to ensure that the flash content

cannot be copied by a third party. It can be used to

prevent any core or memory of the RSL10 from being

accessed externally after the RSL10 has booted.

• Program memory loop caches for each processor to

reduce the RSL10 power consumption. This reduces the

number of flash and RAM memory accesses by caching

the program words that are read in these loops.

Interfaces

RSL10 includes:

• Two independent SPI interfaces that can be configured

in master and slave mode

RSL10 Memory Structure

Table 9 lists the memory structures attached to RSL10,

and the size and width of each memory structure.

• A fully configurable PCM interface

2

• A standard general purpose I C interface

• A standard general purpose UART interface

www.onsemi.com

16

NCV−RSL10

Table 9. RSL10 MEMORY STRUCTURES

Memory type

Program memory (ROM)

Program memory (RAM)

Data memory (RAM)

Flash

Data Width

Memory Size

4 kB

Accessed by

32

40

32

Arm Cortex−M3 processor

4 instances of 8 kB

4 instances of 10 kB

1 instances of 8 kB

2 instances of 8 kB

6 instances of 8 kB

2 instances of 8 kB

384 kB

Arm Cortex−M3 processor

LPDSP32 / Arm Cortex−M3 processor

Arm Cortex−M3 processor

Arm Cortex−M3 processor / LPDSP32

LPDSP32 / Arm Cortex−M3 processor

Baseband / Arm Cortex−M3 processor

Arm Cortex−M3 processor / Flash copier

Chip Identification

For additional information on our Pb−Free strategy and

System identification is used to identify different system

components. For the RSL10 chip, the key identifier

components and values are as follows:

soldering details, please download the onsemi Soldering

and

Mounting

Techniques

Reference

Manual,

SOLDERRM/D.

• Chip Family: 0x09

Development Tools

RSL10 is supported by a full suite of comprehensive tools

including:

• Chip Version: 0x01

• Chip Major Revision: 0x01

• An easy−to−use development board

Electrostatic Discharge (ESD) Sensitive Device

CAUTION: ESD sensitive device. Permanent damage

may occur on devices subjected to high−energy electrostatic

discharges. Proper ESD precautions in handling, packaging

and testing are recommended to avoid performance

degradation or loss of functionality.

• Software Development Kit (SDK) including an Oxygen

Eclipse−based development environment, Bluetooth

protocol stacks, sample code, libraries, and

documentation

Export Control Classification Number (ECCN)

The ECCN designation for RSL10 is 5A991.g

Solder Information

The RSL10 QFN package is constructed with all RoHS

compliant material and should be reflowed accordingly.

This device is Moisture Sensitive Class MSL1 and must

be stored and handled accordingly. Re−flow according to

IPC/JEDEC standard J−STD−020C, Joint Industry

Standard: Re−flow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices. Hand

soldering is not recommended for this part.

Company or Product Inquiries

For more information about onsemi products or services

visit our Web site at http://onsemi.com.

For sales or technical support, contact your local

representative or authorized distributor.

2

onsemi is licensed by the Philips Corporation to carry the I C bus protocol.

AirFuel is a trademark of Air Routing International Corporation.

Bluetooth is a registered trademark of Bluetooth SIG.

Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries).

www.onsemi.com

17

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFNW48 7x7, 0.5P

CASE 512AD

ISSUE B

DATE 18 JAN 2019

1

48

SCALE 2:1

EXPOSED

COPPER

GENERIC

MARKING DIAGRAM*

1

A

= Assembly Location

XXXXXXXXX

AWLYYWWG

*This information is generic. Please refer to

WL = Wafer Lot

YY = Year

WW = Work Week

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

G

= Pb−Free Package

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON72646G

QFNW48 7x7, 0.5P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

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provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

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onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	NCV-RSL10-101Q48-AVG
厂家：	ONSEMI
描述：	无线电 SoC，超低功耗，多协议，Bluetooth® 5 汽车认证无线电信电信集成电路
文件：	总19页 (文件大小：248K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV-RSL10-101Q48-AVG [ONSEMI]

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