NCV1077P065G_技术文档

NCV1072, NCV1075,

NCV1076, NCV1077

Automotive High-Voltage

Switcher for Low Power

SMPS

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The NCV107x products integrate a fixed frequency current mode

controller with a 670 V MOSFET. Available in a PDIP−7 package, the

NCV107x offer a high level of integration, including soft−start,

frequency−jittering, short−circuit protection, skip−cycle, a maximum

peak current set point, ramp compensation, and a Dynamic

Self−Supply (eliminating the need for an auxiliary winding).

Unlike other monolithic solutions, the NCV107x is quiet by nature:

during nominal load operation, the part switches at one of the available

frequencies (65, 100 or 130 kHz). When the output power demand

diminishes, the IC automatically enters frequency foldback mode and

provides excellent efficiency at light loads. When the power demand

reduces further, it enters into a skip mode to reduce the standby

consumption down to a no load condition.

MARKING

DIAGRAM

PDIP−7

P SUFFIX

CASE 626A

V107xyyy

AWL

YYWWG

AYW

Vz7xyG

G

SOT−223

ST SUFFIX

CASE 318E

Protection features include: a timer to detect an overload or a

short−circuit event, Overvoltage Protection with auto−recovery and

AC input line voltage detection.

1

For improved standby performance, the connection of an auxiliary

winding stops the DSS operation and helps to reduce input power

consumption below 50 mW at high line.

x

y

= Current Limit (2, 5, 6 or 7)

= Oscillator Frequency

= A(65 kHz), B(100 kHz), 130(130 kHz)

= 0 (with brown−in), C (without brown−in)

= 065, 100, 130

= Assembly Location

= Wafer Lot

= Year

z

yyy

A

WL

Y, YY

Features

• Built−in 670 V MOSFET with R

11 W (NCV1072/75)

of 4.7 W (NCV1076/77) /

DS(on)

W, WW = Work Week

G or G = Pb−Free Package

• Large Creepage Distance Between High−voltage Pins

• Current−Mode Fixed Frequency Operation – 65 / 100 / 130 kHz

• Peak Current: NCV1072 with 250 mA, NCV1075 with 450 mA,

NCV1076 with 650 mA and NCV1077 with 800 mA

• Fixed Ramp Compensation

ORDERING INFORMATION

Only limited options are released to market. Other

options available upon customer request. See status and

detailed ordering and shipping information on pages 2 &

27 of the document.

• Skip−Cycle Operation at Low Peak Currents Only: No Acoustic

Noise!

• Dynamic Self−Supply: No Need for an Auxiliary Winding

• Internal 1 ms Soft−Start

• Internal Temperature Shutdown

• Auto−Recovery Output Short Circuit Protection with

• NCV Prefix for Automotive and Other Applications

Requiring Unique Site and Control Change

Requirements; AEC−Q100 Qualified and PPAP

Capable

Timer−Based Detection

• Auto−Recovery Overvoltage Protection with Auxiliary

Winding Operation

• These Devices are Pb−Free, Halogen Free/BFR Free

and are RoHS Compliant

• Frequency Jittering for Better EMI Signature, Including

Frequency Foldback Mode

• No Load Input Consumption < 50 mW

Typical Applications

• Options With or Without Brown−in Function Available

• Frequency Foldback to Improve Efficiency at Light

Load

• Auxiliary & Standby Isolated Power Supplies for

HEV/EV

1

Publication Order Number:

July, 2019 − Rev. 6

NCV1070/D

NCV1072, NCV1075, NCV1076, NCV1077

PIN CONNECTIONS

V

1

2

3

4

8

7

V

CC

1

2

3

CC

GND

FB

4

GND

FB

DRAIN

5

DRAIN

(Top View)

PDIP−7

SOT−223

Figure 1. Pin Connections

INDICATIVE MAXIMUM OUTPUT POWER

R

− I

230 Vac

19 W

85−265 Vac

DS(on)

IPK

NCV1072 / 1075

NCV1076 / 1077

11 W − 450 mA

4.7 W − 800 mA

10 W

15 W

25 W

NOTE: Informative values only, with T

= 50°C, F

= 65 kHz, Self supply via Auxiliary winding and circuit mounted on minimum

amb

SW

copper area as recommended.

QUICK SELECTION TABLE

NCV1072

NCV1075

NCV1076

NCV1077

R

(W)

11

4.7

DS(on)

Ipeak (mA)

250

100

No

450

100

P

650

100

P

800

100

S

Freq (kHz)

65

130*

No

65

P

130

No

65

P

130

No

65

P

130

No

Release to Market Status

No

NOTE: PDIP−7 Release (P)/SOT−223 released (S)

*130 kHz on demand only

Figure 2. Typical Application Example

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2

NCV1072, NCV1075, NCV1076, NCV1077

PIN FUNCTION DESCRIPTION

Pin N5

1

Pin Name

Function

Pin Description

V

CC

Powers the internal circuitry

This pin is connected to an external capacitor. The V includes an

active shunt which serves as an auto−recovery over voltage protection.

CC

2

3

4

NC

GND

FB

The IC Ground

Feedback signal input

By connecting an opto−coupler to this pin, the peak current set point is

adjusted accordingly to the output power demand.

5

6

7

8

Drain

Drain connection

The internal drain MOSFET connection

This un−connected pin ensures adequate creepage distance

GND

The IC Ground

Vcc

Drain

V

clamp

I

OVP

−

Vcc OVP

UVLO

Reset

Vdd

+

Vcc

Management

S

R

Q

80−us

filter

SCP

t

Q

OFF UVLO

Ipflag

SCP

t

recovery

line

detection

LineOK

TSD

UVLO

Vcc

OFF

LineOK

Jittering

DRV

OSC

Sawtooth

S

Q

Sawtooth

Foldback

Q

R

I

FBskip

Ramp

compensation

−

SKIP

GND

+

DRV

200 ns

LEB

SKIP = ”1” −−> shut

down some blocks to

reduce consumption

+

V

FB(REF)

−

R

FB(up)

to CS setpoint

I

FB

Reset

+

FB

Soft

Start

−

I

−

freeze

Ipk(0)

Reset SS as recovering from

SCP, TSD, Vcc OVP, or UVLO

+

I

Ipflag

FBfault

Figure 3. Simplified Internal Circuit Architecture

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3

NCV1072, NCV1075, NCV1076, NCV1077

MAXIMUM RATINGS TABLE

Symbol

Rating

Value

Unit

V

CC

Power Supply Voltage on all pins, except Pin 5(Drain)

Drain voltage

−0.3 to 10

−0.3 to 670

BVdss

V

I

Drain current peak during transformer saturation (T = 150°C, Note 3):

DS(PK)

J

NCV1072/75:

NCV1076/77:

870

2200

mA

Drain current peak during transformer saturation (T = 25°C, Note 3):

J

NCV1072/75:

NCV1076/77:

1500

3900

mA

I_V

Maximum Current into Pin 1 when Activating the 8.2 V Active Clamp

PDIP−7, P Suffix, Case 626A

15

mA

CC

R

0.36 Sq. Inch

1.0 Sq. Inch

77

°C/W

q

J−A

Junction−to−Air, 2.0 oz Printed Circuit Copper Clad

Maximum Junction Temperature

60

TJ

150

°C

kV

V

MAX

Storage Temperature Range

−60 to +150

ESD Capability, Human Body Model (All pins except HV)

ESD Capability, Machine Model

2

200

1

ESD Capability, Charged Device Model

kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC JESD22−A114−F

Machine Model Method 200 V per JEDEC JESD22−A115−A

Charged Device Model 1000 V per JEDEC JESD22−C101E

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78

3. Maximum drain current I

is obtained when the transformer saturates. It should not be mixed with short pulses that can be seen at turn

DS(PK)

on. Figure 4 below provides spike limits the device can tolerate.

Figure 4. Spike Limits

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NCV1072, NCV1075, NCV1076, NCV1077

ELECTRICAL CHARACTERISTICS

(For all NCV107X products: For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 8 V unless otherwise noted)

J

CC

Symbol

Rating

Min

Typ

Max

Unit

SUPPLY SECTION AND V MANAGEMENT

CC

V

CC(on)

V

CC

increasing level at which the switcher starts operation

NCV1072/75

NCV1076/77

V

1

7.8

7.7

8.2

8.1

8.6

8.5

V

decreasing level at which the HV current source restarts

1

6.5

6.1

6.8

6.3

4

7.2

6.6

V

CC(min)

CC

V

decreasing level at which the switcher stops operation (UVLO)

voltage at which the internal latch is reset (guaranteed by design)

CC(off)

V

CC(reset)

V

Offset voltage above V

at which the internal clamp activates

mV

CC(clamp)

CC(on)

(measured in skip mode)

NCV1072/75

1

130

190

300

NCV1076/77

I

Internal IC consumption, Mosfet switching

NCV1072/75

NCV1076/77

mA

CC1

1

−

0.7

1.0

1.3

I

Internal IC consumption, FB is 0 V (No switching on MOSFET)

1

360

mA

CCskip

POWER SWITCH CIRCUIT

R

Power Switch Circuit on−state resistance (Id = 50 mA)

5

W

DS(on)

NCV1072/75

T = 25°C

−

11

19

16

24

J

T = 125°C

J

NCV1076/77

T = 25°C

−

4.7

8.7

6.9

10.75

J

T = 125°C

J

BV

Power Switch Circuit & Startup breakdown voltage

5

670

V

DSS

(ID

= 120 mA, T = 25°C)

(off)

J

I

Power Switch & Startup breakdown voltage off−state leakage current

T = 125°C (Vds = 670 V)

mA

ns

DSS(off)

85

J

Switching characteristics (R =50 W, V set for I

= 0.7 x Ilim)

L

DS

drain

t

on

t

off

Turn−on time (90% − 10%)

Turn−off time (10% − 90%)

5

20

10

INTERNAL START−UP CURRENT SOURCE

I

High−voltage current source, V

NCV1076/77

NCV1072/75

V

CC(on)

− 200 mV

mA

start1

=

5

5.2

5

9.2

9

12.2

12

I

High−voltage current source, V = 0 V

5

1

0.5

2.2

mA

V

start2

CC

V

VCC Transient level for Istart1 to Istart2 toggling point

−

CCTH

CURRENT COMPARATOR

I

Maximum internal current setpoint at 50% duty cycle

mA

IPK

FB pin open, Tj = 25°C

NCV1072

−

250

450

650

800

−

NCV1075

NCV1076

NCV1077

I

Maximum internal current setpoint at beginning of switching cycle

mA

IPK(0)

FB pin open, Tj = 25°C

NCV1072

254

467

689

846

282

508

765

940

310

549

NCV1075

NCV1076

841

NCV1077

1034

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. The final switch current is: I

/ (V /L + S ) x V /L + V /L x t

, with S the built−in slope compensation, Vin the input voltage, L

prop a P

IPK(0)

in

P

a

in

P

in

P

the primary inductor in a flyback, and t

5. NCV1072 130 kHz on demand only.

the propagation delay.

prop

6. Oscillator frequency is measured with disabled jittering.

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NCV1072, NCV1075, NCV1076, NCV1077

ELECTRICAL CHARACTERISTICS

(For all NCV107X products: For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 8 V unless otherwise noted)

J

CC

Symbol

Rating

Min

Typ

Max

Unit

CURRENT COMPARATOR

I

Final switch current with a primary slope of 200 mA/ms,

=65 kHz (Note 4)

mA

IPKSW

F

SW

NCV1072

−

296

510

732

881

−

NCV1075

NCV1076

NCV1077

Final switch current with a primary slope of 200 mA/ms,

=100 kHz (Note 4)

mA

F

SW

NCV1072

−

293

500

706

845

−

NCV1075

NCV1076

NCV1077

Final switch current with a primary slope of 200 mA/ms,

=130 kHz

F

SW

NCV1072 (Note 5)

NCV1075

−

291

493

684

814

−

NCV1076

NCV1077

T

Soft−start duration (guaranteed by design)

Leading Edge Blanking Duration

−

1

−

ms

ns

SS

T

LEB

prop

200

100

T

Propagation delay from current detection to drain OFF state

INTERNAL OSCILLATOR

f

Oscillation frequency, 65 kHz version, Tj = 25°C (Note 6)

Oscillation frequency, 100 kHz version, Tj = 25°C (Note 6)

Oscillation frequency, 130 kHz version, Tj = 25°C (Note 5 et 6)

−

59

90

117

−

65

100

130

6

71

110

143

−

kHz

%

OSC

f

Frequency jittering in percentage of f

jitter

OSC

f

Jittering swing frequency

−

300

−

Hz

swing

D

Maximum duty−cycle

NCV1072/75

NCV1076/77

%

max

−

62

65

68

69

72

73

FEEDBACK SECTION

FB current for which Fault is detected

FB current for which internal current set−point is 100% (I

I

4

−35

−44

−90

3.3

mA

V

FBfault

I

)

IPK(0)

FB100%

I

FB current for which internal current set−point is I

−

FBFreeze

Freeze

V

Equivalent pull−up voltage in linear regulation range

(Guaranteed by design)

FB(REF)

R

Equivalent feedback resistor in linear regulation range

(Guaranteed by design)

4

19.5

kW

FB(up)

FREQUENCY FOLDBACK & SKIP

Start of frequency foldback feedback level

I

4

−

4

−

−68

−100

25

−

mA

FBfold

I

End of frequency foldback feedback level, F = F

FBfold(end)

sw

min

F

min

The frequency below which skip−cycle occurs

21

−

29

−

kHz

mA

I

The feedback level to enter skip mode

−120

FBskip

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. The final switch current is: I

/ (V /L + S ) x V /L + V /L x t

, with S the built−in slope compensation, Vin the input voltage, L

prop a P

IPK(0)

in

P

a

in

P

in

P

the primary inductor in a flyback, and t

5. NCV1072 130 kHz on demand only.

the propagation delay.

prop

6. Oscillator frequency is measured with disabled jittering.

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NCV1072, NCV1075, NCV1076, NCV1077

ELECTRICAL CHARACTERISTICS

(For all NCV107X products: For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 8 V unless otherwise noted)

J

CC

Symbol

Rating

Min

Typ

Max

Unit

FREQUENCY FOLDBACK & SKIP

I

Internal minimum current setpoint (I = I )

FBFreeze

mA

Freeze

FB

NCV1072

NCV1075

NCV1076

NCV1077

−

88

−

168

228

280

RAMP COMPENSATION

S

The internal ramp compensation @ 65 kHz

mA/ms

a(65)

NCV1072

NCV1075

NCV1076

NCV1077

−

4.2

7.5

15

−

18

S

a(100)

S

a(130)

The internal ramp compensation @ 100 kHz

NCV1072

NCV1075

NCV1076

NCV1077

−

6.5

11.5

23

−

28

The internal ramp compensation @ 130 kHz

NCV1072 (Note 5)

NCV1075

NCV1076

NCV1077

−

8.4

15

30

36

−

PROTECTIONS

t

Fault validation further to error flag assertion

−

40

53

−

ms

SCP

t

OFF phase in fault mode

NCV1072/5/6/7

recovery

−

420

I

t

V

clamp current at which the switcher stops pulsing

mA

OVP

CC

NCV1072/75/76/77

−

5

6

−

8.5

80

91

11

−

The filter of V OVP comparator

ms

OVP

CC

V

The drain pin voltage above which allows MOSFET operate, which is

72

110

V

HV(EN)

detected after TSD, UVLO, SCP, or V OVP mode. (only for versions

CC

with brown−in)

TEMPERATURE MANAGEMENT

TSD Temperature shutdown (Guaranteed by design)

Hysteresis in shutdown (Guaranteed by design)

−

150

°C

50

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. The final switch current is: I

/ (V /L + S ) x V /L + V /L x t

, with S the built−in slope compensation, Vin the input voltage, L

prop a P

IPK(0)

in

P

a

in

P

in

P

the primary inductor in a flyback, and t

5. NCV1072 130 kHz on demand only.

the propagation delay.

prop

6. Oscillator frequency is measured with disabled jittering.

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NCV1072, NCV1075, NCV1076, NCV1077

TYPICAL CHARACTERISTICS

8.4

8.3

8.2

8.1

8.0

7.9

7.0

6.9

6.8

6.7

6.6

6.5

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 5. V_CC(on)vs. Temperature

Figure 6. V_CC(min)vs. Temperature

6.6

6.5

6.4

6.3

6.2

6.1

240

220

200

180

160

140

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 7. V_CC(off)vs. Temperature

Figure 8. V_CC(clamp)vs. Temperature

0.80

0.75

0.70

0.65

0.60

40

35

30

25

20

15

10

NCV1072/75

NCV1076/77

100

5

0

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

125

TEMPERATURE (°C)

Figure 9. I_CC1vs. Temperature

Figure 10. R_DS(on)vs. Temperature

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NCV1072, NCV1075, NCV1076, NCV1077

TYPICAL CHARACTERISTICS

12

11

10

9

110

100

90

80

70

8

7

6

60

50

5

4

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 11. I_DSS(off)vs. Temperature

Figure 12. I_start1vs. Temperature

0.6

0.5

0.4

0.3

0.2

0.1

0

1000

NCV1077

900

800

700

600

500

400

NCV1076

NCV1075

300

200

NCV1072

100 125

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

TEMPERATURE (°C)

Figure 13. I_start2vs. Temperature

Figure 14. I_IPK(0)vs. Temperature

72

70

68

66

110

100

90

100 kHz

80

70

60

50

65 kHz

100

64

62

−50

−25

0

25

50

75

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 15. F_OSCvs. Temperature

Figure 16. D_(max)vs. Temperature

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NCV1072, NCV1075, NCV1076, NCV1077

TYPICAL CHARACTERISTICS

65

60

55

50

29

28

27

26

25

24

23

22

21

45

40

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 17. F_minvs. Temperature

Figure 18. t_SCPvs. Temperature

10

510

490

9.5

9.0

8.5

8.0

7.5

7.0

470

450

430

410

390

370

350

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 19. t

vs. Temperature

Figure 20. I_OVPvs. Temperature

recovery

6

5

110

105

100

95

NCV1076/77

4

3

2

NCV1072/75

90

85

80

1

0

−50 −25

0

25

50

75

100

125 150

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

T , JUNCTION TEMPERATURE (°C)

J

Figure 21. V_HV(EN)vs. Temperature

Figure 22. Drain Current Peak during Transformer

Saturation vs. Junction Temperature

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NCV1072, NCV1075, NCV1076, NCV1077

TYPICAL CHARACTERISTICS

1.100

1.075

1.050

1.025

1.000

0.975

0.950

0.925

−40 −20

0

20

40

60

80

100 125

TEMPERATURE (°C)

Figure 23. Breakdown Voltage vs. Temperature

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NCV1072, NCV1075, NCV1076, NCV1077

APPLICATION INFORMATION

Introduction

resumes operation. If the fault is still there, e.g. a

broken opto−coupler, the controller protects the load

through a safe burst mode.

The NCV107x offers a complete current−mode control

solution. The component integrates everything needed to

build a rugged and low−cost Switch−Mode Power Supply

(SMPS) featuring low standby power. The Quick Selection

Table on page 2 details the differences between references,

mainly peak current setpoints and operating frequency.

• Line detection: An internal comparator monitors the

drain voltage as recovering from one of the following

situations:

♦ Short Circuit Protection,

• Current−mode operation: the controller uses

current−mode control architecture.

♦ V OVP is confirmed,

CC

♦ UVLO

♦ TSD

• 670 V Power MOSFET: Due to ON Semiconductor

Very High Voltage Integrated Circuit technology, the

circuit hosts a high*voltage power MOSFET featuring

a 11/4.7 W R_DS(on)– T_J= 25°C. This value lets the

designer build a power supply up to respectively 10 W

and 15 W operated on universal mains. An internal

current source delivers the startup current, necessary to

crank the power supply.

If the drain voltage is lower than the internal threshold

(V

), the internal power switch is inhibited. This

HV(EN)

avoids operating at too low ac input. This is also called

brown−in function in some fields. This detection can be

inhibited on demand on NCV1076/77 versions.

• Frequency jittering: an internal low−frequency

modulation signal varies the pace at which the

• Dynamic Self−Supply: Due to the internal high voltage

current source, this device could be used in the

application without the auxiliary winding to provide

supply voltage.

oscillator frequency is modulated. This helps spreading

out energy in conducted noise analysis. To improve the

EMI signature at low power levels, the jittering remains

active in frequency foldback mode.

• Short circuit protection: by permanently monitoring the

feedback line activity, the IC is able to detect the

presence of a short−circuit, immediately reducing the

• Soft−Start: a 1 ms soft−start ensures a smooth startup

sequence, reducing output overshoots.

• Frequency foldback capability: a continuous flow of

pulses is not compatible with no−load/light−load

standby power requirements. To excel in this domain,

the controller observes the feedback current

output power for a total system protection. A t

timer

SCP

is started as soon as the feedback current is below

threshold, I , which indicates the maximum peak

FB(fault)

current. If at the end of this timer the fault is still

present, then the device enters a safe, auto−recovery

burst mode, affected by a fixed timer recurrence,

information and when it reaches a level of I

, the

FBfold

oscillator then starts to reduce its switching frequency

as the feedback current continues to increase (the power

demand continues to reduce). It can go down to 25 kHz

t . Once the short has disappeared, the controller

recovery

resumes and goes back to normal operation.

(typical) reached for a feedback level of I

FBfold(end)

• Built−in V Over Voltage Protection: when the

CC

(100 mA roughly). At this point, if the power continues

to drop, the controller enters classical skip−cycle mode.

auxiliary winding is used to bias the V pin (no DSS),

CC

an internal active clamp connected between V and

CC

• Skip: if SMPS naturally exhibits a good efficiency at

nominal load, they begin to be less efficient when the

output power demand diminishes. By skipping

ground limits the supply dynamics to V

. In

CC(clamp)

case the current injected in this clamp exceeds a level

of 6.0 mA (minimum), the controller immediately stops

un−needed switching cycles, the NCV107x drastically

reduces the power wasted during light load conditions.

switching and waits a full timer period (t

) before

recovery

attempting to restart. If the fault is gone, the controller

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12

NCV1072, NCV1075, NCV1076, NCV1077

APPLICATION INFORMATION

Startup Sequence

When the power supply is first powered from the mains

outlet, the internal current source is biased and charges up

source turns off and pulses are delivered by the output stage:

the circuit is awake and activates the power MOSFET if the

bulk voltage is above V

level. Figure 24 details the

HV(EN)

the V capacitor from the drain pin. Once the voltage on

simplified internal circuitry.

CC

this V capacitor reaches the V

level, the current

CC

CC(on)

V

bulk

I1

R

limit

Drain

5

I

start1

I

CC1

1

I2

I

clamp

+

-

C

VCC

V

clamp

V

CC(on)

CC(min)

I

> I

OVP

clamp

--> OVP fault

8

Figure 24. The Internal Arrangement of the Start−up Circuitry

Being loaded by the circuit consumption, the voltage on

the V capacitor goes down. When V is below V

whose low frequency depends on the V capacitor and the

CC

IC consumption. A 1.4 V ripple takes place on the V pin

CC

CC(min)

CC

level, it activates the internal current source to bring V

whose average value equals (V

+ V )/2.

CC(min)

CC

CC(on)

toward V

level and stops again: a cycle takes place

Figure 25 portrays a typical operation of the DSS.

CC(on)

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13

NCV1072, NCV1075, NCV1076, NCV1077

Figure 25. The Charge/Discharge Cycle Over a 1 mF V_CCCapacitor

As one can see, even if there is auxiliary winding to

protection (OVP) circuit and immediately stops the output

pulses for t duration (420 ms typically). Then a new

provide energy for V , it happens that the device is still

CC

recovery

biased by DSS during start−up time or some fault mode

when the voltage on auxiliary winding is not ready yet. The

start−up attempt takes place to check whether the fault has

disappeared or not. The OVP paragraph gives more design

details on this particular section.

V

capacitor shall be dimensioned to avoid V crosses

CC

level, which stops operation. The DV between

CC(off)

CC(min)

Fault Condition – Short−Circuit on V_CC

In some fault situations, a short−circuit can purposely

and V

is 0.4 V. There is no current source to

CC(off)

charge V capacitor when driver is on, i.e. drain voltage is

CC

occur between V and GND. In high line conditions (V

CC

HV

close to zero. Hence the V capacitor can be calculated

CC

= 370 V ) the current delivered by the startup device will

DC

using

seriously increase the junction temperature. For instance,

I_CC1D_max

since I

equals 5 mA (the min corresponds to the highest

start1

(eq. 1)

C

_VCCw

f

_OSC@ DV

T ), the device would dissipate 370 x 5 m = 1.85 W. To avoid

j

this situation, the controller includes a novel circuitry made

Take the NCV1072 65 kHz device as an example. C

should be above

VCC

of two startup levels, I

and I

. At power−up, as long

start1

start2

as V is below a 2.4 V level, the source delivers I

CC

start2

0.8m @ 72%

59 kHz @ 0.4

(around 500 mA typical), then, when V reaches 2.4 V, the

CC

source smoothly transitions to I

and delivers its nominal

start1

value. As a result, in case of short−circuit between V and

CC

A margin that covers the temperature drift and the voltage

drop due to switching inside FET should be considered, and

thus a capacitor above 0.1 mF is appropriate.

GND, the power dissipation will drop to 370 x 500u =

185 mW. Figure 25 portrays this particular behavior.

The first startup period is calculated by the formula C x V

= I x t, which implies a 1m x 2.4 / 500u = 4.8 ms startup time

for the first sequence. The second sequence is obtained by

The V capacitor has only a supply role and its value

CC

does not impact other parameters such as fault duration or

the frequency sweep period for instance. As one can see on

Figure 24, an internal active zener diode, protects the

toggling the source to 8 mA with a delta V of V

–

CC(on)

V

CCTH

= 8.2 – 2.4 = 5.8 V, which finally leads to a second

switcher against lethal V runaways. This situation can

CC

startup time of 1m x 5.8 / 8m = 0.725 ms. The total startup

time becomes 4.8m + 0.725m = 5.525 ms. Please note that

this calculation is approximated by the presence of the knee

in the vicinity of the transition.

occur if the feedback loop optocoupler fails, for instance,

and you would like to protect the converter against an over

voltage event. In that case, the internal current increase

incurred by the V rapid growth triggers the over voltage

CC

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14

NCV1072, NCV1075, NCV1076, NCV1077

Fault Condition – Output Short−Circuit

asserted, Ipflag, indicating that the system has reached its

maximum current limit set point. The assertion of this flag

triggers a fault counter t (53 ms typically). If at counter

As soon as V

reaches V , drive pulses are

CC(on)

CC

internally enabled. If everything is correct, the auxiliary

SCP

winding increases the voltage on the V pin as the output

completion, Ipflag remains asserted, all driving pulses are

stopped and the part stays off in t duration (about

CC

voltage rises. During the start−sequence, the controller

smoothly ramps up the peak drain current to maximum

recovery

420 ms). A new attempt to re−start occurs and will last 53 ms

providing the fault is still present. If the fault still affects the

output, a safe burst mode is entered, affected by a low

duty−cycle operation (11%). When the fault disappears, the

power supply quickly resumes operation. Figure 26 depicts

this particular mode:

setting, i.e. I , which is reached after a typical period of

IPK

1 ms. When the output voltage is not regulated, the current

coming through FB pin is below I

level (35 mA

FBfault

typically), which is not only during the startup period but

also anytime an overload occurs, an internal error flag is

Figure 26. In Case of Short−Circuit or Overload, the NCV107X Protects Itself and the Power Supply Via a Low

Frequency Burst Mode. The V_CCis Maintained by the Current Source and Self−supplies the Controller.

Auto−Recovery Over Voltage Protection

triggering the OVP as we discussed, but also to avoid

disturbing the V in low / light load conditions. The below

The particular NCV107X arrangement offers a simple

way to prevent output voltage runaway when the

optocoupler fails. As Figure 27 shows, an active zener diode

CC

lines detail how to evaluate the R

value...

limit

Self−supplying controllers in extremely low standby

applications often puzzles the designer. Actually, if a SMPS

operated at nominal load can deliver an auxiliary voltage of

monitors and protects the V pin. Below its equivalent

CC

breakdown voltage, that is to say 8.4 V typical, no current

flows in it. If the auxiliary V pushes too much current

an arbitrary 16 V (V ), this voltage can drop below 10 V

CC

nom

inside the zener, then the controller considers an OVP

situation and stops the internal drivers. When an OVP

occurs, all switching pulses are permanently disabled. After

(V ) when entering standby. This is because the

recurrence of the switching pulses expands so much that the

stby

low frequency re−fueling rate of the V capacitor is not

CC

t

delay, it resumes the internal drivers. If the failure

enough to keep a proper auxiliary voltage. Figure 28

portrays a typical scope shot of a SMPS entering deep

standby (output un−loaded). Thus, care must be taken when

recovery

symptom still exists, e.g. feedback opto−coupler fails, the

device keeps the auto−recovery OVP mode.

Figure 27 shows that the insertion of a resistor (R

)

calculating R

1) to not trigger the V over current latch

limit

CC

between the auxiliary dc level and the V pin is mandatory

(by injecting 6 mA into the active clamp – always use the

minimum value for worse case design) in normal operation

CC

a) not to damage the internal 8.4 V zener diode during an

overshoot for instance (absolute maximum current is

15 mA) b) to implement the fail−safe optocoupler protection

(OVP) as offered by the active clamp. Please note that there

cannot be bad interaction between the clamping voltage of

but 2) not to drop too much voltage over R

when entering

limit

standby. Otherwise, the converter will enter dynamic self

supply mode (DSS mode), which increases the power

dissipation. Based on these recommendations, we are able to

the internal zener and V

actually built on top of V

since this clamping voltage is

with a fixed amount of offset

bound R

between two equations:

CC(on)

limit

CC(on)

(200 mV typical). R

should be carefully selected to avoid

limit

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15

NCV1072, NCV1075, NCV1076, NCV1077

This number decreases compared to normal operation since

the part in standby does almost not switch. It is around

0.36 mA for the NCV1072 65 kHz version.

V

_nom* V

V

_stby* V_CC(min)

^CC(clamp)v R_limitv

(eq. 2)

I_trip

I_CCskip

V

is the level above which the auxiliary voltage must

CC(min)

Where:

be maintained to keep the controller away from the dynamic

self supply mode (DSS mode), which is not a problem in

itself if low standby power does not matter.

V

nom

V

stby

is the auxiliary voltage at nominal load

is the auxiliary voltage when standby is entered

I

is the current corresponding to the nominal operation. It

trip

If a further improvement on standby efficiency is

thus must be selected to avoid false tripping in overshoot

conditions. Always use the minimum of the specification for

a robust design, i.e. I < I

concerned, it is good to obtain V around 8 V at no load

condition in order not to re−activate the internal clamp

circuit.

CC

.

trip

OVP

I

is the controller consumption during skip mode.

CCskip

I

> I

OVP

clamp

Figure 27. A More Detailed View of the NCV107x Offers Better Insight on How to Properly Wire an Auxiliary Winding

Since R

shall not bother the controller in standby, e.g.

1.08. The OVP latch will activate when the clamp current

exceeds 6 mA. This will occur when Vauxiliary grows−up

to:

limit

keep V

to above V

(7.2 V maximum), we

CC

CC(min)

purposely select a V

well above this value. As explained

nom

before, experience shows that a 40% decrease can be seen on

auxiliary windings from nominal operation down to standby

mode. Let’s select a nominal auxiliary winding of 13 V to

offer sufficient margin regarding 7.2 V when in standby

1. 8.4 + 0.77k x (6m + 0.8m) ≈ 13.6 V for the first

boundary (R

= 0.77 kW)

limit

2. 8.4 + 2.2k x (6m +0.8m) ≈ 23.4 V for the second

boundary (R = 2.2 kW)

limit

(R

limit

also drops voltage in standby...). Plugging the values

Due to a 1.08 ratio between the auxiliary V and the

CC

in Equation 2 gives the limits within which R

shall be

limit

power winding, the OVP will be seen as a lower overshoot

on the real output:

selected:

1. 13.6 / 1.08 ≈ 12.6 V

13 * 8.4

8 * 7.2

v R_limitv

2. 23.4 / 1.08 ≈ 21.7 V

6m

0.36m

As one can see, tweaking the R

selection of a given overvoltage output level. Theoretically

predicting the auxiliary drop from nominal to standby is an

value will allow the

limit

that is to say: 0.77 kW < Rlimit < 2.2 kW.

If we design a 65 kHz power supply delivering 12V, then

the ratio between auxiliary and power must be: 13 / 12 =

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16

NCV1072, NCV1075, NCV1076, NCV1077

almost impossible exercise since many parameters are

involved, including the converter time constants. Fine

tuning of R thus requires a few iterations and

variations but also the output voltage excursion in fault.

Once properly adjusted, the fail−safe protection will

preclude any lethal voltage runaways in case a problem

would occur in the feedback loop.

limit

experiments on a breadboard to check the auxiliary voltage

Figure 28. The Burst Frequency Becomes so Low That it is Difficult to Keep an Adequate Level on the Auxiliary

_CC...

V

Figure 29 describes the main signal variations when the

part operates in auto−recovery OVP:

Figure 29. If the V_CCCurrent Exceeds a Certain Threshold, an Auto−Recovery Protection is Activated

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17

NCV1072, NCV1075, NCV1076, NCV1077

Improving the precision in auto−recovery OVP

Soft−Start

Given the OVP variations the internal trip current

dispersion incur, it is sometimes more interesting to explore

a different solution, improving the situation to the cost of a

minimal amount of surrounding elements. Figure 30 shows

that adding a simple zener diode on top of the limiting

resistor, offers a better precision since what matters now is

The NCV107X features a 1 ms soft−start which reduces

the power−on stress but also contributes to lower the output

overshoot. Figure 31 shows a typical operating waveform.

The NCV107X features a novel patented structure which

offers a better soft−start ramp, almost ignoring the start−up

pedestal inherent to traditional current−mode supplies:

the internal V

breakdown plus the zener voltage. A

CC(on)

resistor in series with the zener diodes keeps the maximum

current in the V pin below the maximum rating of 15 mA

CC

just before trip the OVP.

Vcc

D1

Rlimit

Laux

Ground

Figure 30. A Simple Zener Diode Added in Parallel

VCC_ON

Drain current

Figure 31. The 1 ms soft−start sequence

Jittering

sawtooth is internally generated and modulates the clock up

and down with a fixed frequency of 300 Hz. Figure 32

shows the relationship between the jitter ramp and the

frequency deviation. It is not possible to externally disable

the jitter.

Frequency jittering is a method used to soften the EMI

signature by spreading the energy in the vicinity of the main

switching component. The NCV107X offers a 6%

deviation of the nominal switching frequency. The sweep

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18

NCV1072, NCV1075, NCV1076, NCV1077

Jitter ramp

68.9kHz

65kHz

Internal

61.1kHz

sawtooth

adjustable

Figure 32. Modulation Effects on the Clock Signal by the Jittering Sawtooth

Frequency Foldback

Line Detection

An internal comparator monitors the drain voltage as

recovering from one of the following situations:

• Short Circuit Protection,

The reduction of no−load standby power associated with

the need for improving the efficiency, requires to change the

traditional fixed−frequency type of operation. This device

implements a switching frequency folback when the

• V OVP is confirmed,

CC

feedback current passes above a certain level, I

, set

FBfold

• UVLO

• TSD

around 68 mA. At this point, the oscillator enters frequency

foldback and reduces its switching frequency.

The internal peak current set−point is following the

feedback current information until its level reaches the

If the drain voltage is lower than the internal threshold

V

HV(EN)

(91 Vdc typically), the internal power switch is

inhibited. This avoids operating at too low ac input. This is

also called brown−in function in some fields.

minimal freezing level point of I

. The only way to

Freeze

further reduce the transmitted power is to diminish the

operating frequency down to F (25 kHz typically). This

min

value is reached at a feedback current level of I

.

FBfold(end)

Below this point, if the output power continues to decrease,

the part enters skip cycle for the best noise−free performance

in no−load conditions. Figures 33 and 34 depict the adopted

scheme for the part.

Figure 33. By Observing the Current on the Feedback Pin, the Controller Reduces its Switching Frequency for an

Improved Performance at Light Load

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19

NCV1072, NCV1075, NCV1076, NCV1077

Figure 34. Ipk Set−point is Frozen at Lower Power Demand.

Feedback and Skip

In this linear operating range, the dynamic resistance is

Figure 35 depicts the relationship between feedback

voltage and current. The feedback pin operates linearly as

19.5 kW typically (R

) and the effective pull up voltage

FB(up)

is 3.3 V typically (V

). When I is below 40 mA, the

FB(REF)

FB

the absolute value of feedback current (I ) is above 40 mA.

FB voltage will jump to close to 4.5 V.

FB

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Figure 35. Feedback Voltage vs. Current

Figure 36 depicts the skip mode block diagram. When the

FB current information reaches I , the internal clock to

comparator is minimized to lower the ripple of the auxiliary

voltage for V pin and V of power supply during skip

FBskip

CC

OUT

set the flip−flop is blanked and the internal consumption of

mode. It easies the design of V over load range.

CC

the controller is decreased. The hysteresis of internal skip

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20

NCV1072, NCV1075, NCV1076, NCV1077

Figure 36. Skip Cycle Schematic

Ramp Compensation and Ipk Set−point

Here we got a table of the ramp compensation, the initial

current set point, and the final current set−point of different

versions of switcher.

In order to allow the NCV107X to operate in CCM with

a duty cycle above 50%, a fixed slope compensation is

internally applied to the current−mode control.

Fsw

Sa

Ipk(Duty = 50%)

Ipk(0)

65 kHz

100 kHz

130 kHz

65 kHz

4.2 mA/ms

6.5 mA/ms

8.4 mA/ms

7.5 mA/ms

11.5 mA/ms

15 mA/ms

23 mA/ms

30 mA/ms

18 mA/ms

28 mA/ms

36 mA/ms

NCV1072

NCV1075

NCV1076

NCV1077

250 mA

282 mA

100 kHz

130 kHz

65 kHz

450 mA

650 mA

800 mA

508 mA

765 mA

940 mA

100 kHz

130 kHz

65 kHz

100 kHz

130 kHz

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21

NCV1072, NCV1075, NCV1076, NCV1077

The Figure 37 depicts the variation of I set−point vs. the power switcher duty ratio, which is caused by the internal ramp

PK

compensation.

Figure 37. I_PKSet−point Varies with Power Switch On Time, Which is Caused by the Ramp Compensation

Design Procedure

maximum voltage that can be reflected during t_off

.

The design of an SMPS around a monolithic device does

not differ from that of a standard circuit using a controller

and a MOSFET. However, one needs to be aware of certain

characteristics specific of monolithic devices. Let us follow

the steps:

As a result, the Flyback voltage which is reflected

on the drain at the switch opening cannot be larger

than the input voltage. When selecting

components, you thus must adopt a turn ratio

which adheres to the following equation:

V min = 90 Vac or 127 Vdc once rectified, assuming a low

bulk ripple

in

ǒ

Ǔ

N V_out) V_ft V_in,min

(eq. 3)

2. In our case, since we operate from a 127 V DC rail

while delivering 12 V, we can select a reflected

voltage of 120 Vdc maximum. Therefore, the turn

ratio Np:Ns must be smaller than

V max = 265 Vac or 375 Vdc

in

V

= 12 V

= 10 W

out

P

out

Operating mode is CCM

V_reflect

120

h = 0.8

+

+ 9.6

1. The lateral MOSFET body−diode shall never be

forward biased, either during start−up (because of

a large leakage inductance) or in normal operation

as shown by Figure 38. This condition sets the

12 ) 0.5

V

_out) V_f

or Np:Ns < 9.6. Here we choose N = 8 in this case.

We will see later on how it affects the calculation.

350

250

150

50.0

−50.0

> 0 !!

1.004M

1.011M

1.018M

1.025M

1.032M

Figure 38. The Drain−Source Wave Shall Always be Positive

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22

NCV1072, NCV1075, NCV1076, NCV1077

DI_L

K +

I_Lavg

and defines the amount of ripple we want in CCM

(see Figure 39).

♦ Small K: deep CCM, implying a large primary

inductance, a low bandwidth and a large

leakage inductance.

I

Lavg

♦ Large K: approaching BCM where the rms

losses are worse, but smaller inductance,

leading to a better leakage inductance.

From Equation 6, a K factor of 1 (50% ripple), gives

an inductance of:

2

(

)

127 0.44

L +

+ 3.8 mH

65k 1 12.75

V_in,min@ d_max

Figure 39. Primary Inductance Current Evolution in

CCM

127 0.44

3.8 65k

DI_L+

+

LF_SW

3. Lateral MOSFETs have a poorly doped

body−diode which naturally limits their ability to

sustain the avalanche. A traditional RCD clamping

network shall thus be installed to protect the

MOSFET. In some low power applications, a

simple capacitor can also be used since

+ 223 mA peak−to−peak

The peak current can be evaluated to be:

I_avg

d

DI_L

98m

0.44

I_peak

+

)

+ I_peak

+

)

2

+ 335 mA

L_f

On I , I

can also be calculated:

L

Lavg

ǒ

Ǔ

V

_drain,max+ V_in) N V_out) V_f) I_peak

Ǹ

C_tot

DI_L

I

_Lavg+ I_peak

*

+ 0.34 * 0.112 + 223 mA

(eq. 4)

2

6. Based on the above numbers, we can now evaluate

the conduction losses:

where L is the leakage inductance, C the total

f

tot

capacitance at the drain node (which is increased by

the capacitor you will wire between drain and

source), N the N :N turn ratio, V the output

2

DI_L

I_d,rms

+

²* I_peakDI_L)

_dǒ_I

Ǹ

P

S

out

peak

3

voltage, V the secondary diode forward drop and

f

finally, I_peakthe maximum peak current. Worse case

occurs when the SMPS is very close to regulation,

0.223²

3

2

_0.44ǒ_{0.335 * 0.335 @ 0.223 )}

+

Ǹ

e.g. the V target is almost reached and I_peakis still

out

pushed to the maximum. For this design, we have

+ 154 mA

selected our maximum voltage around 650 V (at V

in

= 375 Vdc). This voltage is given by the RCD clamp

installed from the drain to the bulk voltage. We will

see how to calculate it later on.

If we take the maximum R

temperature, i.e. 24 W, then conduction losses worse

case are:

for a 125°C junction

ds(on)

4. Calculate the maximum operating duty−cycle for

this flyback converter operated in CCM:

P

_cond+ I_d,rms²R_DS(on)+ 570 mW

7. Off−time and on−time switching losses can be

ǒ

Ǔ

N V_out) V_f

1

estimated based on the following calculations:

d_max

+

+ 0.44

V

ǒ

Ǔ

N V_out) V_f) V_in,min

in,min

1 )

ǒ_V

Ǔ

I_{peak bulk}) V_clampt_off

_Nǒ_{V )V}Ǔ

(eq. 5)

out

f

P_off

+

2T_sw

5. To obtain the primary inductance, we have the

choice between two equations:

(eq. 7)

(

)

0.335 127 ) 120 @ 2 10n

2 15.4m

ǒ

Ǔ²

V_ind

(eq. 6)

L +

+ 36 mW

f_swKP_in

where

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23

NCV1072, NCV1075, NCV1076, NCV1077

Where, assume the V

reflected voltage.

is equal to two times of

8. The theoretical total power is then 0.570 + 0.036 +

clamp

0.0055 = 611 mW

9. If the NCV107X operates at DSS mode, then the

losses caused by DSS mode should be counted as

losses of this device on the following calculation:

ǒ

ǓǓ

I_valleyV_bulk) N V_out) V_ft_on

P_on

+

6T_sw

P

_DSS+ I_CC1@ V_in,max+ 1m @ 375 + 375 mW

(eq. 8)

(

)

0.111 127 ) 100 20n

(eq. 9)

6 15.4m

+ 5.5 mW

MOSFET protection

As in any Flyback design, it is important to limit the drain

excursion to a safe value, e.g. below the MOSFET BVdss

which is 670 V. Figure 40a, b, c present possible

implementations:

It is noted that the overlap of voltage and current seen

on MOSFET during turning on and off duration is

dependent on the snubber and parasitic capacitance

seen from drain pin. Therefore the t and t in

off

on

Equations 7 and 8 have to be modified after

measuring on the bench.

a

b

c

Figure 40. Different Options to Clamp the Leakage Spike

Figure 40a: the simple capacitor limits the voltage

according to The lateral MOSFET body−diode shall never

be forward biased, either during start−up (because of a large

leakage inductance) or in normal operation as shown by

Figure 38. This condition sets the maximum voltage that can

V

is usually selected 50−80 V above the reflected

clamp

value N x (V + V ). The diode needs to be a fast one and

a MUR160 represents a good choice. One major drawback

of the RCD network lies in its dependency upon the peak

out

f

current. Worse case occurs when I

and V are maximum

peak

in

be reflected during t . As a result, the Flyback voltage

and V is close to reach the steady−state value.

off

out

which is reflected on the drain at the switch opening cannot

be larger than the input voltage. When selecting

components, you thus must adopt a turn ratio which adheres

to the following equation: Equation 3. This option is only

valid for low power applications, e.g. below 5 W, otherwise

chances exist to destroy the MOSFET. After evaluating the

leakage inductance, you can compute C with Equation 4.

Typical values are between 100 pF and up to 470 pF. Large

capacitors increase capacitive losses...

Figure 40c: this option is probably the most expensive of

all three but it offers the best protection degree. If you need

a very precise clamping level, you must implement a zener

diode or a TVS. There are little technology differences

behind a standard zener diode and a TVS. However, the die

area is far bigger for a transient suppressor than that of zener.

A 5 W zener diode like the 1N5388B will accept 180 W peak

power if it lasts less than 8.3 ms. If the peak current in the

worse case (e.g. when the PWM circuit maximum current

limit works) multiplied by the nominal zener voltage

exceeds these 180 W, then the diode will be destroyed when

the supply experiences overloads. A transient suppressor

like the P6KE200 still dissipates 5 W of continuous power

but is able to accept surges up to 600 W @ 1 ms. Select the

zener or TVS clamping level between 40 to 80 V above the

reflected output voltage when the supply is heavily loaded.

Figure 40b: the most standard circuitry is called the RCD

network. You calculate R

and C

using the

clamp

following formulae:

ǒ

Ǔ

ǒ

Ǔ

2 V_clampV_clamp* V_out) V_fN

(eq. 10)

(eq. 11)

R_clamp

+

L_{leak peak}

V_clamp

V_rippleF_swR_clamp

I

²F_sw

C_clamp

+

www.onsemi.com

24

NCV1072, NCV1075, NCV1076, NCV1077

Power Dissipation and Heatsinking

The NCV107X welcomes two dissipating terms, the DSS

current−source (when active) and the MOSFET. Thus, P

75°C/W and thus dissipate more power. The maximum

power the device can thus evacuate is:

tot

T

_Jmax* T_ambmax

(eq. 12)

= P

+ P . It is mandatory to properly manage the

MOSFET

DSS

P_max+

R_qJA

heat generated by losses. If no precaution is taken, risks exist

to trigger the internal thermal shutdown (TSD). To help

dissipating the heat, the PCB designer must foresee large

copper areas around the package. Take the PDIP−7 package

as an example, when surrounded by a surface greater than

which gives around 930 mW for an ambient of 50°C and a

maximum junction of 120°C. If the surface is not large

enough, assuming the R

is 100°C/W, then the maximum

qJA

power the device can evacuate becomes 700 mW. Figure 41

gives a possible layout to help drop the thermal resistance.

2

1.0 cm of 35 mm copper, it becomes possible to drop its

thermal resistance junction−to−ambient, R

down to

qJA

Figure 41. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient

A 10 W NCV1075 based Flyback Converter Featuring

Low Standby Power

is made via a NCP431 whose low bias current (50 mA) helps

to lower the no load standby power.

Figure 43 depicts a typical application showing a

NCV1075−65 kHz operating in a 10 W converter. To leave

more room for the MOSFET, it is recommended to disable

the DSS by shorting the J3. In this application, the feedback

Measurements have been taken from a demonstration

board implementing the diagram in Figure 43 and the

following results were achieved with auxiliary winding to

bias the device:

100 Vac

115 Vac

230 Vac

265 Vac

No load consumption with

auxiliary winding

26 mW

28 mW

38 mW

45 mW

www.onsemi.com

25

NCV1072, NCV1075, NCV1076, NCV1077

Figure 42. V_out= 12 V

R_L3

15

T1

MA5597−AL

C9

10 nF

Figure 43. A 12 V – 0.85 A Universal Mains Power Supply

www.onsemi.com

26

NCV1072, NCV1075, NCV1076, NCV1077

ORDERING INFORMATION

(Only options marked with * are qualified and released to market. Other options available upon customer request.)

Brown−in

Function

Yes

No

Device

Frequency

65 kHz

R

(W)

Ipk (mA)

250

450

650

800

250

450

650

800

DS(on)

NCV1072P065G

NCV1072P100G

NCV1075P065G*

NCV1075P100G*

NCV1075P130G

NCV1076P065G*

NCV1076P100G*

NCV1076P130G

NCV1077P065G*

NCV1077P100G

NCV1077P130G

NCV1072STAT3G

NCV1072STBT3G

NCV1075STAT3G

NCV1075STBT3G

NCV1075STCT3G

NCV1076STAT3G

NCV1076STBT3G

NCV1076STCT3G

NCV1077STAT3G

NCV1077STBT3G*

NCV1077CSTBT3G*

NCV1077STCT3G

11

100 kHz

65 kHz

11

100 kHz

130 kHz

65 kHz

11

4.7

11

100 kHz

130 kHz

65 kHz

100 kHz

130 kHz

65 kHz

100 kHz

65 kHz

11

100 kHz

130 kHz

65 kHz

11

4.7

100 kHz

130 kHz

65 kHz

100 kHz

130 kHz

†

Yes

Package Type

Shipping

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

27

NCV1072, NCV1075, NCV1076, NCV1077

PACKAGE DIMENSIONS

PDIP−7 (PDIP−8 LESS PIN 6)

CASE 626A

ISSUE C

NOTES:

D

A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

E

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-

AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.

4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH

OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE

NOT TO EXCEED 0.10 INCH.

H

8

5

4

E1

5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM

PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR

TO DATUM C.

1

6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE

LEADS UNCONSTRAINED.

7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE

LEADS, WHERE THE LEADS EXIT THE BODY.

8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE

CORNERS).

NOTE 8

c

b2

B

END VIEW

WITH LEADS CONSTRAINED

NOTE 5

TOP VIEW

INCHES

DIM MIN MAX

−−−−

A1 0.015

MILLIMETERS

A2

A

MIN

−−−

0.38

2.92

0.35

MAX

5.33

−−−

4.95

0.56

e/2

A

0.210

−−−−

NOTE 3

A2 0.115 0.195

L

b

b2

C

0.014 0.022

0.060 TYP

0.008 0.014

0.355 0.400

1.52 TYP

0.20

9.02

0.13

7.62

6.10

0.36

10.16

−−−

8.26

7.11

D

SEATING

PLANE

D1 0.005

0.300 0.325

E1 0.240 0.280

−−−−

A1

D1

E

C

M

e

eB

L

0.100 BSC

−−−− 0.430

0.115 0.150

−−−− 10°

2.54 BSC

−−−

2.92

−−−

10.92

3.81

10°

e

eB

8X

b

END VIEW

M

NOTE 6

M

B

0.010

C A

SIDE VIEW

www.onsemi.com

28

NCV1072, NCV1075, NCV1076, NCV1077

PACKAGE DIMENSIONS

SOT−223 (TO−261)

CASE 318E−04

ISSUE N

D

b1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCH.

MILLIMETERS

INCHES

NOM

0.064

0.002

0.030

0.121

0.012

0.256

0.138

0.091

0.037

−−−

4

2

DIM

A

A1

b

b1

c

D

E

e

e1

L

L1

MIN

1.50

0.02

0.60

2.90

0.24

6.30

3.30

2.20

0.85

0.20

1.50

6.70

NOM

1.63

0.06

0.75

3.06

0.29

6.50

3.50

2.30

0.94

−−−

1.75

7.00

−

MAX

1.75

0.10

0.89

3.20

0.35

6.70

3.70

2.40

1.05

−−−

MIN

MAX

0.068

0.004

0.035

0.126

0.014

0.263

0.145

0.094

0.041

−−−

H

E

0.060

0.001

0.024

0.115

0.009

0.249

0.130

0.087

0.033

0.008

0.060

0.264

1

3

b

e1

e

2.00

7.30

0.069

0.276

−

0.078

0.287

C

q

H

E

A

q

0.08 (0003)

A1

L

L1

0°

10°

0°

10°

SOLDERING FOOTPRINT

3.8

0.15

2.0

0.079

6.3

0.248

2.3

0.091

2.3

0.091

2.0

0.079

mm

inches

1.5

0.059

ǒ

Ǔ

SCALE 6:1

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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

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◊

NCV1070/D

www.onsemi.com

29


型号：	NCV1077P065G
厂家：	ONSEMI
描述：	Automotive High-Voltage Switcher for Low Power SMPS
文件：	总29页 (文件大小：814K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV1077P065G [ONSEMI]

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