NCV1362ABDR2G [ONSEMI]
Automotive Primary Side Flyback Controller;型号: | NCV1362ABDR2G |
厂家: | ONSEMI |
描述: | Automotive Primary Side Flyback Controller |
文件: | 总31页 (文件大小:644K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Automotive Primary Side
Flyback Controller
NCV1362
The NCV1362 is a highly integrated primary side quasi−resonant
flyback controller capable of controlling rugged and
high−performance off−line power supplies.
Thanks to a Novel Method this new controller saves the secondary
feedback circuitry for Constant Voltage and Constant Current
regulation, achieving excellent line and load regulation without
traditional opto coupler and TL431 voltage reference.
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8
The NCV1362 operates in valley lockout quasi−resonant peak
current mode control mode at high load to provide high efficiency.
When the power on the secondary side starts to diminish, the
controller automatically adjusts the duty−cycle then at lower load the
controller enters in pulse frequency modulation at fixed peak current
with a valley switching detection. This technique allows keeping the
output regulation with tiny dummy load. Valley lockout at the first 4
valleys prevent valley jumping operation and then a valley switching
at lower load provides high efficiency.
1
SOIC−8
CASE 751−07
MARKING DIAGRAM
8
V1362yy
ALYW
G
Features
1
• Qualified for Automotive Applications
IC (Pb−Free)
• AEC−Q100 Qualified with the Following Results
♦ Device Temperature Grade 1: −40°C to +125°C
♦ Device HBM Classification Level 2: 2 kV
• Constant Voltage Primary−Side Regulation < 5%
V1362yy = Specific Device Code
(See page 28)
A
L
Y
W
G
= Assembly Location
= Wafer Lot
• Constant Current Primary−Side Regulation < 5%
• LFF and BO Feature on a Dedicated Pin:
= Year
= Work Week
= Pb−Free Package
• Quasi−Resonant with Valley Switching Operation
• Optimized Light Load Efficiency and Stand−by Performance
• Maximum Frequency Clamp (No Clamp, 80, 110 and 140 kHz)
• Cycle by Cycle Peak Current Limit
PINOUT DIAGRAM
1
Vs/ZCD
BO/LFF
VCC
GND
• Output Voltage Under Voltage and Over Voltage Protection
COMP
Fault
CS
(UVP or OVP)
DRV
• Secondary Diode or Winding Short−Circuit Protection
(Top View)
• Wide Operation V Range (up to 28 V)
CC
• Low Start−up Current
• CS & V /ZCD Pin Short and Open Protection
S
ORDERING INFORMATION
See detailed ordering and shipping information on page 28 of
this data sheet.
• Internal Temperature Shutdown
• Internal and Fixed Frequency Jittering for Better EMI Signature
• Dual Frozen Peak Current to Both Optimize Light Load Efficiency
(10% Load) and Stand−by Performance (No−load)
• Fault Input for Severe Fault Conditions, NTC Compatible for OTP
• These are Pb−Free Devices
Applications
• Automotive Auxiliary Power Supplies
• On−Board Charger & Traction Inverters Auxiliary Power Supplies
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
June, 2021 − Rev. 4
NCV1362/D
NCV1362
2
0
Ac
Ac
Out
3
5
0
4
1
RTN_Out
NCV1362
VS/ZCD
1
2
3
4
8
7
6
5
BO/LFF
VCC
COMP
Fault
CS
GND
2
DRV
0
Figure 1. NCV1362 Typical Application Schematic for AC Input Voltage
2
0
Dc+
Out
Dc−
3
5
0
4
1
RTN_Out
NCV1362
VS/ZCD
1
2
3
4
8
7
6
5
BO/LFF
VCC
COMP
Fault
CS
GND
2
DRV
0
Figure 2. NCV1362 Typical Application Schematic for DC Input Voltage
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2
NCV1362
Line
FeedForward
POReset
UVLO
I%VBO
Vdd
Vcc
VCC and Logic
Management of
double hiccup
VCC (Reset)
VCC (OVP)
DbleHiccup
POReset
EN_UVP
Double_Hiccup_ends
BO/LFF
SS
Reset
Soft Start
BO_EN
BO_DIS
Blanking
VBO (EN)
VBO (ON)
VHL(on)
QR multi−mode
Valley lockout &
Valley Switching
BO_OK
&
VCO management
Sampled Vout
Vs /
ZCD
Zero Crossing &
Signal Sampling
SS
FB_CC
Control Law
FB
CC
&
High_Line
Control
Primary Peak
Current Control
Vref_CC
FB_CV
UVLO
S
Q
R
V
VCC(OVP)
cc
OVP_Cmp
4 clk
Counter
UVP
SCP
Clamp
OVP
126% Vref_CV 1
DRV
GND
UVP_Cmp
EN_UVP
OTA
Comp
S
R
UVP
DbleHiccup
Q
POReset
VUVP
Vref_CV1
Peak current
Control
VDD
VDD
ICS
1/Kcomp
FB Reset
Vfault(OVP)
VDD
VJitter
ICS_EN
Fault
LEB1
CS
Max_Ipk reset
OCP
Timer
Reset Timer
Count
OCP
VFault (OTP)
VILIM
POReset
Fault
DbleHiccup
R
Q
S
Reset
Counter
SSend
LEB2
Vfault (EN )
4 clk
SCP
Counter
VCS(Stop )
Note:
CS pin Fault
OVP: Over Voltage Protection
UVP: Under Voltage Protection
OCP: Over Current Protection
SCP: Short Circuit Protection
CS pin Open (VCS > 1.2
V) & Short (VCS < 50
mV) detection is
ICS_EN
activated at each startup
t
LEB1 > tLEB2
Figure 3. Functional Block Diagram
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3
NCV1362
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Function
1
V /ZCD
s
Connected to the auxiliary winding; this pin senses the voltage output for the primary regula-
tion and detects the core reset event for the Quasi−Resonant mode of operation.
2
3
Comp
Fault
This is the error amplifier output. The network connected between this pin and the ground
adjusts the regulation loop bandwidth.
The controller enters in fault mode if the voltage of this pin is pulled above or below the fault
thresholds. A precise pullup current allows direct interface with an NTC thermistor. Fault de-
tection triggers a latch.
4
5
6
7
8
CS
This pin monitors the primary peak current.
DRV
GND
The driver’s output to an external MOSFET gate.
Ground reference.
V
CC
This pin is connected to an external auxiliary voltage and supplies the controller.
BO/LFF
Detects too low input voltage conditions (Brown−Out). Also voltage pin level is used for build-
ing Line FeedForward compensation for improving Constant Current regulation tolerance.
Table 2. MAXIMUM RATINGS (Note 1)
Symbol
Rating
Value
Unit
V
Maximum Power Supply voltage, V pin, continuous voltage
−0.3 to 28
Internally limited
V
mA
CC(MAX)
CC(MAX)
CC
I
Maximum current for V pin
CC
DV /Dt
Maximum slew rate on V pin during start−up phase
+0.4
120
V/ms
CC
CC
E
as
Single Pulse Avalanche Rating
mJ
V
Maximum voltage on low power pins (except pins DRV and VCC)
Current range for low power pins (except pins DRV and VCC)
−0.3, 5.5
−2, +5
V
mA
MAX
MAX
I
V
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, V
(Note 2)
V
mA
DRV(MAX)
DRV(MAX)
DRV
I
−300, +500
R
Thermal Resistance Junction−to−Air, 2.0 oz Printed Circuit Copper Clad
Maximum Junction Temperature
190
150
°C/W
°C
°C
°C
kV
V
θ
J−A
T
J(MAX)
Operating Temperature Range
−40 to +125
−60 to +150
2
Storage Temperature Range
Human Body Model ESD Capability per JEDEC JESD22−A114F
Machine Model ESD Capability (All pins except DRV) per JEDEC JESD22−A115C
Charged−Device Model ESD Capability per JEDEC JESD22−C101E
200
500
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
2. V
is the DRV clamp voltage V
when V is higher than V
. V
is V otherwise.
DRV
DRV(high)
CC
DRV(high) DRV CC
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NCV1362
Table 3. ELECTRICAL CHARACTERISTICS
(V = 12 V, For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C, unless otherwise noted)
CC
j
j
j
Characteristics
SUPPLY SECTION AND V MANAGEMENT
Condition
Symbol
Min
Typ
Max
Unit
CC
V
Level at which Driving Pulses
V
increasing
V
V
16.5
6.0
−
18
6.5
19.5
7.0
−
V
V
V
CC
CC
CC(on)
are Authorized
V
CC
Level at which Driving Pulses
V
CC
decreasing
CC(off)
are Stopped
Internal Latch/Logic Reset
Level
V
6.25
CC(reset)
Internal Autorecovery Reset Level
(Note 4)
V
0.6
−
−
−
V
V
CC(reset_auto)
Hysteresis above V
for Fast
V
−
0.2
CC(off)
CC(latch_hyst)
Hiccup in Latch Mode
Hysteresis below V
before Latch Reset
V
0.15
0.30
0.50
V
CC(off)
CC(reset_hyst)
Over Voltage Protection
Over Voltage threshold
V
24
–
26
28
V
CC(OVP)
Start−up Supply Current,
Controller Disabled or Latched
V
CC
< V
& V
CC
I
4.3
7.0
mA
CC(on)
CC(start)
increasing from 0 V
Internal IC Consumption, Steady
State
F
= 65 kHz
I
–
1.6
2.3
mA
SW
L
CC(steady)
C = 1 nF
Internal IC Consumption in
Minimum Frequency Clamp
VCO mode, F
= f
,
I
CC(VCO)
mA
SW
VCO(min)
V
= GND
Comp
f
f
= 1 kHz
= 200 Hz
–
–
325
210
430
370
VCO(min)
VCO(min)
C = 1 nF
L
Internal IC Consumption in Fault
Autorecovery mode
Latch mode
I
–
–
2.0
1.0
2.2
1.2
mA
mA
CC(auto)
Mode (after a fault when V
CC
decreasing to V
)
CC(off)
Internal IC Consumption in Fault
Mode (after a fault when V
I
CC(latch)
CC
decreasing to V
)
CC(off)
CURRENT COMPARATOR
Current Sense Voltage
Threshold
V
V
= V
,
V
0.76
250
–
0.8
320
50
0.84
380
110
90
V
ns
ns
ms
V
Comp
CS
Comp(max)
ILIM
increasing
Cycle by Cycle Leading Edge
Blanking Duration
t
LEB1
Cycle by Cycle Current Sense
Propagation Delay
V
CS
> (V
+ 100 mV) to
t
ILIM
ILIM
DRV turn−off
Timer Delay before Detecting an
Overload Condition
When CS pin w V
(Note 3)
T
OCP
50
1.10
−
70
ILIM
Threshold for Immediate Fault
Protection Activation
V
1.20
120
250
1.30
−
CS(stop)
Leading Edge Blanking
t
ns
mV
LEB2
Duration for V
CS(stop)
Maximum Peak Current Level at
which VCO Takes Over or Frozen
Peak Current
V
CS
increasing
V
−
−
CS(VCO)
0.6 V < V
< 1.9 V
Comp
(other possible options on
demand)
Minimum Peak Current Level
V
V
increasing
Comp
V
−
65
−
mV
CS
CS(STB)
< 0.2 V
(other possible options on
demand)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions.
4. Guaranteed by Design.
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NCV1362
Table 3. ELECTRICAL CHARACTERISTICS
(V = 12 V, For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C, unless otherwise noted)
CC
j
j
j
Characteristics
Condition
Symbol
Min
Typ
Max
Unit
REGULATION BLOCK
Internal Voltage Reference for
Constant Current Regulation
T = 25°C
−40°C < T < 125°C
V
0.98
0.97
1.00
1.00
1.02
1.03
V
V
J
ref_CC
J
Internal Voltage Reference for
Constant Voltage Regulation
T = 25°C
V
2.450
2.425
2.500
2.500
2.550
2.575
J
ref_CV1
−40°C < T < 125°C
J
Error Amplifier Current
Capability
I
EA
−
40
−
mA
Error Amplifier Gain
G
150
200
250
mS
EA
Error Amplifier Output Voltage
Internal offset on Comp pin
V
−
−
−
4.9
0
1.1
−
−
−
V
Comp(max)
Comp(min)
V
V
Comp(offset)
Internal Current Setpoint
Division Ratio
K
Comp
−
4
−
–
Valley Thresholds
V
st
nd
rd
th
Transition from 1 to 2 Valley
V
Comp
V
Comp
V
Comp
V
Comp
V
Comp
V
Comp
V
Comp
V
Comp
decreasing
decreasing
decreasing
decreasing
increasing
increasing
increasing
increasing
V
−
−
−
−
−
−
−
−
2.50
2.30
2.10
1.90
2.50
2.70
2.90
3.10
−
−
−
−
−
−
−
−
H2D
H3D
H4D
nd
Transition from 2 to 3 Valley
V
rd
Transition from 3 to 4 Valley
V
th
Transition from 4 Valley to VCO
V
HVCOD
V
HVCOI
th
Transition from VCO to 4 Valley
th
rd
nd
st
Transition from 4 to 3 Valley
V
V
V
H4I
H3I
H2I
rd
Transition from 3 to 2 Valley
nd
Transition from 2 to 1 Valley
Minimal Difference between any
Two Valleys
V
increasing or V
DV
H
176
−
−
mV
Comp
Comp
decreasing
Internal Dead Time Generation for
VCO Mode
Entering in VCO when
T
−
1.15
−
ms
DT(start)
V
is decreasing and
Comp
crosses V
HVCOD
Internal Dead Time Generation for
VCO Mode
Leaving VCO mode when
is increasing and
T
−
650
−
ns
DT(ends)
V
Comp
crosses V
HVCOI
Internal Dead Time Generation for
VCO Mode
When in VCO mode –
T
DT
ms
1−kHz option
V
Comp
V
Comp
V
Comp
V
Comp
= 1.8 V
= 1.4 V
= 0.9 V
< 0.2 V
−
−
−
−
1.6
11
110
1000
−
−
−
−
Minimum Switching Frequency in
VCO Mode
V
= GND
Option 1
Option 2
f
kHz
kHz
ms
Comp
VCO(MIN)
0.8
1.0
1.2
0.16
0.200
0.24
(other possible options on
demand)
Maximum Switching Frequency
f
MAX
Option 1
Option 2
Option 3
Option 4
−
No Clamp
80
−
88
121
153
72
99
110
140
127
Maximum On Time
T
32
36
40
on(max)
DEMAGNETIZATION INPUT – ZERO VOLTAGE DETECTION CIRCUIT and VOLTAGE SENSE
V
ZCD
V
ZCD
Threshold Voltage
Hysteresis
V
ZCD
V
ZCD
decreasing
increasing
V
ZCD(TH)
25
15
45
30
70
45
mV
mV
V
ZCD(HYS)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions.
4. Guaranteed by Design.
www.onsemi.com
6
NCV1362
Table 3. ELECTRICAL CHARACTERISTICS
(V = 12 V, For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C, unless otherwise noted)
CC
j
j
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Characteristics
Condition
Symbol
Min
Typ
Max
Unit
DEMAGNETIZATION INPUT – ZERO VOLTAGE DETECTION CIRCUIT and VOLTAGE SENSE
Threshold Voltage for Output
Short Circuit or Aux. Winding
Short Circuit Detection
After t
ZCD
if
V
30
50
75
mV
BLANK_ZCD
ZCD(short)
V
< V
ZCD(short)
Delay after On−time that the
S
When V
When V
> 1.7 V
t
−
−
0.750
0.350
−
−
ms
ms
Comp
Comp
short_ZCD
V /ZCD is still Pulled to Ground
< 1.7 V
Blanking Delay after On−time
When V
When V
> 1.7 V
< 1.7 V
t
−
−
1.450
0.750
−
−
Comp
Comp
BLANK_ZCD
(V /ZCD Pin is Disconnected from
S
the Internal Circuitry)
Timeout after Last
t
4.0
−
4.5
−
5.0
0.1
−
ms
mA
ns
out
Demagnetization Transition
Input Leakage Current
V
> V
V
= 4 V,
I
ZCD
CC
CC(on) ZCD
DRV is low
Delay from Valley Detection to
DRV Low
t
−
290
ZCD_delay
DRIVE OUTPUT − GATE DRIVE
Drive resistance
DRV Sink − V = 8 V
R
SNK
R
SRC
−
−
8
10
−
−
W
CC
DRV Source − V = 8 V
CC
Rise time
C
C
= 1 nF, from 10% to 90%
= 1 nF, from 90% to 10%
t
−
−
45
30
−
85
65
−
ns
ns
V
DRV
DRV
r
Fall time
t
f
DRV Low voltage
V
CC
= V
+ 0.2 V, C
V
6.0
CC(off)
DRV
DRV(low)
= 220 pF, R
= 33 kW
DRV
DRV High voltage
V
= V
− 0.2 V, C
= 33 kW
V
−
12.0
13.0
V
CC
CC(OVP)
DRV
DRV(high)
= 220 pF, R
DRV
SOFT START
Internal Fixed Soft Start Duration
Current Sense peak current
t
SS
3
4
5
ms
rising from V
to V
CS(VCO)
ILIM
JITTERING
Frequency of the Jittering CS Pin
Source Current
Option 1
(other possible options on
demand)
f
1.2
1.5
60
1.8
kHz
mV
jitter
Peak Jitter Voltage Added to
PWM Comparator
Option 1
(other possible options on
demand)
V
−
−
jittter
BROWN−OUT & LINE FEED FORWARD
Brown−out Function is Disabled
V
BO(en)
80
100
120
mV
st
below this Level (before the 1
DRV pulse only)
Pull−down Current Source on BO
I
−
300
0.80
0.70
50
−
nA
V
BO
Pin for Open Detection
Brown−out Level at which the
Controller Starts Pulsing
V
V
0.75
0.65
−
0.85
0.75
−
BO(on)
Brown−out Level at which the
Controller Stops Pulsing
V
BO(off)
Brown−out Filter Time
t
ms
BO
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions.
4. Guaranteed by Design.
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7
NCV1362
Table 3. ELECTRICAL CHARACTERISTICS
(V = 12 V, For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C, unless otherwise noted)
CC
j
j
j
Characteristics
Condition
Symbol
Min
Typ
Max
Unit
BROWN−OUT & LINE FEED FORWARD
Line Feed Forward Compensation
Gain
K
LFF
16
20
24
mA/
V
FAULT PROTECTION
Controller Thermal Shutdown
Thermal Shutdown Hysteresis
Fault Level Detection for OVP
Device switching
(F ∼ 65 kHz) – T rising
T
T
−
−
150
120
3.15
−
−
°C
°C
V
SHTDN(on)
SW
j
Device switching
(F ∼ 65 kHz) − T falling
SHTDN(off)
SW
j
Internal sampled V
increasing
V
V
2.95
3.35
out
OVP
V
= V
+ 26%
OVP
ref_CV1
Fault Level Detection for UVP →
Double Hiccup Autorecovery
Internal sampled V
decreasing
1.40
1.50
1.60
V
out
UVP
(UVP detection is disabled during
T
)
EN_UVP
Blanking Time for UVP Detection
Starting after the Soft start
T
−
−
36
60
−
−
ms
EN_UVP
Pull−up Current Source on CS Pin
for Open or Short Circuit Detec-
tion
When V > V
I
CS
mA
CS
CS_min
CS Pin Open Detection
CS pin open
(Note 4)
V
−
1.2
−
V
CS(open)
CS Pin Short Detection
V
−
−
50
3
75
−
mV
ms
CS_min
CS_short
Fault(EN)
CS pin Short Detection Timer
Fault Pin is Disabled below this
T
V
80
100
120
mV
st
Level (before the 1 DRV pulse
only)
Overvoltage Protection (OVP)
Threshold
V
V
V
increasing
V
V
2.79
0.38
3.00
0.40
3.21
0.42
V
V
Fault
Fault
Fault
Fault(OVP)
Overtemperature Protection
(OTP) Threshold
decreasing
Fault(OTP)
OTP Pull−up Current Source
= 0 V
T = 25°C
mA
I
42.5
42.9
45.0
45.0
47.5
46.5
j
j
Fault(OTP)
T = 110°C
I
Fault(OTP_110)
Fault Input Clamp Voltage
Fault Input Clamp Voltage
Fault Filter Time
I
= 0 mA (V
= open)
V
V
1.10
2.2
−
1.35
2.7
2
1.60
3.2
−
V
V
Fault
Fault
Fault
Fault(clamp)0
I
= 1 mA
Fault(clamp)1
t
ms
−
Fault(filter)
Number of Drive Cycle before
Latch Confirmation
V
V
= V
CS(stop)
,
t
latch(count)
−
4
−
Comp
Comp(max)
> V
CS
or Internal rebuilded
> V
V
out
OVP
Fault
ZCD(short)
or 0.40 V < V
< 3.00 V
or V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions.
4. Guaranteed by Design.
www.onsemi.com
8
NCV1362
TYPICAL CHARACTERISTICS
18.09
18.07
18.05
18.03
18.01
17.99
17.97
17.95
6.59
6.585
6.58
6.575
6.57
6.565
6.56
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
125
125
TEMPERATURE (5C)
Figure 4. VCC(on) vs. Junction Temperature
TEMPERATURE (5C)
Figure 5. VCC(off) vs. Junction Temperature
5.2
6.292
4.7
4.2
3.7
3.2
2.7
2.2
6.287
6.282
6.277
6.272
6.267
6.262
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
125
TEMPERATURE (5C)
Figure 6. VCC(reset) vs. Junction Temperature
TEMPERATURE (5C)
Figure 7. ICC(start) vs. Junction Temperature
316.5
0.808
316
315.5
315
0.806
0.804
0.802
0.8
314.5
314
313.5
313
0.798
0.796
0.794
312.5
312
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
125
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 8. VILIM vs. Junction Temperature
Figure 9. tLEB1 vs. Junction Temperature
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9
NCV1362
TYPICAL CHARACTERISTICS (Continued)
1.209
1.207
1.205
1.203
1.201
1.199
1.197
1.195
1.193
1.191
74
69
64
59
54
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
125
125
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 10. tILIM vs. Junction Temperature
Figure 11. VCS(stop) vs. Junction Temperature
70
254
253
252
251
250
249
248
247
246
69.5
69
68.5
68
67.5
67
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 12. VCC(VCO) vs. Junction Temperature
Figure 13. VCS(STB) vs. Junction Temperature
1.013
1.011
1.009
1.007
1.005
1.003
1.001
0.999
0.997
0.995
2.51
2.505
2.5
2.495
2.49
2.485
2.48
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 14. Vref CC vs. Junction Temperature
Figure 15. Vref CV1 vs. Junction Temperature
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10
NCV1362
TYPICAL CHARACTERISTICS (Continued)
48
47.5
47
57.7
57.2
56.7
56.2
55.7
55.2
54.7
54.2
53.7
53.2
46.5
46
45.5
45
44.5
44
43.5
43
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 16. VZCD(TH) vs. Junction Temperature
Figure 17. VZCD(short) vs. Junction Temperature
1.56
1.555
1.55
3.17
3.16
3.15
3.14
3.13
3.12
1.545
1.54
−50
−25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 18. VOVP vs. Junction Temperature
Figure 19. VUVP vs. Junction Temperature
0.84
0.839
0.838
0.837
0.836
0.835
36.32
36.27
36.22
36.17
36.12
36.07
36.02
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 20. TEN UVP vs. Junction Temperature
Figure 21. VBO(on) vs. Junction Temperature
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11
NCV1362
TYPICAL CHARACTERISTICS (Continued)
0.695
0.693
0.691
0.689
0.687
0.685
21.63
21.61
21.59
21.57
21.55
21.53
21.51
21.49
21.47
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 22. VBO(off) vs. Junction Temperature
Figure 23. KLFF vs. Junction Temperature
106.5
3.011
3.006
3.001
2.996
2.991
2.986
2.981
2.976
2.971
2.966
105.5
104.5
103.5
102.5
101.5
100.5
-50
-25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 24. VFault(EN) vs. Junction Temperature
Figure 25. VFault(OVP) vs. Junction Temperature
0.407
45.3
0.406
0.405
0.404
0.403
0.402
0.401
0.4
45.2
45.1
45
44.9
44.8
44.7
44.6
44.5
44.4
0.399
0.398
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 26. VFault(OTP) vs. Junction Temperature
Figure 27. IFault(OTP) vs. Junction Temperature
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12
NCV1362
Table 4. FAULT MODES
Event
Timer Protection
Next Device Status
Release to Normal Operation Mode
Overcurrent
OCP Timer
Double Hiccup
− Resume to normal operation: if 4 pulses from
FB Reset & then Reset timer
V
> V
CS
ILIM
− Resume operation after Double Hiccup
Winding Short
> V
4 Consecutive Pulses
Double Hiccup
Double Hiccup
Double Hiccup
Resume operation after Double Hiccup
V
with V > V
CS
CS(stop)
CS CS(stop)
CS Pin Fault:
Short & Open
Before Start−up
Immediate
Resume operation after Double Hiccup
Resume operation after Double Hiccup
ZCD Short
4 Consecutive Pulses
V
< V
BLANK_ZCD
after
ZCD
ZCD(short)
t
time
Low Supply
< V
10−ms Timer
10−ms Timer
Simple Hiccup
Double Hiccup
Double Hiccup
Resume operation after Simple Hiccup
Resume operation after Double Hiccup
Resume operation after Double Hiccup
V
CC
CC(off)
High Supply
> V
V
CC
CC(ovp)
Internal V
out
4 Consecutive Pulses
out
OVP: V > 126% V
ref_CV1
Internal V
out
4 Consecutive Pulses
Double Hiccup
Double Hiccup
Resume operation after Double Hiccup
out
ref_CV1
UVP: V < 60% V
,
when V is Decreasing Only
out
Internal TSD
10−ms Timer
Resume operation after Double Hiccup &
T < (T
)
SHTDN(off)
NOTE: Latching off protection available upon request.
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13
NCV1362
APPLICATION INFORMATION
The NCV1362 is a flyback power supply controller
providing a means to implement primary side constant−
current regulation and secondary side constant−voltage
regulation. NCV1362 implements a current−mode
architecture operating in quasi−resonant mode. The
controller prevents valley−jumping instability and steadily
locks out in a selected valley as the power demand goes
down. As long as the controller is able to detect a valley, the
new cycle or the following drive remains in a valley. Thanks
to a dedicated valley detection circuitry operating at any line
and load conditions, the power supply efficiency will always
be optimized. In order to prevent any high switching
frequency two frequency clamp options are available.
• Soft−Start: 4−ms internal fixed soft start guarantees
a peak current starting from zero to its nominal value
with smooth transition in order to prevent any
overstress on the power components at each startup.
• Cycle−by−Cycle Peak Current Limit: If the max peak
current reaches the V
level, the over current
ILIM
protection timer is enabled and starts counting. If the
overload lasts T delay, then the fault is detected and
OCP
the controller stops immediately driving the power
MOSFET. The controller enters in a double hiccup
mode before autorecovering with a new startup cycle.
• V Over Voltage Protection: If the V voltage
CC
CC
reaches the V
threshold the controller enters in
CC(OVP)
• Quasi−Resonance Current−mode Operation:
implementing quasi−resonance operation in peak
current−mode control optimizes the efficiency by
switching in the valley of the MOSFET drain−source
voltage. Thanks to a proprietary circuitry, the controller
locks−out in a selected valley and remains locked until
the input voltage significantly changes. Only the four
first valleys could be locked out. When the load current
diminishes, valley switching mode of operation is kept
but without valley lock−out. Valley−switching
operation across the entire input/output conditions
brings efficiency improvement and lets the designer
build higher−density converters.
fault mode. Thus it stops driving pulse on DRV pin.
The part enters in double hiccup mode before resuming
operation.
• Winding Short−Circuit Protection: An additional
comparator senses the CS signal and stops the
controller if V reaches V
+ 50% (after a reduced
CS
ILIM
LEB: t
). Short circuit protection is enabled only if
LEB2
4 consecutive pulses reach SCP level. This small
counter prevents any false triggering of short circuit
protection during surge test for instance. This fault is
detected and operations will be resumed like in a case
of V Over Voltage Protection.
CC
• V Over Voltage Protection: if the internally−built
out
• Frequency Clamp: As the frequency is not fixed and
output voltage becomes higher than V
level
OVP
dependent on the line, load and transformer
(V
ref_CV1
+ 26%) a fault is detected. This fault is
specifications, it is important to prevent switching
frequency runaway for applications requiring maximum
switching frequencies up to 90 kHz or 130 kHz. Three
frequency clamp options at 80 kHz, 110 kHz or
140 kHz are available for this purpose. In case
frequency clamp is not needed, a specific version of the
NCV1362 exists in which the clamp is deactivated.
detected and operations are resumed like in the
Over Voltage Protection case.
V
CC
• V Under Voltage Protection: After each circuit power
out
on sequence, V UVP detection is enabled only after
out
the startup timer T . This timer ensures that the
EN_UVP
power supply is able to fuel the output capacitor before
checking the output voltage in on target. After this
startup blanking time, UVP detection is enabled and
monitors the Output voltage level. When the power
supply is running in constant−current mode and when
• Primary Side Constant Current Regulation: NCV1362
controls and regulates the output current at a constant
level regardless of the input and output voltage
conditions. This function offers tight over power
protection by estimating and limiting the maximum
output current from the primary side, without any
particular sensor.
the output voltage falls below V
level, the controller
UVP
stops sending drive pulses and enters a double hiccup
mode before resuming operations.
• V /ZCD Pin Short Protection: at the beginning of each
S
V
OUT
off−time period, the V /ZCD pin is tested to check
S
CV Mode
whether it is shorted or left open. In case a fault is
detected, the controller enters in a double hiccup mode
before resuming operations.
V
NOM
CC Mode
• EMI Jittering: a low−frequency triangular voltage
waveform is added to the CS pin. This helps spreading
out energy in conducted noise analysis. Jittering is
disabled in frequency foldback mode.
I
OUT
0
I
• Frequency Foldback: In frequency foldback mode,
NOM
the system reduces the switching frequency by adding
Figure 28. Constant−Voltage & Constant−Current
th
some dead−time after the 4 valley is detected.
Mode
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14
NCV1362
The controller will still run in valley switching mode
even when the FF is enabled.
• Line FeedForward: By monitoring the voltage
available on BO pin it is possible to create a line
feedforward compensation in order to improve the
constant current accuracy.
• Temperature Shutdown: if the junction temperature
reaches the T
level, the controller stop driving the
SHTDN
power MOSFET until the junction temperature
decreases to T , then the operation is resumed
after a double hiccup mode.
• Fault Input: the NCV1362 includes a dedicated fault
input. It can be used to sense an overvoltage condition
and latch off the controller by pulling up the pin above
SHTDN(off)
• Brown−Out Detection: BO pin monitors bulk voltage
level via resistive divider and thus assures that the
application is working only for designed bulk voltages.
When BO pin is grounded before start−up
the upper fault threshold, V
, typically 3.0 V.
Fault(OVP)
The controller is also disabled if the Fault pin voltage,
, is pulled below the lower fault threshold,
V
Fault
V
, typically 0.4 V. The lower threshold is
Fault(OTP)
(V < V
dynamic frequency clamp are disabled.
), Brown−Out, Line FeedForward and
normally used for detecting an overtemperature fault
(by the means of an NTC). If this pin is grounded
before start−up, then its associated feature are disabled.
BO
BO(en)
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15
NCV1362
DETAILED APPLICATION INFORMATION
Start−up Sequence
The NCV1362 start−up voltage is made purposely high to
permit large energy storage in a small V capacitor value.
This helps operate with a small start−up current which,
start−up time. To further reduce the standby power, the
start−up current of the controller is extremely low (see
I
). The start−up resistor can therefore be connected
CC
CC(start)
to the bulk capacitor or directly to the mains input voltage to
further reduce the power dissipation.
together with a small V capacitor, will not hamper the
CC
R
Start−up
Input
Mains
V
CC
C
bulk
Aux.
Winding
C
VCC
Figure 29. The Startup Resistor can be Connected to the Input Mains for Further Power Dissipation Reduction
Ǹ
The first step starts with the calculation of the needed V
Vac,rms
2
CC
* VCC(on)
capacitor which will supply the controller when it operates
until the auxiliary winding takes over. Experience shows
p
ICVcc,min
+
(eq. 3)
Rstart−up
that this time t can be between 5 ms and 20 ms. If we
1
To make sure this current is always greater than 18 mA,
consider we need at least an energy reservoir for a t time of
1
then the minimum value for R
can be extracted:
start−up
10 ms, the V capacitor must be larger than:
CC
Ǹ
85 2
p
ICC t1
* 18
1.6 m 10 m
CVCC
w
w
w 1.4 mF (eq. 1)
Rstart−up
v
v 1.13 MW
(eq. 4)
18 * 6.5
V
CC(on) * VCC(off)
18 m
This calculation is purely theoretical, considering
a constant charging current. In reality, the take over time can
be shorter (or longer!) and it can lead to a reduction of the
Let us select a 1.5 mF capacitor at first and experiments in
the laboratory will let us know if we were too optimistic for
the time t . The V capacitor being known, we can now
1
CC
V
capacitor. Thus, a decrease in charging current and an
evaluate the charging current we need to bring the V
CC
CC
increase of the start−up resistor can be experimentally
tested, for the benefit of standby power. Laboratory
experiments on the prototype are thus mandatory to fine tune
the converter. If we chose the 1.2−MW resistor as suggested
by Eq. 4, the dissipated power at high line amounts to:
voltage from 0 V to the V
to be selected to ensure a start−up at the lowest mains (85 V
rms) to be less than 3 s (2.5 s for design margin):
of the IC. This current has
CC(on)
VCC(on) CVcc
18 1.5 m
Icharge
w
w
w 11 mA (eq. 2)
tstart−up
2.5
ǒ230 2Ǔ2
2
Ǹ
Vac,peak
If we account for the I
= 7.0 mA (maximum) that
CC(start)
PRstart−up,max
[
[
[ 24 mW (eq. 5)
will flow inside the controller, then the total charging current
delivered by the start−up resistor must be 18 mA. If we
connect the start−up network to the mains (half−wave
connection then), we know that the average current flowing
4 Rstart−up
4 1.1 M
Primary Side Regulation: Constant Current Operation
Figure 30 portrays idealized primary and secondary
transformer currents of a flyback converter operating in
Discontinuous Conduction Mode (DCM).
into this start−up resistor will be the smallest when V
CC
reaches the V
of the controller:
CC(on)
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16
NCV1362
Ip(t)
Ip, pk
time
Ip, pk
Nps
Is(t), IOUT
Is, pk
=
I
OUT = <Is(t)>
time
ton
tdemag
tsw
Figure 30. Primary and Secondary Transformer Current Waveforms
When the primary power MOSFET is turned on, the
primary current is illustrated by the green curve of
Figure 30. When the power MOSFET is turned off the
primary side current drops to zero and the current into the
secondary winding immediately rises to its peak value equal
to the primary peak current divided by the primary to
secondary turns ratio. This is an ideal situation in which the
leakage inductance action is neglected.
As the controller monitors the primary peak current via
the sense resistor and due to the internal current setpoint
divider (K
) between the CS pin and the internal
comp
feedback information, the output current could be written as
follow:
Vref_CC
Iout
+
(eq. 10)
8Nps Rsense
The output current value is set by choosing the sense
resistor value:
The output current delivered to the load is equal to the
average value of the secondary winding current, thus we can
write:
Vref_CC
Rsense
+
(eq. 11)
8Nps Iout
Ip,pk
tdemag
Iout + 〈isec(t)〉 +
(eq. 6)
tsw
2Nps
Primary Side Regulation: Constant Voltage Operation
In primary side constant voltage regulation, the output
voltage is sensed via the auxiliary winding. During the
on−time period, the energy is stored in the transformer gap.
During the off−time this energy stored in the transformer is
delivered to the secondary and auxiliary windings.
As illustrated by Figure 31, when the transformer energy
is delivered to the secondary, the auxiliary voltage sums the
output voltage scaled by the auxiliary and secondary turns
ratios and the secondary forward diode voltage. This
secondary forward diode voltage could be split in two
elements: the first part is the forward voltage of the diode
Where:
• t is the switching period
SW
• t
is the demagnetizing time of the transformer
demag
• N is the secondary to primary turns ratio, where
PS
N & N are respectively the transformer primary and
P
S
secondary turns:
Ns
Np
Nps
+
(eq. 7)
• I is the magnetizing peak current sensed across the
p,pk
sense resistor on CS pin:
(V ), and the second is related to the dynamic resistance of
f
VCS
the diode multiplied by secondary current (R y I (t)).
D
S
Ip,pk
+
(eq. 8)
Rsense
Where this second term will be dependant of the load and
line conditions.
Internal constant current regulation block is building the
constant current feedback information as follow:
tSW
VFB_CC + Vref_CC
(eq. 9)
tdemag
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17
NCV1362
Npa
Nps
Npa
Nps
VAUX(t)
Vout
+V I
( )
Vout
f
sec
0V
time
N
p
a
*VIN
Nps
Ip, pk
Ip(t)
time
Is(t), IOUT
Ip, pk
Nps
Is, pk
=
I
OUT = <Is(t)>
time
ton
tdemag
tsw
Figure 31. Typical Idealized Waveforms of a Flyback Transformer in DCM
To reach an accurate primary−side constant−voltage
regulation, the controller detects the end of the
demagnetization time and precisely samples output voltage
level seen on the auxiliary winding. As this moment
coincides with the secondary−side current equal to zero, the
diode forward voltage drop becomes independent from the
loading conditions.
Figure 32 illustrates how the constant voltage feedback
has been built. The auxiliary winding voltage must be scaled
down via the resistor divider to V
level before
ref_CV1
building the constant voltage feedback error.
Rs2
Vref_CV1
+
Vaux
(eq. 14)
R
s1 ) Rs2
By inserting Eg. 12 into Eq. 14 we obtain the following
equation:
Thus when the secondary current I (t) reaches zero
s
ampere, the auxiliary is sensed:
Rs2
Npa
Npa
Vref_CV1
+
Vout
(eq. 15)
Vaux + Vout
(eq. 12)
R
s1 ) Rs2
Nps
Nps
Once the sampled V is applied to the negative input
out
Where: N is the auxiliary to primary turns ratio, where N
pa
p
terminal of the operational transconductance amplifier
(OTA) and compared to the internal voltage reference an
adequate voltage feedback is built. The OTA output being
pinned out, it is possible to compensate the converter and
adjust step load response to what the project requires.
& N are respectively the primary and auxiliary turns:
a
Na
Npa
+
(eq. 13)
Np
Vs /ZCD
Sampled Vout
Comp
Zero Crossing &
Signal Sampling
R s1
OTA
t Blank_ZCD
tShort_ZCD
R s2
R1
C1
V ref_CV1
C2
FB_CV
Figure 32. Constant Voltage Feedback Arrangement
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18
NCV1362
When the power MOSFET is released at the end of the on
1. An internal switch grounds the V /ZCD pin during
S
time, because of the transformer leakage inductance and the
drain lumped capacitance some voltage ringing appears on
the drain node. These voltage ringings are also visible on the
auxiliary winding and could cheat the controller detection
circuits. To avoid false detection operations, two protecting
t
+ t
in order to protect the pin from
on
short_ZCD
negative voltage.
2. In order to prevent any misdetection from the zero
crossing block an internal switch disconnects
V /ZCD pin until t
time ends.
S
blank_ZCD
circuits have been implemented on the V /ZCD pin (see
S
Figure 33):
Figure 33. VS/ZCD Pin Waveforms
Constant−Current and Constant−Voltage Overall
Regulation
is detected by monitoring the transformer auxiliary winding
voltage. Turning on the power switch once the transformer
is demagnetized (or reset) reduces turn−on switching losses.
Once the transformer is demagnetized, the drain voltage
starts ringing at a frequency determined by the transformer
magnetizing inductance and the drain lumped capacitance,
eventually settling at the input voltage value. A QR
controller takes advantage of the drain voltage ringing and
turns on the power switch at the drain voltage minimum or
“valley” to reduce turn−on switching losses and
electromagnetic interference (EMI).
As already presented in the two previous paragraphs, the
controller integrates two different feedback loops: the first
one deals with the constant−current regulation scheme while
the second one builds the constant−voltage regulation. One
of the two feedback paths sets the primary peak current into
the transformer. During startup phase, however, the peak
current is controlled by the softstart.
Zero Current Detection
The NCV1362 integrates a quasi−resonant (QR) flyback
controller. The power switch turn−off of a QR converter is
determined by the peak current whose value depends on the
feedback loop. The switch restart event is determined by the
transformer demagnetization end. The demagnetization end
As sketched by Figure 34, a valley is detected once the
ZCD pin voltage falls below the QR flyback
demagnetization threshold, V
, typically 45 mV.
ZCD(TH)
The controller will switch once the valley is detected or
increment the valley counter depending on FB voltage.
ZCD
R
s1
QR multi−mode
Valley lockout &
Valley Switching &
VCO management
R
s2
VZCD(TH)
S
R
DRV
(Internal)
Q
Blanking
Tblank_ZCD
Timeout − tout
Figure 34. Valley Lockout Detection Circuitry Internal Schematic
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19
NCV1362
Timeout
Valley LockOut (VLO) and Frequency Foldback (FF)
The ZCD block actually detects falling edges of the
The operating frequency of a traditional Quasi−Resonant
(QR) flyback controller is inversely proportional to the
system load. In other words, a load reduction increases the
operating frequency. A maximum frequency clamp can be
useful to limit the operating frequency range. However,
auxiliary winding voltage applied to the ZCD pin. At
start−up or during other transient phases, the ZCD
comparator may be unable to detect such an event. Also, in
the case of extremely damped oscillations, the system may
not succeed in detecting all the valleys required by valley
lockout operation (VLO, see next section). In this condition,
the NCV1362 ensures continued operation by incorporating
a maximum timeout period that resets itself when a
demagnetization phase is properly detected. In case the
ringing signal is too weak or heavily damped, the timeout
signal supersedes the ZCD signal for the valley counter.
Figure 34 shows the timeout period generator circuit
when associated with
a
valley−switching circuit,
instabilities can arise because of the discrete frequency
jumps. The controller tends to hesitate between two valleys
and audible noise can be generated
To avoid this issue, the NCV1362 incorporates
a proprietary valley lockout circuitry which prevents
so−called valley jumping. Once a valley is selected, the
controller stays locked in this valley until the input level or
output power changes significantly. This technique extends
QR operation over a wider output power range while
maintaining good efficiency and naturally limiting the
maximum operating frequency.
schematic. The timeout duration, t , is set to 4.5 ms (typ.).
out
In VLO operation, the timeout occurrences are counted
instead of valleys when the drain−source voltage
oscillations are too damped to be detected. For instance,
assume the circuit must turn on at the third valley and the
ZCD ringing only enables the detection of:
st
th
The operating valley (from 1 to 4 valley) is determined
by the internal feedback level (Internal FB node on
Figure 3). As FB voltage level decreases or increases, the
valley comparators toggle one after another to select the
proper valley.
• Valleys #1 to #2: the circuit generates a DRV pulse t
out
(steady−state timeout delay) after valley #2 detection.
• Valley #1: the timeout delay must run twice so that the
The decimal counter increases each time a valley is detected.
The activation of an “n” valley comparator blanks the “n−1”
circuit generates a DRV pulse 9 ms (2 × t typ.) after
out
valley #1 detection.
or “n+1” valley comparator output depending if V
FB
decreases or increases, respectively. Figure 35 shows
a typical frequency characteristic obtained at low line in
a 10−W charger.
Fsw vs. Pout, when Pout is æ
out is
Fsw vs. Pout, when P
5
1.0 × 10
7.5 × 10
5.0 × 10
2.5 × 10
3rd
2nd
1st
5th
4th
VLO mode
Frequency
Foldback
Mode
4
4
4
3rd
2nd
1st
5th
4th
Frequency Foldback
Mode
VLO mode
0
0
1
2
3
4
5
Pout (W)
6
7
8
9
10
Figure 35. Typical Switching Frequency vs. Output Power Relationship in a 10−W Adapter
When an “n” valley is asserted by the valley selection
circuitry, the controller locks in this valley until the FB
voltage decreases to the lower threshold (“n+1” valley
activates) or increases to the “n valley threshold” + 600 mV
(“n−1” valley activates). The regulation loop adjusts the
peak current to deliver the necessary output power at the
valley operating point. Each valley selection comparator
features a 600−mV hysteresis that helps stabilize operation
despite the FB voltage swing produced by the regulation
loop.
www.onsemi.com
20
NCV1362
Table 5. VALLEY FB THRESHOLD ON CONSTANT VOLTAGE REGULATION
FB Falling
FB Rising
st
nd
th
1
to 2 Valley
2.5 V
2.3 V
2.1 V
1.9 V
FF Mode to 4
2.5 V
2.7 V
2.9 V
3.1 V
nd
rd
rd
th
rd
2
to 3 Valley
4
to 3 Valley
th
rd
nd
3
4
to 4 Valley
3
to 2 Valley
th
nd
st
to FF Mode
2
to 1 Valley
Frequency Foldback (FF)
efficiency benefit inherent to the QR operation, the
controller turns on again with the next valley after the dead
time has ended. As a result, the controller will still run in
valley switching mode even when the FF is enabled. This
dead−time increases when the FB voltage decays. There is
no discontinuity when the system transitions from VLO to
FF and the frequency smoothly reduces as FB goes below
1.9 V.
As the output current decreases (FB voltage decreases),
the valleys are incremented from 1 to 4. In case the fourth
valley is reached, the FB voltage further decreases below
1.9 V and the controller enters the frequency foldback mode
(FF). The current setpoint being internally forced to remain
above V
(setpoint corresponding to V
), the
CS(VCO)
Comp
controller regulates the power delivery by modulating the
switching frequency. When an output current increase
causes FB to exceed the 2.5−V FF upper threshold (600−mV
hysteresis), the circuit recovers VLO operation.
In frequency foldback mode, the system reduces the
switching frequency by adding some dead−time after the 4
The dead−time is selected to generate a 1.15−ms
dead−time when V
is decreasing and crossing V
Comp
HVCOD
(1.9 V typ.). At this moment, it can linearly go down to the
minimal frequency limit. The generated dead−time is 650 ns
th
when V
is increasing and crossing V
(2.5 V typ.).
Comp
HVCOI
valley is detected. However, in order to keep the high
Operating
Mode
VCO
th
4
Valley
Valley
Max Peak
Current
Pout Increasing
rd
3
Clamped to
V
CS
= V
ILIM
nd
2
Valley
Valley
Pout decreasing
st
1
V
Comp
1.9
2.1
2.3
2.5
2.7
2.9
3.1
4.3 V
Figure 36. Valley Lockout Threshold
Stand−by Mode
The NCV1362 implements a peak control mode when the
load is closed to 0. From frozen peak current in FF mode
(250 mV here), the maximum voltage threshold on CS pin
is reduced to 65 mV when the Comp voltage crossed
0.260 V. If the 65−mV threshold is reached in 200 ns for
instance due to small primary inductance, the minimum ON
time will be defined by the 320−ns leading edge blanking
duration and the propagation delay (50 ns) so 370 ns
typically.
An high frozen peak current is necessary to have good
efficiency at 10% of the load. On the other hand, the standby
performance will not be optimized. Indeed, in no load
condition, the switching frequency has to be high enough to
have a good transient response and then keep the output
voltage within the limits. If we set a minimum switching
frequency, the only parameter that can be adjusted to deliver
less power is the primary peak current as shown in Eq. 16.
2
1
2
Pout
+
Ip,pk fSW h
(eq. 16)
www.onsemi.com
21
NCV1362
Figure 37. Frequency Foldback and Standby Mode Behavior with 1−kHz Minimum Frequency Clamp,
V
CS(VCO) = 250 mV and VCS(STB) = 65 mV
Current Setpoint
• A minimum setpoint is forced that equals V
CS(VCO)
< 1.9 V
As explained in this operating description, the current
setpoint is affected by several functions. Figure 38
summarizes these interactions. As shown by this figure, the
current setpoint is the output of the control law divided by
(250 mV, typ.) when 0.760 V < V
comp
• A second minimum setpoint is forced that equals
(65 mV, typ.) when V < 0.260 V
V
CS(STB)
comp
• The peak current is linearly reduced between this two
previous frozen peak current (V & V
K
comp
(4 typ.). This current setpoint is clamped by the
)
CS(STB)
CS(VCO)
soft−start slope as long as the peak current requested by the
FB_CV or FB_CC level are higher. The softstart clamp is
starting from the frozen peak current (V
(0.8 V typ.) within 4 ms (t ).
However, this internal FB value is also limited by the
following functions:
• In addition, a second OCP comparator ensures that in
any case the current setpoint is limited to V . This
ILIM
) to V
CS(VCO)
ILIM
ensures the MOSFET current setpoint remains limited
ss
to V
in a fault condition.
ILIM
Peak Current
Control
Comp
SoftStart
FB_CV
FB_CC
Control Law
For
Primary Peak
Current Control
PWM Comp
1/Kcomp
FB Reset
PWM
Latch
Reset
CS
OCP
Comp
LEB1
Max_Ipk reset
RCS
Rsense
CCS
OCP
Timer
Count
OCP
VILIM
Reset Timer
POReset
DbleHiccup
Reset
Counter
Short Circuit
Comp
LEB2
4 clk
SCP
Counter
VCS(Stop)
Figure 38. Current Setpoint
www.onsemi.com
22
NCV1362
A 2nd Over−Current Comparator for Abnormal
Overcurrent Fault Detection
A severe fault like a winding short−circuit can cause the
switch current to increase very rapidly during the on−time.
consecutive abnormal overcurrent faults cause the
controller to enter in auto−recovery mode. The count to 4
provides noise immunity during surge testing. The counter
is reset each time a DRV pulse occurs without activating the
fault overcurrent comparator or after double hiccup
sequence or if the power supply is unplugged with a new
startup sequence after the initial power on reset.
The current sense signal significantly exceeds V
. But,
ILIM
because the current sense signal is blanked by the LEB
circuit during the switch turn on, the power switch current
can abnormally increase, possibly causing system damages.
The NCV1362 protects against this dangerous mode by
adding an additional comparator for abnormal overcurrent
fault detection or short−circuit condition. The current sense
signal is blanked with a shorter LEB duration, t
typically 120 ns, before applying it to the short−circuit
comparator. The voltage threshold of this extra comparator,
Jittering Capability
In order to help meet the EMI requirements, the NCV1362
features the jittering capability to average the spectrum rays
over the frequency range. The function consists of adding a
voltage ripple to the peak current information in order to
change the operation frequency. The peak−to−peak
amplitude of the ripple waveform is 60 mV at 1.5 kHz.
,
LEB2
V
, is typically 1.2 V, set 50% higher than V
. This
CS(stop)
ILIM
is to avoid interference with normal operation. Four
VDD
VCS
VJitter
Time
Vjitter
To CS
Comparator
F
jitter
CS
RLFF
RSense
Figure 39. Frequency Jittering
Brown−out Function
Fault Mode and Protection
The Brown−out circuitry offers a way to protect the
application from operation under too low input voltage. The
controller allows the output pulses, only if the input voltage
• CS Pin: at each startup, a 60−mA (I ) current source
CS
pulls up the CS pin to disable the controller if the pin is
left open or grounded. Then the controller enters in
a double hiccup mode.
is above V
level. An extra comparator detects if the BO
BO(on)
pin is grounded for disabling the BO feature. The internal
circuitry, depicted by Figure 40, offers a way to observe the
bulk voltage.
• V /ZCD Pin: after sending the first drive pulse the
S
controller checks the correct wiring of V /ZCD pin:
S
after the ZCD blanking time, if there is an open or short
conditions, the controller enters in double hiccup mode.
Vbulk
BO/LFF
Rupper
Sample
& Hold
1 ms
Filter
BO_EN
CBO
Rlower
BO_DIS
VBO(EN)
Start−up
IBO
50 ms
Filter
IBO_en
BO_OK
1 ms Filter
STB mode
VBO(ON)
Figure 40. Internal Brown−out Configuration
www.onsemi.com
23
NCV1362
The following figures illustrate the behavior of the
Brown−out pin:
VCC
VCC(on)
VCC(off)
Time
VBO
VBO(on)
VBO(off)
Time
Time
DRV
Figure 41. Brown−out Input Functionality − VCC < VCC(on)
VCC
VCC(on)
VCC(off)
Time
VBO
VBO(on)
VBO(off)
Time
Time
DRV
Figure 42. Brown−out Input Functionality − VCC > VCC(on)
www.onsemi.com
24
NCV1362
0.8
Calculation of the resistors divider:
Rlower + 10 M
+ 71.2 kW
(eq. 18)
113 * 0.8
VBO(on)
Rlower + Rupper
(eq. 17)
With a selected 71.5−kW normalized 1% resistor for
, it is now possible to calculate all the bulk levels
versus the internal voltage references of the BO pin.
V
bulk * VBO(on)
R
lower
If the power supply must start pulsing at V = 80 V rms
in
(V
= 113 V) with a selected R
= 10 MW:
bulk
upper
Table 6. EXAMPLE OF BROWN−OUT LEVELS WITH Rlower = 71.5 kW & Rupper = 10 MW
Parameters
BO Pin Level (V)
Bulk Level (V)
14.0
V
in
Level (V rms)
V
BO(en)
V
BO(on)
V
BO(off)
0.1
0.8
0.7
10
112.7
79.7
69.7
98.6
Line Feed Forward
These resistances have to be adjusted after measurements
according to the bulk capacitor ripple and also the capacitor
connected on the BO pin.
There is the possibility for the customer to disable the BO
protection if this function is not needed. To implement this
Sensing input line voltage via BO pin allows to generate
a current to CS pin directly proportional to the input line
level in order to compensate the over current on CS pin due
to the propagation delay. The resistor in series with the CS
pin adjusts the compensation level.
feature, the BO pin voltage is checked when V crosses
CC
V
CC(on)
threshold. If the BO voltage is still below V
BO(EN)
after the V , the BO function is disabled.
CC(on)
VDD
Rupper
BO/LFF
+
V
−
V bulk
CS
k
LFF *V
ILFF
RLFF
RSense
V BO(on)
Rlower
CBO
Figure 43. Internal Line Feed Forward Configuration
I
LFF
52 mA
K
LFF
= 20 mA/V
0 mA
V
BO(on)
3.4 V
Figure 44. Transfer Function of the Line Feed Forward
www.onsemi.com
25
NCV1362
Calculation of the resistor (R ) for compensating the
Numerical application yields:
LFF
overpower.
Let’s assume the power supply needs to have
a compensation of 45 mV (V ) at 265 V rms (V ).
First, it is needed to calculate what is the BO level
corresponding to the line voltage (here 265 V rms) of the
desired compensation level:
71.5 k
71.5 k ) 10 M
45 mV
Ǹ
(eq. 21)
(eq. 22)
VBO_LFF + 265 2
+ 2.66 V
+ 1.2 kW
LFF
in
RLFF
+
mA
( )
2.66 V * 0.8 V
20
V
The offset voltage can affect the standby power
performance by reducing the peak current setpoint in
light−load conditions. For this reason, it is desirable to
cancel its action as soon as the VCO mode occurs. A typical
curve variation is shown in Figure 45. At low power, below
the VCO mode starting point, the LFF current is linearly
absorbed and no offset is created through the CS pin when
the Comp pin voltage is below 1.6 V. When feedback
increases again and reaches the 1.6−V threshold, OPP starts
to build up and reaches its full value at 1.9 V.
Rlower
VBO_LFF + Vbulk
(eq. 19)
Rlower ) Rupper
Then, the resistor value to be inserted between the CS
resistor and CS pin could be calculated, as illustrated here
after:
VLFF
RLFF
+
(eq. 20)
ǒV
Ǔ
KLFF
BO_LFF * VBO(on)
max
V
Comp
V
Comp
Decreases
Increases
1.9 V
1.6 V
t
100
0
t
Figure 45. The LFF Current is Applied when the Comp Voltage Exceeds 1.6 V. It is 0 below it
Fault Input
This function is typically used to detect a V or auxiliary
CC
The NCV1362 includes a dedicated fault input accessible
via the Fault pin. Figure 46 shows the architecture of the
Fault input. The controller can be latched by pulling up the
winding overvoltage by means of a Zener diode generally in
series with a small resistor (see Figure 46).
Neglecting the resistor voltage drop, the OVP threshold is
then:
pin above the upper fault threshold, V
, typically
Fault(OVP)
3.0 V. An active clamp prevents the Fault pin voltage from
reaching the V if the pin is open. To reach the upper
threshold, the external pull−up current has to be higher than
the pull−down capability of the clamp.
VAUX(OVP) + VZ ) VFault(OVP)
(eq. 24)
Fault(OVP)
where V is the Zener diode voltage.
Z
The controller can also be latched off if the Fault pin
voltage, V , is pulled below the lower fault threshold,
, typically 0.4 V. This capability is normally used
for detecting an overtemperature fault by means of an NTC
V
Fault(OVP) * VFault(clamp)
3 V * 1.35 V
1.35 kW
Fault
+
,
RFault(clamp)
V
Fault(OTP)
(eq. 23)
i.e. approximately 1.2 mA.
www.onsemi.com
26
NCV1362
thermistor. A pull up current source I
, (typically
that is 8.9 kW typically.
Fault(OTP)
45 mA) generates a voltage drop across the thermistor. The
resistance of the NTC thermistor decreases at higher
temperatures resulting in a lower voltage across the
thermistor. The controller detects a fault once the thermistor
The controller bias current is reduced during power up by
disabling most of the circuit blocks including I
.
.
Fault(OTP)
This current source is enabled once V reaches V
CC
CC(on)
A bypass capacitor is usually connected between the Fault
and GND pins. It will take some time for V to reach its
voltage drops below V
.
Fault(OTP)
Fault
The circuit detects an overtemperature situation when:
steady state value once I
is enabled. Therefore, the
Fault(OTP)
lower fault comparator (i.e. overtemperature detection) is
RNTC IFault(OVP) + VFault(OVP)
(eq. 25)
ignored during soft−start.
Hence, the OTP protection trips when
VFault(OVP)
RNTC
+
(eq. 26)
IFault(OTP)
Vaux
2 ms
Blanking
VDD
VFault(OVP)
VZ
Fault
NTC
2 ms
Blanking
Rfault(clamp)
Up Counter
Fault
4
Reset
Clock
SSend
VFault(OTP)
S
Latch
OVP/OTP gone
Q
R
BO_DIS
Sample
& Hold
VCC(Reset)
BO_EN
1 ms
Filter
Fault pin
disabled
BO_NOK
VFault(EN)
Start−up
Figure 46. Fault Detection Schematic
As a matter of fact, the controller operates normally while
the Fault pin voltage is maintained within the upper and
lower fault thresholds. Upper and lower fault detector have
blanking delays to prevent noise from triggering them. Both
OVP and OTP comparator output are validated only if its
high−state duration lasts a minimum of 2 ms. Below this
value, the event is ignored. Then, a counter ensures that
OVP/OTP events occurred for 4 successive drive clock
pulses before actually latching the part.
feature, the fault pin voltage is checked when V crosses
CC
V
CC(on)
threshold. If the voltage is still below V
Fault(EN)
after the V , the fault pin is disabled.
CC(on)
Thermal Shutdown
An internal thermal shutdown circuit monitors the
junction temperature of controller die of the IC. The
controller is disabled if its junction temperature exceeds the
thermal shutdown threshold (T
). A continuous V
SHDN
CC
hiccup is initiated after a thermal shutdown fault is detected.
The controller restarts at the next V once the IC
When the part is latched−off, the drive is immediately
CC(on)
turned off and V goes in endless hiccup mode. The power
CC
temperature drops below T
reduced by the thermal
SHDN
supply needs to be un−plugged to reset the part as a result of
a BO_NOK (BO fault condition) if Brown−Out feature is
shutdown hysteresis (T ). The thermal shutdown is
SHDN(off)
also cleared if V drops below V
sequences commences at the next V
. A new power up
once all the faults
CC
CC(reset)
enabled otherwise V
.
CC(Reset)
CC(on)
There is the possibility for the customer to disable the fault
pin protection if this function is not needed or to reduce the
IC consumption in stand−by mode. To implement this
are removed.
www.onsemi.com
27
NCV1362
Table 7. ORDERING TABLE OPTION
OPN #
NCV1362_ _
Minimum Switching
Frequency in VCO Mode (kHz)
Maximum Switching Frequency (kHz)
Jittering Frequency
0.2
1
x
x
x
No
x
80
110
140
Enable
Disable
NCV1362AADR2G
NCV1362ABDR2G
NCV1362ACDR2G
x
x
x
x
x
Table 8. ORDERING INFORMATION
Device
†
Device Marking
V1362AA
Package
Shipping
NCV1362AADR2G
SOIC−8
(Pb−Free)
NCV1362ABDR2G
V1362AB
2500 / Tape & Reel
NCV1362ACDR2G
V1362AC
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
28
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
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