NCV21912DR2G [ONSEMI]
Precision Operational Amplifier, 25 V Offset, Zero-Drift, 36 V Supply, 2 MHz;型号: | NCV21912DR2G |
厂家: | ONSEMI |
描述: | Precision Operational Amplifier, 25 V Offset, Zero-Drift, 36 V Supply, 2 MHz |
文件: | 总22页 (文件大小:1052K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Precision Operational
Amplifier, 25 mV Offset,
Zero-Drift, 36 V Supply,
2 MHz
NCS21911, NCV21911,
NCS21912, NCV21912,
NCS21914, NCV21914
www.onsemi.com
MARKING
DIAGRAMS
The NCS2191x family of high precision op amps feature low input
offset voltage and near−zero drift over time and temperature. These op
amps operate over a wide supply range from 4 V to 36 V with low
quiescent current. The rail−to−rail output swings within 10 mV of the
rails. The family includes the single channel NCS(V)21911, the dual
channel NCS(V)21912, and the quad channel NCS(V)21914 in a
variety of packages. All versions are specified for operation from
−40°C to +125°C. Automotive qualified options are available under
the NCV prefix.
5
5
AEZAYWG
1
G
TSOP−5
1
CASE 483
8
8
912
1
AYWG
Micro8
G
CASE 846A−02
1
Features
8
• Input Offset Voltage: 25 mV max
• Zero−Drift Offset Voltage: 0.085 mV/°C max
• Voltage Noise Density: 22 nV/√Hz typical
• Unity Gain Bandwidth: 2 MHz typical
• Supply Voltage: 4 V to 36 V
• Quiescent Current: 570 mA max
• Rail−to−Rail Output
912
ALYWX
8
1
G
SOIC−8 NB
1
CASE 751−07
14
XXXX
XXXX
ALYWG
G
14
1
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
TSSOP−14 WB
CASE 948G
1
• These Devices are Pb−free, Halogen free/BFR free and are RoHS
compliant
14
1
XXXXXXXXXG
AWLYWW
14
Typical Applications
• Temperature Measurements
• Transducer Applications
• Electronic Scales
• Medical Instrumentation
• Current Sensing
• Automotive
1
SOIC−14 NB
CASE 751A−03
XXXXX = Specific Device Code
= Assembly Location
L or WL = Wafer Lot
A
Y
W
G
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
June, 2020 − Rev. 2
NCS21911/D
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
PIN CONNECTIONS
Single Channel Configuration
NCS21911
VDD
OUT
VSS
IN+
1
2
3
5
4
IN−
Dual Channel Configuration
NCS21912
Quad Channel Configuration
NCS21914
OUT 1
IN− 1
IN+ 1
VDD
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT 1
IN− 1
IN+ 1
VSS
1
2
3
4
8
7
6
5
OUT 4
VDD
IN− 4
−
−
OUT 2
−
+
+
+
IN+ 4
VSS
IN− 2
−
+
IN+ 2
IN+ 3
IN− 3
OUT 3
IN+ 2
IN− 2
+
+
−
−
OUT 2
8
ORDERING INFORMATION
Channels
Single
Device
Package
Shipping †
NCS21911SN2T1G
SOT23−5 / TSOP−5
SOIC−8
3000 / Tape & Reel
2500 / Tape & Reel
Dual
NCS21912DR2G
(In Development*)
NCS21912DMR2G
MICRO−8
SOIC−14
4000 / Tape & Reel
2500 / Tape & Reel
Quad
NCS21914DR2G
(In Development*)
NCS21914DTBR2G
(In Development*)
TSSOP−14
2500 / Tape & Reel
Automotive Qualified
Channels
Single
†
Device
Package
SOT23−5 / TSOP−5
SOIC−8
Shipping
NCV21911SN2T1G
3000 / Tape & Reel
2500 / Tape & Reel
Dual
NCV21912DR2G
(In Development*)
NCV21912DMR2G
MICRO−8
SOIC−14
4000 / Tape & Reel
2500 / Tape & Reel
Quad
NCV21914DR2G
(In Development*)
NCV21914DTBR2G
(In Development*)
TSSOP−14
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*Contact local sales office for more information.
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2
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Unit
Supply Voltage (VDD− VSS)
INPUT AND OUTPUT PINS
Input Voltage (Note 1)
40
V
VSS – 0.3 to VDD + 0.3
V
Differential Input Voltage (Note 2)
Input Current (Notes 1 and 2)
Output Short Circuit Current (Note 3)
TEMPERATURE
17
10
V
mA
mA
Continuous
Operating Temperature
Storage Temperature
–40 to +125
–65 to +150
+150
°C
°C
°C
Junction Temperature
ESD RATINGS (Note 4)
Human Body Model (HBM)
Charged Device Model (CDM)
OTHER RATINGS
3000
2000
V
V
Latch−up Current (Note 5)
MSL
100
mA
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Input terminals are diode−clamped to the power−supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less.
2. The inputs are diode connected with a total input protection of 1.65 kW, increasing the absolute maximum differential voltage to 17 V
.
DC
If the applied differential voltage is expected to exceed this rating, external resistors should be added in series with the inputs to limit the input
current to 10 mA.
3. Short−circuit to V or V . Short circuits to either rail can cause an increase in the junction temperature. The total power dissipation must
DD
SS
be limited to prevent the junction temperature from exceeding the 150_C limit.
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard JS−001−2017 (AEC−Q100−002)
ESD Charged Device Model tested per JEDEC standard JS−002−2014 (AEC−Q100−011)
5. Latch−up Current tested per JEDEC standard JESD78E (AEC−Q100−004).
THERMAL INFORMATION (Note 6)
Rating
Symbol
Package
Value
Unit
Thermal Resistance, Junction to Ambient
q
TSOP−5 /
SOT23−5
170
°C/W
JA
Micro8/MSOP8
SOIC−8
116
87
SOIC−14
59
TSSOP−14
78
2
6. As mounted on an 80x80x1.5 mm FR4 PCB with 2S2P, 2 oz copper, and a 200 mm heat spreader area. Following JEDEC JESD51−7
guidelines.
OPERATING CONDITIONS
Parameter
Supply Voltage (V − V
Symbol
Range
4 to 36
Unit
V
)
V
T
DD
SS
S
Specified Operating Temperature Range
Input Common Mode Voltage Range
Differential Voltage (Note 7)
−40 to 125
°C
V
A
V
CM
V
SS
to V −1.5
DD
V
DIFF
17
V
7. The inputs are diode connected with a total input protection of 1.65 kW, increasing the absolute maximum differential voltage to 17 V
.
DC
If the applied differential voltage is expected to exceed this rating, external resistors should be added in series with the inputs to limit the input
current to 10 mA.
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3
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
ELECTRICAL CHARACTERISTICS V = 4 V to 36 V
S
At T = +25°C, R = 10 kW connected to midsupply, V
= V
= midsupply, unless otherwise noted.
A
L
CM
OUT
Boldface limits apply over the specified temperature range, T = –40°C to 125°C, guaranteed by characterization and/or design.
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
V
1
25
mV
mV/°C
pA
OS
Offset Voltage Drift vs Temp
Input Bias Current (Note 8)
DV /DT
0.02
100
0.085
500
OS
I
IB
3500
500
pA
Input Offset Current (Note 8)
Common Mode Rejection Ratio
I
200
150
150
140
130
pA
OS
3500
pA
CMRR
V
≤ V
DD
≤
V
V
= 36 V
= 12 V
140
130
130
120
130
120
120
110
dB
SS
CM
S
V
−1.5 V
S
(Note 8)
V
= 8 V
S
(Note 8)
V
= 4 V
S
Input Capacitance
EMI Rejection Ratio
C
Common Mode
f = 5 GHz
3
pF
dB
IN
EMIRR
100
80
f = 400 MHz
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain
A
VOL
V
SS
+ 0.5 V < V < V – 0.5 V
130
150
dB
O
DD
125
135
Open Loop Output Impedance
Z
No Load
No Load
See
W
OUT_OL
Figure 23
Output Voltage High, Referenced to
Rail
V
OH
5
10
mV
100
140
5
210
250
10
R = 10 kW
L
Output Voltage Low, Referenced to
Rail
V
OL
No Load
mV
100
140
18
210
250
R = 10 kW
L
Short Circuit Current
Capacitive Load Drive
I
Sinking Current
Sourcing Current
mA
nF
SC
16
C
1
L
DYNAMIC PERFORMANCE
Gain Bandwidth Product
Gain Margin
GBW
C = 100 pF
2
13
55
1.6
20
45
1
MHz
dB
°
L
A
C = 100 pF
L
M
M
Phase Margin
ϕ
C = 100 pF
L
Slew Rate
SR
G = +1
V/ms
ms
Settling Time
t
S
V
S
= 36 V
0.1%
0.01%
ms
Overload Recovery Time
t
V
S
=
18 V, A = −10,
IN
ms
OR
V
V
= 2.5 V
8. Guaranteed by characterization and/or design.
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4
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
ELECTRICAL CHARACTERISTICS V = 4 V to 36 V
S
At T = +25°C, R = 10 kW connected to midsupply, V
= V
= midsupply, unless otherwise noted.
A
L
CM
OUT
Boldface limits apply over the specified temperature range, T = –40°C to 125°C, guaranteed by characterization and/or design.
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
NOISE PERFORMANCE
Total Harmonic Distortion + Noise
THD+N
f
IN
= 1 kHz, A = 1, V
= 1
0.0003
%
V
OUT
Vrms
Voltage Noise Density
Current Noise Density
Voltage Noise, Peak−to−Peak
Voltage Noise, RMS
e
f = 1 kHz
f = 1 kHz
22
100
400
70
nV/√Hz
fA/√Hz
N
i
N
e
PP
f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
nV
PP
e
rms
nV
rms
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= 4 V to 36 V
0.02
154
475
0.3
mV/V
dB
130
Quiescent Current
I
Q
Per channel
570
mA
570
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NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
GRAPHS
Typical performance at T = 25°C, unless otherwise noted.
A
35
30
25
20
15
10
5
16
V
V
= 36 V
S
V
V
= 36 V
S
14
12
10
8
= mid−supply
CM
= mid−supply
CM
105 units
105 units
6
4
2
0
0
−20 −16 −12 −8 −4
0
4
8
12
16
20
−0.10
−0.06
−0.02
0.02
0.06
0.10
OFFSET VOLTAGE (mV)
OFFSET VOLTAGE DRIFT (mV/°C)
Figure 1. Offset Voltage Distribution
Figure 2. Offset Voltage Drift Distribution
15
10
5
15
10
5
V
= 4 V
S
V
V
= 36 V
S
5 typical units
= mid−supply
CM
5 typical units
0
0
−5
−10
−15
−5
−10
−15
0
0.5
1
1.5
2
2.5
3
−50
−25
0
25
50
75
100
125
COMMON MODE VOLTAGE (V)
TEMPERATURE (°C)
Figure 3. Offset Voltage vs. Temperature
Figure 4. Offset Voltage vs. Common Mode
Voltage
15
10
5
15
10
5
V
= 36 V
V
= mid−supply
S
CM
5 typical units
5 typical units
0
0
−5
−10
−15
−5
−10
−15
0
5
10
15
20
25
30
35
4
8
12
16
20
24
28
32
36
SUPPLY VOLTAGE (V)
Figure 6. Offset Voltage vs. Power Supply
COMMON MODE VOLTAGE (V)
Figure 5. Offset Voltage vs. Common Mode
Voltage
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6
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
120
100
80
25
V
= 36 V
S
20
15
R = 10 kW
C = 25 pF
L
PHASE MARGIN
L
10
60
5
GAIN
0
40
−5
20
−10
−15
−20
A = 1
V
0
V
= 4 V, 36 V
S
A = −1
V
R = 10 kW
L
A = 10
V
−20
10
1k
100k
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Open Loop Gain and Phase vs.
Frequency
Figure 8. Closed Loop Gain vs. Frequency
300
200
100
0
1600
1200
800
400
0
V
V
= 36 V
V
S
= 36 V
S
I +
= mid−supply
IB
CM
I
I
−
IB
OS
−100
−200
−300
I +
IB
I −
IB
I
OS
−400
−40 −20
0
20
40
60
80
100 120 140
0
5
10
15
20
25
30
35
TEMPERATURE (°C)
Figure 10. Input Current vs. Temperature
COMMON MODE VOLTAGE (V)
Figure 9. Input Current vs. Common Mode
Voltage
120
100
80
60
40
20
0
140
120
100
80
R = 10 kW
V = 4 V, 36 V
S
R = 10 kW
L
L
PSRR+
PSRR−
60
V
S
=
=
=
=
2, PSRR+
18, PSRR+
2, PSRR−
18, PSRR−
40
V
S
V
S
V
S
20
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. PSRR vs. Frequency
Figure 12. CMRR vs. Frequency
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NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
5
0.5
0.4
V
= 4 V, 36 V
S
4.5
4
V
CM
V
CM
= V +0.5 to V −1.5 V
SS DD
5 typical units
= V to V −1.5 V
SS
DD
0.3
3.5
3
0.2
0.1
2.5
2
0
−0.1
−0.2
−0.3
−0.4
−0.5
1.5
1
0.5
0
−0.5
−50 −25
0
25
50
75 100
125
150
−50 −25
0
25
50
75 100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. PSRR vs. Temperature
Figure 14. CMRR vs. Temperature at VS = 4 V
2
1.8
1.6
1.4
1.2
1
400
300
V
S
= 36 V
V
CM
V
CM
= V +0.5 to V −1.5 V
SS DD
= V to V −1.5 V
SS
DD
200
100
0.8
0.6
0.4
0.2
0
0
−100
−200
−300
−400
−0.2
−0.4
−50 −25
0
25
50
75 100
125
150
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE (°C)
TIME (s)
Figure 15. CMRR vs. Temperature at VS = 36 V
Figure 16. 0.1 Hz to 10 Hz Noise
1k
100
10
0.01
0.001
V
S
= 36 V
V
= 36 V
A = 1
A = −1
V
S
V
R = 10 kW
L
B
W
= 80 kHz
V
IN
= 1 V
rms
0.0001
1
1
10
100
1k
10k
100k
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Voltage Noise Density vs.
Frequency
Figure 18. THD+N vs. Frequency
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NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
0.50
10
1
V
= 36 V
A = 1
A = −1
V
S
V
0.48
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
R = 10 kW
L
B
W
= 80 kHz
f = 1 kHz
0.1
0.01
0.001
0.0001
0.01
0.1
1
10
0
4
8
12
16
20
24
28
32
36
OUTPUT AMPLITUDE (V
)
rms
SUPPLY VOLTAGE (V)
Figure 19. THD+N vs. Output Amplitude
Figure 20. Quiescent Current vs. Supply
Voltage
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.50
0.48
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
A = 1
A = −1
V
V
V
V
= 4 V
= 36 V
S
S
−50
−25
0
25
50
75
100 125
150
−50 −25
0
25
50
75 100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Quiescent Current vs. Temperature
Figure 22. Open Loop Gain vs. Temperature
50
45
40
35
30
25
20
15
10
5
10k
1k
V
= 36 V
R
R
R
= 0 W
= 25 W
= 50 W
S
iso
iso
iso
R = 10 kW
A = 1 V/V
V
L
100
10
1
0.1
0
1
10
100
1k
10k
100k
1M
10M
0
200
400
600
800
1000
FREQUENCY (Hz)
CAPACITIVE LOAD (pF)
Figure 23. Open Loop Output Impedance vs.
Frequency
Figure 24. Small Signal Overshoot vs.
Capacitive Load (100 mV Output Step)
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NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
5
70
60
50
40
30
20
10
0
R = 10 kW
4
3
L
Input
Output
R
R
R
= 0 W
= 25 W
= 50 W
iso
iso
iso
A = −1
V
100 mV Step
2
1
0
−1
−2
−3
−4
−5
V
S
= 8 V
R = 10 kW
L
C = 15 pF
L
0
200
400
600
800
1000
CAPACITIVE LOAD (pF)
TIME (100 ms/div)
Figure 25. Small Signal Overshoot vs.
Capacitive Load (100 mV Output Step)
Figure 26. No Phase Reversal
4
3
20
15
10
5
2
1
0
0
−1
−2
−3
−4
−5
V
= 18 V
S
−10
R = 10 kW
C = 15 pF
A = −10
L
Input
Output
−15
L
V
−20
TIME (1 ms/div)
Figure 27. Positive Overload Recovery
4
3
20
15
10
5
V
=
18 V
S
Input
Output
R = 10 kW
C = 15 pF
A = −10
L
L
2
V
1
0
0
−1
−2
−3
−4
−5
−10
−15
−20
TIME (1 ms/div)
Figure 28. Negative Overload Recovery
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NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
0.1
0.08
0.06
0.04
0.02
0
0.1
V
= 36 V
S
0.08
0.06
0.04
0.02
0
R = 10 kW
L
C = 15 pF
L
A = 1
V
V
= 36 V
S
R = 10 kW
L
C = 15 pF
L
A = −1
V
−0.02
−0.04
−0.06
−0.08
−0.1
−0.02
−0.04
−0.06
−0.08
−0.1
Input
Output
Input
Output
TIME (10 ms/div)
TIME (10 ms/div)
Figure 29. Non−Inverting Small Signal Step
Figure 30. Inverting Small Signal Step
Response
Response
10
8
10
8
V
= 36 V
S
R = 10 kW
L
C = 15 pF
A = 1
V
L
6
4
6
4
2
V
S
= 36 V
2
R = 10 kW
L
C = 15 pF
A = −1
V
L
0
0
−2
−2
−4
−6
−4
−6
−8
Input
Output
Input
Output
−8
−10
−10
TIME (10 ms/div)
TIME (10 ms/div)
Figure 31. Non−Inverting Large Signal Step
Figure 32. Inverting Large Signal Step
Response
Response
0.01
0.01
V
= 36 V
V = 36 V
S
S
0.008
0.006
0.004
0.002
0
0.008
0.006
0.004
R = 10 kW
R = 10 kW
L
L
C = 15 pF
C = 15 pF
L
L
V
= 10 V Step
V
= 10 V Step
IN
IN
0.002
0
−0.002
−0.004
−0.006
−0.002
−0.004
−0.006
−0.008
−0.01
Output
Input
Output
Input
−0.008
−0.01
TIME (5 ms/div)
TIME (5 ms/div)
Figure 33. Large Signal Settling Time,
Figure 34. Large Signal Settling Time,
Low−to−High
High−to−Low
www.onsemi.com
11
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
35
25
20
I
I
, Source
, Sink
V
S
= 36 V
SC
SC
V = 18 V
S
30
25
20
15
10
5
15
10
5
0
V
S
= 9 V
−5
−10
−15
−20
−25
V
S
=
5 V
V
S
=
2.5 V
0
−50
0
50
100
150
1k
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 35. Short Circuit Current vs.
Temperature
Figure 36. Maximum Output Voltage vs.
Frequency (AV = 1 for VS = + 2.5 V, + 5 V, + 9 V;
AV = 2 for VS = + 18 V)
36
3
2.5
2
V
S
= 36 V
T = −40°C
A
35.5
35
T = 0°C
A
T = 25°C
A
T = 85°C
A
T = 125°C
A
34.5
34
1.5
1
T = −40°C
T = 0°C
A
A
T = 25°C
A
0.5
0
33.5
T = 85°C
A
T = 125°C
A
V
= 36 V
S
33
0
0
2
4
6
8
10 12 14 16 18 20 22 24
2
4
6
8
10
12
14 16 18 20
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 37. Output Voltage Low vs. Output
Current
Figure 38. Output Voltage High vs. Output
Current
160
140
120
100
80
0
−20
V
= 36 V
V = 36 V
S
S
V
= 100 mVp
IN
A = 1
V
−40
−60
−80
60
−100
−120
40
20
−140
−160
0
10M
100M
1G
10G
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 39. EMIRR IN+ vs. Frequency
Figure 40. Channel−to−Channel Crosstalk
www.onsemi.com
12
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
APPLICATION INFORMATION
Overview
The NCS21911 series of amplifiers uses
a
chopper−stabilized architecture, which provides the
advantage of minimizing offset voltage drift over
temperature and time. The simplified block diagram is
shown in Figure 41. Unlike the classical chopper
architecture, the chopper stabilized architecture has two
signal paths.
The NCS21911, NCS21912, and NCS21914 precision op
amps provide low offset voltage and zero drift over
temperature. With a maximum offset voltage of 25 mV and
input common mode voltage range that includes ground, the
NCS21911 series is well−suited for applications where
precision is required, such as low side current sensing and
interfacing with sensors.
Main amp
IN+
+
OUT
−
IN−
−
+
+
−
+
−
Chopper
Chopper
RC notch filter
RC notch filter
Figure 41. Simplified NCS21911 Block Diagram
In Figure 41, the lower signal path is where the chopper
samples the input offset voltage, which is then used to
correct the offset at the output. The offset correction occurs
at a frequency of 250 kHz. The chopper−stabilized
architecture is optimized for best performance at
frequencies up to the related Nyquist frequency (1/2 of the
offset correction frequency). As the signal frequency
exceeds the Nyquist frequency, 125 kHz, aliasing may occur
at the output. This is an inherent limitation of all chopper and
chopper−stabilized architectures. Nevertheless, the
NCS21911 series op amps have minimal aliasing up to
200 kHz and are less susceptible to aliasing effects when
compared to competitor parts from other manufacturers.
ON Semiconductor’s patented approach utilizes two
cascaded, symmetrical, RC notch filters tuned to the
chopper frequency and its fifth harmonic to reduce aliasing
effects.
only does this help retain high frequency components of the
input signal, but it also improves the loop gain at low
frequencies. This is especially useful for low−side current
sensing and sensor interface applications where the signal is
low frequency and the differential voltage is relatively
small.
Application Circuits
Low−Side Current Sensing
Low−side current sensing is used to monitor the current
through a load. This method can be used to detect
over−current conditions and is often used in feedback
control, as shown in Figure 42. A sense resistor is placed in
series with the load to ground. Typically, the value of the
sense resistor is less than 100 mW to reduce power loss
across the resistor. The op amp amplifies the voltage drop
across the sense resistor with a gain set by external resistors
R1, R2, R3, and R4 (where R1 = R2, R3 = R4). Precision
resistors are required for high accuracy, and the gain is set
to utilize the full scale of the ADC for the highest resolution.
The chopper−stabilized architecture also benefits from
the feed−forward path, which is shown as the upper signal
path of the block diagram in Figure 41. This is the high speed
signal path that extends the gain bandwidth up to 2 MHz. Not
www.onsemi.com
13
NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914
R
3
V
LOAD
VDD
VDD
ADC
VDD
Load
R
1
Microcontroller
control
+
R
SENSE
−
R
2
R
4
Figure 42. Low−Side Current Sensing
Differential Amplifier for Bridged Circuits
produced is relatively small and needs to be amplified before
going into an ADC. Precision amplifiers are recommended
in these types of applications due to their high gain, low
noise, and low offset voltage.
Sensors to measure strain, pressure, and temperature are
often configured in a Wheatstone bridge circuit as shown in
Figure 43. In the measurement, the voltage change that is
R
F
VDD
VDD
R
R
3
1
−
R
3
R
x
+
Figure 43. Wheatstone Bridge Circuit Amplification
EMI Susceptibility and Input Filtering
capacitors as close as possible to the supply pins. Keep traces
short, utilize a ground plane, choose surface−mount
components, and place components as close as possible to
the device pins. These techniques will reduce susceptibility
to electromagnetic interference (EMI). Thermoelectric
effects can create an additional temperature dependent
offset voltage at the input pins. To reduce these effects, use
metals with low thermoelectric coefficients and prevent
temperature gradients from heat sources or cooling fans.
Op amps have varying amounts of EMI susceptibility.
Semiconductor junctions can pick up and rectify EMI
signals, creating an EMI−induced voltage offset at the
output, adding another component to the total error. Input
pins are the most sensitive to EMI. The NCS2191x
integrates low−pass filters to decrease its sensitivity to EMI.
Figure 39 shows the EMIRR performance.
General Layout Guidelines
To ensure optimum device performance, it is important to
follow good PCB design practices. Place 0.1 mF decoupling
www.onsemi.com
14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
DATE 12 AUG 2020
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
2X
0.10
T
M
5
4
3
2X
0.20
T
B
S
1
2
K
B
A
DETAIL Z
G
A
MILLIMETERS
TOP VIEW
DIM
A
B
C
D
MIN
2.85
1.35
0.90
0.25
MAX
3.15
1.65
1.10
0.50
DETAIL Z
J
G
H
J
K
M
S
0.95 BSC
C
0.01
0.10
0.20
0
0.10
0.26
0.60
10
3.00
0.05
H
SEATING
PLANE
END VIEW
C
_
_
SIDE VIEW
2.50
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
1.9
5
1
5
0.074
0.95
XXXAYWG
XXX MG
0.037
G
G
1
Analog
Discrete/Logic
2.4
0.094
XXX = Specific Device Code XXX = Specific Device Code
A
Y
W
G
= Assembly Location
= Year
= Work Week
M
G
= Date Code
= Pb−Free Package
1.0
0.039
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
DATE 03 FEB 2016
SCALE 1:1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
1.27
PITCH
WW
G
= Work Week
= Pb−Free Package
14X
0.58
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
STYLE 2:
CANCELLED
STYLE 3:
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
STYLE 6:
STYLE 7:
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX = Specific Device Code
A
Y
W
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
STYLE 1:
STYLE 2:
PIN 1. SOURCE 1
STYLE 3:
PIN 1. SOURCE
PIN 1. N-SOURCE
2. N-GATE
(Note: Microdot may be in either location)
2. SOURCE
3. SOURCE
4. GATE
2. GATE 1
3. SOURCE 2
4. GATE 2
3. P-SOURCE
4. P-GATE
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. P-DRAIN
6. P-DRAIN
7. N-DRAIN
8. N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70246A
TSSOP−14 WB
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
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