NCV4276BDTADJRKG [ONSEMI]
400 mA Low-Drop Voltage Regulator; 400毫安低压差稳压器
| 型号： | NCV4276BDTADJRKG |
| 厂家： | 
ONSEMI |
| 描述： | 400 mA Low-Drop Voltage Regulator |
| 文件： | 总12页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV4276B
400 mA Low-Drop Voltage
Regulator
The NCV4276B is a 400 mA output current integrated low dropout
regulator family designed for use in harsh automotive environments.
It includes wide operating temperature and input voltage ranges. The
device is offered with adjustable voltage versions available in 2%
output voltage accuracy. It has a high peak input voltage tolerance
and reverse input voltage protection. It also provides overcurrent
protection, overtemperature protection and inhibit for control of the
state of the output voltage. The NCV4276B is available in DPAK
surface mount package. The output is stable over a wide output
capacitance and ESR range. The NCV4276B has improved startup
behavior during input voltage transients.
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MARKING
DIAGRAM
DPAK
5−PIN
DT SUFFIX
76BAJG
ALYWW
1
CASE 175AA
5
Features
1
• Adjustable Voltage Version (from 2.5 V to 20 V) ±2% Output
Voltage
• 400 mA Output Current
• 500 mV (max) Dropout Voltage (5.0 V Output)
• Inhibit Input
• Very Low Current Consumption
A
L
Y
= Assembly Location
= Wafer Lot
= Year
WW
G
= Work Week
= Pb−Free Device
*Tab is connected to Pin 3.
• Fault Protection
♦ +45 V Peak Transient Voltage
♦ −42 V Reverse Voltage
♦ Short Circuit
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 11 of this data sheet.
♦ Thermal Overload
• NCV Prefix for Automotive and Other Applications Requiring Site
and Change Controls
• These are Pb−Free Devices
I
Q
Error
Amplifier
Current Limit and
Saturation Sense
Bandgap
Reference
−
+
Thermal
Shutdown
INH
GND
VA
Figure 1. Block Diagram
©
Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
June, 2010 − Rev. 0
NCV4276B/D
NCV4276B
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Description
1
2
3
4
5
I
Input; Battery Supply Input Voltage.
INH
GND
VA
Inhibit; Set low−to inhibit.
Ground; Pin 3 internally connected to heatsink.
Voltage Adjust Input; use an external voltage divider to set the output voltage
Q
Output: Bypass with a capacitor to GND. See Figures NO TAG to 3 and Regulator Stability Considerations sec-
tion.
MAXIMUM RATINGS*
Rating
Symbol
Min
−42
−
Max
45
Unit
V
Input Voltage
V
I
V
I
Input Peak Transient Voltage
Inhibit INH Voltage
45
V
V
−42
−0.3
−1.0
−
45
V
INH
Voltage Adjust Input VA
Output Voltage
V
10
V
VA
V
40
V
Q
Ground Current
I
100
40
mA
V
q
Input Voltage Operating Range
V
V
Q
+ 0.5 V or 4.5 V
(Note 1)
I
ESD Susceptibility
(Human Body Model)
(Machine Model)
−
−
4.0
250
−
−
kV
V
Junction Temperature
Storage Temperature
T
−40
−50
150
150
°C
°C
J
T
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*During the voltage range which exceeds the maximum tested voltage of I, operation is assured, but not specified. Wider limits may apply. Thermal
dissipation must be observed closely.
LEAD TEMPERATURE SOLDERING REFLOW (Note 2)
Lead Temperature Soldering
T
SLD
°C
Reflow (SMD styles only), Leaded, 60−150 s above 183, 30 s max at peak
Reflow (SMD styles only), Lead Free, 60−150 s above 217, 40 s max at peak
Wave Solder (through hole styles only), 12 sec max
−
−
−
240
265
310
THERMAL CHARACTERISTICS
Characteristic
Test Conditions (Typical Value)
Unit
Min Pad Board (Note 3)
1, Pad Board (Note 4)
Junction−to−Tab (psi−JLx, y
)
4.2
4.7
C/W
C/W
JLx
Junction−to−Ambient (R , q
)
100.9
46.8
q
JA JA
1. Minimum V = 4.5 V or (V + 0.5 V), whichever is higher.
I
Q
2. Per IPC / JEDEC J−STD−020C.
2
2
2
3. 1 oz. copper, 0.26 inch (168 mm ) copper area, 0.062″ thick FR4.
2
4. 1 oz. copper, 1.14 inch (736 mm ) copper area, 0.062″ thick FR4.
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2
NCV4276B
ELECTRICAL CHARACTERISTICS (V = 13.5 V; −40°C < T < 150°C; unless otherwise noted.)
I
J
Characteristic
OUTPUT
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
AV
5.0 mA < I < 400 mA
−2%
−
+2%
V
Q
Q
V +1 < V < 40 V
Q
I
V > 4.5 V
I
Output Current Limitation
I
V
V
= 90% V
(V = 2.5 V)
QTYP
400
700
1100
10
mA
Q
Q
QTYP
Quiescent Current (Sleep Mode)
I
= 0 V
−
−
mA
q
INH
I = I − I
q
I
Q
Quiescent Current, I = I − I
I
I
I
I
I
I
= 1.0 mA
= 250 mA
= 400 mA
−
−
−
−
−
−
130
10
200
15
mA
q
I
Q
Q
Q
q
q
q
Q
Q
Q
Q
Q
Quiescent Current, I = I − I
I
I
mA
mA
mV
mV
mV
q
I
Quiescent Current, I = I − I
25
35
q
I
Dropout Voltage
Load Regulation
Line Regulation
V
DR
= 250 mA, V = V − V , V > 4.5 V
250
3.0
4.0
500
20
DR
I
Q
I
DV
= 5.0 mA to 400 mA
Q,LO
DV
DV = 12 V to 32 V,
15
Q
I
I
Q
= 5.0 mA
Power Supply Ripple Rejection
Temperature Output Voltage Drift
PSRR
f = 100 Hz, V = 0.5 V
−
−
70
−
−
dB
r
r
PP
d
−
0.5
mV/K
VQ/dT
INHIBIT
Inhibit Voltage, Output High
V
V
V
V
V
w V
QMIN
−
2.3
2.2
10
2.8
−
V
V
INH
INH
INH
Q
Inhibit Voltage, Output Low (Off)
Input Current
v 0.1 V
1.8
5.0
Q
I
= 5.0 V
20
mA
INH
THERMAL SHUTDOWN
Thermal Shutdown Temperature*
T
SD
I
Q
= 5.0 mA
150
−
210
°C
*Guaranteed by design, not tested in production.
V
Q
= [(R1 + R2) * V ] / R2
ref
Output
I
I
I
Q
I 1
5 Q
Input
C
I1
C
I2
C
Q
C *
b
1.0 mF
100 nF
22 mF
R
R
1
NCV4276B
INH
VA
R
L
2
4
3
I
INH
GND
2
C * − Required if usage of low ESR output capacitor C is demand, see Regulator Stability Considerations section
b
Q
Figure 2. Applications Circuit
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NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS
100
10
C
Q
= 22 mF for these
Output Voltages
Unstable Region
12 V
6 V
1
2.5 V
Stable Region
0.1
0.01
Unstable Region
C capacitor not connected
b
0
50
100
150 200
250
300
350 400
OUTPUT CURRENT (mA)
Figure 3. Output Stability with Output Capacitor ESR
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
5.0
4.5
T = 25°C
R = 20 W
L
J
V = 13.5 V, R = 1 kW
I
L
4.0
3.5
3.0
2.5
2.0
1.5
1.0
2.46
2.45
0.5
0
−40
0
40
80
120
160
0
10
20
30
40
50
T , JUNCTION TEMPERATURE (°C)
J
V , INPUT VOLTAGE (V)
I
Figure 4. Output Voltage vs. Junction
Temperature
Figure 5. Current Consumption vs. Input Voltage
4
3.5
3
2
0
T = 25°C
R = 20 W
L
J
−2
−4
2.5
2
−6
−8
−10
−12
−14
1.5
1
T = 25°C
R = 6.8 kW
L
J
0.5
0
−16
−18
−50
−25
0
25
50
0
2
4
6
8
10
V , INPUT VOLTAGE (V)
I
V , INPUT VOLTAGE (V)
I
Figure 6. Low Voltage Behavior
Figure 7. High Voltage Behavior
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NCV4276B
TYPICAL PERFORMANCE CHARACTERISTICS
600
500
400
300
200
800
700
600
T = 125°C
J
500
400
T = 25°C
J
V
Q
= 0 V
T = 25°C
J
300
200
100
0
100
0
0
50
100
150 200
250 300
350 400
0
10
20
30
40
50
I , OUTPUT CURRENT (mA)
Q
V , INPUT VOLTAGE (V)
I
Figure 9. Maximum Output Current vs.
Input Voltage
Figure 8. Dropout Voltage vs. Output Current,
Regulator Set at 5.0 V
60
50
40
30
20
1.6
1.4
1.2
1.0
0.8
0.6
0.4
T = 25°C
V = 13.5 V
I
T = 25°C
V = 13.5 V
I
J
J
10
0
0.2
0
0
100
200
300
400
500
600
0
10
20
30
40
50
60
I , OUTPUT CURRENT (mA)
Q
I , OUTPUT CURRENT (mA)
Q
Figure 11. Current Consumption vs. Output
Current (Low Load)
Figure 10. Current Consumption vs.
Output Current (High Load)
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NCV4276B
Circuit Description
ESR characteristics were measured with ceramic
capacitors and additional series resistors to emulate ESR.
Low duty cycle pulse load current technique has been used
to maintain junction temperature close to ambient
temperature.
The NCV4276B is an integrated low dropout regulator
that provides a regulated voltage at 400 mA to the output.
It is enabled with an input to the inhibit pin. The regulator
voltage is provided by a PNP pass transistor controlled by
an error amplifier with a bandgap reference, which gives it
the lowest possible dropout voltage. The output current
capability is 400 mA, and the base drive quiescent current
is controlled to prevent oversaturation when the input
voltage is low or when the output is overloaded. The
regulator is protected by both current limit and thermal
shutdown. Thermal shutdown occurs above 150°C to
protect the IC during overloads and extreme ambient
temperatures.
Calculating Bypass Capacitor
If usage of low ESR ceramic capacitors is demanded,
connect the bypass capacitor C between Voltage Adjust
b
pin and Q pin according to Applications circuit at Figure 4.
Parallel combination of bypass capacitor C with the
b
feedback resistor R contributes in the device transfer
1
function as an additional zero and affects the device loop
stability, therefore its value must be optimized. Attention
to the Output Capacitor value and its ESR must be paid. See
also Stability in High Speed Linear LDO Regulators
Application Note, AND8037/D for more information.
Optimal value of bypass capacitor is given by following
expression
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (V ) and drives the base of a
Q
PNP series pass transistor via a buffer. The reference is a
bandgap design to give it a temperature−stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Oversaturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized. See Figure 2, Test Circuit, for
circuit element nomenclature illustration.
1
C
b
+
@ (F)
2 p f R
z
1
where
R = the upper feedback resistor
1
f = the frequency of the zero added into the device
z
transfer function by R and C external components.
1
b
Set the R resistor according to output voltage
1
Regulator Stability Considerations
requirement. Chose the f with regard on the output
z
The input capacitors (C and C ) are necessary to
I1
I2
capacitance C , refer to the table below.
Q
stabilize the input impedance to avoid voltage line
influences. Using a resistor of approximately 1.0 W in
C
Q
(mF)
10
22
47
100
series with C can stop potential oscillations caused by
stray inductance and capacitance.
I2
f Range (kHz)
z
20 - 50
14 - 35
10 - 20
7 – 14
The output capacitor helps determine three main
characteristics of a linear regulator: startup delay, load
transient response and loop stability. The capacitor value
and type should be based on cost, availability, size and
temperature constraints. The aluminum electrolytic
capacitor is the least expensive solution, but, if the circuit
operates at low temperatures (−25°C to −40°C), both the
value and ESR of the capacitor will vary considerably. The
capacitor manufacturer’s data sheet usually provides this
information.
Ceramic capacitors and its part numbers listed bellow
have been used as low ESR output capacitors C from the
Q
table above to define the frequency ranges of additional
zero required for stability.
GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206)
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210)
GRM32ER61C476ME15 (47 mF, 16 V, X5R, 1210)
GRM32ER60J107ME20 (100 mF, 6.3 V, X5R, 1210)
Inhibit Input
The value for the output capacitor C , shown in Figure 2,
Q
The inhibit pin is used to turn the regulator on or off. By
holding the pin down to a voltage less than 1.8 V, the output
of the regulator will be turned off. When the voltage on the
Inhibit pin is greater than 2.8 V, the output of the regulator
will be enabled to power its output to the regulated output
voltage. The inhibit pin may be connected directly to the
input pin to give constant enable to the output regulator.
should work for most applications; see also Figure 3 for
output stability at various load and Output Capacitor ESR
conditions. Stable region of ESR in Figure 3 shows ESR
values at which the LDO output voltage does not have any
permanent oscillations at any dynamic changes of output
load current. Marginal ESR is the value at which the output
voltage waving is fully damped during four periods after
the load change and no oscillation is further observable.
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NCV4276B
Setting the Output Voltage
Use R2 < 50 k to avoid significant voltage output errors
due to VA bias current.
Connecting VA directly to Q without R1 and R2 creates
an output voltage of 2.5 V.
Designers should consider the tolerance of R1 and R2
during the design phase.
The input voltage range for operation (pin 1) of the
The output voltage range can be set between 2.5 V and
20 V. This is accomplished with an external resistor divider
feeding back the voltage to the IC back to the error
amplifier by the voltage adjust pin VA. The internal
reference voltage is set to a temperature stable reference of
2.5 V.
The output voltage is calculated from the following
adjustable version is between (V + 0.5 V) and 40 V.
Q
formula. Ignoring the bias current into the VA pin:
Internal bias requirements dictate a minimum input voltage
of 4.5 V. The dropout voltage for output voltages less than
V
Q
+ [(R1 ) R2) * V ]ńR2
ref
4.0 V is (4.5 V − V ).
Q
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NCV4276B
Calculating Power Dissipation
Heatsinks
in a Single Output Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 12) is:
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
P
+ [V
I(max)
* V
]I
(1)
D(max)
Q(min) Q(max)
) V
I
I(max) q
summed to determine the value of R
:
JA
where
q
(3)
R
+ R
qJC
) R ) R
qCS qSA
V
V
I
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the
application,
qJA
I(max)
Q(min)
Q(max)
where
R
R
R
is the junction−to−case thermal resistance,
is the case−to−heatsink thermal resistance,
is the heatsink−to−ambient thermal
resistance.
JC
q
q
q
CS
SA
I
is the quiescent current the regulator
q
consumes at I
.
Q(max)
Once the value of P
permissible value of R
is known, the maximum
D(max)
R
q
appears in the package section of the data sheet.
JC
can be calculated:
JA
q
Like R , it too is a function of package type. R
and
JA
CS
q
q
o
T
150 C *
A
R
qJA
+
R
are functions of the package type, heatsink and the
interface between them. These values appear in data sheets
of heatsink manufacturers.
(2)
SA
q
P
D
The value of R
can then be compared with those in the
JA
q
package section of the data sheet. Those packages with
Thermal, mounting, and heatsinking considerations are
discussed in the ON Semiconductor application note
AN1040/D.
R
less than the calculated value in Equation 2 will keep
JA
q
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
I
Q
I
I
SMART
REGULATOR®
V
I
V
Q
Control
Features
}
Iq
Figure 12. Single Output Regulator with Key
Performance Parameters Labeled
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NCV4276B
Thermal Model
A discussion of thermal modeling is in the ON Semiconductor web site: http://www.onsemi.com/pub/collateral/BR1487−D.PDF.
Table 1. DPAK 5−Lead Thermal RC Network Models
2
2
2
2
Drain Copper Area (1 oz thick)
(SPICE Deck Format)
168 mm
736 mm
168 mm
736 mm
Cauer Network
Foster Network
2
2
168 mm
1.00E−06
1.00E−05
6.00E−05
1.00E−04
4.36E−04
6.77E−02
1.51E−01
4.80E−01
3.740
736 mm
Units
Tau
Tau
Units
sec
sec
sec
sec
sec
sec
sec
sec
sec
sec
C_C1
C_C2
C_C3
C_C4
C_C5
C_C6
C_C7
C_C8
C_C9
C_C10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1.00E−06
1.00E−05
6.00E−05
1.00E−04
3.64E−04
1.92E−02
1.27E−01
1.018
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
1.36E−08
7.41E−07
1.04E−05
3.91E−05
1.80E−03
3.77E−01
3.79E+00
2.65E+01
8.71E+01
1.361E−08
7.411E−07
1.029E−05
3.737E−05
1.376E−03
2.851E−02
9.475E−01
1.173E+01
8.59E+01
2.955
10.322
0.438
2
2
168 mm
736 mm
R’s
R’s
R_R1
R_R2
R_R3
R_R4
R_R5
R_R6
R_R7
R_R8
R_R9
R_R10
Junction
node1
node2
node3
node4
node5
node6
node7
node8
node9
node1
node2
node3
node4
node5
node6
node7
node8
node9
GND
0.015
0.08
0.015
0.08
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
0.0123
0.0585
0.0304
0.3997
3.115
0.0123
0.0585
0.0287
0.3772
2.68
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
0.4
0.4
0.2
0.2
2.97519
8.2971
25.9805
46.5192
17.7808
0.1
2.6171
1.6778
7.4246
14.9320
19.2560
0.1758
3.571
1.38
12.851
35.471
46.741
5.92
7.39
28.94
NOTE: Bold face items represent the package without the external thermal system.
R
1
R
2
R
3
R
n
Junction
C
1
C
2
C
3
C
n
Time constants are not simple RC products. Amplitudes
of mathematical solution are not the resistance values.
Ambient
(thermal ground)
Figure 13. Grounded Capacitor Thermal Network (“Cauer” Ladder)
R
1
R
2
R
3
R
n
Junction
C
1
C
2
C
3
C
n
Each rung is exactly characterized by its RC−product
time constant; amplitudes are the resistances.
Ambient
(thermal ground)
Figure 14. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)
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NCV4276B
110
100
90
80
70
1 oz
60
2 oz
50
40
30
150 200 250 300 350 400 450 500 550 600 650 700 750
2
COPPER AREA (mm )
Figure 15. qJA vs. Copper Spreader Area
100
10
2
Cu Area 167 mm
2
Cu Area 736 mm
1.0
0.1
sqrt(t)
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
TIME (sec)
Figure 16. Single−Pulse Heating Curves
100
10
50% Duty Cycle
20%
10%
5%
2%
1%
1.0
0.1
Non−normalized Response
0.01
0.0000001
0.000001 0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
PULSE WIDTH (sec)
Figure 17. Duty Cycle for 1, Spreader Boards
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NCV4276B
ORDERING INFORMATION
†
Device
Output Voltage Accuracy
2%
Output Voltage
Package
Shipping
NCV4276BDTADJRKG
Adjustable
DPAK, 5−Pin
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCV4276B
PACKAGE DIMENSIONS
DPAK 5, CENTER LEAD CROP
DT SUFFIX
CASE 175AA−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
−T−
PLANE
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.51
0.46
0.61
MAX
6.22
6.73
2.38
0.71
0.58
0.81
E
V
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
R1
Z
A
K
S
4.56 BSC
1 2 3 4
5
0.87
0.46
2.60
1.01
0.58
2.89
U
K
L
1.14 BSC
R
0.170 0.190
4.32
4.70
0.63
0.51
0.89
3.93
4.83
5.33
1.01
−−−
1.27
4.32
F
J
R1 0.185 0.210
S
U
V
Z
0.025 0.040
0.020 −−−
0.035 0.050
0.155 0.170
L
H
D 5 PL
M
G
0.13 (0.005)
T
SOLDERING FOOTPRINT*
6.4
0.252
2.2
0.086
0.34
0.013
5.8
0.228
5.36
0.217
10.6
0.417
0.8
0.031
mm
inches
ǒ
Ǔ
SCALE 4:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
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