NCV4279BDWG [ONSEMI]
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型号: | NCV4279BDWG |
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描述: | 5V FIXED POSITIVE LDO REGULATOR, 0.6V DROPOUT, PDSO20, LEAD FREE, SOIC-20 稳压器 |
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NCV4279
5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Sense Output
http://onsemi.com
The NCV4279 is a 5.0 V precision micropower voltage regulator
with an output current capability of 150 mA.
MARKING
DIAGRAMS
The output voltage is accurate within 2.0% with a maximum
dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature
drawing only 150 mA with a 1.0 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active reset output RO
with delay and a SI/SO monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending reset
signal. The use of the SI/SO monitor allows the microprocessor to
finish any signal processing before the reset shuts the microprocessor
down.
8
SO−8
D SUFFIX
CASE 751
4279
ALYW
G
8
1
1
14
SO−14
D SUFFIX
CASE 751A
NCV4279
AWLYWWG
14
The active Reset circuit operates correctly at an output voltage as
low as 1.0 V. The Reset function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
1
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
The reset threshold voltage can be decreased by the connection of an
external resistor divider to the R
lead. The regulator is protected
ADJ
against reverse battery, short circuit, and thermal overload conditions.
The device can withstand load dump transients making it suitable for
use in automotive environments. The device has also been optimized
for EMC conditions.
If the application requires pullup resistors at the logic outputs Reset
and Sense Out, the NCV4269 with integrated resistors can be used.
G, G
= Lead Free Indicators
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Features
• 5.0 V 2.0% Output
• Low 150 mA Quiescent Current
• Active Reset Output Low Down to V = 1.0 V
Q
• Adjustable Reset Threshold
• 150 mA Output Current Capability
• Fault Protection
♦ +60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload
• Early Warning through SI/SO Leads
• Internally Fused Leads in SO−14 Package
• Very Low Dropout Voltage
• Electrical Parameters Guaranteed Over Entire Temperature Range
• Pb−Free Packages are Available
• NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
© Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
December, 2005 − Rev. 3
NCV4279/D
NCV4279
I
Q
Error
Amplifier
Current and
Reference
and Trim
Saturation
Control
RO
D
or
Reference
SO
R
ADJ
+
−
SI
GND
Figure 1. Block Diagram
PIN CONNECTIONS
1
14
R
SI
ADJ
1
8
D
I
I
Q
GND
GND
GND
GND
RO
GND
GND
GND
Q
SI
SO
RO
GND
R
ADJ
D
SO
SO−8
SO−14
PACKAGE PIN DESCRIPTION
Package Pin Number
SO−8
SO−14
Pin Symbol
Function
3
4
5
1
2
R
Reset Threshold Adjust; if not used to connect to GND.
Reset Delay; To Set Time Delay, Connect to GND with a Capacitor
Ground
ADJ
D
3, 4, 5, 6,
10, 11, 12
GND
6
7
8
1
2
7
8
RO
SO
Q
Reset Output; This is an Open−Collector Output. Leave Open if Not Used.
Sense Output; This is an Open−Collector Output. If not used, keep open.
5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W.
Input; Connect to GND Directly at the IC with a Ceramic Capacitor.
Sense Input; If not used, Connect to Q.
9
13
14
I
SI
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2
NCV4279
MAXIMUM RATINGS (T = −40°C to 150°C)
J
Parameter
Symbol
Min
Max
Unit
Input to Regulator
V
−40
45
V
I
I
I
Internally Limited Internally Limited
Input Peak Transient Voltage
Sense Input
V
−
60
V
I
V
−40
−1
45
1
V
mA
SI
SI
I
Reset Threshold Adjust
Reset Delay
V
I
−0.3
−10
7
10
V
mA
RADJ
RADJ
V
D
−0.3
7
V
I
D
Internally Limited Internally Limited
Ground
I
50
−
7
mA
V
q
Reset Output
V
RO
RO
−0.3
I
Internally Limited Internally Limited
Sense Output
V
I
−0.3
7
V
SO
SO
Internally Limited Internally Limited
Regulated Output
V
−0.5
−10
7.0
−
V
mA
Q
I
Q
Junction Temperature
Storage Temperature
T
STG
−
−50
150
150
°C
°C
J
T
Input Voltage Operating Range
Junction Temperature Operating Range
V
T
−
−40
45
150
V
°C
I
J
Junction−to−Ambient Thermal Resistance
SO−8
SO−14
R
R
−
−
200
70
k/W
q
JA
Junction−to−Pin 4, all GND Pins Grounded.
Lead Temperature Soldering and MSL
Parameter
SO−14
30
k/W
q
JP
Symbol
Value
Unit
MSL, 8−Lead, 14−Lead, LS Temperature 260°C Peak (Notes 3, 4)
MSL
1
−
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and exceeds the following ratings:
Human Body Model (HBM) ≤ 2.0 kV per JEDEC standard: JESD22–A114.
Machine Model (MM) ≤ 200 V per JEDEC standard: JESD22–A115.
2. Latchup Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78.
3. Lead free: 60−150 Sec above 217°C, 40 Sec Max at Peak, 265°C Peak.
4. Leaded; 60−150 Sec above 183°C, 30 Sec Max at Peak, 240°C Peak.
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3
NCV4279
ELECTRICAL CHARACTERISTICS (T = −40°C ≤ T ≤ 125°C, V = 13.5 V unless otherwise specified)
J
J
I
Characteristic
REGULATOR
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
Current Limit
V
1 mA v I v 100 mA; 6 V v V v 16 V
4.90
150
−
5.00
200
150
250
2.0
5.10
500
250
450
3.0
0.5
20
V
Q
Q
I
I
Q
−
mA
mA
mA
mA
V
Current Consumption; I = I – I
I
I
= 1 mA, RO, SO High
= 10 mA, RO, SO High
= 50 mA, RO, SO High
q
I
Q
Q
Q
q
q
q
Q
Current Consumption; I = I – I
I
I
I
−
q
I
Q
Current Consumption; I = I – I
I
−
q
I
Q
Dropout Voltage
Load Regulation
Line Regulation
V
dr
I
= 100 mA (Note 5)
= 5 mA to 100 mA
Q
−
0.25
10
Q
D
D
I
−
mV
mV
VQ
VQ
V = 6 V to 26 V; I = 1 mA
−
10
30
I
Q
RESET GENERATOR
Reset Switching Threshold
V
−
4.50
1.26
−
4.65
1.35
0.1
1.8
0.45
−
4.80
1.44
0.4
2.2
0.60
0.1
9.5
−
V
V
RT
Reset Adjust Switching Threshold
Reset Output Saturation Voltage
Upper Delay Switching Threshold
Lower Delay Switching Threshold
Saturation Voltage on Delay Capacitor
Charge Current
V
V > 3.5 V
Q
RAD,JTH
V
V
Q
< V , R = 20 kW
V
RO,SAT
RT RO
V
UD
−
−
1.4
0.3
−
V
V
V
LD
V
D,SAT
V
< V
RT
V
Q
I
V
= 1 V
3.0
17
−
6.5
28
mA
ms
ms
D
D
Delay Time L ³ H
t
C
C
= 100 nF
= 100 nF
d
D
D
Delay Time H ³ L
t
1.0
−
t
INPUT VOLTAGE SENSE
Sense Threshold High
V , High
−
−
1.24
1.16
−
1.31
1.20
0.1
1.38
1.28
0.4
V
V
SI
Sense Threshold Low
V , Low
SI
Sense Output Saturation Voltage
Sense Input Current
V , Low
SO
V
SI
< 1.20 V; V > 3 V; R = 20 kW
V
Q
SO
I
SI
−
−1.0
0.1
1.0
mA
5. Dropout voltage = V − V measured when the output voltage has dropped 100 mV from the nominal value obtained at 13.5 V input.
I
Q
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4
NCV4279
I
I
I
Q
I
Q
C
Q
22 mF
C
I
RADJ1
1000 mF
R
470 nF
RO
R
SO
I
SI
I
RADJ
SI
RADJ
V
Q
D
GND
RO
SO
V
I
I
D
I
q
V
RO
V
SO
V
SI
V
RADJ
V
D
C
RADJ2
D
100 nF
Figure 2. Measuring Circuit
V
I
t
< t
RR
V
Q
V
RT
t
t
dV
dt
I
D
+
V
D
C
D
V
UD
V
LD
t
RR
t
d
V
RO
V
RO,SAT
t
Power−on−Reset
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Secondary Overload
Spike at Output
Figure 3. Reset Timing Diagram
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5
NCV4279
Sense Input Voltage
V
SLHIGH
V
SLLOW
t
Sense Output Voltage
t
t
PDSOLH
PDSOHL
HIGH
LOW
t
Figure 4. Sense Timing Diagram
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6
NCV4279
TYPICAL PERFORMANCE CHARACTERISTICS
16
14
12
10
8
3.2
V = 13.5 V
I
V = 13.5 V
I
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
V
D
= 1.0 V
V
V
UD
6
4
LD
2
0
−40
0
40
80
120
160
−40
0
40
80
120
160
T (°C)
J
T (°C)
J
Figure 5. Charge Current ID,c vs. Temperature TJ
Figure 6. Switching Voltage VUD and VLD vs.
Temperature TJ
500
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
400
300
200
100
0
T = 125°C
J
T = 25°C
J
T = −40°C
J
0
30
60
90
(mA)
120
150
180
−40
0
40
80
120
160
I
Q
T (°C)
J
Figure 7. Drop Voltage VDR vs. Output Current IQ
Figure 8. Reset Adjust Switching Threshold
RADJ,TH vs. Temperature TJ
V
35
30
25
20
15
10
5
12
10
8
R = 33 W
L
6
R = 50 W
L
4
R = 50 W
L
2
R = 200 W
L
R = 100 W
L
0
0
0
10
20
30
40
50
0
2
4
6
8
10
V (V)
I
V (V)
I
Figure 9. Current Consumption Iq vs.
Input Voltage VI
Figure 10. Output Voltage VQ vs.
Input Voltage VI
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NCV4279
TYPICAL PERFORMANCE CHARACTERISTICS
5.2
1.6
1.5
1.4
1.3
1.2
1.1
1.0
V = 13.5 V
I
V = 13.5 V
I
2.1
5.0
4.9
4.8
4.7
4.6
Sense Output High
Sense Output Low
−40
0
40
80
120
160
−40
0
40
80
120
160
T (°C)
J
T (°C)
J
Figure 12. Output Voltage VQ vs. Temperature TJ
Figure 11. Sense Threshold VSI vs. Temperature TJ
350
300
250
T = 25°C
J
200
T = 125°C
J
150
100
50
0
0
10
20
30
40
50
V (V)
I
Figure 13. Output Current IQ vs. Input Voltage VI
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8
NCV4279
TYPICAL PERFORMANCE CHARACTERISTICS
12
10
8
1.6
1.4
1.2
1.0
V = 13.5 V
T = 25°C
J
I
6
0.8
0.6
0.4
0.2
V = 13.5 V
T = 25°C
J
I
4
2
0
0
0
20
40
60
80
100
120
0
10
20
30
40
50
I
Q
(mA)
I (mA)
Q
Figure 14. Current Consumption Iq vs.
Output Current IQ
Figure 15. Current Consumption Iq vs.
Output Current IQ
7
6
5
4
3
2
1
0
250
200
150
100
50
T = 25°C
T = 25°C
J
J
I
= 100 mA
Q
I
= 100 mA
Q
I
= 50 mA
Q
I
= 10 mA
Q
0
6
8
10 12
14
16 18 20
22 24
26
6
8
10 12
14
16 18 20
V (V)
22 24
26
V (V)
I
I
Figure 16. Current Consumption Iq vs.
Input Voltage VI
Figure 17. Current Consumption Iq vs.
Input Voltage VI
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9
NCV4279
APPLICATION DESCRIPTION
OUTPUT REGULATOR
If the reset adjust option is not needed, the R
pin
ADJ
The output is controlled by a precision trimmed reference.
The PNP output has drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).
RESET DELAY (D)
The reset delay circuit provides a delay (programmable by
capacitor C ) on the reset output lead RO. The delay lead D
D
provides charge current I (typically 6.5 mA) to the external
D
RESET OUTPUT (RO)
A reset signal, Reset Output, RO, (low voltage) is
delay capacitor C during the following times:
D
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device is
back in regulation. The delay capacitor is set to
generated as the IC powers up. After the output voltage V
Q
increases above the reset threshold voltage V , the delay
RT
timer D is started. When the voltage on the delay timer V
D
passes V , the reset signal RO goes high. A discharge of
UD
discharge when the regulation (V , reset
RT
the delay timer V is started when V drops and stays below
D
Q
threshold voltage) has been violated. When the
the reset threshold voltage V . When the voltage of the
RT
delay capacitor discharges to V , the reset signal
LD
delay timer V drops below the lower threshold voltage V
D
LD
RO pulls low.
the reset output voltage V is brought low to reset the
RO
SETTING THE DELAY TIME
processor.
The delay time is set by the delay capacitor C and the
D
The reset output RO is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
charge current I . The time is measured by the delay
D
capacitor voltage charging from the low level of V
to
DSAT
the higher level V . The time delay follows the equation:
UD
guaranteeing that RO is valid for V as low as 1.0 V.
Q
(eq. 2)
t
d
+ [C (V
* V )]ńI
DSAT D
D
UD
RESET ADJUST (RADJ
)
Example:
Using C = 100 nF.
Use the typical value for V
The reset threshold V can be decreased from a typical
RT
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 18. The resistor divider keeps the voltage
D
= 0.1 V.
DSAT
Use the typical value for V = 1.8 V.
UD
Use the typical value for Delay Charge Current I = 6.5 mA.
above the V
(typical 1.35 V) for the desired input
D
RADJ,TH
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
(eq. 3)
t
d
+ [100 nF(1.8 * 0.1 V)]ń6.5 mA + 26.2 ms
V
RT
+ V
@ (R
) R
)ńR
ADJ2 ADJ2
(eq. 1)
RADJ, TH
ADJ1
V
BAT
I
Q
V
DD
C **
10 mF
R
R
Q
ADJ1
ADJ2
C *
I
0.1 mF
R
ADJ
NCV4279
R
R
SI1
D
R
RO
SI
R
SO
SI2
C
D
RO
I/O
SO
I/O
GND
*C required if regulator is located far from the power supply filter.
I
** C required for Stability. Cap must operate at minimum temperature expected.
Q
Figure 18. Application Diagram
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10
NCV4279
SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE
MONITOR
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturer’s data sheet usually provides this information.
An on−chip comparator is available to provide early
warning to the microprocessor of a possible reset signal. The
output is from an open collector driver. The reset signal
typically turns the microprocessor off instantaneously. This
can cause unpredictable results with the microprocessor.
The signal received from the SO pin will allow the
microprocessor time to complete its present task before
shutting down. This function is performed by a comparator
referenced to the band gap voltage. The actual trip point can
be programmed externally using a resistor divider to the
The value for the output capacitor C shown in Figure 18
Q
should work for most applications; however, it is not
necessarily the optimized solution. Stability is guaranteed at
values C = 10 mF and an ESR = 10 W within the operating
Q
temperature range. Actual limits are shown in a graph in the
typical data section.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 18) is:
input monitor SI (Figure 18). The values for R and R
SI1
SI2
are selected for a typical threshold of 1.20 V on the SI Pin.
SIGNAL OUTPUT
Figure 19 shows the SO Monitor timing waveforms as a
result of the circuit depicted in Figure 18. As the output
P
+ [V
I(max)
* V
]I
) V
I
(eq. 4)
D(max)
Q(min) Q(max)
I(max) q
where:
V
I(max)
is the maximum input voltage,
voltage (V ) falls, the monitor threshold (V
), is
SILOW
Q
V
is the minimum output voltage,
is the maximum output current for the application,
crossed. This causes the voltage on the SO output to go low
sending a warning signal to the microprocessor that a reset
Q(min)
I
Q(max)
and I is the quiescent current the regulator consumes at
signal may occur in a short period of time. T
is the
q
WARNING
I
.
time the microprocessor has to complete the function it is
currently working on and get ready for the reset
shutdown signal.
Q(max)
Once the value of P
is known, the maximum
D(max)
permissible value of R
can be calculated:
qJA
= (150°C – T ) / P
D
R
(eq. 5)
q
JA
A
V
Q
The value of R
can then be compared with those in the
qJA
package section of the data sheet. Those packages with
’s less than the calculated value in equation 2 will keep
the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required. The current
R
qJA
SI
V
SILOW
flow
and
voltages
are
shown
in
the
V
RO
Measurement Circuit Diagram.
HEATSINKS
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
SO
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
T
WARNING
Figure 19. SO Warning Waveform Time Diagram
determine the value of R
:
qJA
R
+ R
) R
) R
qCS qSA
(eq. 6)
qJA
qJC
STABILITY CONSIDERATIONS
where:
The input capacitor C in Figure 18 is necessary for
I
R
R
R
= the junction−to−case thermal resistance,
compensating input line reactance. Possible oscillations
caused by input inductance and input capacitance can be
damped by using a resistor of approximately 1.0 W in series
qJC
= the case−to−heat sink thermal resistance, and
= the heat sink−to−ambient thermal resistance.
appears in the package section of the data sheet. Like
qCS
qSA
R
with C
qJC
I.
R
, it too is a function of package type. R
and R
are
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
qJA
qCS
qSA
functions of the package type, heatsink and the interface
between them. These values appear in data sheets of
heatsink manufacturers. Thermal, mounting, and
heatsinking considerations are discussed in the
ON Semiconductor application note AN1040/D, available
on the ON Semiconductor website.
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11
NCV4279
ORDERING INFORMATION
Device
†
Output Voltage
Package
Shipping
NCV4279D1
SO−8
98 Units/Rail
2500 Tape & Reel
55 Units/Rail
NCV4279D1G
SO−8
(Pb−Free)
NCV4279D1R2
SO−8
NCV4279D1R2G
SO−8
(Pb−Free)
5.0 V
NCV4279D2
SO−14
NCV4279D2G
SO−14
(Pb−Free)
NCV4279D2R2
SO−14
2500 Tape & Reel
NCV4279D2R2G
SO−14
(Pb−Free)
†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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12
NCV4279
PACKAGE DIMENSIONS
SO−8
D SUFFIX
CASE 751−07
ISSUE AF
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
13
NCV4279
PACKAGE DIMENSIONS
SO−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
8.75
4.00
1.75
0.49
1.25
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
_
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
0.337
0.150
0.054
0.014
0.016
−T−
SEATING
PLANE
J
M
G
J
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T
B
A
K
M
P
R
_
_
_
_
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
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