NCV4299CD250R2G [ONSEMI]
150 mA Low-Dropout Voltage Regulator;
| 型号： | NCV4299CD250R2G |
| 厂家： | 
ONSEMI |
| 描述： | 150 mA Low-Dropout Voltage Regulator 光电二极管 输出元件 调节器 |
| 文件： | 总19页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV4299C
150 mA Low-Dropout
Voltage Regulator
The NCV4299C is a family of precision micropower voltage
regulators with an output current capability of 150 mA. It is available in
5.0 V or 3.3 V output voltage.
The output voltage is accurate within 2% with a maximum dropout
voltage of 0.5 V at 100 mA. Low Quiescent current is a feature
drawing only 80 mA with a 100 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
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MARKING
DIAGRAMS
8
The device features microprocessor interfaces including an
adjustable reset output and adjustable system monitor to provide
shutdown early warning. An inhibit function is available. With inhibit
active, the regulator turns off and the device consumes less than
1.0 mA of quiescent current.
SO−8
D1 SUFFIX
CASE 751
299Cx
ALYW
G
8
1
1
14
The part can withstand load dump transients making it suitable for
use in automotive environments.
SO−14
D2 SUFFIX
CASE 751A
V4299CxxG
AWLYWW
14
Features
1
1
• 5.0 V, 3.3 V 2%, 150 mA
• Extremely Low Current Consumption
♦ 80 mA (Typ) in the ON Mode
♦ t1.0 mA in the Off Mode
• Early Warning
x, xx
A
= 3 or 33 (3.3 V Version)
= 5 or 50 (5.0 V Version)
= Assembly Location
WL, L = Wafer Lot
= Year
• Reset Output Low Down to V = 1.0 V
Q
Y
WW, W = Work Week
• Adjustable Reset Threshold
• Wide Temperature Range
G or G = Pb−Free Package
(Note: Microdot may be in either location)
• Fault Protection
♦ 60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
PIN CONNECTIONS
1
14
♦ Thermal Overload
RADJ
D
SI
• Internally Fused Leads on SO−14 Package
• Inhibit Function with 1 mA Current Consumption in the Off Mode
• AEC−Q100 Grade 1 Qualified and PPAP Capable
• These are Pb−Free Devices
I
1
8
Q
I
SI
RADJ
GND
GND
GND
INH
RO
GND
GND
GND
Q
SO
RO
GND
D
SOIC−8
SO
SOIC−14
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
November, 2014 − Rev. 0
NCV4299C/D
NCV4299C
Q
I
Current Limit and
Saturation Sense
Bandgap
Reference
-
+
R
SO
R
RO
SO
RO
1.36 V
+
−
SI
7.1 mA
+
+
-
-
+
RADJ
1.85 V
D
GND
Figure 1. SO−8 Simplified Block Diagram
PIN FUNCTION DESCRIPTION − SO−8 PACKAGE
Pin
1
Symbol
Description
Input. Battery Supply Input Voltage. Bypass directly to GND with ceramic capacitor.
I
2
SI
Sense Input. Can provide an early warning signal of an impending reset condition when used with SO.
Connect to Q if not used.
3
4
5
6
RADJ
D
Reset Adjust. Use resistor divider to Q to adjust reset threshold lower. Connect to GND if not used.
Reset Delay. Connect external capacitor to ground to set delay time.
Ground.
GND
RO
Reset Output. NPN collector output with internal 20 kW pullup to Q. Notifies user of out of regulation
condition. Leave open if not used.
7
8
SO
Q
Sense Output. NPN collector output with internal 20 kW pullup to Q. Can be used to provide early warning
of an impending reset condition. Leave open if not used.
5.0 V, 3.3 V, 2%, 150 mA output. Use 22 mF, ESR t 4 W to ground.
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2
NCV4299C
Q
I
Current Limit and
Saturation Sense
Bandgap
Reference
-
+
R
SO
R
RO
INH
SO
RO
1.36 V
+
−
SI
7.1 mA
+
+
-
-
+
RADJ
1.85 V
D
GND
Figure 2. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
SOIC−14
Symbol
RADJ
D
Description
1
2
3
4
5
6
Reset Adjust. Use resistor divider to Q to adjust reset threshold lower. Connect to GND if not used.
Reset Delay. Connect external capacitor to ground to set delay time.
GND
GND
GND
INH
Ground
Ground
Ground
Inhibit. Connect to I if not needed. A high turns the regulator on. Use a low pass filter if transients with slew rate in
excess of 10 V/ms may be present on this pin during operation. See Figure 34 for details.
7
8
RO
SO
Reset Output. NPN collector output with internal 20 kW pullup to Q. Notifies user of out of regulation condition.
Sense Output. NPN collector output with internal 20 kW pullup to Q. Can be used to provide early warning of an
impending reset condition.
9
Q
GND
GND
GND
I
5.0 V, 3.3 V, "2%, 150 mA output. Use 22 mF, ESR t 4 W to ground.
10
11
12
13
14
Ground
Ground
Ground
Input. Battery Supply Input Voltage.
SI
Sense Input. Can provide an early warning signal of an impending reset condition when used with SO.
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3
NCV4299C
MAXIMUM RATINGS
Rating
Symbol
Min
Max
Unit
Input Voltage to Regulator (DC)
V
−40
−
45
60
45
45
1.0
7.0
10
7.0
7.0
20
7.0
16
−
V
V
I
Input Peak Transient Voltage to Regulator wrt GND (Note 1)
Inhibit (INH)
−
V
INH
−40
−40
−1.0
−0.3
−10
−0.3
−0.3
−20
−0.3
−0.3
−5.0
2.0
V
Sense Input (SI)
V
SI
V
Sense Input (SI)
I
SI
mA
V
Reset Threshold (RADJ)
Reset Threshold (RADJ)
Reset Delay (D)
V
RADJ
RADJ
I
mA
V
V
D
Reset Output (RO)
V
RO
RO
V
Reset Output (RO)
I
mA
V
Sense Output (SO)
V
SO
Output (Q)
V
Q
V
Output (Q)
I
Q
mA
kV
V
ESD Capability, Human Body Model (Note 3)
ESD Capability, Machine Model (Note 3)
ESD Capability, Charged Device Model (Note 3)
Junction Temperature
ESD
−
HB
MM
CDM
J
ESD
200
1.0
−
ESD
T
−
kV
°C
°C
−
150
150
Storage Temperature
T
stg
−50
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING RANGE
Input Voltage
5.0 V Version
3.3 V Version
V
T
5.5
4.4
45
45
V
I
Junction Temperature
−40
150
°C
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
LEAD TEMPERATURE SOLDERING REFLOW (Note 2)
Reflow (SMD styles only), lead free 60 s−150 sec above 217, 40 sec max at peak
T
−
265 Pk
Level 1
°C
SLD
Moisture Sensitivity Level
SO−8
MSL
SO−14
Level 1
1. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class C according to ISO16750−1
2. Per IPC / JEDEC J−STD−020C.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (JS−001−2010)
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A115)
ESD CDM tested per AEC−Q100−011 (EIA/JESD22−C101).
THERMAL CHARACTERISTICS
Test Conditions (Typical Value)
Note 4
Note 5
Note 6
Characteristic
Unit
Thermal Characteristics, SO−8
Junction−to−Lead (y , q
)
)
72
198
58
150.7
58.3
124.5
°C/W
JLx JLx
Junction−to−Ambient (R , q
θ
JA JA
Thermal Characteristics, SO−14
Junction−to−Lead (y , q
)
)
15.1
142.7
19.9
101.2
19.3
86.1
°C/W
°C/W
JLx JLx
Junction−to−Ambient (R , q
θ
JA JA
Thermal Characteristics, TSSOP−14 EP
Junction−to−Tab (y , q
)
)
9.7
111.6
11.4
78.7
11.7
53.7
JLx JLx
Junction−to−Ambient (R , q
θ
JA JA
4. 2 oz Copper, 50 mm sq Copper area, 1.5 mm thick FR4.
5. 2 oz Copper, 150 mm sq Copper area, 1.5 mm thick FR4.
6. 2 oz Copper, 500 mm sq Copper area, 1.5 mm thick FR4.
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4
NCV4299C
ELECTRICAL CHARACTERISTICS (−40°C < T < 150°C; V = 13.5 V unless otherwise noted.)
J
I
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
OUTPUT Q
Output Voltage (5.0 V Version)
Output Voltage (3.3 V Version)
Current Limit
V
V
1.0 mA < I < 150 mA, 6.0 V < V < 16 V
4.9
3.23
250
−
5.0
3.3
430
80
5.1
3.37
500
90
V
Q
Q
I
1.0 mA < I < 150 mA, 5.5 V < V < 16 V
V
Q
Q
I
I
Q
V
Q
= 90% of V
Qnom
mA
mA
mA
mA
mA
mA
V
Quiescent Current (I = I – I )
I
INH ON, I < 100 mA, T = 25°C
Q J
q
I
Q
q
q
q
q
q
Quiescent Current (I = I – I )
I
I
I
I
INH ON, I < 100 mA, T ≤ 125°C
−
80
95
q
I
Q
Q
J
Quiescent Current (I = I – I )
INH ON, I = 10 mA
−
200
0.8
−
500
2.0
1.0
0.50
30
q
I
Q
Q
Quiescent Current (I = I – I )
INH ON, I = 50 mA
−
q
I
Q
Q
Quiescent Current (I = I – I )
INH = 0 V, T = 25°C
−
q
I
Q
J
Dropout Voltage (Note 7)
Load Regulation
V
dr
I
= 100 mA
−
0.26
1.0
2.0
66
Q
Q
DV
DV
I
= 1.0 mA to 100 mA
−
mV
mV
dB
Q
Line Regulation
V = 6.0 V to 28 V, I = 1.0 mA
−
25
Q
I
Q
Power Supply Ripple Rejection
INHIBIT (INH)
PSRR
ƒr = 100 Hz, Vr = 1.0 Vpp, I = 100 mA
−
−
Q
Inhibit Off Voltage
V
V
< 0.1 V
−
−
0.8
V
V
INHOFF
Q
Inhibit On Voltage
5.0 V Version
V
INHON
V
Q
V
Q
> 4.9 V
> 3.23 V
3.5
3.5
−
−
−
−
3.3 V Version
Input Current
I
INH = 5 V
INH = 0 V
−
−
3.8
10
mA
INHON
I
0.01
2.0
INHOFF
RESET (RO)
Switching Threshold
5.0 V Version
V
−
−
V
RT
4.50
2.96
4.67
3.07
4.80
3.16
3.3 V Version
Output Resistance
R
V
10
20
40
kW
RO
Reset Output Low Voltage
5.0 V Version
V
RO
V
Q
V
Q
= 4.5 V, Internal R , I = −1.0 mA
−
−
0.05
0.05
0.40
0.40
RO RO
3.3 V Version
= 2.96 V, Internal R , I = −1.0 mA
RO RO
Allowable External Reset Pullup Resistor
Delay Upper Threshold
V
External Resistor to Q
5.6
1.5
0.4
−
−
kW
V
ROext
V
−
1.85
0.5
2.2
0.6
UD
Delay Lower Threshold
V
−
V
LD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Only for 5 V version. Measured when the output voltage V has dropped 100 mV from the nominal value obtained at V = 13.5 V.
Q
I
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5
NCV4299C
ELECTRICAL CHARACTERISTICS (continued) (−40°C < T < 150°C; V = 13.5 V unless otherwise noted.)
J
I
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
RESET (RO)
Delay Output Low Voltage
5.0 V Version
V
D,sat
V
V
Q
V
Q
= 4.5 V, Internal R
= 2.96 V, Internal R
−
−
−
0.1
0.1
RO
3.3 V Version
0.017
RO
Delay Charge Current
Power On Reset Delay Time
Reset Reaction Time
I
V
= 1.0 V
4.0
17
7.1
28
12
35
mA
ms
ms
V
D
D
t
C
C
= 100 nF
d
D
D
t
= 100 nF
0.5
1.6
4.0
RR
V
RADJ,TH
Reset Adjust Switching Threshold
5.0 V Version
V
Q
V
Q
= 3.5 V
= 2.3 V
1.26
1.26
1.36
1.36
1.44
1.44
3.3 V Version
INPUT VOLTAGE SENSE (SI and SO)
Sense Input Threshold High
Sense Input Threshold Low
Sense Input Hysteresis
V
−
−
1.34
1.26
50
1.45
1.36
90
1.54
1.44
130
V
V
SI,High
V
SI,Low
−
(Sense Threshold High) −
(Sense Threshold Low)
mV
Sense Input Current
I
R
V
V
= 1.2 V
−1.0
10
0.1
20
0.1
−
1.0
40
0.4
−
mA
kW
V
SI
SI
Sense Output Resistance
Sense Output Low Voltage
−
SO
SO
V
SI
= 1.2 V, V = 5.5 V, I = 0 mA
−
I
SO
Allowable External Sense Out
Pullup Resistor
R
−
5.6
kW
SOext
SI High to SO High Reaction Time
SI Low to SO Low Reaction Time
THERMAL SHUTDOWN
t
R
R
= 5.6 kW
= 5.6 kW
−
−
1.3
2.2
8.0
5.0
ms
ms
PSOLH
SOext
SOext
t
PSOHL
Thermal Shutdown Temperature (Note 8)
T
SD
I
= 1 mA
150
−
200
°C
out
8. Values based on design and/or characterization.
I
I
I
Q
V
Q
V
I
I
Q
I
INH
V
INH
INH
D
V
RO
SO
RO
C
D
I
D
100 nF
I
RADJ
V
RADJ
RADJ
SI
V
SO
I
SI
V
SI
GND
I
q
Figure 3. Measurement Circuit
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6
NCV4299C
TYPICAL PERFORMANCE CHARACTERISTICS − 5.0 V OPTION
5.1
6
V = 13.5 V
I
I
Q
= 100 mA
5
4
3
5.0
4.9
2
I
Q
= 100 mA
1
0
T = 25°C
J
−40 −20
0
20 40
60 80 100 120 140 160
0
2
4
6
8
10
12
14
T , JUNCTION TEMPERATURE (°C)
J
V , INPUT VOLTAGE (V)
I
Figure 5. Output Voltage vs. Input Voltage
Figure 4. Output Voltage vs. Junction Temperature
8.0
500
T = 150°C
J
V = 13.5 V
I
V
= 1 V
= 100 mA
D
400
7.6
7.2
6.8
6.4
6.0
I
Q
T = 25°C
J
300
200
100
0
T = −40°C
J
−40 −20
0
20 40
60 80 100 120 140 160
0
50
100
150
T , JUNCTION TEMPERATURE (°C)
J
I , OUTPUT CURRENT (mA)
Q
Figure 6. Charge Current vs. Junction
Temperature
Figure 7. Drop Voltage vs. Output Current
3.2
2.8
2.4
2.0
1.6
1.2
0.8
1.5
V = 13.5 V
I
V = 13.5 V
I
1.4
1.3
1.2
1.1
1.0
0.9
0.4
0
−40
0
40
80
120
160
−40
0
40
80
120
160
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 8. Switching Voltage vs. Junction
Temperature
Figure 9. Reset Adjust Switching Threshold vs.
Junction Temperature
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NCV4299C
400
350
300
250
200
150
100
50
1.6
1.5
T = 125°C
J
V
SI,Low
T = 25°C
J
1.4
1.3
1.2
V
SI,High
1.1
1.0
V
Q
= 0 V
0
−40
0
40
120
160
0
10
20
30
40
80
T , JUNCTION TEMPERATURE (°C)
J
V , INPUT VOLTAGE (V)
I
Figure 11. Output Current vs. Input Voltage
Figure 10. Sense Threshold vs. Junction
Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1000
100
V = 13.5 V
I
V = 13.5 V
T = 25°C
J
I
I
Q
= 100 mA
10
1
−40 −20
0
20 40 60 80 100 120 140 160
0
40
80
120
160
I , OUTPUT CURRENT (mA)
Q
T , JUNCTION TEMPERATURE (°C)
J
Figure 12. Current Consumption vs. Junction
Temperature
Figure 13. Current Consumption vs. Output
Current
16
14
12
10
8
40
35
30
T = 25°C
J
I
Q
= 25 mA
I
Q
= 150 mA
I
Q
= 50 mA
25
20
I
= 100 mA
6
Q
4
15
10
2
0
0
10
20
V , INPUT VOLTAGE (V)
30
40
−40
0
40
80
120
160
T , JUNCTION TEMPERATURE (°C)
J
I
Figure 14. RRO, RSO Resistance vs. Junction
Temperature
Figure 15. Current Consumption vs. Input
Voltage
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NCV4299C
120
110
100
3.0
2.5
2.0
1.5
1.0
0.5
0
T = 25°C
J
T = 25°C
J
90
80
70
60
I
Q
= 100 mA
I
= 100 mA
Q
I
Q
= 50 mA
50
40
I
Q
= 10 mA
6
8
10 12 14 16 18 20 22 24
V , INPUT VOLTAGE (V)
26
6
8
10 12
14 16 18
20 22 24 26
V , INPUT VOLTAGE (V)
I
I
Figure 17. Current Consumption vs. Input
Voltage
Figure 16. Current Consumption vs. Input
Voltage
100
V = 13.5 V
T = 25°C
J
I
Unstable Region
10
1
1 mF to 100 mF
0.1
0.01
Stable Region
0
25
50
75
100
125
150
I , OUTPUT CURRENT (mA)
Q
Figure 18. Output Stability vs. Output Capacitor
ESR
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NCV4299C
TYPICAL PERFORMANCE CHARACTERISTICS − 3.3 V OPTION
1000
100
5
V = 13.5 V
I
V = 13.5 V
I
I
Q
= 100 mA
4
3
2
T = 150°C
J
T = 25°C
J
T = −40°C
J
10
1
1
0
−40 −20
0
20 40 60 80 100 120 140 160
0
20
40
60
80
100
120 140 160
T , JUNCTION TEMPERATURE (°C)
J
I , OUTPUT CURRENT (mA)
Q
Figure 19. Current Consumption vs. Junction
Temperature
Figure 20. Current Consumption vs. Output
Current
12
10
8
3.40
3.35
3.30
T = 25°C
V = 13.5 V
J
I
I
Q
= 100 mA
I
Q
= 150 mA
I
Q
= 100 mA
6
I
Q
= 50 mA
I = 25 mA
Q
4
3.25
3.20
2
0
0
10
20
V , INPUT VOLTAGE (V)
30
40
−40 −20
0
20 40 60 80 100 120 140 160
T , JUNCTION TEMPERATURE (°C)
J
I
Figure 21. Current Consumption vs. Input
Voltage
Figure 22. Output Voltage vs. Junction
Temperature
3.0
2.5
2.0
1.5
1.0
400
350
T = 25°C
J
T = 125°C
J
300
250
200
150
100
T = 25°C
J
I
= 100 mA
Q
I
= 50 mA
= 10 mA
Q
0.5
0
V
Q
= 0 V
30
50
0
I
Q
6
8
10 12
14 16
18 20
22 24
26
0
10
20
V , INPUT VOLTAGE (V)
40
V , INPUT VOLTAGE (V)
I
I
Figure 23. Current Consumption vs. Input
Voltage
Figure 24. Output Current vs. Input Voltage
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NCV4299C
TYPICAL PERFORMANCE CHARACTERISTICS − 3.3 V OPTION
6
5
4
3
2
85
T = 25°C
V = 13.5 V
T = 25°C
J
J
I
80
75
I
Q
= 100 mA
70
65
1
0
0
2
4
6
8
10
12
14
6
8
10
12 14 16 18 20 22 24 26
V , INPUT VOLTAGE (V)
V , INPUT VOLTAGE (V)
I
I
Figure 25. Output Voltage vs. Input Voltage
Figure 26. Current Consumption vs. Input
Voltage
3.20
3.15
3.10
3.05
3.00
1.6
1.5
1.4
1.3
1.2
V = 13.5 V
I
V
SI,High
V
SI,Low
V = 13.5 V
I
2.95
2.90
1.1
1.0
I
Q
= 100 mA
−40 −20
0
20
40 60 80 100 120 140 160
−40
0
40
80
120
160
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 27. Reset Trigger Threshold vs.
Junction Temperature
Figure 28. Sense Threshold vs. Junction
Temperature
3.2
2.8
2.4
2.0
1.6
1.2
0.8
1.5
V = 13.5 V
I
V = 13.5 V
I
1.4
1.3
1.2
1.1
1.0
0.9
0.4
0
−40
0
40
80
120
160
−40
0
40
80
120
160
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 29. Switching Voltage vs. Junction
Temperature
Figure 30. Reset Adjust Switching Threshold
vs. Junction Temperature
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11
NCV4299C
TYPICAL PERFORMANCE CHARACTERISTICS − 3.3 V OPTION
40
30
8.0
V = 13.5 V
I
7.6
7.2
6.8
V
D
= 1 V
I
Q
= 100 mA
20
10
6.4
6.0
−40
0
40
80
120
160
−40
0
40
80
120
160
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 31. Resistance vs. Junction
Temperature
Figure 32. Charge Current vs. Junction
Temperature
100
V = 13.5 V
T = 25°C
J
I
Unstable Region
10
1
2.2 mF to 100 mF
Stable Region
0.1
0.01
0
20
40
60
80
100
120
140
160
I , OUTPUT CURRENT (mA)
Q
Figure 33. Output Capacitor ESR vs. Output
Current
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12
NCV4299C
APPLICATION DESCRIPTION
NCV4299C
Other features of the regulator include an undervoltage
reset function and a sense circuit. The reset function has an
adjustable time delay and an adjustable threshold level. The
sense circuit trip level is adjustable and can be used as an
early warning signal to the controller. An inhibit function
that turns off the regulator and reduces the current
consumption to less than 1.0 mA is a feature available in the
14 pin package.
The NCV4299C is a family of precision micropower
voltage regulators with an output current capability of
150 mA at 5.0 V and 3.3 V.
The output voltage is accurate within "2% with a
maximum dropout voltage of 0.5 V at 100 mA. Low
quiescent current is a feature drawing only 80 mA with a
100 mA load. This part is ideal for any and all battery
operated microprocessor equipment.
Output Regulator
Microprocessor control logic includes an active reset
output RO (with delay), and a SI/SO monitor which can be
used to provide an early warning signal to the
microprocessor of a potential impending reset signal. The
use of the SI/SO monitor allows the microprocessor to finish
any signal processing before the reset shuts the
microprocessor down. Internal output resistors on the RO
and SO pins pulling up to the output pin Q reduce external
component count. An inhibit function is available on the
14−lead part. With inhibit active, the regulator turns off and
the device consumes less that 1.0 mA of quiescent current.
The active reset circuit operates correctly at an output
voltage as low as 1.0 V. The reset function is activated
during the powerup sequence or during normal operation if
the output voltage drops outside the regulation limits.
The reset threshold voltage can be decreased by the
connection of an external resistor divider to the RADJ lead.
The regulator is protected against reverse battery, short
circuit, and thermal overload conditions. The device can
withstand load dump transients making it suitable for use in
automotive environments.
The output is controlled by a precision trimmed reference.
The PNP output has saturation control for regulation while
the input voltage is low, preventing oversaturation. Current
limit and voltage monitors complement the regulator design
to give safe operating signals to the processor and control
circuits.
Stability Considerations
The input capacitor C is necessary for compensating
I
input line reactance. Possible oscillations caused by input
inductance and input capacitance can be damped by using a
resistor of approximately 1.0 W in series with C .
I
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturer’s data sheet usually provides this information.
NCV4299C Circuit Description
The low dropout regulator in the NCV4299C uses a PNP
pass transistor to give the lowest possible dropout voltage
capability. The current is internally monitored to prevent
oversaturation of the device and to limit current during over
current conditions. Additional circuitry is provided to
protect the device during overtemperature operation.
The regulator provides an output regulated to 2%.
The value for the output capacitor C shown in Figure 34
Q
should work for most applications, however, it is not
necessarily the optimized solution. Stability is guaranteed at
values C ≥ 22 mF and an ESR ≤ 4 W within the operating
Q
temperature range. Actual limits are shown in a graph in the
typical performance characteristics section.
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13
NCV4299C
V
BAT
I
Q
V
DD
C *
I
R
R
C **
RADJ1
RADJ2
Q
0.1 mF
22 mF
RADJ
D
C
D
R
S11
SI
R
S12
R
***
INH
51kW
INH
INH
SO
C
***
I/O
RO
INH
GND
I/O
0.01 mF
*C required if regulator is located far from the power supply filter.
I
**C required for stability. Cap must operate at minimum temperature expected.
Q
***This RC filter is only required when transients with slew rate in excess of 10 V/ms may be present on the INH
voltage source during operation. The filter is not required when INH is connected to a noise−free DC voltage.
Figure 34. Test and Application Circuit Showing all Compensation and Sense Elements
V
BAT
I
Q
V
DD
C *
I
R
R
C **
RADJ1
RADJ2
Q
0.1 mF
22 mF
RADJ
D
C
D
R
S11
SI
R
S12
I/O
SO
RO
GND
I/O
*C required if regulator is located far from the power supply filter.
I
**C required for stability. Cap must operate at minimum temperature expected.
Q
Figure 35. Test and Application Circuit Showing all Compensation and Sense Elements for 8 Pin Package Part
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14
NCV4299C
Reset Output (RO)
threshold voltage V . When the voltage of the delay timer
RT
A reset signal, Reset Output (RO, low voltage) is
(V ) drops below the lower threshold voltage V , the reset
D
LD
generated as the IC powers up. After the output voltage V
output voltage V is brought low to reset the processor.
Q
RO
increases above the reset threshold voltage V , the delay
The reset output RO is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
RT
timer D is started. When the voltage on the delay timer V
D
passes V , the reset signal RO goes high. D pin voltage in
UD
steady state is typically 2.5 V. A discharge of the delay timer
guaranteeing that RO is valid for V as low as 1.0 V.
Q
(V ) is started when V drops and stays below the reset
D
Q
V
I
t
< t
RR
V
Q
V
RT
t
t
dV
dt
I
C
D
D
+
V
D
V
UD
V
LD
t
t
d
RR
V
RO
V
RO,SAT
t
Power−on−Reset
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Secondary
Spike
Overload
at Output
Figure 36. Reset Timing Diagram
Reset Adjust (RADJ)
Reset Delay (D)
The reset threshold V can be decreased from a typical
The reset delay circuit provides a delay (programmable by
capacitor C ) on the reset output RO lead. The delay lead D
RT
value of 4.67 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 34. The resistor divider keeps the voltage
D
provides charge current I (typically 7.1 mA) to the external
D
delay capacitor C during the following times:
D
above the V
, (typ. 1.36 V), for the desired input
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device
is back in regulation. The delay capacitor is
RADJ,TH
voltages and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
set to discharge when the regulation (V , reset
threshold voltage) has been violated. When
RT
V
+ V
· (R
) R
)ńR
ADJ2 ADJ2
THRES
RADJ, TH
ADJ1
(eq. 1)
the delay capacitor discharges to down to V
the reset signal RO pulls low.
,
LD
If the reset adjust option is not needed, the RADJ−pin
should be connected to GND causing the reset threshold to
go to its default value (typ. 4.67 V).
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15
NCV4299C
V
Q
Setting the Delay Time
The delay time is set by the delay capacitor C and the
D
charge current I . The time is measured by the delay
D
capacitor voltage charging from the low level of V
to the
V
SI
D,sat
higher level V . The time delay follows the equation:
V
SI,Low
UD
(eq. 2)
t
d
+ [C (V −V )]ńI
UD D, sat D
D
V
RO
Example:
Using C = 100 nF.
D
Use the typical value for V
= 0.1 V.
D,sat
V
SO
Use the typical value for V = 1.85 V.
UD
Use the typical value for Delay Charge Current I = 7.1 mA.
D
T
WARNING
(eq. 3)
t
d
+ [100 nF(1.85−0.1 V)]ń7.1 mA + 24.6 ms
Figure 37. SO Warning Timing Waveform
When the output voltage V drops below the reset
Q
threshold voltage V , the voltage on the delay capacitor V
RT
D
starts to drop. The time it takes to drop below the lower
threshold voltage of V is the reset reaction time, t . This
time is typically 1.6 ms for a delay capacitor of 0.1 mF. The
reset reaction time can be estimated from the following
relationship:
Sense
Input
Voltage
LD
RR
V
SI,High
(eq. 4)
t
+ 16 nsńnF C
D
RR
V
SI,Low
Sense Input (SI)/Sense Output (SO) Voltage Monitor
An on−chip comparator is available to provide early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the SO pin will
allow the microprocessor time to complete its present task
before shutting down. This function is performed by a
comparator referenced to the band gap voltage. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (SI) (Figure 34). The typical
threshold is 1.36 V on the SI Pin.
t
Sense
Output
t
t
PSOHL
PSOLH
High
Low
t
Figure 38. Sense Timing Diagram
Signal Output
Figure 37 shows the SO Monitor waveforms as a result of
the circuits depicted in Figure 34. As the output voltage V
falls, the monitor threshold V
voltage on the SO output to go low sending a warning signal
to the microprocessor that a reset signal may occur in a short
Calculating Power Dissipation in a Single Output
Linear Regulator
The maximum power dissipation for a single output
regulator is:
Q
is crossed. This causes the
SI,Low
P
+ [V
−V
] I
) V
Iq
I(max)
D(max)
I(max) Q(min) Q(max)
period of time. T
is the time the microprocessor has
WARNING
(eq. 5)
to complete the function it is currently working on and get
ready for the reset shutdown signal. When the voltage on the
SO goes low and the RO stays high the current consumption
is typically 400 mA.
where:
V
V
is the maximum input voltage,
is the minimum output voltage,
is the maximum output current for the application,
I(max)
Q(min)
Q(max)
I
and
I is the quiescent current the regulator consumes at I
.
Q(max)
q
Once the value of P
is known, the maximum
D(max)
permissible value of R
can be calculated:
qJA
(eq. 6)
R
+ (150° C−T )ńP
qJA
A
D
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16
NCV4299C
Heatsinks
The value of R
can then be compared with those in the
qJA
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
package section of the data sheet. Those packages with
’s less than the calculated value in Equation 6 will keep
the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required. Thermal
R
qJA
Resistance R
vs. Copper Area is shown in Figure 39.
qJA
determine the value of R
:
qJA
250
(eq. 7)
R
+ R
) R
) R
qCS qSA
qJA
qJC
1 oz SO−8
where:
2 oz SO−8
200
150
100
50
R
R
R
= the junction−to−case thermal resistance,
= the case−to−heatsink thermal resistance, and
= the heatsink−to−ambient thermal resistance.
qJC
qCS
qSA
2 oz SO−14
1 oz SO−14
R
appears in the package section of the data sheet. Like
qJC
R
q
, it too is a function of package type. R
and R
are
JA
qCS
qSA
functions of the package type, heatsink and the interface
between them. These values appear in heatsink data sheets of
heatsink manufacturers. Thermal, mounting, and heatsinking
are discussed in the ON Semiconductor application note
AN1040/D, available on the ON Semiconductor website.
0
0
100
200
300
400
500
600 700
2
COPPER HEAT SPREADER AREA (mm )
Figure 39. Thermal Resistance RqJA vs. Copper Area
ORDERING INFORMATION
Device
†
Package
Shipping
NCV4299CD133R2G
SO−8
(Pb−Free)
2500 / Tape & Reel
NCV4299CD150R2G
NCV4299CD233R2G
NCV4299CD250R2G
SO−8
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
SO−14
(Pb−Free)
SO−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
NCV4299C
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
18
NCV4299C
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
0.25
C A
B
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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For additional information, please contact your local
Sales Representative
NCV4299C/D
相关型号：
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