NCV51198PDR2G [ONSEMI]

1.5 A DDR 端接稳压器;


型号：	NCV51198PDR2G
厂家：	ONSEMI
描述：	1.5 A DDR 端接稳压器双倍数据速率稳压器
文件：	总10页 (文件大小：219K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

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MARKING

DIAGRAM

1.5A DDR Memory

Termination Regulator

SOIC8−NB EP

PD SUFFIX

XXXXXXXXX

ALYWX

NCP51198, NCV51198

The NCP/NCV51198 is a simple, cost−effective, high−speed linear

CASE 751BU

regulator designed to generate the V termination voltage rail for

XXXXX = Specific Device Code

DDR−I, DDR−II and DDR−III memory. The regulator is capable of

actively sourcing or sinking up to 1.5 A for DDR−I, or up to 0.5 A

for DDR−II /−III while regulating the output voltage to within

30 mV.

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

The output termination voltage is tightly regulated to track V

/ 2) over the entire current range.

DDQ

The NCP/NCV51198 incorporates a high−speed differential

amplifier to provide ultra−fast response to line and load transients.

Other features include extremely low initial offset voltage, excellent

load regulation, source/sink soft−start and on−chip thermal shut−down

protection.

PIN CONNECTION

GND

/SS

TTS

The NCP/NCV51198 features the power−saving Suspend To Ram

(STR) function which will tri−state the regulator output and lower the

quiescent current drawn when the /SS pin is pulled low.

The NCP/NCV51198 is available in a SOIC−8 Exposed Pad

package.

DDQ

REF

SOIC−8 EP

ORDERING INFORMATION

See detailed ordering, marking and shipping information in the

package dimensions section on page 8 of this data sheet.

Features

• Generate DDR Memory Termination Voltage (V

)

• For DDR−I, DDR−II, DDR−III Source / Sink Currents

• Supports DDR−I to 1.5 A, DDR−II to 0.5 A (peak)

• Integrated Power MOSFETs with Thermal Protection

• Stable with 10 mF Ceramic V Capacitor

• High Accuracy Output Voltage at Full−Load

• Minimal External Component Count

• Shutdown for Standby or Suspend to RAM (STR) mode

• Built−in Soft Start

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• These are Pb−Free Devices

Appications

• Desktop PC’s, Notebooks, and Workstations

• Graphics Card DDR Memory Termination

• Set Top Boxes, Digital TV’s, Printers

• Embedded Systems

• Active Bus Termination

Publication Order Number:

May, 2022 − Rev. 4

NCP51198/D

NCP51198, NCV51198

1.5 A, DDR−I /−II /−III TERMINATION REGULATOR

Figure 1. Typical Application Schematic

PIN FUNCTION DESCRIPTION – NCP51198

Pin Number

SO8−EP

Pin Name

GND

Pin Function

Common Ground.

/SS

Suspend Shutdown supports Suspend To RAM function. CMOS compatible input sets V output to

high impedance state. Logic HI = Enable, Logic LO = Shutdown.

is the V sense input.

TTS

REF

is an output pin that provides the buffered output of the internal reference voltage equal to half of

. Two resistors dividing down the V

REF

DDQ

voltage on the pin to create the regulated output voltage.

DDQ

The V

pin is an input pin for creating the internal reference voltage to regulate V . The V

volt-

DDQ

age is connected to an internal resistor divider. The central tap of resistor divider (V

/2) is con-

DDQ

nected to the internal voltage buffer, which output is connected to V

of the error amplifier as the reference voltage.

pin and the non−inverting input

REF

Power for the analog control circuitry.

The PV pin provides the rail voltage from where the V pin draws load current. There is a limitation

CC TT

between V and PV . The PV voltage must be less or equal to the V voltage to ensure the

correct output voltage regulation. The V source current capability is dependent on PV voltage. The

higher the voltage on PV , the higher the source current.

Regulator output voltage capable of sinking and sourcing current while regulating the output rail.

THERMAL

PAD

Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple

vias for maximum power dissipation performance.

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NCP51198, NCV51198

ABSOLUTE MAXIMUM RATINGS

Rating

, /SS to GND (Note 1)

Symbol

Value

−0.3 to +6

−65 to +150

−40 to +125

Unit

, PV ,V

CC DDQ

Storage Temperature

stg

°C

Operating Junction Temperature Range

°C

Thermal Characteristics, SO8−EP Thermal Resistance, Junction−to−Air

Power Rating at 25°C ambient = 2.3 W, derate 23 mW/°C

°C/W

ESD Capability, Human Body Model (Note 2)

ESD Capability, Machine Model (Note 2)

ESD

2000

150

HBM

ESD

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. No pin to exceed V . Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

2. This device series incorporates ESD protection and is tested by the following method:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)

Latchup Current Maximum Rating tested per JEDEC standard: JESD78.

RECOMMENDED OPERATING CONDITIONS

Rating

Symbol

Value

Unit

Bias Supply Voltage

Input Voltage

2.2 to 5.5

1.35 to 2.5

1.35 to 2.7

Reference Input Voltage

DDQ

ELECTRICAL CHARACTERISTICS

−40°C ≤ T ≤ 125°C; V = PV = V

= 2.5 V; unless otherwise noted. Typical values are at T = +25°C

DDQ

Parameter

Condition

Symbol

Min

Typ

Max

Unit

Reference Voltage (DDR I)

= 0 mA (unloaded)

PV = V

= 2.3 V

= 2.5 V

= 2.7 V

REF

1.125

1.225

1.325

1.151

1.251

1.351

1.175

1.275

1.375

DDQ

(DDR−I)

REF

Reference Voltage (DDR II)

= 0 mA (unloaded)

PV = V

= 1.7 V

= 1.8 V

= 1.9 V

0.830

0.880

0.925

0.851

0.901

0.951

0.880

0.930

0.975

REF

(DDR−II)

REF

Reference Voltage (DDR III)

= 0 mA (unloaded)

PV = V

= 1.35 V

= 1.5 V

= 1.6 V

REF

0.660

0.735

0.785

0.676

0.751

0.801

0.695

0.770

0.820

(DDR−III)

REF

− Output Impedance

= −30 mA to +30 mA

REF

2.5

REF

Output Voltage

(DDR−I)

= 0 A

−

OUT

PV = V

= 2.3 V

= 2.5 V

= 2.7 V

(DDR−I)

1.112

1.202

1.312

1.150

1.250

1.350

1.182

1.282

1.382

DDQ

PV = V

= +1.5 A

−

OUT

PV = V

= 2.3V

= 2.5V

= 2.7V

(DDR−I)

1.115

1.215

1.315

1.150

1.250

1.350

1.185

1.285

1.385

DDQ

PV = V

= −1.5 A

−

OUT

PV = V

= 2.3V

= 2.5V

= 2.7V

(DDR−I)

1.117

1.217

1.317

1.150

1.250

1.350

1.182

1.282

1.382

DDQ

PV = V

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NCP51198, NCV51198

ELECTRICAL CHARACTERISTICS

−40°C ≤ T ≤ 125°C; V = PV = V

= 2.5 V; unless otherwise noted. Typical values are at T = +25°C

DDQ

Parameter

Condition

= 0 A

Symbol

Min

Typ

Max

Unit

Output Voltage

(DDR−II)

−

OUT

(DDR−II)

PV = V

= 1.7 V

= 1.8 V

= 1.9 V

0.816

0.866

0.916

0.850

0.900

0.950

0.881

0.931

0.981

DDQ

PV = V

= +0.5 A

−

OUT

PV = V

= 1.7 V

= 1.8 V

= 1.9 V

(DDR−II)

0.815

0.863

0.914

0.851

0.900

0.950

0.885

0.933

0.984

DDQ

PV = V

= −0.5 A

−

OUT

PV = V

= 1.7 V

= 1.8 V

= 1.9 V

(DDR−II)

0.814

0.862

0.913

0.850

0.900

0.950

0.884

0.932

0.983

DDQ

PV = V

Output Voltage

= 0 A

VCC

(DDR−III)

−

OUT

(DDR−III)

= V

= 1.35 V

= 1.5 V

= 1.6 V

0.650

0.725

0.775

0.675

0.750

0.800

0.700

0.775

0.825

DDQ

PV = V

= +0.2 A,

−

0.649

−

OUT

(DDR−III)

0.675

−

0.700

−

PV = V

= 1.35 V

DDQ

= −0.2 A,

OUT

0.675

0.700

PV = V

0.640

= +0.4 A,

−

OUT

PV = V

= 1.5 V

(DDR−III)

0.722

−

0.751

−

0.776

−

DDQ

= −0.4 A,

OUT

PV = V

0.725

0.750

0.774

DDQ

= +0.5 A,

−

OUT

PV = V

= 1.6 V

(DDR−III)

0.773

−

0.801

−

0.827

−

DDQ

= −0.5 A,

OUT

PV = V

0.775

0.800

0.824

DDQ

Output Offset Voltage

1.5 A,

(DDR−I)

−30

+30

500

OUT

PV = V

= 2.5 V

= 1.8V

= 1.5V

0.5A,

(DDR−II)

OUT

PV = V

0.5A,

(DDR−III)

OUT

PV = V

Quiescent Current

Input Impedance

= 0 A

380

100

OUT

DDQ

VDDQ

L_SS

Q_SS

/SS Leakage Current

/SS = 0 V

Quiescent Current in Suspend Shutdown

Suspend Shutdown Threshold

115

150

1.9

L_VTT

0.8

leakage Current in Suspend Shutdown

/SS = 0 V, V = 1.25 V

°C

Current

TTS

Thermal Shutdown Temperature

Thermal Shutdown Hysteresis

165

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NCP51198, NCV51198

TYPICAL PERFORMANCE CHARACTERISTICS

140

120

700

600

100

500

400

300

200

100

(V)

Figure 2. Iq_SDvs. V_CC

Figure 3. Iq vs. V_CC

3.5

3.0

2.5

3.0

2.5

2.0

1.5

1.0

2.0

1.5

1.0

0.5

(V)

DDQ

Figure 4. V_IHand V_IL

Figure 5. V_REFvs. V_DDQ

3.0

2.5

2.0

1.5

1.0

160

140

120

100

−40°C

25°C

85°C

0.5

125°C

DDQ

(V)

Figure 6. V_TTvs. V_DDQ

Figure 7. Iq_SDvs. V_CCover Temperature

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NCP51198, NCV51198

TYPICAL PERFORMANCE CHARACTERISTICS

800

700

600

500

400

300

200

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

−40°C

25°C

85°C

100

0.2

125°C

(V)

Figure 8. Iq vs. V_CCover Temperature

Figure 9. Maximum Sourcing Current vs. V_CC

(V_DDQ= PV_CC= 1.8 V)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

(V)

Figure 10. Maximum Sourcing Current vs. V_CC

(V_DDQ= 2.5 V, PV_CC= 1.8 V

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NCP51198, NCV51198

APPLICATIONS INFORMATION

General

significant IR drop resulting in a sagging termination

voltage at one end of the bus than the other. The V pin can

The NCP/NCV51198 is a bus termination, linear

TTS

regulator designed to meet the JEDEC requirements for

DDR−I, DDR−II and DDR−III memory termination. The

NCP/NCV51198 is capable of sourcing and sinking current

be used to improve performance by connecting it to the

middle of the bus. This will provide better power

distribution across the entire termination bus. If remote load

while accurately tracking and regulating the V output

regulation is not used, then the V

pin must still be

TTS

voltage equal to (V

/ 2). The output stage has been

connected to V . Care should be taken when a long V

DDQ

TTS

designed to maintain excellent load regulation and

preventing shoot−through. The NCP/NCV51198 uses two

distinct power rails to separate the analog circuitry from the

power output stage and decrease internal power dissipation.

trace is implemented in close proximity to the memory.

Noise pickup in the V trace can cause problems with

TTS

precise regulation of V . A small 0.1 mF ceramic capacitor

placed next to the V

pin can help filter out any high

TTS

frequency noise and thereby keeping the V power rail in

spec.

Supply Voltage Inputs

For added flexibility, separate input pins (V and PV

are provided for each required supply input. V is used to

supply all the internal control circuitry and PV is used

)

Regulator Shutdown Function

The NCP/NCV51198 contains an active low enable pin

(/SS) that can be used for suspend to RAM functionality. In

exclusively to provide the rail voltage for the output stage

this condition the V output will tri−state, with the V

used to create V . These pins have the capability to work

REF

output remaining active in order to provide a constant

reference signal for the memory and chipset. During

off separate supplies with the condition that V is always

greater than or equal to PV , and should always be used

with either a 1.8 V or 2.5 V rail. If the junction temperature

exceeds the thermal shutdown threshold, the part will enter

a shutdown state identical to the manual shutdown where

shutdown, V should not be exposed to voltages that

exceed PV

With the enable pin asserted low the quiescent current of

the NCP/NCV51198 will drop, however the V input pin

is tri−stated and V

remains active. Lower voltage

DDQ

REF

will always draw a constant current due to the integrated

100 kW impedance used for generating the internal

reference. Therefore, to calculate the total power loss in

shutdown, both currents need to be considered. The enable

pin also has an internal pull−up current. Therefore, to turn

rails, such as 1.5 V can be used but will reduce the maximum

available output current.

Generation of Internal Voltage Reference

DDQ

is the input used to create the internal reference

voltage for regulating V . The reference voltage is

the part on, the enable pin can either be connected to V or

generated from a resistor divider of two internal 50 kW

left open.

resistors. This guarantees that V will precisely track

Termination Voltage Output Regulation

/ 2). The optimal implementation of the V

input

DDQ

is the regulated output that is used to terminate the

pin is as a remote sense. This can be achieved by connecting

directly to the 1.8 V rail at the DIMM memory

bus resistors. It is capable of sourcing and sinking current

while regulating the output precisely to V / 2. The

DDQ

module instead of connecting it to PV . This ensures that

NCP/NCV51198 is designed to handle continuous currents

of up to 1.5 A with excellent load regulation. If a transient

is expected to last above the maximum continuous current

rating for a significant amount of time, then the bulk output

capacitor should be sized large enough to prevent an

excessive voltage drop.

the reference voltage precisely tracks the DDR memory

power rail without introducing a large voltage drop due to

power traces. For DDR−II applications the V

input will

DDQ

be 1.8 V, which will create a (V

/ 2) = 0.9 V termination

DDQ

voltage at the V output.

REF

provides a buffered output of the internal reference

voltage (V

/ 2). For improved performance, an output

Thermal Shutdown with Hysteresis

DDQ

bypass capacitor can be placed, close to the pin, to help

reduce any potential stray noise. A ceramic capacitor in the

If the NCP/NCV51198 is to operate in elevated

temperatures for long durations, care should be taken to

ensure that the maximum operating junction temperature is

not exceeded. To guarantee safe operation, the

NCP/NCV51198 provides on−chip thermal shutdown

protection. When the chip junction temperature exceeds

165°C (typical) the part will shutdown. When the junction

temperature falls back to 155°C (typical) the device resumes

normal operation. If the junction temperature exceeds the

range of 0.01mF to 0.1 mF is recommended. The V

output

REF

remains active during the shutdown state and thermal

shutdown events for the suspend to RAM functionality.

Remote Voltage Feedback Sensing

The purpose of the V

sense pin is to provide improved

TTS

remote load regulation. In most motherboard applications,

the termination resistors will connect to V in a long plane.

thermal shutdown threshold, V will tri−state until the part

If the output voltage was regulated only at the output of the

NCP/NCV51198, then any long traces will generate a

returns below the temperature hysteresis trip−point.

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NCP51198, NCV51198

Table 1. ORDERING INFORMATION

Device

†

Marking

Package

Shipping

NCP51198PDR2G

51198

SOIC−8

(Pb-Free)

2500 / Tape & Reel

NCV51198PDR2G*

V51198

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC8−NB EP

CASE 751BU

ISSUE E

SCALE 1:1

DATE 01 APR 2015

NOTES:

NOTE 5

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL

BE 0.10mm IN EXCESS OF MAXIMUM MATERIAL

CONDITION.

4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH,

PROTRUSIONS, OR GATE BURRS SHALL NOT EX-

CEED 0.15mm PER SIDE. DIMENSION E DOES NOT

INCLUDE INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT

EXCEED 0.25mm PER SIDE. DIMENSIONS D AND E

ARE DETERMINED AT DATUM F.

5. DIMENSIONS A AND B ARE TO BE DETERMINED

AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

7. TAB CONTOUR MAY VARY MINIMALLY TO INCLUDE

TOOLING FEATURES.

0.10 C D

NOTE 6

NOTE 4

2X 4 TIPS

SEATING

PLANE

0.20

DETAIL A

8X b

NOTE 5

0.25

A-B D

TOP VIEW

0.10

A-B

NOTE 4

DETAIL A

0.10

MILLIMETERS

DIM MIN

MAX

1.75

0.10

0.51

0.48

0.25

0.23

1.35

0.00

0.31

0.28

0.17

END VIEW

SEATING

PLANE

SIDE VIEW

NOTE 7

4.90 BSC

6.00 BSC

3.90 BSC

1.27 BSC

1.55

2.39

0.50

1.27

c c1

SECTION B−B

1.55

0.25

0.40

0.25 BSC

GENERIC

MARKING DIAGRAM*

BOTTOM VIEW

RECOMMENDED

SOLDERING FOOTPRINT*

XXXXXXXXX

2.60

ALYWX

2.60

1.52

7.00

XXXXX = Specific Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

0.76

1.27

PITCH

DIMENSION: MILLIMETERS

*This information is generic. Please refer

to device data sheet for actual part

marking. Pb−Free indicator, “G”, may

or not be present.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON66222E

SOIC8−NB EP

PAGE 1 OF 1

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

NCV51198PDR2G [ONSEMI]

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