NCV51513ABMNTWG [ONSEMI]
Automotive 130 V, 2.0/3.0 A High and Low Side Drivers with Dead Time & Interlock;
| 型号： | NCV51513ABMNTWG |
| 厂家： | 
ONSEMI |
| 描述： | Automotive 130 V, 2.0/3.0 A High and Low Side Drivers with Dead Time & Interlock |
| 文件： | 总27页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Automotive 130 V
High and Low Side Driver with
Interlock and Dead Time
DFNW10 (3x3)
CASE 507AG
NCV51513
MARKING DIAGRAM
Description
51513
Vxy
ALYW
G
NCV51513 is 130 V half bridge driver with high drive current
capabilities and options for DC−DC power supplies and inverters.
NCV51513 offers best in class propagation delay, low quiescent
current and low switching current at high frequencies of operation.
This device is tailored for highly efficient power supplies operating
at high frequencies. NCV51513 is offered in two versions
for propagation delays. With filter version, it has a typical 50 ns
propagation delay, while without filter version it has a typical
propagation delay of 20 ns. Internal 80 ns dead time (xB version) and
interlock function protect the output MOSFETs against cross
conduction events. Enable functionality provides additional system
flexibility and helps reducing power consumption.
x
y
= Input Noise Filter
= Internal Dead Time
= Assembly Location
= Wafer Lot
A
L
Y
W
G
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Features
PIN CONNECTION
• High Voltage Range: Up to 130 V
VCC
NC
10 DRVL
1
2
3
4
5
• dV/dt Immunity Up to 50 V/ns
GND
LIN
9
8
7
6
• Output Source / Sink Current Capability 2.0 A / 3.0 A
• Rise / Fall Time 9 ns / 7 ns for 1 nF Load
• Independent Logic Inputs 3.3 V and 5 V Compatible
• Enable Input
VB
DRVH
HB
HIN
EN
• Propagation Delay 50 ns Ay Version, 20 ns By Version
• Input Filter Time 30 ns for Ay Version and No Filter for By Version
Top View
• Dead Time Option
ORDERING INFORMATION
No Dead Time (xA Version)
†
Package
Shipping
Device
Internal Fixed 80 ns Dead Time (xB Version)
3000 /
Tape & Reel
NCV51513AAMNTWG
DFNW10
(Pb−free)
• Input Cross−Conduction Prevention
• Extended Allowable Negative Bridge Pin Voltage Swing to
−10 V @ Vcc = 10 V
3000 /
Tape & Reel
NCV51513ABMNTWG
DFNW10
(Pb−free)
• Matched Propagation Delays Between Both Channels Max 11 ns
• Independent Under Voltage Lock Out (UVLO) for Both Channels
• This is a Pb−Free Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Typical Applications
• 48 V Automotive DC/DC Converters
• On−Board Chargers
• Electric Power Steering
• 48 V BSB and ISG
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
July, 2022 − Rev. 2
NCV51513/D
NCV51513
QUICK SELECTION TABLE
Drive Current
[A]
UVLO Levels
t and t at 1 nF Prop Delay
r
f
Max [V]
[ns]
[ns]
Dead
Time
[ns]
Delay
Match
[ns]
Vcc/Vb Vcc/Vb
Filter
[ns]
ON
7.1
7.1
OFF
Source
2.0
Sink
3.0
Rise
Fall
7
ON
50
OFF
OPN
Package
NCV51513AAMNTWG DFNW10
NCV51513ABMNTWG DFNW10
NA
80
30
30
6.6
9
9
50
50
11
11
2.0
3.0
6.6
7
50
OPTION TABLE
Suffix
Value
Description
x
x
y
y
y
A
B
A
B
C
Input filter time 30 ns
No input filter (on demand)
No dead time
80 ns fixed dead time
200 ns fixed dead time (on demand)
Table 1. PIN DESCRIPTION
Pin Out
Name
VCC
NC
Function
1
2
Power Ground
Not Connected
High Side Supply
High Side Output
3
VB
4
DRVH
HB
5
High Side Supply Return, Half Bridge Pin
Enable Input
6
EN
7
HIN
High Side Input
8
LIN
Low Side Input
9
GND
DRVL
EP
Low Side and Logic Supply
Low Side Output
10
EP
Connect the EP Flag to GND
V
HV
M1
V
CC
LOAD
HB
HIN DRVH
6
7
8
9
EN
5
4
3
C
BOOT
CONTROLLER
LIN
VB
NC
R
BOOT
GND
2
1
10 DRVL VCC
D
BOOT
M2
C
Vcc
Figure 1. Typical Application Schematic
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2
NCV51513
UV
Detect
V
CC
VB
Pulse
Trigger
Level
Shifter
Q
Q
S
R
Input
filter
HIN
EN
DRVH
HB
UV
Detect
Dead time and
Cross conduction
prevention logic
Input
filter
V
CC
Input
filter
DELAY
DRVL
LIN
GND
Figure 2. NCV51513Ay Version
UV
Detect
V
CC
VB
Pulse
Trigger
Level
Shifter
S
Q
Q
HIN
EN
R
DRVH
HB
UV
Detect
Dead time and
Cross conduction
prevention logic
V
CC
DRVL
DELAY
LIN
GND
Figure 3. NCV51513By Version
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3
NCV51513
MAXIMUM RATINGS
Rating
Symbol
Value
Units
V
Supply Voltage Range
High Side Boot Pin Voltage
High Side Floating Voltage
High Side Bridge Pin Voltage
High Side Drive Output Voltage
Low Side Output Voltage
Allowable Output Slew Rate
Inputs HIN, LIN
V
CC
−0.3 to 20
−0.3 to 150
−0.3 to 20
V
B
V
V −V
V
B
HB
V
V
−20 to V + 0.3
V
HB
B
B
V
DRVH
V
HB
−0.3 to V + 0.3
V
B
V
DRVL
−0.3 to V + 0.3
V
CC
dV /dt
HB
50
V/ns
V
V
, V
−5 to V + 0.3
CC
LIN
HIN
EN
Input EN
V
−0.3 to V + 0.3
V
CC
Junction Temperature
T
+150
°C
°C
J_max
Storage Temperature Range
T
ST
−55 to +150
ESD Capability (Note 1):
− HBM Model
− CDM Model
2000
1000
V
V
Lead Temperature Soldering
Reflow (SMD Styles ONLY), Pb−Free Versions (Note 2)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods. ESD Human Body Model tested
perAEC−Q100−002(EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−11(EIA/JESD22−C101E)
Latchup Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78E.
2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
THERMAL CHARACTERISTICS
Rating
Thermal Resistance Junction to Air (Note 3)
Junction to Top Characterization Parameter
Symbol
RqJA
Value
157
Units
°C/W
°C/W
°C/W
YJ−T
8.5
Junction to Bottom Characterization Parameter
YJ−B
0.12
2
3. Values based on copper area of 100 mm 1 oz copper thickness and FR4 PCB substrate
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Min
8
Max
19
Unit
V
Supply Voltage Range
V
CC
Floating Supply Voltage Range
V −V
8
19
V
B
HB
Bridge Pin Voltage Range @ Vcc = 10 V
High Side Driver Voltage
V
−2
110
V
HB
V
DRVH
V
HB
V
B
V
Low Side Driver Voltage
V
GND
−3
V
V
V
V
DRVL
CC
CC
CC
Input Signal Voltage
V
, V
LIN
V
HIN
Input Signal Voltage
V
GND
−40
V
EN
Operating Junction Temperature Range
T
J
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
NCV51513
ELECTRICAL CHARACTERISTICS
(VCC = VB = 12 V, VGND = VHB, −40°C < Tj < 125°C, Outputs loaded with 1 nF, typical values are valid for 25°C. All voltages are
referenced to GND pin)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SUPPLY SECTION
V
V
V
V
Current Consumption in Active Mode
I
f
f
= 100 kHz
= 100 kHz
−
−
−
−
−
−
−
−
−
1.8
1.8
0.6
0.3
150
100
150
100
2
2.3
2.3
1.2
0.5
250
150
250
150
5
mA
mA
mA
mA
mA
CC
CC1
SW
Current Consumption in Active Mode
I
B
B1
CC1_noload
SW
Current Consumption in Active Mode
I
f
f
= 100 kHz, C
= 100 kHz, C
= 0
= 0
CC
SW
LOAD
LOAD
Current Consumption in Active Mode
I
B1_noload
B
SW
Vcc Current Consumption in Active Mode
I
f
f
= 0 Hz, V = 3 V
EN
CC2_EN_H
SW
SW
V
V
V
Current Consumption in Active Mode
I
= 0 Hz, V = 3 V
mA
B
B2_EN_H
EN
Current Consumption in Inhibition Mode
I
V
V
= 0 V
= 0 V
mA
CC
CC2
EN
EN
Current Consumption in Inhibition Mode
I
mA
B
B2
HV_LEAK
Leakage Current on High Voltage Pins to GND
INPUT SECTION
I
V
= HB = DRVH = 130 V
mA
B
Low Level Input Voltage Threshold
Input Pull−Down Resistor
V
, V
−
100
2.3
60
−
−
175
−
0.8
250
−
V
xINL
ENL
R
V
= 5 V, V = 0 V
kW
V
xIN
xIN
EN
High Level Input Voltage Threshold
Enable Pin Pull−Down Resistor
Logic “1” Input Bias Current
Logic “0” Input Bias Current
Logic “1” Input Bias Current
Logic “0” Input Bias Current
UVLO SECTION
V
xINH
, V
ENH
R
V
EN
= 5 V
95
30
−
135
50
kW
mA
mA
mA
mA
EN
xIN+
xIN−
I
I
V
V
= 5 V, V = 5 V
EN
xIN
= 0 V, V = 0 V
−
2.0
85
xIN
EN
I
V
= 5 V
= 0 V
−
50
−
EN+
EN
EN
I
V
−
2.0
EN−
V
V
UV Start−Up Voltage Threshold
UV Shut−Down Voltage Threshold
V
V
5.8
5.3
0.2
5.8
6.4
5.9
0.5
6.4
7.0
6.5
−
V
V
V
V
CC
CC
CCon
CCoff
Hysteresis on V
V
CChyst
CC
Vboot Start−Up Voltage Threshold Reference to
Bridge Pin
V
V
Bon
= V − HB
7.0
Bon
B
Vboot UV Shut−Down Voltage Threshold
V
5.3
0.2
−
5.9
0.5
−
6.5
−
V
V
Boff
Hysteresis on Vboot
V
Bhyst
st
Time between Vboot > V
& 1 DRVH Pulse
t
10
ms
Bon
startup
OUTPUT SECTION
Output High Short Circuit Pulsed Current
(Note 4)
I
V
= 0 V, PW = 300 ns
−
−
2.0
3.0
−
−
A
A
DRVxsource
DRVx
Output Low Short Circuit Pulsed Current
(Note 4)
I
V
= V (V ), PW = 300 ns
DRVxsink
DRVx
CC
B
Output Resistance Source
R
I
I
= 30 mA
= 30 mA
−
−
−
−
2.5
1.5
7
W
W
V
V
OH
DRVx
DRVx
DRVx
Output Resistance Sink
R
5
OL
DRVx H
High Level Output Voltage
V
V
− V
@ I
= 20 mA
0.06
0.04
0.25
0.15
BIAS
DRVx
Low Level Output Voltage
V
V
@ I
= 20 mA
DRVx L
DRVx
DRVx
OUTPUT RISE AND FALL TIME
Output Voltage Rise Time (from 10% to 90%)
Output Voltage Fall Time (from 90% to 10%)
t
V
V
= 3 V
−
−
9
7
30
25
ns
ns
r
xIN
t
= 0 V
f
xIN
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NCV51513
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VB = 12 V, VGND = VHB, −40°C < Tj < 125°C, Outputs loaded with 1 nF, typical values are valid for 25°C. All voltages are
referenced to GND pin)
Parameter
PROPAGATION DELAY NCV51513Ay
Turn−On Propagation Delay
Symbol
Test Condition
Min
Typ
Max
Unit
t
HB = 0 V, 50 V or 130 V,
−
−
50
50
50
50
30
100
100
100
100
−
ns
ns
ns
ns
ns
ON
Cload = 0 pF, V
= 3 V
xIN
Turn−Off Propagation Delay
t
HB = 0 V, 50 V or 130 V,
Cload = 0 pF
OFF
Enable High Signal Propagation Delay
Enable Low Signal Propagation Delay
t
HB = 0 V, 50 V or 130 V,
−
EN
Cload = 0 pF, V
= 3 V
xIN
t
HB = 0 V, 50 V or 130 V,
Cload = 0 pF, V = 3 V
−
ENoff
xIN
Minimum Input Filter Time
t
V
xIN
= 3 V
20
FLT
PROPAGATION DELAY NCV51513By
Turn−On Propagation Delay
t
HB = 0 V, 50 V or 130 V,
Cload = 0 pF, V = 3 V
−
−
−
−
20
20
20
20
40
40
40
40
ns
ns
ns
ns
ON
xIN
Turn−Off Propagation Delay
Enable High Signal Propagation Delay
Enable Low Signal Propagation Delay
DELAY MATCHING
t
HB = 0 V, 50 V or 130 V,
Cload = 0 pF
OFF
t
HB = 0 V, 50 V or 130 V,
EN
Cload = 0 pF, V
= 3 V
xIN
t
HB = 0 V, 50 V or 130 V,
Cload = 0 pF, V = 3 V
ENoff
xIN
Propagation Delay Matching
between the High Side and the Low Side
Dt
V
= 3 V
−
−
0
−
11
10
ns
ns
xIN
TIMING
Minimum Input Width that Changes the Output
(B Version Only)
t
V
V
= 3 V
= 3 V
PW
xIN
Internal Dead Time (B Version Only)
Dead Time Matching (B Version Only)
t
DT
60
−
80
2
100
20
ns
ns
xIN
Dt
DT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Parameter guaranteed by design.
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NCV51513
t
t
= higher of {t
, t
}
50%
ON
ONL ONH
= higher of {t
, t
}
OFF
OFFL OFFH
LIN
(HIN)
D
D
= the highest of {t
, t
, t
, t
}
tA
tB
ONL ONH OFFL OFFH
90%
10%
= the lowest of {t
, t
, t
, t
}
ONL ONH OFFL OFFH
D = D − D
tB
t
tA
t = higher of {t , t
r
}
rL rH
DRVL
(DRVH)
t = higher of {t , t
}
f
fL fH
t
t
fL
t
t
rL
OFFL
ONL
(t
OFFH
)
(t
fH
)
(t
ONH
)
(t
rH
)
Figure 4. Propagation Delay, Propagation Delay Matching,
Rise Time and Fall Time Testing
DRVH
DRVL
90%
t
t
is in limit of t
is in limit of t
DT A
DT
DT B
DT
Dt = ⎪t
− t
DT B
⎪
DRVL
DRVH
DT
DT A
10%
90%
10%
t
t
DT B
DT A
Figure 5. Dead Time and Dead Time Matching Measurement (xB Version Only)
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NCV51513
TYPICAL ELECTRICAL CHARACTERISTICS
6.50
6.45
6.40
6.35
6.30
6.00
5.99
5.98
5.97
5.96
5.95
5.94
5.93
5.92
5.91
5.90
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 6. VCCon vs. Temperature
Figure 7. VCCoff vs. Temperature
0.50
0.49
0.48
0.47
0.46
0.45
0.44
0.43
0.42
0.41
0.40
6.40
6.39
6.38
6.37
6.36
6.35
6.34
6.33
6.32
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 9. VBon vs. Temperature
Figure 8. VCChyst vs. Temperature
0.45
0.44
0.43
0.42
0.41
0.40
0.39
0.38
6.00
5.99
5.98
5.97
5.96
5.95
5.94
5.93
5.92
5.91
5.90
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 11. VBhyst vs. Temperature
Figure 10. VBoff vs. Temperature
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NCV51513
TYPICAL ELECTRICAL CHARACTERISTICS (continued)
0.270
0.265
0.260
0.255
0.250
0.245
0.240
0.235
0.230
1.65
1.63
1.61
1.59
1.57
1.55
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 13. ICC1 noload vs. Temperature
Figure 12. ICC1 vs. Temperature
125
123
121
119
117
115
113
111
109
150
140
130
120
110
100
90
80
70
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 15. ICC2 vs. Temperature
Figure 14. ICC2 EN H vs. Temperature
1.55
1.53
1.51
1.49
1.47
1.45
0.250
0.245
0.240
0.235
0.230
0.225
0.220
0.215
0.210
0.205
0.200
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80 100 120
Temperature [°C]
Temperature [°C]
Figure 17. IB1 noload vs. Temperature
Figure 16. IB1 vs. Temperature
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NCV51513
TYPICAL ELECTRICAL CHARACTERISTICS (continued)
100
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 18. IB2 EN H vs. Temperature
Figure 19. IB2 vs. Temperature
200
150
145
140
135
130
125
120
115
110
105
100
195
190
185
180
175
170
165
160
155
150
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 20. RxIH vs. Temperature
Figure 21. REN vs. Temperature
68
66
64
62
60
58
56
54
66
64
62
60
58
56
54
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 23. tOFF vs. Temperature
(Ay Version Only)
Figure 22. tON vs. Temperature
(Ay Version Only)
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NCV51513
TYPICAL ELECTRICAL CHARACTERISTICS (continued)
64
63
62
61
60
59
58
57
56
55
6
5
4
3
2
1
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 24. Dt vs. Temperature
Figure 25. tEN vs. Temperature
(Ay Version Only)
80.0
79.5
79.0
78.5
78.0
77.5
77.0
6
4
2
0
−2
−4
−6
−8
−10
−12
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 27. DtDT vs. Temperature
Figure 26. tDT vs. Temperature
(xB Version Only)
(xB Version Only)
14
13
12
11
10
9
8.0
7.9
7.8
7.7
7.6
7.5
7.4
7.3
7.2
7.1
7.0
8
7
6
5
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 28. tr vs. Temperature
Figure 29. tf vs. Temperature
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NCV51513
TYPICAL ELECTRICAL CHARACTERISTICS (continued)
70
65
60
55
50
45
40
35
30
90
85
80
75
70
65
60
55
50
45
40
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 30. tr 10 nF vs. Temperature
Figure 31. tf 10 nF vs. Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 32. ROH vs. Temperature
Figure 33. ROL vs. Temperature
6
5
4
3
2
1
0
800
700
600
500
400
300
200
100
Icc 500 kHz
Ib 500 kHz
Icc 100 kHz
Ib 100 kHz
6.5
15.5
17.0 18.5 20.0
8.0 9.5 11.0 12.5 14.0
Voltage [V]
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Figure 34. IHV_leak vs. Temperature
Figure 35. Current Consumption vs. Voltage.
Cload = 0 nF
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12
NCV51513
TYPICAL ELECTRICAL CHARACTERISTICS (continued)
4.0
3.5
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
3.0
2.5
2.0
1.5
1.0
R sink DRVH
R sink DRVL
R source DRVH
0.5
R source DRVL
0.0
4
8
0
6
10
12
2
2
0
4
6
8
10
12
Vcc(Vb) − DRVx Pin Voltage [V]
DRVx −GND(HB) Pin Voltage [V]
Figure 36. DRVx Source Resistance.
Figure 37. DRVx Sink Resistance.
255C. GBD
255C. GBD
General Description
logic is still defined. Driver inputs are compatible with both
CMOS and TTL logic hence it provides easy interface with
analog and digital controllers. NCV51513 has under voltage
lock out feature for both high and low side drivers which
For popular topologies like LLC, half bridge full brige
converters, synchronous buck converters, etc. low−side and
high−side drivers are needed which perform the function of
both buffer and level shifter. These devices can drive the gate
of the topside MOSFETs whose source node is a
dynamically changing node. The bias for the high side driver
in these devices is usually provided through a bootstrap
circuit.
In a bid to make modern power supplies more compact
and efficient, power supply designers are increasingly
opting for high frequency operations. High frequency
operation causes higher losses in the drivers, hence reducing
the efficiency of the power supply.
NCV51513 are 130 V high side−low side drivers for
DC−DC power supplies and inverters. NCV51513 offer best
in class propagation delay, low quiescent current and low
switching current at high frequencies of operation. This
device thus enables highly efficient power supplies
operating at high frequencies.
NCV51513 are available in two versions,
NCV51513Ay or By. The Ay version includes a 30 ns input
filter time, so propagation delay is 50 ns, the By version is
without any filter, the propagation delay is reduced to 20 ns.
NCV51513 also offers Dead Time options. There are
versions without any dead time (xA version) that let
designers insert the dead time their application needs and
versions (xB version) with an internal 80 ns dead time to
eliminate cross conduction of the output MOSFETs.
Interlock function is available in both versions.
ensures operation at correct V and V voltage levels.
CC
B
The output stage of NCV51513 has 2.0/3.0 A source/sink
capability which can effectively charge and discharge a 1nF
load in 9/7 ns.
Features
Input Stages
NCV51513 driver have three input pins HIN, LIN and
EN, allowing it to be used in a variety of applications. The
input stages of NCV51513 are TTL and CMOS compatible.
This ensures that the inputs of NCV51513 can be driven with
3.3 V or 5 V logic signals from analog or digital PWM
controllers or logic gates.
The input pins have Schmitt triggers to avoid noise
induced logic errors.
NCV51513 come with an important feature wherein
outputs (DRVH, DRVL) stays low in case any of the input
pin is floating. At all the input pins there is an internal pull
down resistor to define its logic value in case the pin is left
open or NCV51513 are driven by open drain signal.
NCV51513Ay features a noise rejection function to
ensure that any pulse glitch shorter than 30 ns will not
produce any output change. This feature is well illustrated
in the Figure 39.
NCV51513By have no such filter in the input stages. The
timing diagram NCV51513By is depicted in Figure 39.
Enable pin in L state sets both outputs to L state. Enable
pin in H state lets outputs to switch according to input
signals. See Figure 40 for more details.
NCV51513 have three input pins HIN, LIN and EN,
allowing it to be used in a variety of applications. This device
also includes features where in case of floating input, the
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13
NCV51513
50 ns
+ t
50 ns
OFF
LIN
HIN
80 ns
(t
+ t
)
50 ns
(t
)
FLT
50 ns
FLT
OFF
15 ns
10 ns
50 ns
Pulse is
filtered out
50 ns
(t + t
DRVL
DRVH
Pulse is
filtered out
(t + t
)
110 ns
)
FLT
ON
FLT
ON
80 ns
Figure 38. Version with Input Filter (NCV51513Ay)
20 ns
LIN
HIN
(t
OFF
)
80 ns
40 ns
50 ns
15 ns
20 ns
10 ns
50 ns
20 ns
(t
DRVL
DRVH
20 ns
(t
(t
ON
)
15 ns
40 ns
)
)
80 ns
ON
ON
10 ns
Figure 39. Version without Input Filter (NCV51513By)
EN
LIN
DRVL
HIN
DRVH
Figure 40. Enable Pin Function
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14
NCV51513
Under Voltage Lock−Out
(DRVL) can still turn on and off based on the low side driver
NCV51513 has under voltage lockout protection on both
the high side and the low side driver. The function of the
UVLO circuits is to ensure that there is enough supply
voltages (V and V ) to correctly bias high side and low
input (LIN) and is not affected by the V status. This ensures
proper charging of the bootstrap capacitor to bring the high
B
side bias supply V above UVLO voltage. Both the V and
B
CC
V UVLO circuits are provided with hysteresis feature. This
B
CC
B
side circuits. This also ensures that the gate of external
hysteresis feature avoids errors due to ground noise in the
power supply. The hysteresis also ensures continuous
operation in case of a small drop in the bias voltage. This
drop in the bias can happen when device starts switching
MOSFET and the operating current of the device increases.
The UVLO feature of the device is explained in the
Figure 41.
MOSFETs are driven at an optimum voltage. If the V is
CC
below the V UVLO voltage, the low side driver output
CC
(DRVL) and high side driver output (DRVH) both remain
low. If V is below V
UVLO voltage the high side driver
B
Boff
output (DRVH) remains low. However if the V is above
CC
V
CCon
UVLO voltage level, the low side driver output
V
CCon
Legend:
1. Vcc crossed Vcc ON level, LIN is set to H.
The DRVH is set to H immediately. Current
starts to flow from Vcc to Cboot via bootstrap
diode.
V
CCoff
2. Cboot is not fully charged in first pulse.
3. Vb cross Vbon level. HIN is in L, output stays
in L. Both UVLOs are activated, pulses Can
pass the driver.
4. Vccoff level is activated, DRVL is set to L,
DRVH had been in L, it stayes in L
5. Vccon level crossed, HS UVLO had been
activated earlier, the pulse is ignored.
6. Vboff level crossed while DRVH is H. DRVH
is set to L immediately.
V
CC
LIN
DRVL
V
Bon
V
Boff
7. Vbon level crossed. Current (ongoing) HIN
pulse is ignored.
8. Both UVLOs are activated, all pulses passes
the driver. Steady state conditions.
9. Vccoff level is croosed while DRVH is in H.
Both drivers are inhibited, DRVH is set to L
immediately. From now on, no pulse will pass
the driver (LS nor HS).
V
B
− V
HB
HIN
DRVH
9
1
2
3
4
5
6
7
8
Figure 41. UVLO Timing Diagram
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15
NCV51513
Dead Time Control & Interlock
switched on. Version NCV51513xA offer no dead time, this
version is better for high frequency application with external
dead time control. Both versions NCV51513xA and xB are
equipped with cross conduction prevention logic
(interlock), which does not let to set both drivers to High
simultaneously. See detail function in Figure 42.
NCV51513xB features inbuild 80 ns dead control logic.
The logic inserts the 80 ns delay after any driver turn off to
postpone turn on of the opposite one. The delay helps to
minimize cross conduction current through the MOSFETs
when one is switched off and simultaneously other one is
HIN
LIN
t
t
DRVH
t
DRVL
t
t
Cross
Prevention
Active
DT timer
t
Figure 42. Dead Time Timing Diagram, NCV51513xB
HIN
LIN
t
t
t
DRVH
DRVL
t
t
Interlock
signal
Figure 43. Interlock Timing Diagram, NCV51513xA
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16
NCV51513
Table 2. TRUE TABLE
#
1
Vcc Supply
Vb Supply
EN
x
LIN
x
HIN
x
DRVL
DRVH
Vcc < Vccoff
Vb = x
L (Note 7)
L (Note 7)
2
Vcc > Vccon (Note 5)
Vcc > Vccon (Note 5)
Vcc > Vccon (Note 5)
Vcc > Vccon (Note 5)
Vcc > Vccon (Note 5)
Vcc > Vccon (Note 5)
Vcc > Vccon (Note 5)
Vcc ↑ Vccon (Note 6)
Vcc ↑ Vccon (Note 6)
Vcc ↑ Vccon (Note 6)
Vcc ↑ Vccon (Note 6)
Vcc > Vccon (Note 6)
Vcc ↓ Vccoff
Vb = x
L
x
x
L
L (Note 7)
3
Vb < Vboff
Vb < Vboff
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
x
L
L
4
H
L
L
H
L
5
Vb > Vbon (Note 5)
Vb > Vbon (Note 5)
Vb > Vbon (Note 5)
Vb > Vbon (Note 5)
Vb < Vboff
L
L
L
6
H
L
L
H
L
7
H
H
x
L
H
8
H
L
L
L
9
L
L
10
11
12
13
14
15
16
17
Vb < Vboff
H
L
L
L ↑ H
L
Vb > Vbon (Note 5)
Vb > Vbon (Note 5)
Vb ↑ Vbon (Note 6)
Vb > Vbon (Note 5)
Vb > Vbon (Note 5)
Vb ↓ Vboff
L
L
L
L
H
H
L
L
L
L
L
L
H ↓ L
L
H
L
L
Vcc ↓ Vccoff
H
L
H ↓ L
L
Vcc > Vccon (Note 5)
Vcc > Vccon (Note 5)
H
L
H
Vb ↓ Vboff
H
L
H ↓ L
5. The voltage has crossed Vcc/Vb on level and it is higher than Vcc/Vb off level.
6. The voltage is rising from 0 V.
7. If the Vcc/Vb is lower than 3 V, the driver is pulled down via 150 kW.
NOTE: x − Any value
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17
NCV51513
Output Stages
received from input stage, Qsource turns on and V /V
CC
B
NCV51513 are equipped with two independent drivers
with typical source/sink current is 2.0/3.0 A. The driver can
effectively charge/discharge a 1 nF load in 9/7 ns.
NCV51513 output drivers can not be turned on at the same
time. The xB version feature internal dead time generator,
which inserts 80 ns dead time to eliminate short through
current through the MOSFETs. See Figure 42.
starts charging C through R . Once the C is charged to the
gs
g
gs
drive voltage level, the external power MOSFET turns on
and connects HB pin either to GND node (low side switch)
or to HV line (high side switch).
When a logic low signal is received from the input stage,
Qsource turns off and Qsink turns on providing a path for
gate terminal discharging.
The Figure 44 shows the output stage structure and the
charging and discharging path of the external power
MOSFET. The bias supply V or V supplies energy to
As seen in the Figure 44, there are parasitic inductances in
charging and discharging path of the C . This can result in
gs
a little dip in the bias voltages V /V . If the V /V drops
CC
B
CC
B
CC
B
charge the gate capacitance C of the low side or the high
side external MOSFETs respectively. When a logic high is
below UVLO level, the power supply can shut down the
device.
gs
turn on turn off
Voltage probes
NCV51513
L
bond
L
trace
Q
source
VCC(VB)
turn on
MOSFET
C
(C
)
VCC boot
turn off
C
turn on
turn off
GD
L
trace
R
DSon
L
bond
R
DRVL(DRVH)
g
R
DSon
C
GS
turn on
turn off
L
trace
Q
sink
L
trace
L
bond
GND(HB)
All voltages are refered to GND(HB) pin
Figure 44. NCV51513 Turn ON−OFF Paths
Short Propagation Delay
NCV51513By offers 20 ns propagation delay between input
and output.
The device allows 100 % duty cycle operation. The
DRVH or DRVL can be continuously in H or L state. It is
necessary to have a floating source to supply DRVH driver
when using the driver under this 100% DC.
NCV51513 boast short propagation delay between input
and output. NCV51513Ay have a typical of 50 ns
propagation delay. The best in class propagation delay in
NCV51513 makes it suitable for high frequency operation.
Since NCV51513By doesn’t have the input filter
included, the propagation delays are even faster.
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18
NCV51513
Negative Transient Immunity (NTI) Operating
Conditions
In any HB switching applications the HB node is often
pulled under the ground during the switching operation
because of parasitic inductances and inductive load. These
negative spikes may lead to malfunction or damage of the
circuit.
Below schematics depicts parasitic and current
circulation during switching operations that could create the
negative deep of the HB node.
R
D
boot
boot
V+
I1−Positive current
I2−Reverse current
I3−Short through current
I4−Negative current
HB driver
Vcc
VB
L
1
C
boot
D
1
Q
1
2
I2
DRVH
L
−
HB
+
−
I1
L
3
I4
+
Q
2
D
2
Load
DRVL
L
res+prim
−
+
−
C
res
L
4
I3
+
GND
Figure 45. HB Negative Voltage in an LLC Configuration
NTI Robustness Measurement
The capability of NCV51513 to operate under negative
voltage conditions is reported in NTI graph using below test
set up.
22 Ω
MUR160
BAT54
220 μF
12V
470 nF
VCC
VB
9 V
DRVH
probe
DRVH
EN
HIN
LIN
HB
HB
probe
V
NTI
DRVL
GND
DRVL
probe
HIN
LIN
Figure 46. NTI Test Set Up
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19
NCV51513
HIN
LIN
V
NTI
VB − HB
VB
Case B
Case A
Figure 47. Timing Diagram
NCV51513 robustness against negative spikes is shown in
Figure 48. The result is a curve which shows negative
voltage level for specific pulse width under which driver
could still operate properly.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
100
150
0
50
200
250
300
Time [ns]
Figure 48. Indicative Negative Transient Immunity
Important note:
Even though above figure shows that NCV51513 is able to
handle negative transient voltage conditions, it is highly
recommended that the application circuit design is such that
it removes or at least always limit the negative transient
voltage on VB pin as much as possible via careful PCB
layout and proper component selection.
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20
NCV51513
Applications information & Component Selection
This section outlines the key design steps and components
selection to get full benefit of NCV51513 performances. It
includes as well some power dissipation considerations and
layout recommendations.
Rboot
Dboot
Cboot
IC1
Q_HI
Rhsnk
Dhsnk
Dlsnk
DRVL
GND
LIN
VCC
NC
VB
DRVH
HB
Rhgate
HIN
Cbulk
EN
Rlsnk
Q_LO
Cvcc
Rlgate
Figure 49. Recommended Schematic
Cboot Capacitor Value Calculation
The device features two independent drivers. The low side
driver (DRVL) supplies a MOSFET whose source is
charge Q (from zero voltage to V of the MOSFET) is
g th
taken from V capacitor (through an external boot strap
CC
connected to ground. The driver is powered from V line.
diode) so the voltage drop on C
is smaller. For the
CC
boot
The high side driver (DRVH) supplies a MOSFET whose
source is floating from GND to bulk voltage. The floating
calculation of C
account.
value the ZVS conditions are taken
boot
driver is powered from C
charged only when HB pin is pulled to GND (by inductance
or the low side MOSFET when turned on). If too small C
capacitor. The capacitor is
The switching cycle is divided into two parts, the charging
(t ) and the discharging (t ) of the C
charge
capacitor. The discharging can be divided even more to
boot
discharge
boot
boot
capacitor is used the high side UVLO protection can disable
the high side driver which leads to improper switching.
Expected voltage on Cboot is pictured in Figure 50. The
curves are valid for ZVS (Zero Voltage Switching) observed
in LLC applications. For hard switch the curves are slightly
discharging by floating driver current consumption I
B2
(t ), and to discharging by transfering energy from C
dsIb
boot
to gate terminal of the MOSFET (t
) and discharging by
dsQm
leakage current of the bootstrap diode (not taken account).
Discharging by I becoming more dominant when driver
CC4
different, but from charge on C
favorable. Under the hard switch conditions the energy to
point of view more
runs at lower frequencies and/or during skip mode
operation. To calculate C value, follow these steps:
boot
boot
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21
NCV51513
Legend:
DRVL
DRVH
HB
low side driver
high side driver
bridge pin
DRVL
0 V
V
V
V
boot strap capacitor voltage
Cboot
Cmax
Cmin
maximum C
voltage
voltage
boot
minimum C
boot
DRVH
0 V
t
t
t
t
charging period
discharging period
charge
discharge
dsIb
discharging by I current
B
discharging by transcer a
charge to a MOSFET
dsQm
HB
0 V
V
Cmax
V
Cboot
V
Cmin
t
t
t
t
discharge
charge
V
Cboot
t
t
t
t
charge
dsIb dsQm
dsIb
Figure 50. Boot Strap Capacitor Charging
1. For example, let’s have a MOSFET with
Q = 49 nC, V = 10 V.
resistor value selection is critical for proper function of the
high side driver. If too small high current peaks are drown
g
DD
2. Charge stored in C
necessary to cover the period
from V line, if too high the capacitor will not be charged
boot
CC
the C
is not supplied from V line (which is
to appropriate level and the high side driver can be disabled
by internal UVLO protection.
First of all keep in mind the capacitor is charged through
the external bootstrap diode, so it can be charged to a
boot
CC
basically the period the high side MOSFET is turned
on). Let’s say the application is switching at
100 kHz, 50% duty cycle, which means the upper
MOSFET is conductive for 5 ms. It means the C
maximum voltage level of V – V . The resistor value is
boot
CC f
calculated using this equation:
is discharged by I current (100 mA typ) for 5 ms, so
B2
the charge consumed by floating driver is:
tcharge
Rboot
+
+
Qb + IB2 @ tdischarge + 100 m @ 5 m + 500 pC
Vmax*VCmin
Vmax*VCmax
(eq. 1)
@ lnǒ
Ǔ
Cboot
3. Total charge loss during one switching cycle is sum
of charge to supply the high side driver and
MOSFET’s gate charge:
5 m
^ 4.6 W
9.4*9.25
9.4*9.35
1 m @ lnǒ
Ǔ
Qtot + Qg ) Qb + 49 n ) 500 p + 49.5 nC
(eq. 2)
(eq. 4)
4. Let’s determine acceptable voltage ripple on C
to
boot
Where:
1% of nominal value, which is 100 mV. To cover
charge losses from Eq. 2.
t
time period the Cboot is being charged,
usually the period the low side MOSFET
is turned on,
charge
Qtot
49.5 n
0.1
Cboot
+
+
+ 495 nF
Vripple
(eq. 3)
C
boot
boot strap capacitor value,
Rboot Resistor Value Calculation
V
max
maximum voltage the C
capacitor
boot
To keep the application running properly, it is necessary
to charge the C again. This is done by external diode
can be theoretically charged to. Usually the
– V . The V is forward voltage of
V
CC
boot
f
f
from V line to VB pin. In serial with the diode a resistor
used diode,
CC
is placed to reduce the current peaks from V line. The
CC
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22
NCV51513
V
V
the voltage level the capacitor is charge
from,
The Boot strap resistor must be designed to accept the
current from Eq. 8 and power loss from Eq. 9 for a while.
Cmin
the voltage level the capacitor is charged
to. It is necessary to determine the target
voltage for charging, because in theory,
when a capacitor is charged from a voltage
source through a resistor, the capacitor can
never reach the voltage of the source. In
this particular case a 50 mV difference
(between the voltage behind the diode and
Cmax
VCC Capacitor Selection
V
CC
capacitor value should be selected at least ten times
the value of C
. In this case thus C
> 10 mF.
boot
Vcc
Very close to the driver should be placed a ceramic
capacitor at least the same value of C , to cover current
boot
peaks for low side MOSFET gate charging.
Rgate Selection
V
Cmax
) is used.
The R
are selected to limit the peak gate current during
gate
charging and discharging of the gate capacitance. This
resistance also helps to damp the ringing due to the parasitic
inductances, reduce dV/dt on HB pin to safe level and
attenuate EMI radiation. If high dV/dt (during rise/fall edge
and/or ringing after switching) is applied on HB pin, it can
cause unexpected behavior of the driver.
On the other hand, too high resistor will increase power
loss on MOSFETs, which leads to lower efficiency. It is
recommended to start evaluation with a high resistor value
and decrease the value if behavior is safe under all
conditions. We recommend to have at least a 4.7 W resistor
between NCV51513 outputs and MOSFET’s gate.
The resistor value obtained from Eq. 4 does not count with
the quiescent current I of the high side driver. This current
B2
will create another voltage drop of:
VIB2_drop + Rboot @ IB2 + 4.6 @ 100 m ^ 460 mV
(eq. 5)
The current consumed by high side driver will be higher,
because the I is valid when the device is not switching.
B2
While switching, losses by charging and discharging
internal transistors as well as the level shifters will be added.
This current will increase with frequency.
The additional 460 mV drop will be added to V
value.
Cmax
The additional 460 mV drop can be either accepted or the
value can be recalculated to eliminate this additional
The resistors also help to decrease power dissipation of
the driver, because part of the energy from charging and
R
boot
drop.
The resistor R
discharging C is radiated on the resistors R
(and on
gs
xgate
calculated in Eq. 4 is valid under steady
boot
R
xsnk
if they are used) outside the driver see Figure 49. The
state conditions. During start and/or skip operation the
starting point voltage value is different (lower) and it takes
more time to charge the boot strap capacitor. More over it is
not counted with temperature and voltage variability during
normal operation or the dynamic resistance of the boot strap
diode (approximately 0.34 W for MURA160). From these
reasons the resistor value should be decreased especially
with respect to skip operation.
gate resistor selection is tricky task. It depends on
application, topology, on used MOSFETs, layout etc.
For example for an R
value of 4.7 W, the peak source
xgate
and sink currents would be limited to the following values.
= 4.7 W
R
gate
10 V
Vcc
IDRVL_Source
+
+
+ 787 mA
RLgate ) RLOL ) Rg
12.7 W
(eq. 10)
Boot strap resistor loss calculation.
10 V
Vcc
PRboot ^ Qtot @ Vmax @ f + 49.5 n @ 9.4 @ 100 k ^ 46.3 mW
IDRVL_Sink
+
+
+ 935 mA
RLgate ) RLOL ) Rg
10.7 W
(eq. 6)
(eq. 11)
Boot strap diode loss calculation.
Where:
PDboot ^ Qtot @ Vf @ f + 49.5 n @ 0.6 @ 100 k ^ 3 mW
(eq. 7)
R
LOH
R
DSon
of internal source MOSFET
(see parametric table R parameter),
OH
Please keep in mind the value is temperature and voltage
dependent. Especially C
voltage can be higher than
R
LOL
R
DSon
of internal sink MOSFET
boot
calculated value. See “Layout recommendation” section for
more details. Also keep in mind, the Boot strap resistor
power dissipation calculated in Eq. 6 is valid for steady state
(see parametric table R parameter),
OL
Rg
internal gate resistance of external
MOSFET (see appropriate DS), in this
case 1 W.
conditions. For first C
charging, the power loss (the
boot
current) is much higher.
CVcc * VDboot * VCboot
10 * 0.6 * 0
In some applications it is desired/advantageous to use
separated current paths for charging and discharging the gate
capacitance. For this purpose external MOSFET gate
connection must be extended (see Figure 49). Two
components Rxsnk and Dxsnk can be added in parallel to
Rxgate resistor. The charging path is now only through
IRboot
+
+
^ 2 A
(eq. 8)
4.6
Rboot
PRboot + (CVcc * VDboot * VCboot ) @ IRboot
(
)
+ 10 * 0.6 * 0 @ 2 ^ 18.8 W
(eq. 9)
www.onsemi.com
23
NCV51513
Rxgate resistor, while discharging path is through Rxsnk and
3. Level shifter power loss
Rxgate in parallel combination. Consider both resistors are
the same value 10 W. The source current is calculated using
Eq. 10. The current is 556 mA.
Plvlshft + (VHV ) VB) @ fSW @ (QS ) QR)
(
)
(
)
+ 100 ) 9.4 @ 100 k @ 190 p ) 190 p
R
= 10 W
lgate
^ 4.2 mW
(eq. 17)
V
* V
Dlsnk
V
cc
cc
I
+
)
DRVL
R
) (R
) R ) @ 2
R
) (R
) R ) @ 2
Sink
g
g
Where:
lgate
LOL
lsnk
LOL
V
V
is DC link voltage, here 100 V,
is boot strap voltage, here 9.6 V,
is duty frequency, here 100 kHz,
HV
B
10 V
9.4 V
+
)
+ 882 mA
22 W
22 W
(eq. 12)
f
SW
For high side driver current calculation use the same
method. Use Eq. 10 to Eq. 12, but use V voltage
(usually diminished by V of used bootstrap diode).
Q , Q
S
is energy needed to transfer information
from LS part to HS part of the driver.
The worst case is ZVS mode. In hard switch
R
Cboot
f
mode is Q very small, as the set pulse
S
Total Power Dissipation
come when HB pin is on low voltage.
Total power dissipation of NCV51513 is sum of partial
dissipations which can be calculated as follows. For more
details, please refer to AND90004.
4. HS leakage power loss
Pleak + IHV
@ (VHV ) VB) @ DC
1. Power loss of device (except drivers) while
switching at appropriate frequency is calculated
from current consumption at given voltage for
specific frequency. The current can be estimated
from Figure 35, or it could be calculated using these
formulas:
LEAK
(
)
+ 1.8 m @ 100 ) 9.4 @ 0.5 ^ 0.1 mW
(eq. 18)
Where:
V
HV
V
B
is DC link voltage, here 100 V,
is boot strap voltage, here 9.4 V,
is duty cycle, here 50%.
Icc + 21.1 m @ f @ V ) 7.01 m @ V ) 783 m @ f ) 53.6 m
(eq. 13)
DC
Ib + 28.6 m @ f @ V ) 6.75 m @ V ) 633 m @ f ) 17.6 m
5. Total power losses
(eq. 14)
Ptotal + Plogic ) Pdrivers ) Plvlshft ) Pleak
Where:
+ 3.8 m ) 95.1 m ) 4.2 m ) 0.1 m
f
is frequency in kHz,
is voltage in V,
V
^ 103 mW
(eq. 19)
Calculated current will be in mA.
6. Junction temperature rises for calculated power
loss
The power dissipation of device (without drivers) is equal to.
tJ + RtJa @ Ptotal + 157 @ 0.103 ^ 16 K
+ ǒV
Ǔ) ǒV
Ǔ
Plogic + PHS ) PLS
boot @ IB1
CC @ ICC1
noload
noload
(eq. 20)
The temperature calculated in Eq. 15 is the value which
has to be added to ambient temperature. In case the ambient
temperature is 30°C, the junction temperature will be 46°C.
(
)
(
)
+ 9.4 @ 0.171 m ) 10 @ 0.223 m ^ 3.8 mW
(eq. 15)
2. Power loss of drivers
+ ǒǒ
Ǔ
ǒ
ǓǓ @ f
Pdrivers
Qg @ Vboot ) Qg @ VCC
+ ((49 n @ 9.4) ) (49 n @ 10)) @ 100 k
^ 95.1 mW
(eq. 16)
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24
NCV51513
Layout Recommendations
The NCV51513 are high speed drivers suitable for
mid−high power application. To avoid any damage and/or
malfunction during switching (and/or during transients,
overloads, shorts etc.) it is very important to avoid a high
parasitic inductances in high current paths (see “MOSFET
turn on and turn off current path” section). It is
recommended to fulfill some rules in layout. One of
a possible layout for the IC is depictured in Figure 51.
featured high current capability driver. Any parasitic
inductance in this path will result in slow Q_HI turn on
and voltage drop on VB pin which can result in UVLO
activation.
• To limit bootstap switching current from the C
it is
VCC
recommended to add a resistor in serial with bootstrap
diode. The resistor also protect HS driver against
overvoltage on V – HB pins in case of negative spikes
B
• Keep loop HB_pin – GND_pin – Q_LO as small as
possible. This loop (parasitic inductance) has potential to
increase negative spike on HB pin which can cause
malfunction or damage of HB driver. The negative
on HB pin.
• Do not let high current flow through trace between
GND_pin and C
.Even a small parasitic inductance
VCC
here will create high voltage drop if high current flows
through this path. This voltage is added or subtracted from
HIN, LIN and EN signal, which results in incorrect
thresholds or device damaging.
voltage presented on HB pin is added to V −V voltage
CC
f
so V
is increased. In extreme case the C
voltage
Cboot
boot
can be so high it will cross maximum rating value which
can lead to device damage.
• Keep loops DRVL_pin – Q_LO – GND_pin and
DRVH_pin – Q_HI – HB_pin as small as possible. A high
parasitic inductance in these paths will result in slow
MOSFET switching and undesired resonance on gate
terminal.
• Keep loop VCC_pin – GND_pin – C
as small as
as close to the IC as possible).
VCC
possible (locate C
VDD
The IC features high current capability driver. Any
parasitic inductance in this path will result in slow Q_LO
turn on and voltage drop on VCC pin which can result in
UVLO activation.
• The high side driver is jumping up and down with high
dV/dt at high frequency. The generated noise can
influence devices and traces around. Do not place low
voltage and sensitive traces into the vicinity of this HV
node.
• To avoid switching current (a noise) from the driver to
disturb the Vcc line a small resistance in serie with C
VCC
and V supply line is good to add.
CC
• Keep loop VB_pin – HB_pin – C
as small as possible
as close to the IC as possible). The IC
boot
(locate C
boot
Figure 51. Recommended Layout
www.onsemi.com
25
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW10, 3x3, 0.5P
CASE 507AG
ISSUE B
1
DATE 14 APR 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
1
XXXXX
XXXXX
ALYWG
G
XXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON73716G
DFNW10, 3x3, 0.5P
PAGE 1 OF 1
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