NCV5703A [ONSEMI]
High Current IGBT Gate Drivers;
| 型号： | NCV5703A |
| 厂家： | 
ONSEMI |
| 描述： | High Current IGBT Gate Drivers 栅 双极性晶体管 |
| 文件： | 总20页 (文件大小：672K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV5703A, NCV5703B,
NCV5703C
High Current IGBT Gate
Drivers
The NCV5703A, NCV5703B and NCV5703C are high−current,
high−performance stand−alone IGBT drivers for high power
applications that include solar inverters, motor control and
uninterruptible power supplies. The devices offer a cost−effective
solution by eliminating external output buffer. Devices protection
features include accurate Under−voltage−lockout (UVLO),
desaturation protection (DESAT) and Active open−drain FAULT
output. The drivers also feature an accurate 5.0 V output. The drivers
are designed to accommodate a wide voltage range of bias supplies
including unipolar and NCV5703B even bipolar voltages.
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MARKING
DIAGRAM
8
8
1
1
NCV5703X
ALYW
SOIC−8
D SUFFIX
CASE 751
G
Depending on the pin configuration the devices also include Active
Miller Clamp (NCV5703A) and separate high and low (V and V
)
OL
OH
NCV5703 = Specific Device Code
driver outputs for system design convenience (NCV5703C).
All three available pin configuration variants have 8−pin SOIC
package.
X
A
L
Y
W
G
= A, B or C
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
• High Current Output (+4/−6 A) at IGBT Miller Plateau voltages
• Low Output Impedance for Enhanced IGBT Driving
• Short Propagation Delay with Accurate Matching
PIN CONNECTIONS
1
2
3
4
8
7
6
5
• Direct Interface to Digital Isolator/Opto−coupler/Pulse Transformer
for Isolated Drive, Logic Compatibility for Non−isolated Drive
• DESAT Protection with Programmable Delay
VIN
VREF
FLT
CLAMP
GND
VO
• Tight UVLO Thresholds for Bias Flexibility
DESAT
VCC
• Wide Bias Voltage Range
NCV5703A
NCV5703B
• This Device is Pb−Free, Halogen−Free and RoHS Compliant
1
2
3
4
8
7
6
5
VIN
VREF
FLT
VEE
GND
VO
NCV5703A Features
• Active Miller Clamp to Prevent Spurious Gate Turn−on
DESAT
VCC
NCV5703B Features
• Negative Output Voltage for Enhanced IGBT Driving
1
2
3
4
8
7
6
5
NCV5703C Features
• Separate Outputs for V and V
VIN
VREF
FLT
GND
VOL
VOH
VCC
OL
OH
Typical Applications
• Motor Control
• Uninterruptible Power Supplies (UPS)
• Automotive Power Supplies
• HEV/EV PTC Heaters
DESAT
NCV5703C
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
August, 2019 − Rev. 1
NCV5703/D
NCV5703A, NCV5703B, NCV5703C
NCV5703A
VREF
DESAT
VCC
VCC
VO
CLAMP
GND
VIN
FLT
NCV5703B
VREF
DESAT
VCC
VCC
VO
VIN
FLT
GND
VEE
VEE
NCV5703C
VREF
DESAT
VCC
VCC
VOH
VOL
VIN
FLT
GND
Figure 1. Simplified Application Schematics
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2
NCV5703A, NCV5703B, NCV5703C
FLT
SET
TSD
Q
Q
S
CLR
R
NCV5703A
IDESAT-CHG
DELAY
DESAT
+
-
SET
VDESAT-THR
S
Q
Q
VCC
CLR
R
VREF
VO
VIN
RIN-
DELAY
VREF
Bandgap
VUVLO
-
+
VCC
SET
S
Q
Q
CLR
R
-
CLAMP
+
VMC-THR
GND
Figure 2(a). Detailed Block Diagram NCV5703A
NCV5703A
CLAMP
VIN
CLAMP
VCC
VREF
FLT
GND
VO
LDO
TSD
VCC
UVLO
VCC
DESAT
DESAT
Figure 2(b). Simplified Block Diagram NCV5703A
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3
NCV5703A, NCV5703B, NCV5703C
FLT
SET
TSD
Q
Q
S
CLR
R
NCV5703B
IDESAT-CHG
DELAY
DESAT
+
-
SET
VDESAT-THR
S
Q
Q
VCC
CLR
R
VREF
VIN
RIN-L
VO
DELAY
Bandgap
VREF
VUVLO
VEE
-
+
VCC
GND
VEE
Figure 3(a). Detailed Block Diagram NCV5703B
NCV5703B
VEE
VIN
VCC
GND
VO
LDO
VREF
FLT
TSD
VCC
UVLO
VCC
DESAT
DESAT
Figure 3(b). Simplified Block Diagram NCV5703B
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4
NCV5703A, NCV5703B, NCV5703C
FLT
SET
TSD
Q
Q
S
CLR
R
NCV5703C
IDESAT-CHG
DELAY
DESAT
+
-
SET
VDESAT-THR
S
Q
Q
VCC
CLR
R
VREF
VOH
VIN
RIN-L
VOL
DELAY
VUVLO
VREF
Bandgap
-
+
VCC
GND
Figure 4(a). Detailed Block Diagram NCV5703C
NCV5703C
GND
VIN
VCC
VOL
VOH
LDO
VREF
FLT
TSD
VCC
UVLO
DESAT
VCC
DESAT
Figure 4(b). Simplified Block Diagram NCV5703C
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5
NCV5703A, NCV5703B, NCV5703C
Table 1. PIN FUNCTION DESCRIPTION
Pin Name
No.
I/O/x
Description
VIN
1
I
Input signal to control the output. In applications which require galvanic isolation, VIN is generat-
ed at the opto output, the pulse transformer secondary or the digital isolator output. VO (VOH/
VOL) signal is in phase with VIN. VIN is internally clamped to GND and has a pull−down resistor
of 1 MW to ensure that an output is low in the absence of an input signal. A minimum pulse−
width is required at VIN before VO (VOH/VOL) is activated.
VREF
FLT
2
3
O
O
5 V Reference generated within the driver is brought out to this pin for external bypassing and
for powering low bias circuits (such as digital isolators).
Fault open drain output (active low) that allows communication to the main controller that the
driver has encountered a fault condition and has deactivated the output. Open drain allows easy
setting of (inactive) high level and parallel connection of multiple fault signals.
Connect to 10k pull−up resistor recommended. Truth Table is provided in the datasheet to indi-
cate conditions under which this signal is asserted. Capable of driving optos or digital isolators
when isolation is required.
DESAT
VCC
4
5
6
I
Input for detecting the desaturation of IGBT due to a fault condition. A capacitor connected to
this pin allows a programmable blanking delay every ON cycle before DESAT fault is processed,
thus preventing false triggering.
x
Positive bias supply for the driver. The operating range for this pin is from UVLO to the maxi-
mum. A good quality bypassing capacitor is required from this pin to GND and should be placed
close to the pins for best results.
VO
(NCV5703A,
NCV5703B)
O
Driver output that provides the appropriate drive voltage, source and sink current to the IGBT
gate. VO is actively pulled low during start−up and under Fault conditions.
VOH
6
7
7
O
O
x
Driver high output that provides the appropriate drive voltage and source current to the IGBT
gate.
(NCV5703C)
VOL
(NCV5703C)
Driver low output that provides the appropriate drive voltage and sink current to the IGBT gate.
VOL is actively pulled low during start−up and under Fault conditions.
GND
(NCV5703A,
NCV5703B)
This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors
should be referenced to this pin and kept at a short distance from the pin.
GND
8
8
x
x
This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors
should be referenced to this pin and kept at a short distance from the pin.
(NCV5703C)
VEE
(NCV5703B)
A negative voltage with respect to GND can be applied to this pin and that will allow VO to go to
a negative voltage during OFF state. A good quality bypassing capacitor is needed from VEE to
GND. If a negative voltage is not applied or available, this pin must be connected to GND.
CLAMP
(NCV5703A)
8
I/O
Provides clamping for the IGBT gate during the off period to protect it from parasitic turn−on. To
be tied directly to IGBT gate with minimum trace length for best results.
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6
NCV5703A, NCV5703B, NCV5703C
Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1)
Parameter
Differential Power Supply
Symbol
−V (V )
max
Minimum
Maximum
Unit
V
V
0
36
22
CC
EE
Positive Power Supply
Negative Power Supply
Gate Output High
Gate Output Low
Input Voltage
V
−GND
−GND
−0.3
−18
V
CC
V
0.3
V
EE
(V , V )−GND
V
V
+ 0.3
V
O
OH
CC
(V , V )−GND
V − 0.3
EE
V
O
OL
V
IN
−GND
−0.3
−0.3
5.5
V
DESAT Voltage
V
−GND
DESAT
+ 0.3
V
CC
FLT current
Sink
mA
I
20
FLT−SINK
Power Dissipation
SO−8 package
PD
700
mW
Maximum Junction Temperature
Storage Temperature Range
T
150
°C
°C
kV
V
J(max)
TSTG
−65 to 150
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
Moisture Sensitivity Level
ESDHBM
ESDMM
MSL
4
200
1
−
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
T
SLD
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78, 25°C
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 3. THERMAL CHARACTERISTICS
Parameter
Symbol
Value
Unit
Thermal Characteristics, SOIC−8 (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
°C/W
R
176
q
JA
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2
2
5. Values based on copper area of 100 mm (or 0.16 in ) of 1 oz copper thickness and FR4 PCB substrate.
Table 4. OPERATING RANGES (Note 6)
Parameter
Differential Power Supply
Symbol
−V (V )
max
Min
Max
30
20
0
Unit
V
V
CC
EE
Positive Power Supply
Negative Power Supply
Input Voltage
V
CC
UVLO
−15
0
V
V
EE
V
V
IN
5
V
Input pulse width
t
40
ns
°C
on
Ambient Temperature
T
−40
125
A
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCV5703A, NCV5703B, NCV5703C
Table 5. ELECTRICAL CHARACTERISTICS V = 15 V, V = 0 V, Kelvin GND connected to V . For typical values T = 25°C,
CC
EE
EE
A
for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
LOGIC INPUT and OUTPUT
Input Threshold Voltages
Pulse−Width = 150 ns, V = 5 V
V
EN
High−state (Logic 1) Required Voltage applied to get output to go high
Low−state (Logic 0) Required Voltage applied to get output to go low
V
V
4.3
1.2
IN−H1
0.75
3.7
IN−L1
No state change
Voltage applied without change in output state
V
IN−NC
Input Current
High−state
Low−state
mA
V
V
= 4.5 V
= 0.5 V
I
I
10
1
IN−H
IN−H
IN−L
IN−L
Input Pulse−Width
No Response at the Output
Voltage thresholds consistent with input
specs
ns
t
15
on−min1
Guaranteed Response at the
Output
t
40
on−min2
FLT Threshold Voltage
Low State
V
(I
= 15 mA)
V
FLT−L
0.5
1.0
FLT−SINK
High State
External pull−up
V
FLT−H
V
CC
+0.3
DRIVE OUTPUT
Output Low State
V
V
I
I
I
= 200 mA, T = 25°C
V
V
V
0.1
0.2
0.8
0.2
0.5
1.2
sink
sink
sink
A
OL1
OL2
OL3
= 200 mA, T = −40°C to 125°C
A
= 1.0 A, T = 25°C
A
Output High State
I
src
I
src
I
src
= 200 mA, T = 25°C
V
OH1
V
OH2
V
OH3
14.5
14.2
13.8
14.8
14.7
14.1
A
= 200 mA, T = −40°C to 125°C
A
= 1.0 A, T = 25°C
A
Peak Driver Current, Sink
(Note 7)
R
V
V
= 0.1 W, V = 15 V, V = −8 V
= 13 V
= 9 V (near Miller Plateau)
A
A
G
O
O
CC
EE
I
I
6.8
6.1
PK−snk1
PK−snk2
Peak Driver Current, Source
(Note 7)
R
= 0.1 W, V = 15 V, V = −8 V
G
O
O
CC
EE
V
V
= −5 V
= 9 V (near Miller Plateau)
I
I
7.8
4.0
PK−src1
PK−src2
DYNAMIC CHARACTERISTICS
Turn−on Delay
Negative input pulse width = 10 ms
Positive input pulse width = 10 ms
For input or output pulse width > 150 ns,
t
t
45
45
59
54
75
75
ns
ns
ns
pd−on
(see timing diagram)
Turn−off Delay
(see timing diagram)
pd−off
Propagation Delay Distortion
(=t
− t
)
T
T
A
= 25°C
= −40°C to 125°C
t
−5
−25
5
15
25
pd−on pd−off
A
distort1
t
distort2
Prop Delay Distortion between
Parts (Note 7)
t
−30
0
30
ns
ns
ns
ms
ns
distort −tot
Rise Time (Note 7)
(see timing diagram)
C
C
= 1.0 nF
= 1.0 nF
t
9.2
7.9
12
load
load
rise
Fall Time (Note 7)
(see timing diagram)
t
fall
Delay from FLT under UVLO/
TSD to VO/VOL
t
t
9
15
d1−OUT
d2−OUT
Delay from DESAT to VO/VOL
(Note 7)
220
7. Values based on design and/or characterization.
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NCV5703A, NCV5703B, NCV5703C
Table 5. ELECTRICAL CHARACTERISTICS V = 15 V, V = 0 V, Kelvin GND connected to V . For typical values T = 25°C,
CC
EE
EE
A
for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
DYNAMIC CHARACTERISTICS
Delay from UVLO/TSD to FLT
(Note 7)
t
7.3
ms
d3−FLT
MILLER CLAMP (NCV5703A ONLY)
Clamp Voltage
I
I
= 500 mA, T = 25°C
V
clamp
1.2
2.0
1.4
2.2
V
V
sink
A
= 500 mA, T = −40°C to 125°C
sink
A
Clamp Activation Threshold
DESAT PROTECTION
DESAT Threshold Voltage
Blanking Charge Current
Blanking Discharge Current
UVLO
V
1.8
2.2
MC−THR
V
6.0
6.35
0.24
30
7.0
V
DESAT−THR
I
0.20
0.28
mA
mA
DESAT−CHG
I
DESAT−DIS
UVLO Startup Voltage
UVLO Disable Voltage
UVLO Hysteresis
V
13.2
12.2
13.5
12.5
1.0
13.8
12.8
V
V
V
UVLO−OUT−ON
V
UVLO−OUT−OFF
V
UVLO−HYST
VREF
Voltage Reference
I
= 10 mA
V
4.85
100
5.00
5.15
20
V
REF
REF
Reference Output Current
(Note 7)
I
mA
REF
Recommended Capacitance
C
nF
VREF
SUPPLY CURRENT
Current Drawn from V
V
= 15 V
I
0.9
1.5
mA
mA
CC
CC
CC−SB
Standby (No load on output, FLT, VREF)
Current Drawn from V
(NCV5703B ONLY)
V
EE
= −10 V
I
−0.2
−0.14
EE
EE−SB
Standby (No load on output, FLT, VREF)
THERMAL SHUTDOWN
Thermal Shutdown Temperature
(Note 7)
T
T
188
33
°C
°C
SD
Thermal Shutdown Hysteresis
(Note 7)
SH
7. Values based on design and/or characterization.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
ORDERING INFORMATION
†
Device
NCV5703ADR2G
Package
Shipping
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCV5703BDR2G
NCV5703CDR2G
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
(Pb−Free)
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NCV5703A, NCV5703B, NCV5703C
TYPICAL CHARACTERISTICS
80
70
60
t
t
pd−on
pd−off
50
40
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
Figure 5. Propagation Delay vs. Temperature
20
15
14
13
12
15
10
5
t
fall
t
rise
11
10
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. Fault to Output Low Delay
Figure 7. Output Rise/Fall Time
8
7
8
7
6
6
5
4
3
2
5
4
3
2
1
0
1
0
−5
0
5
10
15
−5
0
5
10
V (V, V = 15 V, V = −8 V)
O
15
V
O
(V, V = 15 V, V = −8 V)
CC
EE
CC
EE
Figure 8. Output Source Current vs. Output
Voltage
Figure 9. Output Sink Current vs. Output
Voltage
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NCV5703A, NCV5703B, NCV5703C
TYPICAL CHARACTERISTICS
5.05
5.04
5.03
5.02
5.01
5.00
4.99
4.98
4.97
5.05
5.04
5.03
5.02
V
@ I
= 0 mA
REF
REF
5.01
5.00
4.99
4.98
4.97
V
REF
@ I
= 10 mA
60
REF
4.96
4.95
4.96
4.95
0
2
4
6
8
10
−40 −20
0
20
40
80
100 120
I
(mA)
TEMPERATURE (°C)
REF
Figure 10. VREF Voltage vs. Current
Figure 11. VREF Voltage vs. Temperature
260
6.5
6.4
250
240
6.3
6.2
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. DESAT Charge Current vs.
Temperature
Figure 13. DESAT Threshold Voltage vs.
Temperature
15
10
20
15
10
5
UVLO−OUT−OFF
UVLO−OUT−ON
5
0
0
−5
10
11
12
13
14
15
0
1
2
3
4
5
V
CC
, SUPPLY VOLTAGE (V)
V
IN
(V)
Figure 14. UVLO Threshold Voltages
Figure 15. VO vs. VIN at 255C
(VCC = 15 V, VEE = 0 V)
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NCV5703A, NCV5703B, NCV5703C
TYPICAL CHARACTERISTICS
1.0
2.5
2.0
0.5
1.5
1.0
0.5
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Fault Output, Sinking 15 mA
Figure 17. VCLAMP at 0.5 A (NCV5703A Only)
1.4
1.2
1.0
I
CC
0.8
0.6
0.4
I
EE
(NCV5703B Only)
0.2
0
0
20
40
60
80
100
FREQUENCY (kHz)
Figure 18. Supply Current vs. Switching
Frequency (VCC = 15 V, VEE = −10 V, 255C)
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NCV5703A, NCV5703B, NCV5703C
Applications and Operating Information
This section lists the details about key features and
operating guidelines for the NCV5703.
High Drive Current Capability
The NCV5703 driver family is equipped with many
features which facilitate a superior performance IGBT
driving circuit. Foremost amongst these features is the high
drive current capability. The drive current of an IGBT driver
is a function of the differential voltage on the output pin
(V −VOH/VO for source current, VOL/VO−V for sink
CC
EE
current) as shown in Figure 19. Figure 19 also indicates that
for a given VOH/VOL value, the drive current can be
increased by using higher V /V power supply). The
CC EE
drive current tends to drop off as the output voltage goes up
(for turn−on event) or goes down (for turn−off event). As
explained in many IGBT application notes, the most critical
phase of IGBT switching event is the Miller plateau region
where the gate voltage remains constant at a voltage
(typically in 9−11 V range depending on IGBT design and
the collector current), but the gate drive current is used to
Figure 19. Output Current vs. Output Voltage Drop
When driving larger IGBTs for higher current
applications, the drive current requirement is higher, hence
lower R is used. Larger IGBTs typically have high input
G
capacitance. On the other hand, if the NCV5703 is used to
drive smaller IGBT (lower input capacitance), the drive
charge/discharge the Miller capacitance (C ). By
current requirement is lower and a higher R is used. Thus,
GC
G
providing a high drive current in this region, a gate driver can
significantly reduce the duration of the phase and help
reducing the switching losses. The NCV5703 addresses this
requirement by providing and specifying a high drive
current in the Miller plateau region. Most other gate driver
ICs merely specify peak current at the start of switching –
which may be a high number, but not very relevant to the
application requirement. It must be remembered that other
considerations such as EMI, diode reverse recovery
performance, etc., may lead to a system level decision to
trade off the faster switching speed against low EMI and
reverse recovery. However, the use of NCV5703 does not
preclude this trade−off as the user can always tune the drive
current by employing external series gate resistor. Important
thing to remember is that by providing a high internal drive
current capability, the NCV5703 facilitates a wide range of
gate resistors. Another value of the high current at the Miller
plateau is that the initial switching transition phase is shorter
and more controlled. Finally, the high gate driver current
(which is facilitated by low impedance internal FETs),
ensures that even at high switching frequencies, the power
dissipation from the drive circuit is primarily in the external
series resistor and more easily manageable. Experimental
results have shown that the high current drive results in
for most typical applications, the driver load RC time
constant remains fairly constant. Caution must be exercised
when using the NCV5703 with a very low load RC time
constant. Such a load may trigger internal protection
circuitry within the driver and disable the device. Figure 20
shows the recommended minimum gate resistance as a
function of IGBT gate capacitance and gate drive trace
inductance.
Figure 20. Recommended Minimum Gate Resistance
as a Function of IGBT Gate Capacitance
reduced turn−on energy (E ) for the IGBT switching.
ON
www.onsemi.com
13
NCV5703A, NCV5703B, NCV5703C
Gate Voltage Range
controller to initiate a more orderly/sequenced shutdown. In
case the controller fails to do so, the driver output shutdown
The negative drive voltage for gate (with respect to GND,
or Emitter of the IGBT) is a robust way to ensure that the gate
voltage does not rise above the threshold voltage due to the
Miller effect. In systems where the negative power supply is
available, the VEE option offered by NCV5703B allows not
only a robust operation, but also a higher drive current for
turn−off transition. Adequate bypassing between VEE pin
and GND pin is essential if this option is used.
ensures IGBT protection after t
.
d1−OUT
The V range for the NCV5703 is quite wide and allows
CC
the user the flexibility to optimize the performance or use
available power supplies for convenience.
Under Voltage Lock Out (UVLO)
This feature ensures reliable switching of the IGBT
connected to the driver output. At the start of the driver’s
operation when V is applied to the driver, the output
CC
remains turned−off. This is regardless of the signals on V
IN
until the V
(V
V
reaches the UVLO Output Enabled
CC
UVLO−OUT−ON
UVLO−OUT−ON
) level. After the V
rises above the
CC
level, the driver is in normal operation. The
state of the output is controlled by signal at V .
IN
If the V
falls below the UVLO Output Disabled
CC
(V ) level during the normal operation of the
UVLO−OUT−OFF
driver, the Fault output is activated and the output is shut−down
(after a delay) and remains in this state. The driver output
does not start to react to the input signal on V until the V
IN
CC
Figure 21. UVLO Function and Limits
rises above the V
again. The waveform
UVLO−OUT−ON
showing the UVLO behavior of the driver is in Figure 21.
In an IGBT drive circuit, the drive voltage level is
Timing Delays and Impact on System Performance
The gate driver is ideally required to transmit the input
signal pulse to its output without any delay or distortion. In
the context of a high−power system where IGBTs are
typically used, relatively low switching frequency (in tens of
kHz) means that the delay through the driver itself may not
be as significant, but the matching of the delay between
different drivers in the same system as well as between
different edges has significant importance. With reference to
Figure 22(a), two input waveforms are shown. They are
typical complementary inputs for high−side (HS) and
low−side (LS) of a half−bridge switching configuration. The
dead−time between the two inputs ensures safe transition
between the two switches. However, once these inputs are
through the driver, there is potential for the actual gate
voltages for HS and LS to be quite different from the
intended input waveforms as shown in Figure 22(a). The end
result could be a loss of the intended dead−time and/or
pulse−width distortion. The pulse−width distortion can
create an imbalance that needs to be corrected, while the loss
of dead−time can eventually lead to cross−conduction of the
switches and additional power losses or damage to the
system.
important for drive circuit optimization. If V
UVLO−OUT−OFF
is too low, it will lead to IGBT being driven with insufficient
gate voltage. A quick review of IGBT characteristics can
reveal that driving IGBT with low voltage (in 10−12 V
range) can lead to a significant increase in conduction loss.
So, it is prudent to guarantee V
at a
UVLO−OUT−OFF
reasonable level (above 12 V), so that the IGBT is not forced
to operate at a non−optimum gate voltage. On the other hand,
having a very high drive voltage ends up increasing
switching losses without much corresponding reduction in
conduction loss. So, the V
value should not
UVLO−OUT−ON
be too high (generally, well below 15 V). These conditions
lead to a tight band for UVLO enable and disable voltages,
while guaranteeing a minimum hysteresis between the two
values to prevent hiccup mode operation. The NCV5703
meets these tight requirements and ensures smooth IGBT
operation. It ensures that a 15 V supply with 8% tolerance
will work without degrading IGBT performance, and
guarantees that a fault will be reported and the IGBT will be
turned off when the supply voltage drops below 12.2 V.
A UVLO event (V voltage going below V
)
CC
UVLO−OUT−OFF
also triggers activation of FLT output after a delay of t
.
d3−FLT
The NCV5703 driver is designed to address these timing
challenges by providing a very low pulse−width distortion
and excellent delay matching. As an example, the delay
This indicates to the controller that the driver has
encountered an issue and corrective action needs to be taken.
However, a nominal delay t
= 12 ms is introduced
d1−OUT
matching is guaranteed to t
= 25 ns while many
DISTORT2
between the initiation of the FLT output and actual turning
off of the output. This delay provides adequate time for the
of competing driver solutions can be >250 ns.
www.onsemi.com
14
NCV5703A, NCV5703B, NCV5703C
Figure 22(a). Timing Waveforms (Other Drivers)
Figure 22(b). NCV5703 Timing Waveforms
Active Miller Clamp Protection
An alternative way is to provide an additional path from
gate to GND with very low impedance. This is exactly what
Active Miller Clamp protection does. Additional trace from
the gate of the IGBT to the Clamp pin of the gate driver is
This feature (offered by NCV5703A) is a cost savvy
alternative to a negative gate voltage. The main requirement
is to hold the gate of the turned−off (for example low−side)
IGBT below the threshold voltage during the turn−on of the
opposite−side (in this example high−side) IGBT in the half
bridge. The turn−on of the high−side IGBT causes high dv/dt
transition on the collector of the turned−off low−side IGBT.
This high dv/dt then induces current (Miller current) through
introduced. After the V output has gone below the Active
O
Miler Clamp threshold V
the Clamp pin is shorted
MC−THR
to GND and thus prevents the voltage on the gate of the
IGBT to rise above the threshold voltage as shown in
Figure 24. The Clamp pin is disconnected from GND as
soon as the signal to turn on the IGBT arrives to the gate
driver input. The fact that the Clamp pin is engaged only
the C
capacitance (Miller capacitance) to the gate
GC
capacitance of the low−side IGBT as shown in Figure 23. If
the path from gate to GND has critical impedance (caused
after the gate voltage drops below the V
threshold
MC−THR
by R ) the Miller current could rise the gate voltage above
ensures that the function of this pin does not interfere with
G
the threshold level. As a consequence the low−side IGBT
could be turned on for a few tens or hundreds of
nanoseconds. This causes higher switching losses. One way
to avoid this situation is to use negative gate voltage, but this
requires second DC source for the negative gate voltage.
the normal turn−off switching performance that is user
controllable by choice of R .
G
www.onsemi.com
15
NCV5703A, NCV5703B, NCV5703C
Figure 23. Current Path without Miller Clamp
Figure 24. Current Path with Miller Clamp Protection
Protection
Desaturation Protection (DESAT)
At the turned−on output state of the driver, the current
This feature monitors the collector−emitter voltage of the
IGBT in the turned−on state. When the IGBT is fully turned
on, it operates in a saturation region. Its collector−emitter
voltage (called saturation voltage) is usually low, well below
3 V for most modern IGBTs. It could indicate an overcurrent
or similar stress event on the IGBT if the collector−emitter
voltage rises above the saturation voltage, after the IGBT is
fully turned on. Therefore the DESAT protection circuit
compares the collector−emitter voltage with a voltage level
I
from current source starts to flow to the
DESAT−CHG
blanking capacitor C
Appropriate value of this capacitor has to be selected to
ensure that the DESAT pin voltage does not rise above the
threshold level V
The blanking time is given by following expression.
According to this expression, a 47 pF C will provide
, connected to DESAT pin.
BLANK
before the IGBT fully turns on.
DESAT−THR
BLANK
a blanking time of (47p *6.5/0.25m =) 1.22 ms.
VDESAT−THR
IDESAT−CHG
t
BLANK + CBLANK @
V
to check if the IGBT didn’t leave the saturation
DESAT−THR
region. It will activate FLT output and shut down driver
output (thus turn−off the IGBT), if the saturation voltage
After the IGBT is fully turned−on, the I
flows
DESAT−CHG
through the DESAT pin to the series resistor R
through the high voltage diode and then through the
collector and IGBT to the emitter. Care must be taken to
and
S−DESAT
rises above the V . This protection works on
DESAT−THR
every turn−on phase of the IGBT switching period.
At the beginning of turning−on of the IGBT, the
collector−emitter voltage is much higher than the saturation
voltage level which is present after the IGBT is fully turned
on. It takes almost 1 ms between the start of the IGBT turn−on
and the moment when the collector−emitter voltage falls to
the saturation level. Therefore the comparison is delayed by
a configurable time period (blanking time) to prevent false
triggering of DESAT protection before the IGBT
collector−emitter voltage falls below the saturation level.
select the resistor R
value so that the sum of the
S−DESAT
saturation voltage, drop on the HV diode and drop on the
caused by current I flowing from
R
S−DESAT
DESAT−CHG
DESAT source current is smaller than the DESAT threshold
voltage. Following expression can be used:
V
DESAT−THR u
R
S−DESAT @ IDESAT−CHG ) VF_HV diode ) VCESAT_IGBT
Blanking time is set by the value of the capacitor C
The exact principle of operation of DESAT protection is
described with reference to Figure 25.
At the turned−off output state of the driver, the DESAT pin
is shorted to ground via the discharging transistor (Q ).
.
Important part for DESAT protection to work properly is
the high voltage diode. It must be rated for at least same
voltage as the low side IGBT. The safety margin is
application dependent.
The typical waveforms for IGBT overcurrent condition
are outlined in Figure 26.
BLANK
DIS
Therefore, the inverting input holds the comparator output
at low level.
www.onsemi.com
16
NCV5703A, NCV5703B, NCV5703C
Figure 25. Desaturation Protection Schematic
Figure 26. Desaturation Protection Waveforms
www.onsemi.com
17
NCV5703A, NCV5703B, NCV5703C
Input Signal
The input signal controls the gate driver output. Figure 27
shows the typical connection diagrams for isolated
applications where the input is coming through an
opto−coupler or a pulse transformer.
Figure 27. Opto−coupler or Pulse Transformer At Input
The relationship between gate driver input signal from a
pulse transformer (Figure 28) or opto−coupler (Figure 29)
and the output is defined by many time and voltage values.
The time values include output turn−on and turn−off delays
delay times are defined from 50% of input transition to first
10% of the output transition to eliminate the load
dependency. The input voltage parameters include input
high (V
) and low (V
) thresholds as well as the
IN−H1
IN−L1
(t
and t
), output rise and fall times (t and t )
input range for which no output change is initiated
(V ).
pd−on
pd−off
rise
fall
and minimum input pulse−width (t
). Note that the
on−min
IN−NC
V
IN-H1
V
IN-NC
V
IN
V
IN-L1
t
pd-on
t
fall
t
on-min
t
t
rise
pd-on
90%
10%
V
OUT
Figure 28. Input and Output Signal Parameters for Pulse Transformer
www.onsemi.com
18
NCV5703A, NCV5703B, NCV5703C
V
IN-H1
V
IN-NC
V
IN
V
t
IN-L1
t
t
t
fall
on-min
pd-on
t
rise
pd-on
V
OUT
90%
10%
Figure 29. Input and Output Signal Parameters for Opto−coupler
Use of VREF Pin
The NCV5703 provides an additional 5.0 V output
(VREF) that can serve multiple functions. This output is
capable of sourcing up to 10 mA current for functions such
as opto−coupler interface or external comparator interface.
The VREF pin should be bypassed with at least a 100 nF
capacitor (higher the better) irrespective of whether it is
being utilized for external functionality or not. VREF is
highly stable over temperature and line/load variations (see
characteristics curves for details)
Fault Output Pin
This pin provides the feedback to the controller about the
driver operation. The situations in which the FLT signal
becomes active (low value) are summarized in the Table 6.
Table 6. FLT LOGIC TRUTH TABLE
VIN
L
UVLO
Inactive
Inactive
Active
DESAT
Internal TSD
VOUT
FLT
Open drain
Open drain
L
Notes
Normal operation − Output Low
Normal operation − Output High
L
L
L
L
L
L
H
L
H
X
X
UVLO activated − FLT Low (t
), Output Low
-
d3 FLT
(t
+ t
)
-
d3 FLT
d1−OUT
H
X
Inactive
Inactive
H
X
L
L
L
L
L
DESAT activated (only when V is High) − Output
IN
Low (t
), FLT Low
d2_OUT
H
Internal Thermal Shutdown − FLT Low (t
), Out-
-
d3 FLT
put Low (t
+ t
)
-
d3 FLT
d1−OUT
Thermal Shutdown
The NCV5703 also offers thermal shutdown function that
is primarily meant to self−protect the driver in the event that
the internal temperature gets excessive. Once the
(12 ms), the output is pulled low and many of the internal
circuits are turned off. The 12 ms delay is meant to allow the
controller to perform an orderly shutdown sequence as
appropriate. Once the temperature goes below the second
threshold, the part becomes active again.
temperature crosses the T threshold, the FLT output is
SD
activated after a delay of t
. After a delay of t
d3-FLT
d1−OUT
www.onsemi.com
19
NCV5703A, NCV5703B, NCV5703C
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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