NCV5705BDR2G [ONSEMI]
IGBT Gate Drivers, High-Current, Stand-Alone;
| 型号： | NCV5705BDR2G |
| 厂家： | 
ONSEMI |
| 描述： | IGBT Gate Drivers, High-Current, Stand-Alone 栅 双极性晶体管 |
| 文件： | 总15页 (文件大小：659K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
High Current IGBT Gate
Drivers
8
1
SOIC−8 NB
CASE 751−07
NCV5705B, NCD5705B
The NCV/NCD5705B is a high−current, high−performance
stand−alone IGBT driver for high power automotive applications that
include PTC heaters, traction inverters, high voltage DC−DC and
other auxiliary subsystems. The device offers a cost−effective
solution by eliminating external output buffer. Device’s protection
features include accurate Under−voltage−lockout (UVLO),
desaturation protection (DESAT) and Active open−drain FAULT
output. The driver also features an accurate 5.0 V output. The driver is
designed to accommodate a wide voltage range of bias supplies
including unipolar and even bipolar voltages. NCV5705B is available
in 8−pin SOIC package.
MARKING DIAGRAM
8
NCx5705B
ALYW
G
NCx5705B
= Specific Device Code
x = D or V
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
• High Current Output (+4/−6 A) at IGBT Miller Plateau Voltages
• Low Output Impedance for Enhanced IGBT Driving
• Short Propagation Delay with Accurate Matching
• Direct Interface to Digital Isolator/Opto−coupler/Pulse Transformer
for Isolated Drive, Logic Compatibility for Non−isolated Drive
• DESAT Protection with Programmable Delay
• Tight UVLO Thresholds for Bias Flexibility
• Wide Bias Voltage Range
• This Device is Pb−Free, Halogen−Free and RoHS Compliant
• Negative Output Voltage for Enhanced IGBT Driving
PIN CONNECTIONS
1
2
3
4
8
7
6
5
VIN
VREF
FLT
VEE
GND
VO
DESAT
VCC
NCV5705B, NCD5705B
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
Typical Applications
• PTC Heaters
• Traction Inverters
• HV DC−DC
• OBC
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
March, 2022 − Rev. 3
NCV5705B/D
NCV5705B, NCD5705B
V
V
DESAT
REF
V
CC
V
CC
V
O
GND
IN
V
EE
V
EE
FLT
Figure 1. Simplified Application Schematics
Figure 2. Detailed Block Diagram NCV5705B
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2
NCV5705B, NCD5705B
V
EE
VIN
V
CC
GND
LDO
V
GND
VO
REF
FLT
LOGIC
UNIT
TSD
V
CC
GND
UVLO
V
CC
DESAT
DESAT
Figure 3. Simplified Block Diagram NCV5705B
Table 1. PIN FUNCTION DESCRIPTION
Pin Name
No.
I/O/x
Description
VIN
1
I
Input signal to control the output. In applications which require galvanic isola-
tion, VIN is generated at the opto output, the pulse transformer secondary or
the digital isolator output. VO (VOH/ VOL) signal is in phase with VIN. VIN is
internally clamped to GND and has a pull− down resistor of 1 M to ensure that
an output is low in the absence of an input signal. A minimum pulse−width is
required at VIN before VO (VOH/VOL) is activated.
VREF
FLT
2
3
O
O
5 V Reference generated within the driver is brought out to this pin for external
bypassing and for powering low bias circuits (such as digital isolators).
Fault open drain output (active low) that allows communication to the main
controller that the driver has encountered a fault condition and has deactivated
the output. Open drain allows easy setting of (inactive) high level and parallel
connection of multiple fault signals. Connect to 10k pull−up resistor recom-
mended. Truth Table is provided in the datasheet to indicate conditions under
which this signal is asserted. Capable of driving optos or digital isolators when
isolation is required.
DESAT
VCC
VO
4
5
6
7
8
I
x
Input for detecting the desaturation of IGBT due to a fault condition. A capacitor
connected to this pin allows a programmable blanking delay every ON cycle
before DESAT fault is processed, thus preventing false triggering.
Positive bias supply for the driver. The operating range for this pin is from
UVLO to the maximum. A good quality bypassing capacitor is required from
this pin to GND and should be placed close to the pins for best results.
O
x
Driver output that provides the appropriate drive voltage, source and sink cur-
rent to the IGBT gate. VO is actively pulled low during start−up and under
Fault conditions.
GND
VEE
This pin should connect to the IGBT Emitter with a short trace. All power pin
bypass capacitors should be referenced to this pin and kept at a short distance
from the pin.
x
A negative voltage with respect to GND can be applied to this pin and that will
allow VO to go to a negative voltage during OFF state. A good quality bypass-
ing capacitor is needed from VEE to GND. If a negative voltage is not applied
or available, this pin must be connected to GND.
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3
NCV5705B, NCD5705B
Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1)
Parameter
Symbol
− V
Minimum
Maximum
Unit
Differential Power Supply
V
0
36
V
CC
EE
(V
)
max
Positive Power Supply
V
−GND
−GND
−0.3
−18
22
V
V
CC
Negative Power Supply
Gate Output High
V
0.3
EE
(V ,V )−GND
O
V
V
+ 0.3
V
OH
CC
Gate Output Low
(V ,V )−GND
O
V − 0.3
EE
V
OL
Input Voltage
V
−GND
−0.3
−0.3
5.5
V
IN
DESAT Voltage
V
−GND
I−SINK
+ 0.3
20
V
DESAT
CC
FLT Current Sink
mA
mW
°C
°C
kV
V
Power Dissipation SO−8 package
Maximum Junction Temperature
Storage Temperature Range
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
Moisture Sensitivity Level
PD
TJ(max)
TSTG
700
150
−65 to 150
ESDHBM
ESDMM
MSL
4
200
1
−
Lead Temperature Soldering
TSLD
260
°C
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115).
Latchup Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78, 25°C.
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 3. THERMAL CHARACTERISTICS
Parameter
Symbol
Value
Unit
Thermal Characteristics, SOIC−8 (Note 4)
R JA
q
176
°C/W
Thermal Resistance, Junction−to−Air (Note 5)
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2
2
5. Values based on copper area of 100 mm (or 0.16 in ) of 1 oz copper thickness and FR4 PCB substrate.
Table 4. OPERATING RANGES (Note 6)
Parameter
Symbol
Min
Max
Unit
Differential Power Supply
30
V
V
− V (V
)
EE
max
CC
Positive Power Supply
Negative Power Supply
Input Voltage
VCC
VEE
VIN
ton
UVLO
−15
0
20
0
V
V
5
V
Input pulse width
40
ns
Ambient Temperature
TA
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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4
NCV5705B, NCD5705B
Table 5. ELECTRICAL CHARACTERISTICS V = 15 V, V = 0 V, Kelvin GND connected to V . For typical values T = 25°C,
CC
EE
EE
A
for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
LOGIC INPUT AND OUTPUT
Input Threshold Voltages
High−state (Logic 1) Required
Low−state (Logic 0) Required
No state change
Pulse−Width = 150 ns, V = 5 V
V
EN
Voltage applied to get output to go low
Voltage applied to get output to go high
Voltage applied without change in output state
VIN−H1
VIN−L1
VIN−NC
4.3
1.2
0.75
3.7
Input Current
High−state
Low−state
A
V
IN−H
V
IN−L
= 4.5 V
= 0.5 V
IIN−H
IIN−L
10
1
Input Pulse−Width
No Response at the Output
Guaranteed Response at the
Output
Voltage thresholds consistent with input specs
10
ns
ton−min1
ton−min2
30
Threshold Voltage
Low State
High State
1.0
CC
0.3
V
VFLT−L
VFLT−H
0.5
V
+
(I SINK = 15 mA)
-
External pull−up
DRIVE OUTPUT
Output Low State
I
I
I
= 200 mA, T = 25°C
VOL1
VOL2
VOL3
0.1
0.2
0.8
0.2
0.5
1.2
V
V
A
A
sink
sink
sink
A
= 200 mA, T = −40°C to 125°C
A
= 1.0 A, T = 25°C
A
Output High State
I
src
I
src
I
src
= 200 mA, T = 25°C
VOH1
VOH2
VOH3
14.5
14.2
13.8
14.8
14.7
14.1
A
= 200 mA, T = −40°C to 125°C
A
= 1.0 A, T = 25°C
A
Peak Driver Current, Sink
(Note 7)
R
V
V
= 0.1 , V = 15 V, V = −8 V
G CC EE
= 13 V
= 9 V (near Miller Plateau)
IPK−snk1
IPK−snk2
6.8
6.1
O
O
Peak Driver Current, Source
(Note 7)
R
V
V
= 0.1 , V = 15 V, V = −8 V
G
O
O
CC
EE
= −5 V
= 9 V (near Miller Plateau)
IPK−src1
IPK−src2
7.8
4.0
DYNAMIC CHARACTERISTICS
Turn−on Delay
(see timing diagram)
Negative input pulse width = 10 s
Positive input pulse width = 10 s
For input or output pulse width > 150 ns,
tpd−on
tpd−off
45
45
59
54
75
75
ns
ns
ns
Turn−off Delay
(see timing diagram)
Propagation Delay Distortion
(=tpd−on− tpd−off)
T = 25°C
T = −40°C to 125°C
A
−5
−25
5
15
25
A
tdistort1
tdistort2
tdistort −tot
Prop Delay Distortion be-
tween Parts (Note 7)
−30
0
30
15
ns
ns
ns
Rise Time (Note 7) (see tim-
ing diagram)
C
C
= 1.0 nF
= 1.0 nF
trise
tfall
9.2
7.9
load
load
Fall Time (Note 7) (see timing
diagram)
Delay from FLT under UVLO/
TSD to VO/VOL
td1−OUT
td2−OUT
10
12
µs
Delay from DESAT to VO/
VOL (Note 7)
220
ns
Delay from UVLO/TSD to FLT
(Note 7)
td3−FLT
7.3
µs
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NCV5705B, NCD5705B
Table 5. ELECTRICAL CHARACTERISTICS V = 15 V, V = 0 V, Kelvin GND connected to V . For typical values T = 25°C,
CC
EE
EE
A
for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
Parameter
DESAT PROTECTION
DESAT Threshold Voltage
Test Conditions
Symbol
Min
Typ
Max
Unit
VDESAT
−THR
6.0
6.35
0.24
30
7.0
V
Blanking Charge Current
IDESAT
−CHG
0.20
0.28
mA
mA
Blanking Discharge Current
IDESAT
−DIS
UVLO
UVLO Startup Voltage
VUVLO
7.5
6.5
8.0
7.0
1.0
8.5
7.5
1.2
V
V
V
−OUT−ON
UVLO Disable Voltage
UVLO Hysteresis
VUVLO
−OUT−OFF
VUVLO
−HYST
0.45
VREF
Voltage Reference
I
= 10 mA
VREF
IREF
4.85
100
5.00
5.15
20
V
REF
Reference Output Current
(Note 7)
mA
Recommended Capacitance
CVREF
nF
SUPPLY CURRENT
Current Drawn from V
V
= 15 V
ICC−SB
IEE−SB
0.9
1.5
mA
mA
CC
CC
Standby (No load on output, FLT, VREF)
= −10 V
Current Drawn from V
(NCV5705B ONLY)
−0.2
−0.14
V
EE
EE
Standby (No load on output, FLT, VREF)
THERMAL SHUTDOWN
Thermal Shutdown
TSD
TSH
188
33
°C
°C
Temperature (Note 7)
Thermal Shutdown Hysteresis
(Note 7)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Values based on design and/or characterization.
ORDERING INFORMATION
†
Device
Package
Shipping
NCD5705BDR2G
NCV5705BDR2G*
SOIC−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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6
NCV5705B, NCD5705B
APPLICATIONS AND OPERATING INFORMATION
This section lists the details about key features and
operating guidelines for the NCV5705B.
High Drive Current Capability
The NCV5705B driver is equipped with many features
which facilitate a superior performance IGBT driving
circuit. Foremost amongst these features is the high drive
current capability. The drive current of an IGBT driver is a
function of the differential voltage on the output pin
(VCC−VOH/VO for source current, VOL/VO−VEE for
sink current) as shown in Figure 4. Figure 4 also indicates
that for a given VOH/VOL value, the drive current can be
increased by using higher VCC/VEE power supply). The
drive current tends to drop off as the output voltage goes up
(for turn−on event) or goes down (for turn−off event). As
explained in many IGBT application notes, the most critical
phase of IGBT switching event is the Miller plateau region
where the gate voltage remains constant at a voltage
(typically in 9−11 V range depending on IGBT design and
the collector current), but the gate drive current is used to
Figure 4. Output Current vs. Output Voltage Drop
When driving larger IGBTs for higher current
applications, the drive current requirement is higher, hence
lower R is used. Larger IGBTs typically have high input
G
capacitance. On the other hand, if the NCV5705B is used to
drive smaller IGBT (lower input capacitance), the drive
current requirement is lower and a higher R is used. Thus,
G
charge/discharge the Miller capacitance (C ). By
GC
for most typical applications, the driver load RC time
constant remains fairly constant. Caution must be exercised
when using the NCV5705B with a very low load RC time
constant. Such a load may trigger internal protection
circuitry within the driver and disable the device. Figure 4
shows the recommended minimum gate resistance as a
function of IGBT gate capacitance and gate drive trace
inductance.
providing a high drive current in this region, a gate driver can
significantly reduce the duration of the phase and help
reducing the switching losses. The NCV5705B addresses
this requirement by providing and specifying a high drive
current in the Miller plateau region. Most other gate driver
ICs merely specify peak current at the start of switching –
which may be a high number, but not very relevant to the
application requirement. It must be remembered that other
considerations such as EMI, diode reverse recovery
performance, etc., may lead to a system level decision to
trade off the faster switching speed against low EMI and
reverse recovery. However, the use of NCV5705B does not
preclude this trade−off as the user can always tune the drive
current by employing external series gate resistor. Important
thing to remember is that by providing a high internal drive
current capability, the NCV5705B facilitates a wide range of
gate resistors. Another value of the high current at the Miller
plateau is that the initial switching transition phase is shorter
and more controlled. Finally, the high gate driver current
(which is facilitated by low impedance internal FETs),
ensures that even at high switching frequencies, the power
dissipation from the drive circuit is primarily in the external
series resistor and more easily manageable. Experimental
results have shown that the high current drive results in
Figure 5. Recommended Minimum Gate Resistance
as a Function of IGBT Gate Capacitance
reduced turn−on energy (E ) for the IGBT switching.
ON
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7
NCV5705B, NCD5705B
Gate Voltage Range
A
UVLO event (V
voltage going below
CC
The negative drive voltage for gate (with respect to GND,
or Emitter of the IGBT) is a robust way to ensure that the gate
voltage does not rise above the threshold voltage due to the
Miller effect. In systems where the negative power supply is
available, the VEE option offered by NCV5705B allows not
only a robust operation, but also a higher drive current for
turn−off transition. Adequate bypassing between VEE pin
and GND pin is essential if this option is used.
V
−OFF) also triggers activation of FLT
−
UVLO OUT
output after a delay of td3−FLT. This indicates to the
controller that the driver has encountered an issue and
corrective action needs to be taken. However, a nominal
delay td1−OUT = 12 µs is introduced between the initiation
of the FLT output and actual turning off of the output. This
delay provides adequate time for the controller to initiate a
more orderly/sequenced shutdown. In case the controller
fails to do so, the driver output shutdown ensures IGBT
The V
CC
range for the NCV5705B is quite wide and
allows the user the flexibility to optimize the performance or
use available power supplies for convenience.
protection after t
d1 OUT
.
−
Under Voltage Lock Out (UVLO)
This feature ensures reliable switching of the IGBT
connected to the driver output. At the start of the driver’s
operation when V
is applied to the driver, the output
CC
remains turned−off. This is regardless of the signals on V
IN
until the V
reaches the UVLO Output Enabled
CC
(V
) level. After the V
rises above the
level, the driver is in normal operation.
−
−
UVLO OUT ON
CC
V
−
−
UVLO OUT ON
The state of the output is controlled by signal at V
.
IN
If the V
falls below the UVLO Output Disabled
CC
(V
) level during the normal operation
−
−
UVLO OUT OFF
of the driver, the Fault output is activated and the output is
shut−down (after a delay) and remains in this state. The
driver output does not start to react to the input signal on VIN
Figure 6. UVLO Function and Limits
until the VCC rises above the V
UVLO OUT ON
again.
−
−
The waveform showing the UVLO behavior of the driver is
in Figure 6.
Figure 7. Timing Waveforms (Other Drivers)
Figure 8. NCV5705B Timing Waveforms
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8
NCV5705B, NCD5705B
Timing Delays and Impact on System Performance
turn−on and the moment when the collector−emitter
voltage falls to the saturation level. Therefore the
comparison is delayed by a configurable time period
(blanking time) to prevent false triggering of DESAT
protection before the IGBT collector−emitter voltage falls
below the saturation level. Blanking time is set by the value
of the capacitor CBLANK.
The exact principle of operation of DESAT protection is
described with reference to Figure 9.
At the turned−off output state of the driver, the DESAT
pin is shorted to ground via the discharging transistor
The gate driver is ideally required to transmit the input
signal pulse to its output without any delay or distortion. In
the context of a high−power system where IGBTs are
typically used, relatively low switching frequency (in tens of
kHz) means that the delay through the driver itself may not
be as significant, but the matching of the delay between
different drivers in the same system as well as between
different edges has significant importance. With reference to
Figure 7, two input waveforms are shown. They are typical
complementary inputs for high−side (HS) and low−side
(LS) of a half−bridge switching configuration. The
dead−time between the two inputs ensures safe transition
between the two switches. However, once these inputs are
through the driver, there is potential for the actual gate
voltages for HS and LS to be quite different from the
intended input waveforms as shown in Figure 8. The end
result could be a loss of the intended dead−time and/or
pulse−width distortion. The pulse−width distortion can
create an imbalance that needs to be corrected, while the loss
of dead−time can eventually lead to cross−conduction of
the switches and additional power losses or damage to the
system.
(Q
). Therefore, the inverting input holds the comparator
DIS
output at low level.
At the turned−on output state of the driver, the current
I
from current source starts to flow to the
−
DESAT CHG
blanking capacitor CBLANK, connected to DESAT pin.
Appropriate value of this capacitor has to be selected to
ensure that the DESAT pin voltage does not rise above the
threshold level V
DESAT THR
before the IGBT fully turns
−
on. The blanking time is given by following expression.
According to this expression, a 47 pF CBLANK will provide
a blanking time of (47p *6.5/0.25m =) 1.22 s.
VDESAT*THR
IDESAT*CHG
tBLANK + CBLANK
(eq. 1)
Desaturation Protection (DESAT)
This feature monitors the collector−emitter voltage of the
IGBT in the turned−on state. When the IGBT is fully turned
on, it operates in a saturation region. Its collector−emitter
voltage (called saturation voltage) is usually low, well below
3 V for most modern IGBTs. It could indicate an overcurrent
or similar stress event on the IGBT if the collector−emitter
voltage rises above the saturation voltage, after the IGBT is
fully turned on. Therefore the DESAT protection circuit
compares the collector−emitter voltage with a voltage level
After the IGBT is fully turned−on, the I
−
DESAT CHG
flows through the DESAT pin to the series resistor
RS−DESAT and through the high voltage diode and then
through the collector and IGBT to the emitter. Care must be
taken to select the resistor RS−DESAT value so that the sum
of the saturation voltage, drop on the HV diode and drop on
the R
caused by current I flowing
DESAT CHG
−
−
S DESAT
from DESAT source current is smaller than the DESAT
threshold voltage. Following expression can be used:
V
to check if the IGBT didn’t leave the
−
DESAT THR
VDESAT*THR
u
(eq. 2)
saturation region. It will activate FLT output and shut down
RS*DESAT IDESAT*CHG ) VF_HV_diode ) VCESAT_IGBT
driver output (thus turn−off the IGBT), if the saturation
voltage rises above the V
works on every turn−on phase of the IGBT switching
period.
At the beginning of turning−on of the IGBT, the
collector−emitter voltage is much higher than the saturation
voltage level which is present after the IGBT is fully turned
on. It takes almost 1 µs between the start of the IGBT
. This protection
Important part for DESAT protection to work properly is
the high voltage diode. It must be rated for at least same
voltage as the low side IGBT. The safety margin is
application dependent.
The typical waveforms for IGBT overcurrent condition
are outlined in Figure 10.
−
DESAT THR
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9
NCV5705B, NCD5705B
Figure 9. Desaturation Protection Schematic
Figure 10. Desaturation Protection Waveforms
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10
NCV5705B, NCD5705B
Input Signal
Figure 11. Opto−coupler or Pulse Transformer At Input
The input signal controls the gate driver output. Figure 11
shows the typical connection diagrams for isolated
applications where the input is coming through an
opto−coupler or a pulse transformer.
and t ) and minimum input pulse−width (ton−min).
fall
Note that the delay times are defined from 50% of input
transition to first 10% of the output transition to eliminate
the load dependency. The input voltage parameters include
The relationship between gate driver input signal from a
pulse transformer (Figure 12) or opto−coupler (Figure 13)
and the output is defined by many time and voltage values.
The time values include output turn−on and turn−off
input high (VIN−H1) and low (V
as the input range for which no output change is initiated
(VIN−NC).
) thresholds as well
−
IN L1
delays (t
pd on
and t
), output rise and fall times (t
rise
−
−
pd off
V
IN−H1
V
IN−NC
V
IN
V
IN−L1
t
fall
t
t
pd−on
on−min
t
t
pd−on
rise
90%
10%
V
OUT
Figure 12. Input and Output Signal Parameters for Pulse Transformer
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11
NCV5705B, NCD5705B
V
IN−H1
V
IN−NC
V
IN−L1
V
IN
t
t
t
fall
on−min
pd−on
t
rise
t
pd−on
90%
V
OUT
10%
Figure 13. Input and Output Signal Parameters for Opto−coupler
Use of VREF Pin
being utilized for external functionality or not. VREF is
highly stable over temperature and line/load variations
The NCV5705B provides an additional 5.0 V output
(VREF) that can serve multiple functions. This output is
capable of sourcing up to 10 mA current for functions such
as opto−coupler interface or external comparator interface.
The VREF pin should be bypassed with at least a 100 nF
capacitor (higher the better) irrespective of whether it is
Fault Output Pin
This pin provides the feedback to the controller about the
driver operation. The situations in which the signal becomes
active(low value) are summarized in the Table 6.
Table 6. FLT LOGIC TRUTH TABLE
VIN
L
UVLO
Inactive
Inactive
Active
DESAT
Internal TSD
VOUT
FLT
Open drain
Open drain
L
Notes
Normal operation − Output Low
Normal operation − Output High
L
L
L
L
L
L
H
L
H
X
X
UVLO activated − FLT Low (t -FLT), Output Low
d3
(td3-FLT + td1−OUT)
L
Inactive
Inactive
H
X
L
L
L
L
L
DESAT activated (only when V is low) − Output Low
IN
d2_OUT
(t
), FLT Low
X
H
Internal Thermal Shutdown − FLT Low (t -FLT ),
d3
Out−put Low (td3-FLT + td1−OUT)
Thermal Shutdown
(12 ms), the output is pulled low and many of the internal
circuits are turned off. The 12 ms delay is meant to allow the
controller to perform an orderly shutdown sequence as
appropriate. Once the temperature goes below the second
threshold, the part becomes active again.
The NCV5705B also offers thermal shutdown function
that is primarily meant to self−protect the driver in the event
that the internal temperature gets excessive. Once the
temperature crosses the T
threshold, the FLT output is
. After a delay of t
SD
activated after a delay of t
d3 FLT
-
−
d1 OUT
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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