NCV571MN12TBG [ONSEMI]
150 mA CMOS Low Iq Low Output Voltage Regulator; 150毫安CMOS低Iq低输出电压稳压器
| 型号： | NCV571MN12TBG |
| 厂家： | 
ONSEMI |
| 描述： | 150 mA CMOS Low Iq Low Output Voltage Regulator |
| 文件： | 总12页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP571, NCV571
150 mA CMOS Low Iq Low
Output Voltage Regulator
The NCP571 series of fixed output low dropout linear regulators are
designed for handheld communication equipment and portable battery
powered applications which require low quiescent current. The
NCP571 series features an ultra−low quiescent current of 4.0 mA.
Each device contains a voltage reference unit, an error amplifier, a
PMOS power transistor, resistors for setting output voltage, current
limit, and temperature limit protection circuits.
The NCP571 has been designed to be used with low cost ceramic
capacitors and requires a minimum output capacitor of 0.1 mF. The
device is housed in the TSOP−5 or DFN6 surface mount package.
Standard voltage versions are 0.8 V, 0.9 V, 1.0 V and 1.2 V.
http://onsemi.com
6
5
1
1
TSOP−5
DFN6
SN SUFFIX
CASE 483
MN SUFFIX
CASE 506BA
Features
• Low Quiescent Current of 4.0 mA Typical
• Maximum Operating Voltage of 12 V
• Low Output Voltage Option down to 0.8 V
• High Accuracy Output Voltage of 3.0%
• Industrial Temperature Range of −40°C to +85°C
MARKING DIAGRAMS
1
XXXAYWG
XX MG
G
G
(NCV571, T = −40°C to +125°C)
A
• NCV Prefix for Automotive and Other Applications Requiring Site
and Change Controls
• These are Pb−Free Devices
XXX = Specific Device Code
A
Y
W
M
G
= Assembly Location
= Year
= Work Week
= Date Code
Typical Applications
• Battery Powered Instruments
• Hand−Held Instruments
• Camcorders and Cameras
= Pb−Free Package
(Note: Microdot may be in either location)
Vin
Vout
1
5
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Driver w/
Current
Limit
Thermal
Shutdown
+
Enable
ON
3
OFF
GND
2
Figure 1. Representative Block Diagram
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
May, 2010 − Rev. 3
NCP571/D
NCP571, NCV571
PIN CONNECTIONS
TSOP−5 package
DFN6 package
V
1
2
V
1
5
V
6 V
in
in
out
out
GND
NC
2
3
5 NC
EP
4
Enable
Enable
GND
3
4
NC
(Top View)
(Top View)
PIN FUNCTION DESCRIPTION
DFN6
TSOP−5
Pin Name
Description
1
2
3
4
5
4
2
3
V
Regulated output voltage.
out
NC
No Internal Connection. It is recommended to connect this pin to GND potential.
Power supply ground.
GND
Enable
This input is used to place the device into low−power standby. When this input is
pulled low, the device is disabled. If this function is not used, Enable pin should be
connected to V .
in
5
6
−
1
−
NC
No Internal Connection. It is recommended to connect this pin to GND potential.
Positive power supply input voltage.
V
in
EP
EP
No Internal Connection. It is recommended to connect this pin to GND potential.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Input Voltage
V
in
0 to 12
Enable Voltage
V
EN
−0.3 to V + 0.3
V
in
Output Voltage
V
out
−0.3 to V + 0.3
V
in
Power Dissipation
P
Internally Limited
+150
W
°C
°C
D
Operating Junction Temperature
Operating Ambient Temperature
T
J
NCP571
NCV571
T
A
−40 to +85
−40 to +125
Storage Temperature
T
−55 to +150
2000
°C
V
stg
ESD Capability, Human Body Model (Note 1)
ESD Capability, Machine Mode (Note 1)
ESD
HBM
ESD
200
V
MM
ESD Capability, Charged Device Model (Note 1)
ESD
1000
V
CDM
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
ESD Charged Device Model tested per EIA/JES D22/C101, Field Induced Charge Model (Jedec Standard)
2. Latchup capability (85°C) $100 mA DC with trigger voltage.
THERMAL CHARACTERISTICS
Rating
Junction−to−Ambient
Symbol
Test Conditions
Typical Value
Unit
°C/W
°C/W
°C/W
°C/W
2
2
2
2
TSOP−5
TSOP−5
DFN6
R
1 oz Copper Thickness, 100 mm
1 oz Copper Thickness, 100 mm
1 oz Copper Thickness, 100 mm
1 oz Copper Thickness, 100 mm
250
68
q
JA
PSIJ−Lead 2
Y
J−L2
Junction−to−Ambient
PSIJ−Lead 2
R
190
84
q
JA
DFN6
Y
J−L2
NOTE: Single component mounted on an 80 x 80 x 1.5 mm FR4 PCB with stated copper head spreading area. Using the following
boundary conditions as stated in EIA/JESD 51−1, 2, 3, 7, 12.
http://onsemi.com
2
NCP571, NCV571
V
in
V
out
1
5
4
3
V
out
V
in
NC
EN
2
GND
C1
C2
0.1 mF
0.1 mF
GND
GND
Enable
Figure 2. Typical Application Schematic for TSOP−5 Package
http://onsemi.com
3
NCP571, NCV571
ELECTRICAL CHARACTERISTICS (V = V
+ 1.0 V, V = V , C = 1.0 mF, C = 1.0 mF, T = 25°C, unless otherwise
in
out(nom)
EN
in
in
out
A
noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage (TA = 25°C, Iout = 10 mA)
V
out
− 3%
0.776
0.873
0.970
1.164
+ 3%
0.824
0.927
1.030
1.236
V
0.8 V
0.9 V
1.0 V
1.2 V
0.8
0.9
1.0
1.2
Output Voltage (TA = −40°C to +85°C for NCP571 or TA = −40°C to
V
out
− 4%
+ 4%
V
+125°C for NCV571, I = 10 mA) (Note 5)
out
0.8 V
0.9 V
1.0 V
1.2 V
0.768
0.864
0.960
1.152
0.8
0.9
1.0
1.2
0.832
0.936
1.040
1.248
Line Regulation (Vin = V + 1.0 V to 12 V, Iout = 10 mA)
Reg
−
−
10
40
30
65
mV
mV
mA
out
line
Load Regulation (Iout = 10 mA to 150 mA, V = V + 2.0 V)
Reg
in
out
load
Output Current (V = (V at I = 100 mA) − 3%)
I
o(nom)
out
out
out
0.8 V (V = 3.0 V)
150
150
150
150
−
−
−
−
−
−
−
−
in
0.9 V (V = 3.0 V)
in
1.0 V (V = 3.0 V)
in
1.2 V (V = 3.0 V)
in
Dropout Voltage (I = 10 mA, Measured at V − 3.0%)
V −V
in out
mV
uA
out
out
0.8 V
0.9 V
1.0 V
1.2 V
−
−
−
−
730
650
550
350
850
750
650
450
Quiescent Current
(Enable Input = 0 V)
(Enable Input = V , I = 1.0 mA to 150 mA)
I
Q
−
−
0.1
4.0
1.0
8.0
in out
Output Voltage Temperature Coefficient
Enable Input Threshold Voltage
T
−
100
−
ppm/°C
c
V
V
th(en)
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
1.3
−
−
−
−
0.3
Output Short Circuit Current (V = 0 V) (Note 4)
I
mA
out
out(max)
0.8 V (V = 3.0 V)
160
160
160
160
260
260
260
260
600
600
600
600
in
0.9 V (V = 3.0 V)
in
1.0 V (V = 3.0 V)
in
1.2 V (V = 3.0 V)
in
3. Maximum package power dissipation limits must be observed.
T
J(max) * TA
PD
+
RqJA
4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
5. NCP571
NCV571
T
low
T
low
= −40°C
= −40°C
T
high
T
high
= +85°C
= +125°C.
http://onsemi.com
4
NCP571, NCV571
3.2
3.0
2.8
2.6
2.4
2.2
3.2
V
= 6 V
in
3.0
2.8
2.6
2.4
V
= 3 V
in
V
in
= 6 V
V
in
= 3 V
T = 25°C
A
T = 25°C
A
V
out
= 0.8 V
V
out
= 1.2 V
2.2
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 3. Ground Pin Current vs. Output
Current
Figure 4. Ground Pin Current vs. Output
Current
3.5
3.0
2.5
2.0
1.5
3.5
V
in
= 6 V
3.0
2.5
2.0
1.5
V
= 6 V
V
in
V
= 3 V
in
= 3 V
in
V
= 0.8 V
= 30 mA
out
V
= 1.2 V
= 30 mA
out
I
out
I
out
−40
−20
0
20
40
60
80
100
−40
−20
0
20
40
60
80 100
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 5. Ground Pin Current vs. Temperature
Figure 6. Ground Pin Current vs. Temperature
3
2.5
2
3.5
3
2.5
2
1.5
1
1.5
1
T = 25°C
T = 25°C
A
A
0.5
0
0.5
0
V
out
= 0.8 V
V
out
= 1.2 V
I
= 30 mA
I
= 30 mA
10
out
out
0
2
4
6
8
10
12
0
2
4
6
8
12
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 7. Ground Pin Current vs. Input Voltage
Figure 8. Ground Pin Current vs. Input Voltage
http://onsemi.com
5
NCP571, NCV571
1.0
0.8
0.6
0.4
0.2
0.0
1.4
T = 25°C
T = 25°C
A
A
1.2
1.0
0.8
0.6
0.4
0.2
0.0
I
= 70 mA
out
I
= 70 mA
out
I
= 10 mA
out
I
= 10 mA
out
I
= 150 mA
out
I
= 150 mA
out
0
2
4
6
8
10
12
0
2
4
6
8
10
12
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 9. Output Voltage vs. Input Voltage
Figure 10. Output Voltage vs. Input Voltage
Figure 11. Line Transient Response
Figure 12. Line Transient Response
Figure 13. Line Transient Response
Figure 14. Line Transient Response
http://onsemi.com
6
NCP571, NCV571
Figure 15. Load Transient Response
Figure 16. Load Transient Response
Figure 17. Enable Operation
Figure 18. Enable Operation
http://onsemi.com
7
NCP571, NCV571
APPLICATIONS INFORMATION
A typical application circuit for the NCP571 series is
shown in Figure 2.
without fear of instabilities. Larger values improve noise
rejection and load regulation transient response.
Input Decoupling (C1)
Enable Operation
A 0.1 mF capacitor either ceramic or tantalum is
recommended and should be connected close to the NCP571
package. Higher values and lower ESR will improve the
overall line transient response.
The enable pin will turn on or off the regulator. These
limits of threshold are covered in the electrical specification
section of this data sheet. If the enable is not used then the
pin should be connected to V . It is not recommended to
in
leave this pin on air. In case the voltage of Enable signal is
higher then Input voltage of NCP571 device it is necessary
add an resistor divider in order to keep voltage at Enable pin
bellow Input voltage. A single gate device of VHC family
could be used for this logic level translation. The NL17SZ06
device could be chosen for non inverting open−drain buffer
as shown in Figure 19. Other possibility is using NL17SZ16
device as shown in Figure 20. More information is
mentioned in Application Note AND8101/D.
Output Decoupling (C2)
The NCP571 is a stable Regulator and does not require
any specific Equivalent Series Resistance (ESR) or a
minimum output current. Capacitors exhibiting ESRs
ranging from a few mW up to 3.0 W can thus safely be used.
The minimum decoupling value is 0.1 mF and can be
augmented to fulfill stringent load transient requirements.
The regulator accepts ceramic chip capacitors as well as
tantalum devices. Larger output capacitors can be used
NCP571
V
out
Vin
V
in
V
out
NC
GND
C1
C2
Enable
0.1 mF
0.1 mF
GND
GND
3.3 V
3.3 V
0 V
Enable
NL17SZ06
Figure 19.
http://onsemi.com
8
NCP571, NCV571
NCP571
V
2.7 V
Vin
out
V
in
V
out
NC
GND
C2
Enable
C1
0.1 mF
0.1 mF
GND
GND
2.7 V
3.3 V
0 V
0 V
Enable
NL17SZ16
Figure 20.
Hints
conductivity through the PCB, the junction temperature will
be relatively low with high power dissipation applications.
The maximum dissipation the package can handle is given
by:
Please be sure the V and GND lines are sufficiently wide.
in
When the impedance of these lines is high, there is a chance
to pick up noise or cause the regulator to malfunction.
Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads as short as
possible.
T
J(max) * TA
PD
+
RqJA
If junction temperature is not allowed above the
maximum 125°C, then the NCP571 can dissipate up to
400 mW @ 25°C.
The power dissipated by the NCP571 can be calculated
from the following equation:
Thermal
As power across the NCP571 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and also the ambient
temperature effect the rate of temperature rise for the part.
This is stating that when the NCP571 has good thermal
ǒ Ǔ
tot + Vin(max) IGND ) Iout * Vout * Iout
P
If a 150 mA output current is needed then the ground
current from the data sheet is 4.0 mA.
http://onsemi.com
9
NCP571, NCV571
ORDERING INFORMATION
Nominal
Output Voltage
†
Device
Marking
Package
Shipping
NCP571SN08T1G
0.8
0.9
1.0
1.2
0.8
0.9
1.0
1.2
0.8
0.9
1.0
1.2
0.8
0.9
1.0
1.2
N6A
TSOP−5
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
(Pb−Free)
NCP571SN09T1G
NCP571SN10T1G
NCP571SN12T1G
NCV571SN08T1G
NCV571SN09T1G
NCV571SN10T1G
NCV571SN12T1G
NCP571MN08TBG
NCP571MN09TBG
NCP571MN10TBG
NCP571MN12TBG
NCV571MN08TBG
NCV571MN09TBG
NCV571MN10TBG
NCV571MN12TBG
N6E
N6C
N6D
N6F
N6G
N6H
N6J
AC
TSOP−5
(Pb−Free)
TSOP−5
(Pb−Free)
TSOP−5
(Pb−Free)
TSOP−5
(Pb−Free)
TSOP−5
(Pb−Free)
TSOP−5
(Pb−Free)
TSOP−5
(Pb−Free)
DFN6
(Pb−Free)
AD
DFN6
(Pb−Free)
AE
DFN6
(Pb−Free)
AA
DFN6
(Pb−Free)
AF
DFN6
(Pb−Free)
AG
DFN6
(Pb−Free)
AH
DFN6
(Pb−Free)
AJ
DFN6
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
10
NCP571, NCV571
PACKAGE DIMENSIONS
TSOP−5
(SOT23−5, SC59−5)
SN SUFFIX
CASE 483−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
C
D
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
0.90
1.10
0.50
C
0.25
SEATING
PLANE
0.05
G
H
J
K
L
M
S
0.95 BSC
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
10
3.00
T
_
_
SOLDERING FOOTPRINT*
2.50
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
NCP571, NCV571
PACKAGE DIMENSIONS
DFN6, 2x2.2, 0.65P
CASE 506BA−01
ISSUE A
NOTES:
A
B
D
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.20 mm FROM TERMINAL.
L1
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
0.30
2X
A
0.10
C
A3
EXPOSED Cu
MOLD CMPD
TOP VIEW
b
D
0.20
2.00 BSC
2X
D2 1.10
1.30
0.10
C
C
E
2.20 BSC
E2 0.70
0.90
A
A1
e
K
L
0.65 BSC
0.20
0.25
−−−
0.35
0.10
DETAIL B
DETAIL B
0.10
0.08
ALTERNATE
L1 0.00
CONSTRUCTIONS
7X
SOLDERING FOOTPRINT*
C
SIDE VIEW
A1
SEATING
PLANE
6X
0.58
C
1.36
PACKAGE
OUTLINE
D2
DETAIL A
6X L
e
6X
L1
3
1
2.50
0.96
E2
1
6
4
K
0.65
6X
0.35
6X b
PITCH
0.10
0.05
C
C
A B
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP571/D
相关型号：
©2020 ICPDF网 联系我们和版权申明