NCV6323FELMTW18TBG [ONSEMI]
Automotive, Buck converter, Synchronous, PWM, Fixed Output Voltage DC to DC converter, up to 1.6 A DC, Wettable flank DFN8, 2x2 mm (0.8 mm thickness), 0.5 mm pitch package;
| 型号： | NCV6323FELMTW18TBG |
| 厂家： | 
ONSEMI |
| 描述： | Automotive, Buck converter, Synchronous, PWM, Fixed Output Voltage DC to DC converter, up to 1.6 A DC, Wettable flank DFN8, 2x2 mm (0.8 mm thickness), 0.5 mm pitch package |
| 文件： | 总34页 (文件大小：8356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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onsemi andꢀꢀꢀꢀꢀꢀꢀand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
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3 MHz, 1.6 A, PWM
Synchronous Buck
Converter
High Efficiency, PWM Only, Low Ripple,
Fixed Output Voltage
NCV6323F-xx
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NCV6323F is a synchronous Buck converter optimized to supply
different sub−systems from a pre−regulator supply rail in the 2.8 V to
5.5 V range. The device is able to deliver up to 1.6 A DC (85°C
ambient temperature) on a fixed output voltage. Operation with
3 MHz switching frequency allows employing small size inductor and
capacitors. Technology and internal structure allows the IC to operate
from a wide input voltage range. Synchronous rectification offers
improved system efficiency and integrated feedback network allows
very simple and straightforward implementation to power supply
designers with only a few components to select.
1
WDFNW8 2x2, 0.5P
CASE 511CL
MARKING DIAGRAM
1
XXMG
The NCV6323F is housed in in a space saving Wettable flank
DFN8, 2x2 mm (0.8 mm thickness), 0.5 mm pitch package.
G
Features
XX = Specific Device Code
M
= Date Code
= Pb−Free Package
• 2.8 V to 5.5 V Input Voltage Range
• Fixed Output Voltage
G
(Note: Microdot may be in either location)
• Up to 1.6 A DC Output Current (85°C Ambient Temperature)
• Up to 1.2 A DC Output Current (105°C Ambient Temperature)
• 3 MHz Switching Frequency
PIN ASSIGNMENT
1
2
3
4
8
7
6
5
• Synchronous Rectification
PGND
SW
PVIN
AVIN
PG
• Soft Start / Over Current Protection
• Thermal Shutdown Protection
9
• Output Active Discharge (Disabled)
• Enable Input / Power Good (PG) Option
• WDFNW8, 2x2 mm, 0.5 mm Pitch Package
• Maximum 0.8 mm Thickness
EPAD
AGND
FB
EN
(Package Top View)
8−pin, 2x2 mm, 0.5mm Pitch
• AEC−Q100 Qualified and PPAP Capable
• These are Pb−Free Devices
Typical Applications
ORDERING INFORMATION
See detailed ordering and shipping information on page 31 of
this data sheet.
• Automotive Advanced Driver−Assistance System (ADAS)
♦ Front Camera – Rear View Camera
♦ Surround View
♦ Blind Spot Monitoring
• Automotive Telematics Clusters − Camera
• Automotive Space−Optimized Systems
• Point Of Load
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
June, 2021 − Rev. 2
NCV6323F/D
NCV6323F−xx
NCV6323F
Supply Input
AVIN
Supply Input
PVIN
Core
AGND
10 mF
DCDC
2 A
Thermal
Protection
Output Voltage
SW
1.0 mH
Driver
10 mF
EN
PG
Enable Control
Input
PGND
FB
Enabling
Output
Monitoring
Power Good
DCDC
3.0 MHz
Controller
Error Amp
Figure 1. Application Schematic
FUNCTIONAL BLOCK DIAGRAM
VIN
L
1m H
PVIN (8)
SW (2)
VOU T
CIN
10 mF
COU T
10 mF
(*) CANA Optional
AVIN (7)
CANA (*)
UVLO / BIASING /
INTERNAL POWER
SUPPLY
1 mF
PWM
CO NTROL
RPG
PGND (1)
FB (4)
EN (5)
PG (6)
E N
−
ERROR
AMP
LOGIC CONTROL
CURRENT LIMIT
POWER
GOOD
+
THERMAL
SHUTDOWN
REFERENCE
VOLTAGES
INTEGRATED
COMPENSATION
&
FB NETWORK
AGND (3)
THERMAL PAD
AGND
PGND
Figure 2. Functional Block Diagram
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2
NCV6323F−xx
PIN OUT DESCRIPTION
1
2
3
4
8
7
6
5
PGND
SW
PVIN
AVIN
PG
9
EPAD
AGND
FB
EN
Figure 3. Pin Out (Top View)
PIN FUNCTION DESCRIPTION
Pin No.
Name
Type
Description
1
PGND
Power Ground
Switch Ground. This pin is the power ground and carries the high switching current. High
quality ground must be provided to prevent noise spikes. To avoid high−density current flow
in a limited PCB track, a local ground plane that connects all PGND terminals together is
recommended. Analog and power grounds should only be connected together in one location
with a trace.
2
SW
Power Output
Switch Node. This pin supplies drive power to the inductor. Typical application uses 1.0 mH
inductor; refer to application section for more information.
This pin must be connected with short large PCB connections.
3
4
AGND
FB
Analog Ground Analog Ground. Analog and digital modules ground. Must be connected to the system ground.
Analog Input
Feedback Voltage from the buck converter output. This is the input for the internal regulation
loop. Connect this pin directly to the output voltage rail, preferably as close as possible to
positive terminal of the output capacitor.
It is recommended to follow as much as possible PCB layout recommendation in the
application section to avoid noise on this input.
5
6
EN
PG
Digital Input
Open Drain
Enable Input. High level at this pin enables the device. Low level at this pin disables the device.
Power Good. It is open drain output. Low level at this pin indicates the device is out of
regulation, while high impedance at this pin indicates the device output voltage is within
expected range.
If not used this pin can be left unconnected.
7
8
AVIN
PVIN
Analog Input
Analog Input
Analog Supply. This pin is the device analog and digital supply. Can be connected directly to
the V plane with an optional 1 mF or 4.7 mF ceramic capacitor
IN
Power Supply. This pin is the power supply of the device. A 10 mF or larger ceramic capacitor
must bypass this input to the ground. This capacitor should be placed as close as possible to
pin.
This pin must be connected with short large PCB connections.
9
EPAD
Analog Ground Exposed Thermal Pad. Must be soldered to system Ground plane to achieve power dissipation
performances. This pin is internally connected to AGND
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3
NCV6323F−xx
MAXIMUM RATINGS
Symbol
Parameter
Min
− 0.3
− 0.3
− 0.3
−0.3
−
Typ
Max
6.0
6.0
7.5
Unit
V
V
Analog Pins DC Non Switching: AVIN, FB (Note 1)
Power Pin DC Non Switching: PVIN, SW (Note 1)
Between PVIN−PGND Pins, Transient 3 ns – 3 MHz (Note 1)
Digital Pins Voltage: EN, PG
−
A−DC
V
P−DC
−
V
V
−
V
P−TR
V
−
V
A−DC
V
DG
HBM
CDM
Human Body Model (HBM) ESD Rating (Note 2)
Charged Device Model (CDM) ESD Rating (Note 2)
Latch Up Current (Note 3)
−
−
2000
V
−
500
−
V
I
LU
−
100
−
mA
°C
°C
−
T
STG
Storage Temperature Range
− 55
− 40
−
150
TSD
−
T
JMAX
Junction Temperature Range
−
MSL
Moisture Sensitivity (Note 4)
Level1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22−A114.
Charged Device Model (CDM) 500 V per JEDEC standard: JESD22−C101 Class IV.
3. Latch up Current per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.8
Typ
−
Max
5.5
Unit
V
AV
PV
Analog Input Supply
Power Input Supply
INR
INR
2.8
−
5.5
V
T
Operating Junction Temperature Range (Note 6)
Inductor for DC to DC Converter (Note 5)
− 40
0.67
6.4
25
1.0
10
+125
1.3
°C
mH
mF
J
L
OUT
C
Output Capacitor for DC to DC Converter NCV6323FxL Version
(Note 5, 7)
100
OUT
Output Capacitor for DC to DC Converter NCV6323FxH Version
(Note 5, 7)
50
150
250
C
C
Optional Input Capacitor for Analog Supply (Note 5)
Input Capacitor for Power Supply (Note 5)
0.47
4.7
1.0
10
−
−
mF
mF
AVIN
PVIN
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Including de−ratings (Refer to the Application Information section of this document for further details)
6. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
7. NCV632F compensation network is integrated. Special care should be taken with the capacitive load (refer to the application information)
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4
NCV6323F−xx
THERMAL INFORMATION
Symbol
JEDEC JESD51−3
(Calculated)
Demo Board
(Measured)
Parameter
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
q
Thermal Resistance Junction to Case Top (Note 8)
135
43
121
−
−
JCTOP
JCBOT
q
Thermal Resistance Junction to Case Bottom (Exposed Pad) (Note 9)
Thermal Resistance Junction to Ambient. (Note 10)
−
q
40
15
20
JA
Y
CTOP
Thermal Characterization Parameter Junction to Case Top (Note 11)
Y
JB
Thermal Characterization Parameter Junction to Board.
Measured on the AGND Footprint (Note 11)
−
CC
Current Capability (T ≤ 105°) (Note 12)
−
−
1.2
1.6
A
A
105
A
CC
Current Capability (T ≤ 85°) (Note 12)
85
A
8. Calculated with infinite heatsink affixed to case top without any board present
9. Calculated with infinite heatsink affixed to case bottom without any board present.
10.Rq is dependent on the PCB heat dissipation. Refer to AND8215/D (AND8215−D.PDF)
JA
11. The thermal characterization parameters are measured on the Demo Board
12.The current capability (CC) is dependent on input voltage, PCB stack up and layout, as well as the external components selected. Filled with
AV = PV = 5.0 V V = 1.8 V
IN
IN
OUT
ELECTRICAL CHARACTERISTICS (Refer to the Application Information section of this data sheet for more details.
Min and Max Limits apply for T = −40°C to +125°C, A = P = 3.3 V (10, 11, 12, 18 Versions) or 5.0 V (33 Versions), L = 1 mH, C
=
=
J
VIN
VIN
IN
C
= 10 mF and default configuration, unless otherwise specified.
OUT
Typical values are referenced to T = + 25°C, A
= P = 3.3 V (10, 11, 12, 18 Versions) or 5.0 V (33 Versions), L = 1 mH, C = C
VIN IN OUT
J
VIN
10 mF and default configuration, unless otherwise specified.)
Symbol Parameter
SUPPLY VOLTAGE AND CURRENT (APPLIES TO A
Min
Typ
Max
Unit
/ P
VIN
PIN)
VIN
V
IN
Input Voltage Range (Note 13)
2.8 or
−
5.5
V
V
OUT
+
0.5 V
I
V
Quiescent Supply Current
−
−
−
5.7
7.8
1
9
12
6
mA
mA
mA
Q
IN
· No Load
· V ≤ 1.8 V
OUT
I
V
IN
Quiescent Supply Current
Q33
· No Load
· V > 1.8 V
OUT
I
V
IN
Shutdown Current
SD
· EN Pin LOW
· A = P = 5.5 V
VIN
VIN
OUTPUT VOLTAGE
DV
Output Voltage DC Error − NCV6323F−x
−2
−
+2
%
OUT
· V = 2.8 V (10, 11, 12, 18 versions) or V
+ 0.5 V (33 version) ≤ V ≤ 5.5 V
IN
IN
OUT
· 0 mA ≤ I
≤ 1 A (Note 14)
OUT
V
V
V
V
V
Output Voltage NCV6323F−18
· V = 3.3 V, I = 200 mA (Note 14)
1.773
1.182
1.083
0.985
3.25
−
1.8
1.2
1.1
1.0
3.3
0.5
1.827
1.218
1.117
1.015
3.35
−
V
V
OUT18_200mA
OUT12_200mA
OUT11_200mA
OUT10_200mA
OUT33_200mA
IN
OUT
Output Voltage NCV6323F−12
· V = 3.3 V, I = 200 mA (Note 14)
IN
OUT
Output Voltage NCV6323F−11
· V = 3.3 V, I = 200 mA (Note 14)
V
IN
OUT
Output Voltage NCV6323F−10
· V = 3.3 V, I = 200 mA (Note 14)
V
IN
OUT
Output Voltage NCV6323F−33
· V = 5.0 V, I = 200 mA (Note 14)
V
IN
OUT
V
Output Voltage in Load Regulation
· V = 3.3 V (10, 11, 12, 18 Versions) or 5.0 V (33 Version)
%/A
OUT_LOAD
IN
· V = V
FB
OUT
· I
OUT
from 200 mA to I
OUT_MAX
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5
NCV6323F−xx
ELECTRICAL CHARACTERISTICS (Refer to the Application Information section of this data sheet for more details.
Min and Max Limits apply for T = −40°C to +125°C, A
= P
= 3.3 V (10, 11, 12, 18 Versions) or 5.0 V (33 Versions), L = 1 mH, C
=
=
J
VIN
VIN
IN
C
= 10 mF and default configuration, unless otherwise specified.
OUT
Typical values are referenced to T = + 25°C, A
= P = 3.3 V (10, 11, 12, 18 Versions) or 5.0 V (33 Versions), L = 1 mH, C = C
VIN IN OUT
J
VIN
10 mF and default configuration, unless otherwise specified.) (continued)
Symbol
Parameter
Min
Typ
Max
Unit
OUTPUT VOLTAGE
V
Output Voltage in Line Regulation
· I = 200 mA,
−
0
−
%
OUT_LINE
OUT
· V = V
· V from V
IN
FB
OUT
2.8 V (10, 11, 12, 18 Versions) or V
+ 0.5 V (33 Version)
IN_MIN
OUT
to 5.5 V
D
Duty Cycle
−
−
100
%
MAX
OUTPUT CURRENT
I
DC Output Current Capability
· T = 105°C (Note 15, 16)
A
1.2
1.6
−
−
−
−
A
A
OUT_MAX105
I
DC Output Current Capability
OUT_MAX85
· T = 85°C (Note 15, 16)
A
I
Output Peak Current Limit – High Side Switch (P−MOS) (Note 18)
Output Peak Current Limit – Low Side Switch (N−MOS) (Note 17, 18)
2.3
−
2.8
3.3
−
A
A
LIM_P
I
−0.8
LIM_N
VOLTAGE MONITOR
V
V
IN
V
IN
V
IN
UVLO Falling Threshold
UVLO Rising Threshold
UVLO Hysteresis
−
−
−
−
2.62
2.8
V
V
INUVLO_FALL
INUVLO_RISE
V
V
INHYS
60
150
250
mV
· UVLO Released for V = V
+ V
INHYS
IN
INUVLO_FALL
V
Power Good Low Threshold
87
0
90
92.5
5
%
%
PGL
· V
OUT
drops until Threshold (Percentage of FB Voltage)
V
Power Good Hysteresis
· V Rises up to the Threshold (Percentage of Power Good Low (V
2.5
PGHYS
)
PLG
OUT
Threshold)
TD
Power Good High Delay at Start Up
· From EN Rising Edge to PG L to H Transition
−
−
−
1.1
4
−
−
−
ms
ms
ms
PGH1
TD
Power Good Low Delay at Shut Down
· From EN Falling Edge to PG Going Low
PGL1
TD
Power Good High Delay in Regulation
11
PGH
· From V Going Higher than 95% Nominal Level to PG Going High. Does
FB
Not Apply to First Start Up.
TD
Power Good Low Delay in Regulation
−
−
−
8
−
−
−
ms
V
PGL
· From V Going Lower than 90% Nominal Level to PG Going Low.
FB
V
PG_L
Power Good Pin Low Voltage
· Voltage at PG Pin with 5 mA Sink Current
0.3
100
I
Power Good Pin Leakage Current
nA
PG_LK
· 3.3 V at PG Pin when Power Good Valid
INTEGRATED MOSFET
R
High−Side MOSFET ON Resistance
· V = 3.3 V (10, 11, 12, 18 Versions) (Note 19)
IN
120
90
170
135
250
200
mW
mW
ON_HSP3
R
High−Side MOSFET ON Resistance
ON_HSP5
· V = 5.0 V
IN
R
R
Low−Side MOSFET ON Resistance
· V = 3.3 V (10, 11, 12, 18 Versions) (Note 19)
IN
60
60
115
95
180
150
mW
mW
ON_LSN3
ON_LSN5
Low−Side MOSFET ON Resistance
· V = 5.0 V
IN
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6
NCV6323F−xx
ELECTRICAL CHARACTERISTICS (Refer to the Application Information section of this data sheet for more details.
Min and Max Limits apply for T = −40°C to +125°C, A
= P
= 3.3 V (10, 11, 12, 18 Versions) or 5.0 V (33 Versions), L = 1 mH, C
=
=
J
VIN
VIN
IN
C
= 10 mF and default configuration, unless otherwise specified.
OUT
Typical values are referenced to T = + 25°C, A
= P = 3.3 V (10, 11, 12, 18 Versions) or 5.0 V (33 Versions), L = 1 mH, C = C
VIN IN OUT
J
VIN
10 mF and default configuration, unless otherwise specified.) (continued)
Symbol
Parameter
Min
Typ
Max
Unit
SWITCHING FREQUENCY
F
SW
Normal Operation Frequency
2.7
3.0
3.3
MHz
START UP
T
Start Up Time: Applies to NCV6323FE−xx Version
· Time from EN to 90% of Output Voltage Target
0.3
0.2
0.51
0.42
0.75
0.68
ms
ms
START_E
T
SS_E
Soft Start time: Applies to NCV6323FE−xx Version
· Time from 50 mV to 90% of Output Voltage Target
CONTROL LOGIC
V
EN Input High Voltage
1.1
−
−
−
−
0.4
1
V
V
EN_H
V
EN Input Low Voltage
EN_L
I
EN Input Bias Current
−
0.1
4
mA
ms
EN_BIAS
T
Digital Input EN Filter: Rising and Falling (Note 20)
−
8
ENFTR
MISCELLANEOUS
R
Internal Output Discharge Resistance
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
390
−
490
150
25
600
−
W
DIS
T
°C
°C
SD
SD_HYST
T
−
−
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
13.Operation above 5.5 V input voltage for extended period of time may affect device reliability
14.V ≥ V
+ 0.5 V or 2.8 V
IN
OUT
15.Junction temperature must be maintained below 125°C. Output load current capability depends on the application thermal capability.
16.Characterized and not tested in Production
17.Limit for reverse current from SW to GND
18.The Output Peak Current Limit does not operate when V
< 300 mA
OUT
19.Maximum values apply for T = 125°C
J
20.Covered by Scan
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NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS
Figure 4. Shutdown Current vs. Input Voltage
Figure 5. Quiescent Current vs. Input Voltage
(EN = High, VOUT = 1.0 V, No Load)
(EN = Low, No Load)
Figure 6. Quiescent Current vs. Input Voltage
(EN = High, VOUT = 1.1 V, No Load)
Figure 7. Quiescent Current vs. Input Voltage
(EN = High, VOUT = 1.2 V, No Load)
Figure 8. Quiescent Current vs. Input Voltage
(EN = High, VOUT = 1.8 V, No Load)
Figure 9. Quiescent Current vs. Input Voltage
(EN = High, VOUT = 3.3 V, No Load)
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NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
Figure 10. Quiescent Current vs. Temperature
(EN = High, VOUT = 1.8 V, No Load)
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NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
Figure 11. Efficiency vs. Output Current and Input
Figure 12. Efficiency vs. Output Current and Temperature
Voltage (VOUT = 1.0 V, TA = 255C, L = FDSD0420−H−1R0M) at VIN = 3.3 V (VOUT = 1.0 V, L = FDSD0420−H−1R0M)
Figure 13. Efficiency vs. Output Current and Input
Voltage (VOUT = 1.1 V, TA = 255C, L = FDSD0420−H−1R0M)
Figure 14. Efficiency vs. Output Current and Temperature
at VIN = 3.3 V (VOUT = 1.1 V, L = FDSD0420−H−1R0M)
Figure 15. Efficiency vs. Output Current and Input
Figure 16. Efficiency vs. Output Current and Input Voltage
Voltage (VOUT = 1.2 V, TA = 255C, L = FDSD0420−H−1R0M)
(VOUT = 1.2 V, TA = 255C, L = FDSD0420−H−1R0M)
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NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
Figure 17. Efficiency vs. Output Current and Input
Voltage (VOUT = 1.8 V, TA = 255C, L = FDSD0420−H−1R0M)
Figure 18. Efficiency vs. Output Current and Temperature
at VIN = 3.3 V (VOUT = 1.8 V, L = FDSD0420−H−1R0M)
Figure 19. Efficiency vs. Output Current and Input
Voltage (VOUT = 3.3 V, TA = 255C, L = FDSD0420−H−1R0M)
Figure 20. Efficiency vs. Output Current and Temperature
at VIN = 5.0 V (VOUT = 3.3 V, L = FDSD0420−H−1R0M)
Figure 21. Load Regulation (VIN = 5.0 V, VOUT = 1.0 V)
Figure 22. Load Regulation (VIN = 3.3 V, VOUT = 1.0 V)
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11
NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
Figure 23. Load Regulation (VIN = 5.0 V, VOUT = 1.1 V)
Figure 24. Load Regulation (VIN = 3.3 V, VOUT = 1.1 V)
Figure 25. Load Regulation (VIN = 5.0 V, VOUT = 1.2 V)
Figure 26. Load Regulation (VIN = 3.3 V, VOUT = 1.2 V)
Figure 27. Load Regulation (VIN = 5.0 V, VOUT = 1.8 V)
Figure 28. Load Regulation (VIN = 3.3 V, VOUT = 1.8 V)
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12
NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
Figure 29. Load Regulation (VIN = 5.0 V, VOUT = 3.3 V)
Figure 30. Output Voltage DC Error vs Output
Current (VOUT = 1.0 V, TA = 255C)
Figure 31. Output Voltage DC Error vs Output
Figure 32. Output Voltage DC Error vs Output
Current (VOUT = 1.1 V, TA = 255C)
Current (VOUT = 1.2 V, TA = 255C)
Figure 33. Output Voltage DC Error vs Output
Figure 34. Output Voltage DC Error vs Output
Current (VOUT = 1.8 V, TA = 255C)
Current (VOUT = 3.3 V, TA = 255C)
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NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
Figure 35. Switching Frequency vs Output Current
(VOUT = 1.8 V, TA = 255C)
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14
NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
NCV6323F VOUT (AC COUPLING)
NCV6323F VOUT (AC COUPLING)
NCV6323F LOAD
NCV6323F LOAD
Figure 36. Load Transient (VIN = 3.3 V, VOUT = 1.0 V,
OUT = GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
500 mA " 1.2 A " 500 mA
Figure 37. Load Transient (VIN = 3.3 V, VOUT = 1.0 V,
OUT = GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
50 mA " 600 mA " 50 mA
C
C
Figure 38. Load Transient (VIN = 3.3 V, VOUT = 1.1 V,
Figure 39. Load Transient (VIN = 3.3 V, VOUT = 1.1 V,
C
OUT = GCM21BR70J106KE22, L = FDSD0420−H−1R0M) COUT = GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
500 mA " 1.2 A " 500 mA
50 mA " 600 mA " 50 mA
NCV6323F VOUT (AC COUPLING)
NCV6323F VOUT (AC COUPLING)
NCV6323F LOAD
NCV6323F LOAD
Figure 40. Load Transient (VIN = 3.3 V, VOUT = 1.2 V,
OUT = GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
Figure 41. Load Transient (VIN = 3.3 V, VOUT = 1.2 V,
OUT = GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
50 mA " 600 mA " 50 mA
C
C
500 mA " 1.2 A " 500 mA
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15
NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
NCV6323F VOUT (AC COUPLING)
NCV6323F VOUT (AC COUPLING)
NCV6323F LOAD
NCV6323F LOAD
Figure 42. Load Transient (VIN = 3.3 V, VOUT = 1.8 V,
OUT = GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
500 mA " 1.2 A " 500 mA
Figure 43. Load Transient (VIN = 3.3 V, VOUT = 1.8 V,
OUT = GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
50 mA " 600 mA " 50 mA
C
C
NCV6323F VOUT (AC COUPLING)
NCV6323F VOUT (AC COUPLING)
NCV6323F LOAD
NCV6323F LOAD
Figure 44. Load Transient (VIN = 5.0 V, VOUT = 3.3 V,
Figure 45. Load Transient (VIN = 5.0 V, VOUT = 3.3 V,
C
OUT = GCM21BR70J106KE22, L = FDSD0420−H−1R0M) COUT = GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
500 mA " 1.2 A " 500 mA
50 mA " 600 mA " 50 mA
NCV6323F VOUT (AC COUPLING)
NCV6323F LOAD (800 mA)
NCV6323F VIN
Figure 46. Line Transient (VOUT = 1.0 V, COUT
=
Figure 47. Line Transient (VOUT = 1.1 V, COUT =
GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
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NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
NCV6323F VOUT (AC COUPLING)
NCV6323F VOUT (AC COUPLING)
NCV6323F LOAD (800 mA)
NCV6323F VIN
NCV6323F LOAD (800 mA)
NCV6323F VIN
Figure 48. Line Transient (VOUT = 1.2 V, COUT
=
Figure 49. Line Transient (VOUT = 1.8 V, COUT =
GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
NCV6323F VOUT (AC COUPLING)
NCV6323F LOAD (800 mA)
NCV6323F VIN
Figure 50. Line Transient (VOUT = 3.3 V, COUT
=
GCM21BR70J106KE22, L = FDSD0420−H−1R0M)
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NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
NCV6323F VOUT (AC COUPLING)
NCV6323F LOAD (1.2 A)
NCV6323F SW
Figure 51. Output Voltage Ripple (VIN = 3.3 V,
Figure 52. Output Voltage Ripple (VIN = 3.3 V,
V
OUT = 1.0 V, COUT = GCM21BR70J106KE22,
IOUT = 500 mA)
V
OUT = 1.1 V, COUT = GCM21BR70J106KE22,
IOUT = 500 mA)
NCV6323F VOUT (AC COUPLING)
NCV6323F VOUT (AC COUPLING)
NCV6323F LOAD (1.2 A)
NCV6323F SW
NCV6323F LOAD (1.2 A)
NCV6323F SW
Figure 53. Output Voltage Ripple (VIN = 3.3 V,
OUT = 1.2 V, COUT = GCM21BR70J106KE22,
Figure 54. Output Voltage Ripple (VIN = 3.3 V,
V
V
OUT = 1.8 V, COUT = GCM21BR70J106KE22,
OUT = 500 mA)
IOUT = 500 mA)
I
NCV6323F VOUT (AC COUPLING)
NCV6323F LOAD (1.2 A)
NCV6323F SW
Figure 55. Output Voltage Ripple (VIN = 5.0 V,
VOUT = 3.3 V, COUT = GCM21BR70J106KE22,
IOUT = 500 mA)
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NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
1 ms
516 ms
NCV6323F Input Current
NCV6323F PG
90% of VOUT
NCV6323F VOUT
NCV6323F SW
NCV6323F EN
Figure 56. Inrush Current (VIN = 3.3 V, VOUT = 1.8
V, IOUT = 800 mA, COUT = GCM21BR70J106KE22,
L = FDSD0420−H−1R0M)
Figure 57. PG Delay after Start Up – NCV6323F−E
(VIN = 3.3 V, VOUT = 1.8 V, COUT = GCM21BR70J106KE22,
L = FDSD0420−H−1R0M)
118 ms
200 ms
NCV6323F VOUT
90% of VOUT
NCV6323F VOUT
90% of VOUT
NCV6323F EN
NCV6323F EN
10% of VOUT
Figure 58. Startup Time TSTART
Figure 59. Soft Start Time TSS
(NCV6323FCLMTW12, COUT = 10 mF)
(NCV6323FCLMTW12, COUT = 10 mF)
Figure 60. Startup Time TSTART
Figure 61. Soft Start Time TSS
(NCV6323FELMTW11, COUT = 10 mF)
(NCV6323FELMTW11, COUT = 10 mF)
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NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
502 ms
415 ms
NCV6323F VOUT
NCV6323F VOUT
NCV6323F EN
90% of VOUT
90 % of VOUT
NCV6323F EN
10% of VOUT
Figure 62. Startup Time TSTART
Figure 63. Soft Start Time TSS
(NCV6323FELMTW10, COUT = 10 mF)
(NCV6323FELMTW10, COUT = 10 mF)
452 ms
590 ms
NCV6323F VOUT
NCV6323F VOUT
90% of VOUT
90% of VOUT
NCV6323F EN
NCV6323F EN
10% of VOUT
Figure 64. Startup Time TSTART
Figure 65. Soft Start Time TSS
(NCV6323FELMTW18, COUT = 10 mF)
(NCV6323FELMTW18, COUT = 10 mF)
506 ms
380 ms
NCV6323F VOUT
NCV6323F VOUT
90% of VOUT
90% of VOUT
NCV6323F EN
NCV6323F EN
10% of VOUT
Figure 66. Startup Time TSTART
Figure 67. Soft Start Time TSS
(NCV6323FELMTW33, COUT = 10 mF)
(NCV6323FELMTW33, COUT = 10 mF)
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NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
Figure 69. Bode Plot NCV6323FxLMTW18TBG
Figure 68. Bode Plot NCV6323FxLMTW18TBG
L = 1.0 mH – COUT = 100 mF
L = 1.0 mH – COUT = 10 mF
Figure 70. Bode Plot NCV6323FxLMTW33TBG
Figure 71. Bode Plot NCV6323FxLMTW33TBG
L = 1.0 mH – COUT = 10 mF
L = 1.0 mH – COUT = 100 mF
Figure 72. Bode Plot NCV6323FxLMTW12TBG
Figure 73. Bode Plot NCV6323FxLMTW12TBG
L = 1.0 mH – COUT = 10 mF
L = 1.0 mH – COUT = 100 mF
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NCV6323F−xx
TYPICAL OPERATING CHARACTERISTICS (continued)
Figure 74. Bode Plot NCV6323FxLMTW10TBG
Figure 75. Bode Plot NCV6323FxLMTW10TBG
L = 1.0 mH – COUT = 10 mF
L = 1.0 mH – COUT = 100 mF
Figure 76. Bode Plot NCV6323FxLMTW11TBG
Figure 77. Bode Plot NCV6323FxLMTW11TBG
L = 1.0 mH – COUT = 10 mF
L = 1.0 mH – COUT = 100 mF
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NCV6323F−xx
DETAILLED OPERATING DESCRIPTION
PWM Operation
General
The NCV6323F is
a
voltage mode standalone
The device operates in PWM mode with 3 MHz typical
fixed switching frequency. In this operating scheme, the
output voltage is regulated by on−time Pulse Width
Modulation (PWM) of an integrated high side P−MOSFET.
A low side N−MOSFET, also integrated in the IC, operates
as synchronous rectifier and its turn−on signal is
complimentary to that of the P−MOSFET (with built in dead
time control to avoid cross conduction)
synchronous PWM DC−DC converter optimized to supply
the different sub systems of automotive applications from a
pre−regulator supply rail in the 2.8 V to 5.5 V range. It can
deliver up to 1.6 A to an internally factory set voltage (please
refer to the ORDERING INFORMATION table). The
3 MHz switching frequency allows using small output filter
components. A Power Good (PG) indicator is available. The
synchronous rectification offers high system efficiency and
integrated feedback network allows very simple and
straightforward implementation to power supply designers
with only a few components to select.
Under Voltage Lockout
The input voltage VIN must reach or exceed 2.8 V
(maximum) before the NCV6323F enables the converter
output to begin the startup sequence. The UVLO threshold
hysteresis is typically 150 mV.
The NCV6323F is housed in a low profile 2.0 x 2.0 mm
uDFN−8 package.
Enable
DC−DC Converter Operation
The NCV6323F has an enable logic input pin EN. A high
level (above 1.1 V) on this pin enables the device to active
mode. A low level (below 0.4 V) on this pin disables the
device and makes the device in shutdown mode. There is an
internal filter with 5 ms time constant. The EN pin is pulled
down by an internal 100 nA sink current source.
The converter integrates both high side and low side
(synchronous) switches. Neither external transistors nor
diodes are required for NCV6323F operation. The feedback
and compensation networks are also fully integrated. It
operates in PWM.
EN
1.1 V
0.4 V
VOUT
80 ms
T
SS
(1)
95%
90%
90%
10%
1.1 ms
PG
8 ms
11 ms
4 ms
ACTIVE DISCHARGE
8 ms
OUT OF
REGULATION
START UP
REGULATION
REGULATION
(1) T timing depends on the IC version.
SS
Please refer to the full part number of the considered version and to the electrical tables
Figure 78. Power Good and Active Discharge Timing Diagrams
Power Good Output (PG)
During the startup sequence, this signal indicates that the
The device monitors the output voltage and provides a
power good signal at the PG pin. This pin is an open−drain
output. This signal indicates that the desired voltage is
regulated properly and is valid as soon as the Enable (EN)
pin enables the device. When EN is high, the power good pin
is tied to low level when the output voltage is considered as
out of regulation (less than 90% of the desired value).
output voltage is not yet established, while during normal
operation, a High to Low transition of PG indicates that the
output voltage sags under 90% of its target and is out of
regulation. A low level at the power good signal indicates a
power failure. An internal 5% hysteresis is implemented on
the power good comparator.
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NCV6323F−xx
When EN is low (NCV6323F disabled), the discharge
In output short circuit condition, if the short impedance
becomes low enough to maintain the NCV6323F V
lower than 300 mA (max), because of the internal delays in
the detection system, the Peak Current Limit can become
non operative.
path (refer to the “Discharge Path” section) drives the output
voltage to ground. In that condition, the PG is maintained to
low by a weak pull down.
OUT
Soft−Start (SS)
A soft start limits inrush current when the converter is
enabled. After a minimum 80 ms typical delay time
following the enable signal, the output voltage ramp is
Negative Current Protection
The NCV6323F includes a cycle by cycle 0.8 A typical
negative current protection in the N−MOSFET Low Side
Switch (LSS). This current limitation protects the internal
LSS when the output cap has to be discharged during
regulation to allow fast recovery to the target output voltage.
This can happen mainly when the capacitive load is pretty
high and the IC recovers after a fast negative load transient
(load release).
controlled during the T time. The T time is factory
SS
SS
programmed. Please refer to the ordering information to
select the T that fit better with the application
SS
requirements or that is available. If not available, please
contact your sales representative office.
T
= 440 ms (NCV6323F−xxE).
SS
In output short circuit condition, if the short impedance
Active Output Discharge
becomes low enough to maintain the NCV6323F V
OUT
An output discharge operation is active in when EN is low.
A discharge resistor (450 W typical) is enabled in 4 ms after
the High to Low transition of the EN signal to discharge the
output capacitor through SW pin.
lower than 300 mA (max), because of the internal delays in
the detection system, the Peak Current Limit can become
non operative.
Thermal Shutdown (TSD)
Cycle−by−Cycle Current Limitation
The power dissipation of the output stage can lead the die
temperature to exceed the maximum rating of the silicon. To
avoid irreversible damage and hazard in its normal
operation, the NCV6323F features a Thermal Shutdown to
protect the device from overheating when the die
temperature exceeds 150°C.
When activated, the TSD will immediately stop the power
stage switching activity, turns it off and the output voltage
is switched off. The PG indicator will transition to Low
level, indicating a power fail.
The NCV6323F protects the device from over current
with a fixed−value cycle−by−cycle current limitation. The
typical peak current limit ILMT is 2.6 A (10, 11, 12, 18
versions) and 2.45 A (33 version). If the inductor current
exceeds the current limit threshold, the P−MOSFET will be
turned off cycle−by−cycle. The maximum output current
can be calculated by
VOUT (VIN * VOUT
2 VIN fSW L
)
IMAX + ILIMIT
*
(eq. 1)
During TSD activation, the die will cool down to a more
acceptable temperature level and, when the temperature gets
down below 125°C again , the switching activity will be
released and the PG pin will transition to high again as soon
as the output voltage has recovered.
Where V is input supply voltage, V
L is inductance of the filter inductor, and f
normal switching frequency.
is output voltage,
IN
OUT
is 3 MHz
SW
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NCV6323F−xx
APPLICATION INFORMATION
Output Filter Design Considerations
50% of the maximum output current I
for a
OUT_MAX
The output filter introduces a double pole in the system at
a frequency of
trade−off between transient response and output ripple. The
inductance corresponding to the given current ripple is
1
(VIN * VOUT) VOUT
L +
fLC
+
(eq. 2)
Ǹ
2 p L C
(eq. 3)
VIN fSW IL_PP
The internal compensation network design of the
NCV6323F is optimized for a typical output filter comprised
of a 1.0 mH inductor and a 10 mF ceramic output capacitor,
which has a double pole frequency at about 50 kHz. Other
possible output filter combinations may have a double pole
around 50 kHz to have optimum operation with the typical
feedback network. Normal selection range of the inductor is
from 0.47 mH to 4.7 mH, and normal selection range of the
output capacitor is from 4.7 mF to 22 mF.
The selected inductor must have high enough saturation
current rating to be higher than the maximum peak current
that is
IL_PP
IL_MAX + IOUT_MAX
)
(eq. 4)
2
The inductor also needs to have high enough current
rating based on temperature rise concern. Low DCR is good
for efficiency improvement and temperature rise reduction.
Table xx shows some recommended inductors for high
power applications and Table xx shows some recommended
inductors for low power applications.
Inductor Selection
The inductance of the inductor is determined by given
peak−to−peak ripple current I
of approximately 20% to
L_PP
Table 1. LIST OF RECOMMENDED INDUCTORS FOR HIGH POWER APPLICATIONS
Rated Current (mA)
(Inductance Drop)
Manufacturer
MURATA
MURATA
MURATA
TDK
Part #
Case Size (mm)
2.5 x 2.0 x 1.2
2.5 x 2.0 x 0.9
2.5 x 2.0 x 1.1
2.5 x 2.0 x 1.2
2.0 x 1.6 x 1.0
L (mH)
1.0
DFE252012PD−1R0M#
LQH2HPZ1R0MGR#
3800
2100
2600
4200
3700
1.0
LQH2HPZ1R0NJR#
1.0
TFM252012ALMA1R0MTAA
TFM201610ALMA1R0MTAA
1.0
TDK
1.0
Table 2. LIST OF RECOMMENDED INDUCTORS FOR LOW POWER APPLICATIONS
Rated Current (mA)
(Inductance Drop)
Manufacturer
MURATA
TDK
Part #
Case Size (mm)
3.0 x 3.0 x 0.9
2.0 x 1.6 x 0.9
2.0 x 1.25 x 1
L (mH)
1.0
LQH3NPZ1R0MGR#
MLD2016S1R0MTD25
TFM201210ALMA1R0MTAA
1700
1100
2000
1.0
TDK
1.0
Output Capacitor Selection
equivalent ESL of the output capacitors. In PWM operation
mode, the three ripple components can be obtained by
The output capacitor selection is determined by output
voltage ripple and load transient response requirement. For
a given peak−to−peak ripple current IL_PP in the inductor
of the output filter, the output voltage ripple across the
output capacitor is the sum of three ripple components as
below
IL_PP
VOUT_PP(C)
+
(eq. 6)
(eq. 7)
8 C fSW
VOUT_PP(ESR) + IL_PP ESR
ESL
VOUT_PP [ VOUT_PP(C) ) VOUT_PP(ESR) ) VOUT_PP(ESL)
VOUT_PP(ESL)
+
VIN
(eq. 5)
(eq. 8)
(eq. 9)
ESL ) L
And the peak−to−peak ripple current is
Where V
is a ripple component by an equivalent
OUT_PP(C)
total capacitance of the output capacitors, V
a ripple component by an equivalent ESR of the output
capacitors, and V is a ripple component by an
is
OUT_PP(ESR)
(VIN * VOUT) VOUT
IL_PP
+
VIN fSW L
OUT_PP(ESL)
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25
NCV6323F−xx
IOUT_MAX (D * D2)
VIN_PP fSW
In applications with all ceramic output capacitors, the
main ripple component of the output ripple is V
CIN_MIN
+
.
OUT_PP(C)
(eq. 11)
(eq. 12)
So that the minimum output capacitance C
can be
OUT_MIN
Where
calculated regarding to a given output ripple requirement
V
in PWM operation mode.
VOUT
VIN
OUT_PP
D +
IL_PP
COUT_MIN
+
(eq. 10)
8 VOUT_PP fSW
In addition, the input capacitor needs to be able to absorb
the input current, which has an RMS value of
Input Capacitor Selection
Ǹ
D * D2
IIN_RMS + IOUT_MAX
(eq. 13)
One of the input capacitor selection guides is the input
voltage ripple requirement. To minimize the input voltage
ripple and get better decoupling in the input power supply
rail, ceramic capacitor is recommended due to low ESR and
The input capacitor also needs to be sufficient to protect
the device from over voltage spike, and normally at least a
4.7 mF capacitor is required. The input capacitor should be
located as close as possible to the IC on PCB.
ESL. The minimum input capacitance C
regarding to
IN_MIN
the input ripple voltage V
is
IN_PP
Table 3. LIST OF RECOMMENDED INPUT AND OUTPUT CAPACITORS
Manufacturer
TDK
Part #
Case Size (mm)
0805
Technology
X7R
C (mF)
4.7
2.2
4.7
10
Rated Voltage (V)
CGA4J3X7R1A475K125AB
CGA3E3X7S1A225K080AB
GCM21BC71A475KA73
GCM188D70J106M
10
10
TDK
0603
X7S
MURATA
MURATA
MURATA
TDK
0805
X7S
10
0603
X7T
6.3
6.3
6.3
GCM21BR70J106KE22#
CGA4J1X7R0J106K125
0805
X7R
10
0805
X7R
10
Stability of the Regulation Loop
If the output capacitor is comprised within the overlap
range (50 ~ 100 mF), it is suggested to select the L option if
C ≤ 80 mF and the H option if C > 80 mF.
The NCV6323F is a voltage mode DC to DC converter
with a double pole at the f frequency and a zero at the f
LC
0
frequency:
Maximum Current and Thermal Considerations
To avoid irreversible damage and overheating, the
Thermal Shut Down (TSD) of the NCV6323F will stop the
power stage switching activity as soon as the die temperature
rises up to 150°C TSD threshold. Dissipation in the power
stage mainly depends on the losses in the HSS (High Side
Switch) and LSS (Low Side Switch) and is then directly
function of the loading current.
1
fLC
+
(eq. 14)
Ǹ
2 p L C
1
fESR
+
(eq. 15)
2 p ESR C
With L = the output inductor and C the total amount of
capacitance connected to the NCV6323F output. This
capacitance value should not only take into account the LC
filter capacitor, but also all other capacitors connected
between the rail NCV6323F supplies and the GND.
The loop is compensated by a type III network.
As, besides the external LC filter, all the other parameters
that govern the loop response and stability are integrated in
the NCV6323F, it is important to evaluate and consider,
during the design stage, the real value of the output capacitor
C and select the right NCV6323F option.
The NCV6323F specification is guaranteed for a
maximum Junction Temperature (T
) of 125°C. When
J_MAX
the junction temperature ranges from 125°C to the TSD
threshold, the IC will still operate and will not be damaged,
but the specifications are not guaranteed and the parameters
value may deviate significantly. It is then important to try to
keep the T ≤ 125°C.
J
The THERMAL INFORMATION table provides the
thermal parameters (R ) defined by the JEDEC
QJx
In order to accommodate a large range of applications, 2
options of the compensation loop are available (please refer
to the ORDERING INFORMATION table):
JESD51−3 as well as some thermal characterization
parameters (Y ). The thermal characterization parameters
Jx
are the result of measurements on the standard NCV6323F
demo board, while the thermal parameters are the result of
simulations in the JESD51 defined environment.
• NCV6323FxL that address the application with output
capacitor ranging from 10 to ~100 mF
• NCV6323FxH that address the application with output
capacitor ranging from 50 to ~250 mF
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NCV6323F−xx
Based on those parameters and the efficiency, a Safe
Table 4. MAXIMUM OUTPUT CURRENT AT TA = 1055C
Operating Area, that keeps the junction temperature lower
than 125°C, can be defined.
On the standard demo board, the maximum power
V
IN
(V)
V
OUT
(V)
Max I
(A)
OUT
5.0
1.0
1.2
1.2
1.2
1.2
1.2
1.1
1.1
1.2
1.2
(P
) the package can dissipate with 105°C ambient
1.1
1.2
1.8
3.3
1.0
1.1
1.2
1.8
D_MAX
temperature (T ), can be calculated as:
A
TJ_MAX * TA_MAX
PD_MAX
+
(eq. 16)
RQJA
With: T
= maximum junction temperature (125°C),
J_MAX
3.3
T
R
= maximum ambient temperature (105°C) and
A_MAX
= Junction to Ambient thermal resistance measured on
QJA
our evaluation board (~40°C/W), P
= 500 mW.
D_MAX
Thus, for T = 105°C:
A
The below figure is a simulation result showing the die
temperature gradient when the NCV6323F dissipates
500 mW. As expected, the output stage is the hottest part of
the die and gets to about 125°C.
Figure 79. Die Temperature Simulation (500 mW Dissipated Power)
FeedBack (FB) Pin Leakage Current
This ladder has a typical impedance of 260 kW, thus, the FB
The FB pin is internally connected to the resistor ladder
pin input leakage current value is:
that divides the V
voltage and feeds the error amplifier.
IFB + (VOUT * 0.6) ń 260.103
OUT
(eq. 17)
www.onsemi.com
27
NCV6323F−xx
LAYOUT CONSIDERATIONS
Switching Noise Consideration
VIN
SW
FB
VIN
LOGIC,
CONTROL,
BIASING ...
Power Stage
Drivers
AGND
PGND
PGND
AGND
Connect A
& P
in one point
GND
GND
I
I
1
2
I = I + I
L
1
2
Figure 80. AC Current Flowing Loops
and end of the active time. These sharp edges have fast
rise and fall times (high dI/dt). Therefore they have a lot
of high frequency content.
• The DC/DC buck converter has two main loops where
high AC currents flow.
• When the High−Side Switch (HSS) is on, the current
flows from VCC via HSS and L to the output capacitor
and the load. The current flows back via ground to the
input. The AC portion of the current will flow via the
input and output capacitors. This current is shown in red
color (I1).
• I1 and I2 share a common path from switch node to
inductor to output capacitor to ground back to the source
of LSS. The sum of I1 and I2 is a relatively smooth
continuous saw−tooth waveform, which has less high
frequency content due to the absence of high dI/dt edges.
• From noise point of view, the current loop with the high
dI/dt current is the red shaded area. This loop will
generate the most high frequencies and should be
considered the most critical loop for noise in buck
converters. The dI/dt of the current in the blue shaded area
is not as high as it is in the other area and generally
generates a lot less noise.
• When HSS switches off, the inductor current will keep
flowing in the same direction, and the Low−Side Switch
(LSS) is switched on. The current flows via LSS, L, load
and output capacitor and back via ground to LSS. This
loop is shown in blue (I2).
• Both I1 and I2 are discontinuous currents, meaning that
they have sharp rising and falling edges at the beginning
www.onsemi.com
28
NCV6323F−xx
Electrical Layout Considerations
point. Directly connect AGND pin to the exposed pad and
then connect to AGND ground plane through vias. Try
best to avoid overlap of input ground loop and output
ground loop to prevent noise impact on output regulation.
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
• Since the red shaded area is the noisiest loop, it is critical
to identify it and to place the input cap in such a way that
this loop is minimized. It is also important to make sure
that the path between the 2 terminals of the input cap and
the PVIN & PGND pins is as short as possible and free of
any vias to either the VIN or the GND PCB plane. It can
also be a good practice to make a local PGND and VIN
planes and to keep those planes as solid as possible below
and in the input switching loop. Any trace or vias in this
area reduces the plane effectiveness and increase the
plane impedance. Vias from these planes to the other main
planes of the PCB should be placed outside of the critical
loop.
• Arrange a “quiet” path for output voltage sense, and make
it surrounded by a ground plane.
Component Placement
• C Input capacitor placed as close as possible to the IC.
IN
• PVIN directly connected to C input capacitor, and then
IN
connected to the VIN plane. Local mini planes used on the
top layer and the layer just below the top layer with laser
vias.
• AVIN connected to the VIN plane just after the capacitor.
• AGND directly connected to the GND plane.
• PGND directly connected to C input capacitor, and then
IN
connected to the GND plane: Local mini planes used on
the top layer and the layer just below the top layer with
laser vias.
• Also, it is important to place the output capacitor ground
in an area that does not overlap the input capacitor
switching loop : this could generate extra high frequency
noise in the output voltage
• Connecting the PGND plane to the main PCB GND plane
(to whitch the AGND pin should be connected too) in one
point (doing a kind of “star routing”) is also important to
isolate the AGND and keep them quiet.
• SW connected to the L
inductor with local mini
OUT
planes on the top layer.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from a
small package with reduced temperature rise. Thermal
layout guidelines are:
• Use wide and short traces for power paths (such as P
,
VIN
V
OUT
, SW, and PGND) to reduce parasitic inductance and
• The exposed pad must be well soldered on the board.
high−frequency loop area. It is also good for efficiency
improvement.
• A four or more layers PCB board with solid ground planes
is preferred for better heat dissipation.
• The device should be well decoupled by input capacitor
and input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission.
• More free vias are welcome to be around IC and/or
underneath the exposed pad to connect the inner ground
layers to reduce thermal impedance.
• Use large area copper especially in top layer to help
thermal conduction and radiation.
• SW node should be a large copper pour, but compact
because it is also a noise source.
• Do not put the inductor to be too close to the IC, thus the
heat sources are distributed
• It would be good to have separated local ground planes for
PGND and AGND and connect the two planes at one
www.onsemi.com
29
NCV6323F−xx
Figure 81. Recommended Minimal Size PCB Layout (Without Optional CAVIN
)
Figure 82. Recommended Large Size PCB Layout (With Optional CAVIN
)
www.onsemi.com
30
NCV6323F−xx
ORDERING INFORMATION
ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NCV6323FELMTW12TBG
AA
AC
AD
AM
AL
WDFN8 with Wettable Flanks
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
NCV6323FELMTW18TBG
NCV6323FELMTW10TBG
NCV6323FELMTW33TBG
NCV6323FELMTW11TBG
WDFN8 with Wettable Flanks
(Pb−Free)
WDFN8 with Wettable Flanks
(Pb−Free)
WDFN8 with Wettable Flanks
(Pb−Free)
WDFN8 with Wettable Flanks
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCV6323F y z MTW xx(x) TBG
Compensation optimized for output
capacitor range
Fixed Output Voltage Options (*)
T
= Time for V
to rise
SS
OUT
from 10 % to 90 % of Target
(*) (**)
y
TSS
0 (*)
Z
L
COUT Range
xx (x)
VOUT
10 mF ≤ C
50 mF ≤ C
< 100 mF
10
12
1.0 V
OUT
20 ms (*)
40 ms (*)
60 ms (*)
80 ms (*)
100 ms (*)
H
< 250 mF (*)
1.2 V
OUT
13
1.3 V (*)
1.5 V (*)
1.8 V
15
18
25
2.5 V (*)
2.8 V (*)
3.3 V
28
120 ms (*)
160 ms (*)
180 ms (*)
200 ms (*)
33
09
0.9 V (*)
1.1 V
11
135
185
27
1.35 V (*)
1.85 V (*)
2.7 V (*)
2.85 V (*)
2.9 V (*)
3.0 V (*)
220 ms (*)
240 ms (*)
360 ms (*)
400 ms (*)
440 ms
285
29
E
30
(*) Available upon request (Please contact your ON Semiconductor sales office)
(**) For more detailed information, refer to the Enable section of the DETAILLED OPERATING DESCRIPTION
Figure 83.
www.onsemi.com
31
NCV6323F−xx
PACKAGE DIMENSIONS
WDFNW8 2x2, 0.5P
CASE 511CL
ISSUE B
www.onsemi.com
32
NCV6323F−xx
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◊
相关型号：
NCV6323FELMTW33TBG
Automotive, Buck converter, Synchronous, PWM, Fixed Output Voltage DC to DC converter, up to 1.6 A DC, Wettable flank DFN8, 2x2 mm (0.8 mm thickness), 0.5 mm pitch package
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