NCV6336BMFCCT1G [ONSEMI]
同步降压转换器，处理器电源，I2C 编程，瞬变负载帮助器，5.0 A;
| 型号： | NCV6336BMFCCT1G |
| 厂家： | 
ONSEMI |
| 描述： | 同步降压转换器，处理器电源，I2C 编程，瞬变负载帮助器，5.0 A 转换器 |
| 文件： | 总31页 (文件大小：1852K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV6336
Step Down Converter -
Transient Load Helper,
Configurable
5.0 A
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MARKING
The NCV6336 is a synchronous buck converter optimized to supply
the different sub systems of portable applications powered by one cell
Li−Ion or three cell Alkaline/NiCd/NiMH batteries. The device is able
to deliver up to 5.0 A, with programmable output voltage from 0.6 V
to 1.4 V. It can share the same output rail with another DC−to−DC
converter and works as a transient load helper. Operation at a
2.74 MHz switching frequency allows the use of small components.
Synchronous rectification and automatic PWM/PFM transitions
improve overall solution efficiency. The NCV6336 is in a space
saving, low profile 2.0 x 1.6 mm CSP−20 package.
DIAGRAM
6336xx
AWLYWW
G
WLCSP20
CASE 568AG
6336xx = Specific Device Code
xx = BM for NCV6336BM
= CV for NCV6336C
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
Features
• Input Voltage Range from 2.3 V to 5.5 V: Battery and 5 V Rail
Powered Applications
Y
G
= Pb−Free Package
• Programmable Output Voltage: 0.6 V to 1.4 V in 6.25 mV Steps
• 2.74 MHz Switching Frequency with On Chip Oscillator
Pb−Free indicator, G or microdot (G), may or may
not be present
• Uses 330 nH Inductor and 47 mF Capacitors for Optimized Footprint
and Solution Thickness
PIN OUT
• PFM/PWM Operation for Optimum Increased Efficiency
1
2
3
4
• Low 35 mA Quiescent Current
A
VSEL
EN
SCL
FB
2
• I C Control Interface with Interrupt and Dynamic Voltage Scaling
Support
• Enable Pins, Power Good / Fail Signaling
• Thermal Protections and Temperature Management
• Transient Load Helper: Share the Same Rail with Another Rail
• Small 2.0 x 1.6 mm / 0.4 mm Pitch CSP Package
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
PGND
INTB*
PGND
PG*
B
SDA
PGND
AVIN
PVIN
AGND
PGND
C
D
E
PGND
PGND
SW
SW
SW
PVIN
PVIN
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
SW
Typical Applications
• Smartphones
• Webtablets
(Top View)
*Optional
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 29 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
August, 2019 − Rev. 0
NCV6336BM/D
NCV6336
NCV6336
AVIN
PVIN
D1
D2
E1
E2
Supply Input
Core
AGND
B4
4.7 uF
Thermal
Protection
D3
D4
E3
E4
Enable Control EN
DCDC
5.0 A
A2
A1
SW
Input
Operating
Mode
Control
330 nH
47 uF
Voltage VSEL
Selection
C1
C2
C3
C4
PGND
FB
Output
Monitoring
PGND
Power Fail
PG
B3
PGND
Interrupt
B2
B1
INTB
A4
DCDC
2.74 MHz
Controller
Processor
Core
SDA
Sense
I@C
Processor I@C
Control Interface
SCL
A3
Figure 1. Typical Application Circuit
PVIN
PVIN
PVIN
POWER
INPUT
SUPPLY INPUT
AVIN
Core
ANALOG GROUND
AGND
SW
SW
5.0 A
DC−DC
SWITCH
NODE
Thermal
Protection
SW
SW
Output Voltage
Monitoring
POWER GOOD
(optional)
PG
EN
ENABLE CONTROL INPUT
VOLTAGE SELECTION
2.74 MHz DC−DC
converter
Operating
Mode Control
PGND
Controller
POWER
GROUND
VSEL
PGND
PGND
PGND
INTERRUPT OUTPUT
(optional)
INTB
SCL
SDA
Logic Control
Interrupt
I2C
FEEDBACK
PROCESSOR I2C
CONTROL INTERFACE
FB
Sense
Figure 2. Simplified Block Diagram
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2
NCV6336
1
2
3
4
A
VSEL
EN
SCL
FB
PGND
INTB*
PGND
PG*
B
SDA
PGND
AVIN
AGND
PGND
SW
C
D
E
PGND
PGND
SW
PVIN
PVIN
SW
PVIN
SW
*Optional
Figure 3. Pin Out (Top View)
PIN FUNCTION DESCRIPTION
Pin
Name
Type
Description
REFERENCE
D1
AVIN
Analog Input
Analog Supply. This pin is the device analog and digital supply. Could be connected
directly to the VIN plane just next to the 4.7 mF PVIN capacitor or to a dedicated
1.0 mF ceramic capacitor.
B4
AGND
Analog Ground
Analog Ground. Analog and digital modules ground. Must be connected to the sys-
tem ground.
CONTROL AND SERIAL INTERFACE
A2
EN
Digital Input
Enable Control. Active high will enable the part. There is an internal pull down resist-
or on this pin.
A1
VSEL
Digital Input
Output voltage / Mode Selection. The level determines which of two programmable
configurations to utilize (operating mode / output voltage). There is an internal pull
down resistor on this pin; could be left open if not used.
2
A3
B1
B3
SCL
SDA
Digital Input
I C interface Clock line. There is an internal pull down resistor on this pin; could be
left open if not used
2
Digital
Input/Output
I C interface Bi−directional Data line. There is an internal pull down resistor on this
pin; could be left open if not used
PGND
PG
Digital Output
Analog Ground
Power Good open drain output. If not used has to be connected to ground plane
B2
PGND
INTB
Digital Output
Analog Ground
Interrupt open drain output. If not used has to be connected to ground plane
DC to DC CONVERTER
D2, E1, E2
PVIN
SW
Power Input
Power Output
Power Ground
Switch Supply. These pins must be decoupled to ground by a 4.7 mF ceramic capa-
citor. It should be placed as close as possible to these pins. All pins must be used
with short heavy connections.
D3, D4,
E3, E4
Switch Node. These pins supply drive power to the inductor. Typical application uses
0.33 mH inductor; refer to application section for more information.
All pins must be used with short heavy connections.
C1, C2,
C3, C4
PGND
Switch Ground. This pin is the power ground and carries the high switching current.
High quality ground must be provided to prevent noise spikes. To avoid high−density
current flow in a limited PCB track, a local ground plane that connects all PGND pins
together is recommended. Analog and power grounds should only be connected
together in one location with a trace.
A4
FB
Analog Input
Feedback Voltage input. Must be connected to the output capacitor positive termin-
al with a trace, not to a plane. This is the positive input to the error amplifier.
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3
NCV6336
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Analog and power pins: AVIN, PVIN, SW, PG, INTB, FB (Note 1)
V
A
−0.3 to + 6.0
V
Digital pins: SCL, SDA, EN, VSEL, Pin:
Input Voltage
V
−0.3 to V + 0.3 ≤ 6.0
V
mA
DG
DG
A
Input Current
I
10
Human Body Model (HBM) ESD Rating (Note 2)
Charged Device Model (CDM) ESD Rating (Note 2)
ESD HBM
ESD CBM
2500
1250
V
V
Latch Up Current: (Note 3)
Digital Pins
I
LU
mA
10
100
All Other Pins
Storage Temperature Range
Maximum Junction Temperature
Moisture Sensitivity (Note 4)
T
−65 to +150
−40 to +150
Level 1
°C
°C
STG
T
JMAX
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM) 2.5 kV per JEDEC standard: JESD22−A114.
Charged Device Model (CDM) 1250 V per JEDEC standard: JESD22−C101 Class IV
3. Latch up Current per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
OPERATING CONDITIONS
Symbol
AV PV
Parameter
Conditions
Min
2.3
−40
−40
−
Typ
Max
5.5
+125
+125
−
Unit
V
Power Supply
IN,
IN
T
A
Ambient Temperature Range
25
25
°C
T
J
Junction Temperature Range (Note 6)
Thermal Resistance Junction to Ambient (Note 7)
Power Dissipation Rating (Note 8)
°C
R
CSP−20 on Demo−board
55
°C/W
mW
mW
mH
q
JA
P
P
T
≤ 85°C
= 65°C
A
−
727
1090
0.33
−
−
D
A
Power Dissipation Rating (Note 8)
T
−
−
D
L
Inductor for DC to DC converter (Note 5)
Output Capacitor for DC to DC Converter (Note 5)
Input Capacitor for DC to DC Converter (Note 5)
0.26
30
0.56
150
−
Co
mF
Cin
4.7
−
mF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Including de−ratings (Refer to the Application Information section of this document for further details)
6. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
7. The R
is dependent of the PCB heat dissipation. The board used to drive this data was a NCP6336EVB board. It is a multilayer board
q
JA
with 1−ounce internal power and ground planes and 2−1 ounce copper traces on top and bottom of the board.
8. The maximum power dissipation (P ) is dependent by input voltage, maximum output current and external components selected.
D
125 * TA
RqJA
+
PD
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4
NCV6336
ELECTRICAL CHARACTERISTICS (Note 9)
Min and Max Limits apply for T = −40°C to +125°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
J
Typical values are referenced to T = +25°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY CURRENT: PINS AVIN – PVINx
I
Operating quiescent current PWM
Operating quiescent current PFM
Product sleep mode current
DCDC active in Forced PWM
no load
−
−
−
15
35
7
25
70
60
mA
mA
mA
Q PWM
I
DCDC active in Auto mode
no load − minimal switching
Q PFM
I
EN high, DCDC off or
EN low and VSEL high
SLEEP
V
IN
= 2.5 V to 5.5 V
I
Product in off mode
EN, VSEL low
= 2.5 V to 5.5 V
−
7
60
mA
OFF
V
IN
DC to DC CONVERTER
PV
Input Voltage Range
2.3
3.5
4.0
4.5
5.0
−1
−
−
−
−
−
−
−
5.5
−
V
A
IN
OUTMAX
I
Maximum Output Current
Ipeak[1..0] = 00 (Note 11)
Ipeak[1..0] = 01 (Note 11)
Ipeak[1..0] = 10 (Note 11)
Ipeak[1..0] = 11 (Note 11)
Forced PWM mode, No load
−
−
−
D
Output Voltage DC Error
Switching Frequency
1
%
VOUT
Forced PWM mode, V range,
−1
1
IN
I
up to I
(Note 11)
OUT
OUTMAX
Auto mode, V range,
−1
−
2
IN
(Note 11)
OUTMAX
I
up to I
OUT
F
SW
2.46
2.74
23
3.01
40
MHz
R
P−Channel MOSFET On
Resistance
From PVIN to SW
V = 5.0 V
IN
−
mW
ONHS
R
N−Channel MOSFET On
Resistance
From SW to PGND
V = 5.0 V
IN
−
12
20
mW
ONLS
I
Peak Inductor Current
Open loop – Ipeak[1..0] = 00 (Note 11)
Open loop – Ipeak[1..0] = 01 (Note 11)
Open loop – Ipeak[1..0] = 10 (Note 11)
Open loop – Ipeak[1..0] = 11
−
−
5.2
5.8
−
−
A
PK
−
6.2
−
6.1
−
6.8
7.8
−
DC
Load Regulation
Line Regulation
I
from 0 A to I (Note 11)
OUTMAX
−0.2
%/A
%
LOAD
OUT
Forced PWM mode
DC
I
= 3 A
−
−
0
−
−
LINE
OUT
2.3 V ≤ V ≤ 5.5 V (Note 11)
IN
Forced PWM mode
AC
Transient Load Response
tr = ts = 100 ns
Load step 1.2 A (Note 11)
40
mV
LOAD
D
Maximum Duty Cycle
Turn on time
−
−
100
100
−
%
t
Time from EN transitions from Low to
High to 90% of Output Voltage
(DELAY[2..0] = 000b)
125
ms
START
R
DCDC Active Output Discharge
V
OUT
= 1.15 V
−
25
35
W
DISDCDC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Refer to the Application Information section of this data sheet for more details.
2
10.Devices that use non−standard supply voltages which do not conform to the intent I C bus system levels must relate their input levels
to the V voltage to which the pull−up resistors R are connected.
DD
P
11. Guaranteed by design and characterized.
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5
NCV6336
ELECTRICAL CHARACTERISTICS (Note 9)
Min and Max Limits apply for T = −40°C to +125°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
J
Typical values are referenced to T = +25°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
EN, VSEL
V
High input voltage
1.05
−
−
−
−
−
V
V
IH
V
Low input voltage
0.4
4.8
IL
T
FTR
Digital input X Filter
EN, VSEL rising and falling
DBN_Time = 01 (Note 11)
0.5
ms
I
Digital input X Pull−Down
(input bias current)
−
0.05
1.00
mA
PD
PG (Optional)
V
Power Good Threshold
Power Good Hysteresis
Falling edge as a percentage of
nominal output voltage
86
0
90
3
94
5
%
PGL
V
%
PGHYS
T
RT
Power Good Reaction Time for
DCDC
Falling (Note 11)
Rising (Note 11)
−
3.5
3.5
−
−
15.5
ms
V
Power Good low output voltage
Power Good leakage current
Power Good high output voltage
I
= 5 mA
−
−
−
−
−
−
0.2
100
5.5
V
nA
V
PGL
PG
PG
3.6 V at PG pin when power good valid
Open drain
LK
V
PGH
INTB (Optional)
V
INTB low output voltage
INTB high output voltage
INTB leakage current
I
= 5 mA
0
−
−
−
−
−
0.2
5.5
V
V
INTBL
INTBH
INT
V
Open drain
INTB
3.6 V at INTB pin when INTB valid
100
nA
LK
2
I C
V 2
I CINT
High level at SCL/SCA line
SCL, SDA low input voltage
SCL, SDA high input voltage
1.7
−
−
−
−
5.0
0.5
−
V
V
V
V 2
I CIL
SCL, SDA pin (Notes 10, 11)
SCL, SDA pin (Notes 10, 11)
V 2
I CIH
0.8 *
V 2
I CINT
V 2
I COL
SDA low output voltage
I
= 3 mA (Note 11)
−
−
−
−
0.4
3.4
V
SINK
2
F
SCL
I C clock frequency
(Note 11)
MHz
TOTAL DEVICE
V
Under Voltage Lockout
V
V
falling
rising
−
60
−
−
−
2.3
200
−
V
mV
°C
°C
°C
°C
°C
°C
UVLO
IN
V
Under Voltage Lockout Hysteresis
Thermal Shut Down Protection
Warning Rising Edge
UVLOH
IN
T
150
135
105
30
15
6
SD
WARNING
T
−
−
2
T
PWTH
Pre − Warning Threshold
I C default value
−
−
T
Thermal Shut Down Hysteresis
Thermal warning Hysteresis
Thermal pre−warning Hysteresis
−
−
SDH
WARNINGH
T
−
−
T
−
−
PWTH H
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Refer to the Application Information section of this data sheet for more details.
2
10.Devices that use non−standard supply voltages which do not conform to the intent I C bus system levels must relate their input levels
to the V voltage to which the pull−up resistors R are connected.
DD
P
11. Guaranteed by design and characterized.
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NCV6336
TYPICAL OPERATING CHARACTERISTICS
AV = PV = 3.6 V, T = +25°C, DCDC = 1.15 V, Ipeak = 6.8 A (Unless otherwise noted).
IN
IN
J
L = 0.33 mH PIFE25201B – C
= 2 x 22 mF 0603, C = 4.7 mF 0603
OUT
IN
Figure 4. Efficiency vs ILOAD and VIN
VOUT = 1.39375 V, SPM5030 Inductor
Figure 5. Efficiency vs ILOAD and Temperature
OUT = 1.39375 V, SPM5030 Inductor
V
Figure 6. Efficiency vs ILOAD and VIN
VOUT = 1.15 V, SPM5030 Inductor
Figure 7. Efficiency vs ILOAD and Temperature
OUT = 1.15 V, SPM5030 Inductor
V
Figure 8. Efficiency vs ILOAD and VIN
VOUT = 0.60 V, SPM5030 Inductor
Figure 9. Efficiency vs ILOAD and Temperature
VOUT = 0.60 V, SPM5030 Inductor
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NCV6336
TYPICAL OPERATING CHARACTERISTICS
AV = PV = 3.6 V, T = +25°C, DCDC = 1.15 V, Ipeak = 6.8 A (Unless otherwise noted).
IN
IN
J
L = 0.33 mH PIFE25201B – C
= 2 x 22 mF 0603, C = 4.7 mF 0603
OUT
IN
Figure 10. Efficiency vs ILOAD and VIN
VOUT = 1.15 V
Figure 11. Efficiency vs ILOAD and Temperature
OUT = 1.15 V
V
Figure 12. VOUT Accuracy vs ILOAD and VIN
VOUT = 1.15 V
Figure 13. VOUT Accuracy vs VIN and
Temperature, VOUT = 1.15 V
Figure 14. VOUT Accuracy vs ILOAD and VIN
VOUT = 0.60 V
Figure 15. VOUT Accuracy vs ILOAD and VIN
VOUT = 1.39375 V
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NCV6336
TYPICAL OPERATING CHARACTERISTICS
AV = PV = 3.6 V, T = +25°C, DCDC = 1.15 V, Ipeak = 6.8 A (Unless otherwise noted).
IN
IN
J
L = 0.33 mH PIFE25201B – C
= 2 x 22 mF 0603, C = 4.7 mF 0603
OUT
IN
Figure 16. HSS RON vs VIN and Temperature
Figure 18. IOFF vs VIN and Temperature
Figure 20. IQ PFM vs VIN and Temperature
Figure 17. LSS RON vs VIN and Temperature
Figure 19. ISLEEP vs VIN and Temperature
Figure 21. IQ PWM vs VIN and Temperature
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NCV6336
TYPICAL OPERATING CHARACTERISTICS
AV = PV = 3.6 V, T = +25°C, DCDC = 1.15 V, Ipeak = 6.8 A (Unless otherwise noted).
IN
IN
J
L = 0.33 mH PIFE25201B – C
= 2 x 22 mF 0603, C = 4.7 mF 0603
OUT
IN
Figure 22. Switchover Point VOUT = 1.15 V
Figure 23. Switchover Point VOUT = 1.50 V
Figure 24. PWM Ripple 2 A Load
Figure 25. PFM Ripple
Figure 26. Normal Power Up, VOUT = 1.15 V
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NCV6336
TYPICAL OPERATING CHARACTERISTICS
AV = PV = 3.6 V, T = +25°C, DCDC = 1.15 V, Ipeak = 6.8 A (Unless otherwise noted).
IN
IN
J
L = 0.33 mH PIFE25201B – C
= 2 x 22 mF 0603, C = 4.7 mF 0603
OUT
IN
Figure 27. Transient Load 0.2 to 1.5 A − Single Shot
Transient Line 3.9 to 3.3 V − Auto Mode
Figure 28. Transient Load 0.2 to 1.5 A − Single Shot
Transient Line 3.3 to 3.9 V − Auto Mode
Figure 29. Transient Load 0.01 to 1.3 A − Multi Shot
Transient Line 3.9 to 3.3 V − Auto Mode
Figure 30. Transient Load 0.1 to 1.4 A − Multi Shot
Transient Line 3.9 to 3.3 V − PWM Mode
Figure 31. Transient Load 4 to 5.5 A −
Figure 32. Transient Load 0 mA / 600 mA to 1.2 A / 1.8 A
Single Shot Auto Mode
Transient Line 3.9 to 3.3 V − Auto Mode − Multi Shot
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NCV6336
DETAILED OPERATING DESCRIPTION
Forced PWM
Detailed Descriptions
The NCV6336 is voltage mode stand−alone synchronous
DC to DC converter optimized to supply different sub
systems of portable applications powered by one cell Li−Ion
or three cells Alkaline/NiCd/NiMh. The IC can deliver up to
The NCV6336 can be programmed to only use PWM and
disable the transition to PFM if so desired.
Output Stage
NCV6336 is a 3.5 A to 5.0 A output current capable
integrated DC to DC converter. To supply such a high
current, the internal MOSFETs need to be large.
2
5 A at an I C selectable voltage ranging from 0.6 V to 1.5 V.
It can share the same output rail with another DC to DC
converter and works as a transient load helper without
sinking current on shared rail. A 2.74 MHz switching
frequency allows the use of smaller output filter
components. Synchronous rectification and automatic
PWM/PFM transitions improve overall solution efficiency.
Forced PWM is also configurable. Operating modes,
configuration, and output power can be easily selected either
by using digital I/O pins or by programming a set of registers
Inductor Peak Current Limitation
During normal operation, peak current limitation will
monitor and limit the current through the inductor. This
current limitation is particularly useful when size and/or
height constrain inductor power. The user can select peak
current to keep inductor within its specifications. The peak
current can be set by writing IPEAK[1..0] bits in LIMCONF
register.
2
using an I C compatible interface capable of operation up to
2
3.4 MHz. Default I C settings are factory programmable.
Table 1. IPEAK VALUES
DC to DC Converter Operation
IPEAK[1..0]
Inductor Peak Current (A)
5.2 − for 3.5 output current
5.8 − for 4.0 output current
6.2 − for 4.5 output current
6.8 − for 5.0 output current
The converter is a synchronous rectifier type with both
high side and low side integrated switches. Neither external
transistor nor diodes are required for NCV6336 operation.
Feedback and compensation network are also fully
integrated. The converter can operate in two different
modes: PWM and PFM. The transition between PWM/PFM
modes can occur automatically or the switcher can be placed
00
01
10
11
Output Voltage
2
in forced PWM mode by I C programming (PWMVSEL0
Output voltage is set internally by integrated resistor
bridge and error amplifier that drives the PWM/PFM
controller. No extra component is needed to set output
voltage. However, writing in the VoutVSEL0[6..0] bits of
the PROGVSEL0 register or VoutVSEL1[6..0] bits of the
PROGVSEL1 register will change settings. Output voltage
level can be programmed in the 0.6 V to 1.40 V range by
6.25 mV steps.
The VSEL pin and VSELGT bit will determine which
register between PROGVSEL0 and PROGVSEL1 will set
the output voltage.
• If VSELGT = 1 AND VSEL=0 ³ Output voltage is set
by VoutVSEL0[6..0] bits (PROGVSEL0 register)
• Else ³ Output voltage is set by VoutVSEL1[6..0] bits
(PROGVSEL1 register)
/ PWMVSEL1 bits of COMMAND register).
PWM (Pulse Width Modulation) Operating Mode
In medium and high load conditions, NCV6336 operates
in PWM mode from a fixed clock and adapts its duty cycle
to regulate the desired output voltage. In this mode, the
inductor current is in CCM (Continuous Current Mode) and
the voltage is regulated by PWM. The internal N−MOSFET
switch operates as synchronous rectifier and is driven
complementary to the P−MOSFET switch. In CCM, the
lower switch (N−MOSFET) in a synchronous converter
provides a lower voltage drop than the diode in an
asynchronous converter, which provides less loss and higher
efficiency.
PFM (Pulse Frequency Modulation) Operating Mode
In order to save power and improve efficiency at low loads
the NCV6336 operates in PFM mode as the inductor current
drops into DCM (Discontinuous Current Mode). The upper
FET on time is kept constant and the switching frequency is
variable. Output voltage is regulated by varying the
switching frequency which becomes proportional to loading
current. As it does in PWM mode, the internal N−MOSFET
operates as synchronous rectifier after each P−MOSFET
on−pulse. When load increases and current in inductor
becomes continuous again, the controller automatically
turns back to PWM mode.
Under Voltage Lock Out (UVLO)
NCV6336 core does not operate for voltages below the
Under Voltage Lock Out (UVLO) level. Below UVLO
threshold, all internal circuitry (both analog and digital) is
held in reset.
NCV6336 operation is guaranteed down to VUVLO
when battery voltage is dropping off. To avoid erratic on / off
behavior, a maximum 200 mV hysteresis is implemented.
Restart is guaranteed at 2.5 V when VBAT voltage is
recovering or rising.
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12
NCV6336
Thermal Management
When EN pin is set to a high level, the DC to DC converter
can be enabled / disabled by writing the ENVSEL0 or
ENVSEL1 bit of the PROGVSEL0 and PROGVSEL1
Thermal Shut Down (TSD)
The thermal capability of IC can be exceeded due to step
down converter output stage power level. A thermal
protection circuitry is therefore implemented to prevent the
IC from damage. This protection circuitry is only activated
when the core is in active mode (output voltage is turned on).
During thermal shut down, output voltage is turned off.
When NCV6336 returns from thermal shutdown, it can
re−start in 2 different configurations depending on REARM
bit in the LIMCONF register (see register description
section):
2
registers: If ENx I C bit is high, DC to DC converter is
2
activated, If ENx I C is low the DC to DC converter is turned
off and device enters in Sleep Mode
A built in pull down resistor disables the device when this
pin is left unconnected or not driven. EN pin activity does
not generate any digital reset.
Power Up Sequence (PUS)
In order to power up the circuit, the input voltage AVIN
has to rise above the VUVLO threshold. This triggers the
internal core circuitry power up which is the “Wake Up
Time” (including “Bias Time”).
This delay is internal and cannot be bypassed. EN pin
transition within this delay corresponds to the “Initial power
up sequence” (IPUS):
• If REARM = 0 then NCV6336 does not re−start after
TSD. To restart, an EN pin toggle is required.
• If REARM = 1, NCV6336 re−starts with register values
set prior to thermal shutdown.
A Thermal shut down interrupt is raised upon this event.
Thermal shut down threshold is set at 150°C (typical)
when the die temperature increases and, in order to avoid
erratic on / off behavior, a 30°C hysteresis is implemented.
After a typical 150°C thermal shut down, NCV6336 will
resume to normal operation when the die temperature cools
to 120°C.
AVIN
UVLO
POR
EN
DELAY[2..0]
VOUT
~ 750us
35 us
Thermal Warnings
In addition to the TSD, the die temperature monitoring
will flag potential die over temperature. A thermal warning
and thermal pre−warning sensor and interrupts are
implemented. These can inform the processor that
NCV6336 is closed to its thermal shutdown, so preventive
measures to cool down die temperature can be taken by
software.
The Warning threshold is set by hardware to 135°C typical
when the die temperature increases. The Pre−Warning
threshold is set by default to 105°C, but can be changed by
user by setting the TPWTH[1..0] bits in the LIMCONF
register.
Wake up
Time
Init DVS ramp
Time
Time
Figure 33. Initial Power Up Sequence
In addition a user programmable delay will also take place
between end of Core circuitry turn on (Wake Up Time and
Bias Time) and Init time: The DELAY[2..0] bits of TIME
register will set this user programmable delay with a 2.2 ms
resolution. With default delay of 0 ms, the NCV6336 IPUS
takes roughly 900 ms, means DC to DC converter output
voltage will be ready within 1 ms.
The power up output voltage is defined by VSEL state.
Active Output Discharge
2
NOTE: During the Wake Up time, the I C interface is not
active. Any I C request to the IC during this time period will
result in a NACK reply.
To make sure that no residual voltage remains in the power
supply rail when disabled, an active discharge path can
ground the NCV6336 output voltage.
2
For maximum flexibility, this feature can be easily
disabled or enabled with DISCHG bit in PGOOD register.
By default the discharge path is enabled.
However the discharged path is activated during the first
100 ms after battery insertion.
Normal, Quick and Fast Power Up Sequence
The previous description applies only when the EN
transitions during the internal core circuitry power up (Wake
up and calibration time). Otherwise 3 different cases are
possible:
• Enabling the part by setting EN pin from Off Mode will
result in “Normal power up sequence” (NPUS, with
DELAY;[2..0]).
• Enabling the part by setting EN pin from Sleep Mode
will result in “Quick power up sequence” (QPUS, with
DELAY;[2..0]).
Enabling
The EN pin controls NCV6336 start up. EN pin Low to
High transition starts the power up sequencer. If EN is made
low, the DC to DC converter is turned off and device enters:
2
• In Sleep Mode if Sleep_Mode I C bit is high or VSEL
is high,
2
• In Off Mode if Sleep_Mode I C bit and VSEL are low.
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13
NCV6336
DC to DC converter shutdown is initiated by either
• Enabling the DC to DC converter, whereas EN is
already high, either by setting ENVSEL0 or ENVSEL1
bits or by VSEL pin transition will results in “Fast
power up sequence” (FPUS, without DELAY[2..0]).
Sleep mode is when VSEL is high and EN low, or when
grounding the EN pin (Hardware Shutdown) or, depending
on the VSEL internal signal level, by clearing the ENVSEL0
or ENVSEL1 bits (Software shutdown) in PROGVSEL0 or
PROGVSEL1 registers.
2
In hardware shutdown (EN = 0), the internal core is still
Sleep_Mode I C bit is set and EN is low, or finally when DC
to DC converter is off and EN high.
2
active and I C accessible.
NCV6336 shuts internal core down when AVIN falls
below UVLO.
AVIN
UVLO
POR
Dynamic Voltage Scaling (DVS)
This converter supports dynamic voltage scaling (DVS)
allowing the output voltage to be reprogrammed via I C
EN
S
L
E
E
P
2
commands and provides the different voltages required by
the processor. The change between set points is managed in
a smooth fashion without disturbing the operation of the
processor.
M
O
D
E
DELAY[2..0]
VOUT
35 us
TFTR
Init
Time
DVS ramp
Time
When programming a higher voltage, output raises with
controlled dV/dt defined by DVS[1..0] bits in TIME
register. When programming a lower voltage the output
voltage will decrease accordingly.
Figure 34. Normal Power Up Sequence
AVIN
The DVS step is fixed and the speed is programmable.
DVS sequence is automatically initiated by changing
output voltage settings. There are two ways to change these
settings:
UVLO
POR
EN
S
L
E
E
P
• Directly change the active setting register value
M
O
D
E
DELAY[2..0]
35 us
VOUT
(VoutVSEL0[6..0] of PROGVSEL0 register or
2
VoutVSEL1[6..0] of the PROGVSEL1 register) via I C
command
TFTR
Init
Time
DVS ramp
Time
• Change the VSEL internal signal level by toggling
Figure 35. Quick Power Up Sequence
VSEL pin.
2
The second method eliminates the I C latency and is
AVIN
therefore faster.
The DVS transition mode can be changed with the
DVSMODE bit in COMMAND register:
UVLO
POR
VSEL
S
L
• In forced PWM mode when accurate output voltage
E
E
P
control is needed.
M
O
D
E
VOUT
35 us
V2
Internal
Output
Reference
Voltage
TFTR Init
Time
DVS ramp
Time
DV
Figure 36. Fast Power Up Sequence
Dt
In addition the delay set in DELAY[2..0] bits in TIME
register will apply only for the EN pins turn ON sequence
(NPUS and QPUS).
V1
Figure 37. DVS in Forced PWM Mode Diagram
The power up output voltage is defined by VSEL state.
Note that the sleep mode needs about 150 ms to be
established.
• In Auto mode when output voltage has not to be
discharged. Note that approximately 30 ms is needed to
transition from PFM mode to PWM mode.
DC to DC Converter Shut Down
When shutting down the device, no shut down sequence
is required. Output voltage is disabled and, depending on the
DISCHG bit state of PGOOD register, output may be
discharged.
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14
NCV6336
Power Good operation during DVS can be controlled by
setting / clearing the bit PGDVS in PGOOD register
V2
Output
Voltage
Internal
Reference
DV
Dt
DCDC_EN
V1
95%
90%
32 us
min
Figure 38. DVS in Auto Mode Diagram
DCDC
3.5−
14 us
3.5−
14 us
3.5 us
PG
Digital IO Settings
Figure 39. Power Good Signal
VSEL Pin
By changing VSEL pin levels, the user has a latency free
way to change NCV6336 configuration: operating mode
(Auto or PWM forced), the output voltage as well as enable.
Power Good Delay
In order to generate a Reset signal, a delay can be
programmed between the output voltage gets 95% of its
final value and Power Good pin is released to high level.
The delay is set from 0 ms to 70.4 ms through the
TOR[1..0] bits in the TIME register. The default delay is
0 ms.
Table 2. VSEL PIN PARAMETERS
Parameter VSEL
Pin Can Set
REGISTER
VSEL = LOW
REGISTER
VSEL = HIGH
ENABLE
ENVSEL0
PROGVSEL0[7]
ENVSEL1
PROGVSEL1[7]
Vout
VOUT
VoutVSEL0[6..0]
VoutVSEL1[6..0]
OPERATING MODE
(Auto / PWM Forced)
PWMVSEL0
COMMAND[7]
PWMVSEL1
COMMAND[6]
PG
No
TOR[2:0]
Delay
VSEL pin action can be masked by writing 0 to the
VSELGT bit in the COMMAND register. In that case I C bit
corresponding to VSEL high will be taken into account.
2
Delay Programmed in
TOR [2:0]
Figure 40. Power Good Operation
EN Pin
The EN pin can be gated by writing the ENVSEL0 or
ENVSEL1 bits of the PROGVSEL0 and PROGVSEL1
registers, depending on which register is activated by the
VSEL internal signal.
Interrupt Pin (Optional)
The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when a
system status change is detected (dual edge monitoring).
Power Good Pin (Optional)
To indicate the output voltage level is established, a power
good signal is available.
Table 3. INTERRUPT SOURCES
Interrupt Name
TSD
Description
Thermal Shut Down
The power good signal is low when the DC to DC
converter is off. Once the output voltage reaches 95% of the
expected output level, the power good logic signal becomes
high and the open drain output becomes high impedance.
During operation when the output drops below 90% of the
programmed level the power good logic signal goes low (and
the open drain signal transitions to a low impedance state)
which indicates a power failure. When the voltage rises
again to above 95% the power good signal goes high again.
During a positive DVS sequence, when target voltage is
higher than initial voltage, the Power Good logic signal will
be set low during output voltage ramping and transition to
high once the output voltage reaches 95% of the target
voltage. When the target voltage is lower than the initial
voltage, Power Good pin will remain at high level during
transition.
TWARN
TPREW
UVLO
Thermal Warning
Thermal Pre Warning
Under Voltage Lock Out
DC to DC converter current Over / below limit
Power Good
IDCDC
PG
Individual bits generating interrupts will be set to 1 in the
2
INT_ACK register (I C read only registers), indicating the
interrupt source. INT_ACK register is automatically reset
2
by an I C read. The INT_SEN register (read only register)
contains real time indicators of interrupt sources.
All interrupt sources can be masked by writing in register
INT_MSK. Masked sources will never generate an interrupt
request on INTB pin.
The INTB pin is an open drain output. A non masked
interrupt request will result in INTB pin being driven low.
Power Good signal during normal operation can be
disabled by clearing the PGDCDC bit in PGOOD register.
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15
NCV6336
When the host reads the INT_ACK registers the INTB pin
UVLO
is released to high impedance and the interrupt register
INT_ACK is cleared.
SEN_UVLO
MASK_UVLO
Figure 41 is UVLO event example: INTB pin with
2
INT_SEN/INT_MSK/INT_ACK and an I C read access
ACK_UVLO
INTB
behavior.
2
I C access on INT_ACK
read
read
read
read
Figure 41. Interrupt Operation Example
INT_MSK register is set to disable INTB feature by
default.
Configurations
Default output voltages, enables, DCDC modes, current limit and other parameters can be factory programmed upon request.
Below is the default configurations pre−defined:
Configuration
NCV6336BM − 5.0 A
NCV6336C − 5.0 A
2
Default I C address
0x1C
15h
xxh
0x1C
15h
xxh
PID product identification
RID revision identification
FID feature identification
00h
00h
Default VOUT – VSEL=1
Default VOUT – VSEL=0
Default MODE – VSEL=1
Default MODE – VSEL=0
Default IPEAK
1.20 V
1.20 V
1.15 V
1.15 V
Auto mode − ON
Auto mode − ON
6.8 A
Auto mode − ON
Auto mode − ON
6.8 A
OPN
NCV6336BMFCCT1G
6336BM
NCV6336CFCCT1G
6336CV
Marking
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NCV6336
2
I C Compatible Interface
NCV6336 can support a subset of I C protocol Detailed below.
2
I2C Communication Description
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
1
0
DATA 1
IC ADDRESS
ACK
ACK
/ACK
READ OUT FROM PART
WRITE INSIDE PART
START
ACK
ACK
DATA n
DATA n
STOP
STOP
1
READ
à
/ACK
ACK
IC ADDRESS
DATA 1
START
If PART does not Acknowledge, the /NACK will be followed by a STOP or Sr.
If PART Acknowledges, the ACK can be followed by another data or STOP or Sr
0
WRITE
à
Figure 42. General Protocol Description
The first byte transmitted is the Chip address (with the LSB bit set to 1 for a read operation, or set to 0 for a Write operation).
The following data will be:
• In case of a Write operation, the register address (@REG) pointing to the register we want to write in followed by the
data we will write in that location. The writing process is auto−incremental, so the first data will be written in @REG,
the contents of @REG are incremented and the next data byte is placed in the location pointed to by @REG + 1 …, etc.
• In case of read operation, the NCV6336 will output the data from the last register that has been accessed by the last
write operation. Like the writing process, the reading process is auto−incremental.
Read Out from Part
The Master will first make a “Pseudo Write” transaction with no data to set the internal address register. Then, a stop then
start or a Repeated Start will initiate the read transaction from the register address the initial write transaction has pointed to:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
0
ACK
ACK STOP
IC ADDRESS
REGISTER ADDRESS
START
0
WRITE
à
/ACK
1
DATA 1
DATA n
STOP
START
IC ADDRESS
ACK
ACK
REGISTER ADDRESS + (n−1)
REGISTER ADDRESS
VALUE
VALUE
n REGISTERS READ
1
READ
à
Figure 43. Read Out from Part
The first WRITE sequence will set the internal pointer to the register we want access to. Then the read transaction will start
at the address the write transaction has initiated.
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NCV6336
Transaction with Real Write then Read
With Stop Then Start
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
WRITE VALUE IN
REGISTER REG0 + (n−1)
WRITE VALUE IN
REGISTER REG0
ACK
START
IC ADDRESS
0
REGISTER REG0 ADDRESS
ACK
REG VALUE
ACK
REG+ (n– 1) VALUE
ACK
STOP
n REGISTERS WRITE
à
0
WRITE
ACK
START
IC ADDRESS
1
DATA 1
ACK
DATA k
/ACK
STOP
REGISTER REG + (n−1)
REGISTER ADDRESS + (n−1) +
(k−1) VALUE
VALUE
k REGISTERS READ
à
1
READ
Figure 44. Write Followed by Read Transaction
Write in Part
Write operation will be achieved by only one transaction. After chip address, the MCU first data will be the internal register
we want access to, then following data will be the data we want to write in Reg, Reg + 1, Reg + 2, …, Reg +n.
Write n Registers:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
WRITE VALUE IN
REGISTER REG0 + (n−1)
WRITE VALUE IN
REGISTER REG0
START
IC ADDRESS
0
ACK
REGISTER REG0 ADDRESS
REG VALUE
ACK
REG + (n−1) VALUE
ACK
STOP
ACK
n REGISTERS WRITE
0àWRITE
Figure 45. Write in n Registers
I2C Address
2
NCV6336 has four available I C address selectable by factory settings (ADD0 to ADD3). Different address settings can be
generated upon request to ON Semiconductor. The default address is set to 38h / 39h since the NCV6336 supports 7−bit address
only and ignores A0.
Table 4. I2C ADDRESS
2
I C Address
Hex
A7
A6
A5
A4
A3
A2
A1
A0
ADD0
W 0x20
R 0x21
0
0
1
0
0
0
0
R/W
Add
0x10
0
−
ADD1
ADD2
W 0x28
R 0x29
0
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
R/W
Add
0x14
1
−
W 0x30
R 0x31
R/W
Add
0x18
1
−
ADD3 (default)
W 0x38
R 0x39
R/W
Add
0x1C
−
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NCV6336
Register Map
Table 5 describes I C registers.
Registers / bits can be:
2
R
Read only register
RC
Read then Clear
RW
Read and Write register
Reserved
Spare
Address is reserved and register/bit is not physically designed
Address is reserved and register/bit is physically designed
Table 5. I2C REGISTERS MAP 5 A CONFIGURATION (NCV6336BM)
Add.
00h
Register Name
INT_ACK
INT_SEN
INT_MSK
PID
Type
RC
R
Def.
00h
01h
FFh
15h
xxh
00h
−
Function
Interrupt register
01h
Sense register (real time status)
02h
RW
R
Mask register to enable or disable interrupt sources (trim)
Product Identification
03h
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 0Fh
10h
−
−
Reserved for future use
PROGVSEL1
PROGVSEL0
PGOOD
TIME
RW
RW
RW
RW
RW
RW
RW
−
E0h
E0h
10h
01h
01h
80h
E3h
−
Output voltage settings and EN for VSEL pin = High (trim)
Output voltage settings and EN for VSEL pin = Low (trim)
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
11h
12h
13h
14h
COMMAND
MODULE
LIMCONF
−
Enabling and Operating mode Command register (trim)
Active module count settings (test)
Reset and limit configuration register (trim)
Reserved for future use
15h
16h
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
Table 6. I2C REGISTERS MAP 5 A CONFIGURATION (NCV6336C)
Add.
00h
Register Name
INT_ACK
INT_SEN
INT_MSK
PID
Type
RC
R
Def.
00h
01h
FFh
15h
xxh
00h
−
Function
Interrupt register
01h
Sense register (real time status)
02h
RW
R
Mask register to enable or disable interrupt sources (trim)
Product Identification
03h
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 0Fh
10h
−
−
Reserved for future use
PROGVSEL1
PROGVSEL0
PGOOD
TIME
RW
RW
RW
RW
RW
RW
RW
−
D8h
D8h
10h
01h
01h
80h
E3h
−
Output voltage settings and EN for VSEL pin = High (trim)
Output voltage settings and EN for VSEL pin = Low (trim)
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
11h
12h
13h
14h
COMMAND
MODULE
LIMCONF
−
Enabling and Operating mode Command register (trim)
Active module count settings (test)
Reset and limit configuration register (trim)
Reserved for future use
15h
16h
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
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NCV6336
Registers Description
Table 7. INTERRUPT ACKNOWLEDGE REGISTER
Name: INTACK
Address: 00h
Default: 00000000b (00h)
Type: RC
Trigger: Dual Edge [D7..D0]
D7
D6
D5
D4
D3
D2
D1
D0
ACK_TSD
ACK_TWARN
ACK_TPREW
Spare = 0
Spare = 0
ACK_UVLO
ACK_IDCDC
ACK_PG
Bit
Bit Description
ACK_PG
ACK_IDCDC
ACK_UVLO
ACK_TPREW
ACK_TWARN
ACK_TSD
Power Good Sense Acknowledgement
0: Cleared
1: DCDC Power Good Event detected
DCDC Over Current Sense Acknowledgement
0: Cleared
1: DCDC Over Current Event detected
Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event detected
Thermal Pre Warning Sense Acknowledgement
0: Cleared
1: Thermal Pre Warning Event detected
Thermal Warning Sense Acknowledgement
0: Cleared
1: Thermal Warning Event detected
Thermal Shutdown Sense Acknowledgement
0: Cleared
1: Thermal Shutdown Event detected
Table 8. INTERRUPT SENSE REGISTER
Name: INTSEN
Type: R
Address: 01h
Default: 00000000b (00h)
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
SEN_TSD
SEN_TWARN
SEN_TPREW
Spare = 0
Spare = 0
SEN_UVLO
SEN_IDCDC
SEN_PG
Bit
Bit Description
SEN_PG
SEN _IDCDC
SEN _UVLO
SEN _TPREW
SEN _TWARN
SEN _TSD
Power Good Sense
0: DCDC Output Voltage below target
1: DCDC Output Voltage within nominal range
DCDC over current sense
0: DCDC output current is below limit
1: DCDC output current is over limit
Under Voltage Sense
0: Input Voltage higher than UVLO threshold
1: Input Voltage lower than UVLO threshold
Thermal Pre Warning Sense
0: Junction temperature below thermal pre−warning limit
1: Junction temperature over thermal pre−warning limit
Thermal Warning Sense
0: Junction temperature below thermal warning limit
1: Junction temperature over thermal warning limit
Thermal Shutdown Sense
0: Junction temperature below thermal shutdown limit
1: Junction temperature over thermal shutdown limit
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NCV6336
Table 9. INTERRUPT MASK REGISTER
Name: INTMASK
Type: RW
Address: 02h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
MASK_TSD
MASK_TWARN
MASK_TPREW
Spare = 1
Spare = 1
MASK_UVLO
MASK_IDCDC
MASK_PG
Bit
Bit Description
MASK_PG
MASK _IDCDC
MASK _UVLO
MASK _TPREW
MASK _TWARN
MASK _TSD
Power Good interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
DCDC over current interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Under Voltage interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Thermal Pre Warning interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Thermal Warning interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Thermal Shutdown interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Table 10. PRODUCT ID REGISTER
Name: PID
Type: R
Address: 03h
Default: 00010101b (15h)
Reset on N/A
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
PID_7
PID_6
PID_5
PID_4
PID_3
PID_2
PID_1
PID_0
Table 11. REVISION ID REGISTER
Name: RID
Type: R
Address: 04h
Default: xxh
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
RID_7
RID_6
RID_5
RID_4
RID_3
RID_2
RID_1
RID_0
Bit
RID[7..0]
Bit Description
Revision Identification
00000000
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NCV6336
Table 12. FEATURE ID REGISTER
Name: FID
Type: R
Address: 05h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare
Spare
Spare
Spare
FID_3
FID_2
FID_1
FID_0
Bit
FID[3..0]
Bit Description
Feature Identification
00000000: NCV6336 5.0 A configuration
Table 13. DC TO DC VOLTAGE PROG (VSEL = 1) REGISTER
Name: PROGVSEL1
Type: RW
Trigger: N/A
D7
Address: 10h
Default: See Register map
D6
D5
D4
D3
D2
D1
D0
ENVSEL1
Bit
VoutVSEL1[6..0]
Bit Description
VoutVSEL1[6..0]
Sets the DC to DC converter output voltage when VSEL pin = 1 and VSEL pin function is enabled in register
COMMAND.D0, or when VSEL pin function is disabled in register COMMAND.D0
0000000b = 600 mV – 1111111b = 1393.75 mV (steps of 6.25 mV)
ENVSEL1
EN Pin Gating for VSEL internal signal = High
0: Disabled
1: Enabled
Table 14. DC TO DC VOLTAGE PROG (VSEL = 0) REGISTER
Name: PROGVSEL0
Type: RW
Address: 11h
Default: See Register map
Trigger: N/A
D7
ENVSEL0
Bit
D6
D5
D4
D3
D2
D1
D0
VoutVSEL0[6..0]
Bit Description
VoutVSEL0[6..0]
Sets the DC to DC converter output voltage when VSEL pin = 0 and VSEL pin function is enabled in register
COMMAND.D0
0000000b = 600 mV – 1111111b = 1393.75 mV (steps of 6.25 mV)
ENVSEL0
EN Pin Gating for VSEL internal signal = Low
0: Disabled
1: Enabled
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22
NCV6336
Table 15. POWER GOOD REGISTER
Name: PGOOD
Address: 12h
Default: See Register map
Type: RW
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 0
Bit
Spare = 0
Spare = 0
DISCHG
TOR[1..0]
PGDVS
PGDCDC
Bit Description
PGDCDC
Power Good Enabling
0 = Disabled
1 = Enabled
PGDVS
Power Good Active On DVS
0 = Disabled
1 = Enabled
TOR[1..0]
Time out Reset settings for Power Good
00 = 0 ms
01 = 8.8 ms
10 = 35.2 ms
11 = 70.4 ms
DISCHG
Active discharge bit Enabling
0 = Discharge path disabled
1 = Discharge path enabled
Table 16. TIMING REGISTER
Name: TIME
Address: 13h
Default: See Register map
Type: RW
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
DELAY[2..0]
DVS[1..0]
Spare = 0
DBN_Time[1..0]
Bit
Bit Description
DBN_Time[1..0]
EN and VSEL debounce time
00 = No debounce
01 = 1.1−2.2 ms
10 = 2.2−3.3 ms
11 = 3.3−4.4 ms
DVS[1..0]
DVS Speed
00 = 6.25 mV step / 0.365 ms
01 = 6.25 mV step / 0.730 ms
10 = 6.25 mV step / 1.460 ms
11 = 6.25 mV step / 2.920 ms
DELAY[2..0]
Delay applied upon enabling (ms)
000b = 0 ms − 111b = 15.4 ms (Steps of 2.2 ms)
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23
NCV6336
Table 17. COMMAND REGISTER
Name: COMMAND
Type: RW
Address: 14h
Default: See Register map
Trigger: N/A
D7
PWMVSEL0
Bit
D6
D5
D4
D3
D2
D1
D0
PWMVSEL1
DVSMODE
Spare = 0
Spare = 0
Spare = 0
Spare = 0
VSELGT
Bit Description
VSELGT
VSEL Pin Gating
0 = Disabled
1 = Enabled
DVSMODE
PWMVSEL1
PWMVSEL0
DVS transition mode selection
0 = Auto
1 = Forced PWM
Operating mode for VSEL internal signal = High
0 = Auto
1 = Forced PWM
Operating mode for VSEL internal signal = Low
0 = Auto
1 = Forced PWM
Table 18. OUTPUT STAGE MODULE SETTINGS REGISTER
Name: MODULE
Type: RW
Trigger: N/A
D7
Address: 15h
Default: 10000000b (80h)
D6
D5
D4
D3
D2
D1
D0
MODUL[3..0]
Spare = 0
Spare = 0
Spare = 0
Spare = 0
Bit
Bit Description
MODUL [3..0]
Number of modules
0000 = 1 Module
0001 = 2 Modules
0010 ~ 1111 = 9 Modules
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24
NCV6336
Table 19. LIMITS CONFIGURATION REGISTER
Name: LIMCONF
Type: RW
Adress: 16h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
IPEAK[1..0]
TPWTH[1..0]
Spare = 0
Spare = 0
RSTSTATUS
REARM
Bit
Bit Description
REARM
Rearming of device after TSD
0: No re−arming after TSD
2
1: Re−arming active after TSD with no reset of I C registers: new power−up sequence is initiated with
2
previously programmed I C registers values
RSTSTATUS
TPWTH[1..0]
Reset Indicator Bit
0: Must be written to 0 after register reset
1: Default (loaded after Registers reset)
Thermal pre−Warning threshold settings
00 = 83°C
01 = 94°C
10 = 105°C
11 = 116°C
IPEAK
Inductor peak current settings
00 = 5.2 A (for 3.5 A output current)
01 = 5.8 A (for 4.0 A output current)
10 = 6.2 A (for 4.5 A output current)
11 = 6.8 A (for 5.0 A output current)
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25
NCV6336
APPLICATION INFORMATION
NCV6336
AVIN
PVIN
D1
D2
E1
E2
Supply Input
Core
AGND
B4
4.7 uF
Thermal
Protection
D3
D4
E3
E4
Enable Control EN
DCDC
5 A
A2
A1
SW
Input
Operating
Mode
Control
330 nH
Voltage VSEL
Selection
47 uF
C1
C2
C3
C4
PGND
FB
Output
Monitoring
PGND
Power Fail
PG
B3
PGND
Interrupt
B2
B1
INTB
A4
DCDC
2.74 MHz
Controller
Processor
Core
SDA
I2C
Sense
Processor I2C
Control Interface
SCL
A3
Figure 46. Typical Application Schematic
Output Filter Design Considerations
The output filter introduces a double pole in the system at
a frequency of:
Components Selection
Inductor Selection
The inductance of the inductor is determined by given
peak−to−peak ripple current I of approximately 20% to
50% of the maximum output current I
trade−off between transient response and output ripple. The
L_PP
1
fLC
+
for a
OUT_MAX
(eq. 1)
Ǹ
2 @ p @ L @ C
The NCV6336 internal compensation network is
optimized for a typical output filter comprising a 330 nH
inductor and 47 mF capacitor as described in the basic
application schematic shown in Figure 46.
inductance corresponding to the given current ripple is:
ǒV
Ǔ
IN * VOUT @ VOUT
IN @ fSW @ IL_PP
(eq. 2)
L +
V
The selected inductor must have high enough saturation
current rating to be higher than the maximum peak current
that is
Voltage Sensing Considerations
In order to regulate power supply rail, NCV6336 should
sense its output voltage. Thanks to the FB pin, the IC can
support two sensing methods:
• Normal case: the voltage sensing is achieved close to
the output capacitor. In that case, FB is connected to the
output capacitor positive terminal (voltage to regulate).
• Remote sensing: In remote sensing, the power supply
rail sense is made close to the system powered by the
NCV6336. The voltage to system is more accurate,
since PCB line impedance voltage drop is within the
regulation loop. In that case, we recommend connecting
the FB pin to the system decoupling capacitor positive
terminal.
IL_PP
(eq. 3)
I
L_MAX + IOUT_MAX )
2
The inductor also needs to have high enough current
rating based on temperature rise concern. Low DCR is good
for efficiency improvement and temperature rise reduction.
Table 20 shows recommended.
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26
NCV6336
Table 20. INDUCTOR SELECTION
Value
(mH)
Size (mm)
Saturation
Current Max (A)
DCR Max at 255C
(mW)
(L x l x T) (mm)
2.0 x 1.6 x 1.2
2.5 x 2.0 x 1.2
3.2 x 2.5 x 1.2
2.0 x 1.6 x 1.2
2.5 x 2.0 x 1.2
4.2 x 4.2 x 1.2
2.5 x 2.0 x 1.2
7.1 x 6.5 x 3.0
Supplier
Cyntec
Cyntec
Cyntec
TOKO
TOKO
TOKO
TDK
Part #
PIFE20161B−R33MS−11
PIFE25201B−R33MS−11
PIFE32251B−R33MS−11
DFE201612P−H−R30M
DFE252012P−H−R33M
FDSD0412−H−R33M
VLS252012HBX−R33M
SPM5030T−R35M
0.33
0.33
0.33
0.30
0.33
0.33
0.33
0.35
4.0
5.2
6.5
4.8
5.2
7.5
5.3
14.9
33
17
14
29
24
19
25
4
TDK
Output Capacitor Selection
Input Capacitor Selection
The output capacitor selection is determined by output
voltage ripple and load transient response requirement. For
high transient load performance high output capacitor value
One of the input capacitor selection guides is the input
voltage ripple requirement. To minimize the input voltage
ripple and get better decoupling in the input power supply
rail, ceramic capacitor is recommended due to low ESR and
ESL. The minimum input capacitance regarding to the input
must be used. For a given peak−to−peak ripple current I
L_PP
in the inductor of the output filter, the output voltage ripple
across the output capacitor is the sum of three components
as below.
ripple voltage V
is
IN_PP
2
ǒ Ǔ
OUT_MAX @ D * D
I
(eq. 10)
V
OUT_PP [ VOUT_PP(C) ) VOUT_PP(ESR) ) VOUT_PP(ESL)
,
CIN_MIN
+
V
IN_PP @ fSW
(eq. 4)
where
Where V
is a ripple component by an equivalent
OUT_PP(C)
VOUT
VIN
total capacitance of the output capacitors, V
is
OUT_PP(ESR)
(eq. 11)
D +
a ripple component by an equivalent ESR of the output
capacitors, and V is a ripple component by an
OUT_PP(ESL)
In addition, the input capacitor needs to be able to absorb
the input current, which has a RMS value of
equivalent ESL of the output capacitors. In PWM operation
mode, the three ripple components can be obtained by
Ǹ
IN_RMS + IOUT_MAX @
D * D2
(eq. 12)
I
IL_PP
(eq. 5)
VOUT_PP(C)
+
,
The input capacitor also needs to be sufficient to protect
the device from over voltage spike, and normally at least
4.7 mF capacitor is required. The input capacitor should be
located as close as possible to the IC. All PGNDs are
connected together to the ground terminal of the input cap
which then connects to the ground plane. All PVIN are
connected together to the Vbat terminal of the input cap
which then connects to the Vbat plane.
8 @ C @ fSW
and
V
OUT_PP(ESR) + IL_PP @ ESR
(eq. 6)
(eq. 7)
ESL
VOUT_PP(ESL)
+
@ VIN
ESL ) L
and the peak−to−peak ripple current is
ǒV
Ǔ
Electrical Layout Considerations
IN * VOUT @ VOUT
IN @ fSW @ L
(eq. 8)
IL_PP
+
Good electrical layout is a key to ensuring proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
• Use wide and short traces for power paths (such as
PVIN, VOUT, SW, and PGND) to reduce parasitic
inductance and high−frequency loop area. It is also
good for efficiency improvement.
• The device should be well decoupled by input capacitor
and input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission.
V
In applications with all ceramic output capacitors, the
main ripple component of the output ripple is V
So that the minimum output capacitance can be calculated
regarding to a given output ripple requirement V
PWM operation mode.
.
OUT_PP(C)
in
OUT_PP
IL_PP
(eq. 9)
CMIN
+
8 @ VOUT_PP @ fSW
• SW node should be a large copper, but compact
because it is also a noise source.
www.onsemi.com
27
NCV6336
• It would be good to have separated ground planes for
PGND and AGND and connect the two planes at one
point. Try best to avoid overlap of input ground loop
and output ground loop to prevent noise impact on
output regulation.
• Arrange a “quiet” path for output voltage sense, and
make it surrounded by a ground plane.
Thermal Layout Considerations
Good PCB layout helps high power dissipation from a
small package with reduced temperature rise. Thermal
layout guidelines are:
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More free vias are welcome to be around IC to connect
the inner ground layers to reduce thermal impedance.
• Use large area copper especially in top layer to help
thermal conduction and radiation.
• Use two layers for the high current paths (PVIN,
PGND, SW) in order to split current in two different
paths and limit PCB copper self heating.
Figure 48. Demo Board Example
(See demo board example Figure 48)
Input capacitor placed as close as possible to the IC.
PVIN directly connected to Cin input capacitor, and then
connected to the Vin plane. Local mini planes used on the top
layer (green) and layer just below top layer (yellow) with
laser vias.
4.3 mm
0603
47 uF
AVIN connected to the Vin plane just after the capacitor.
AGND directly connected to the GND plane.
2.3 x 1.2 mm
PGND directly connected to Cin input capacitor, and then
connected to the GND plane: Local mini planes used on the
top layer (green) and layer just below top layer (yellow) with
laser vias.
AGND PGND
FB
SCL
EN
SW
SW
SW
SW
PGND
PGND
PG
PGND
PGND PVIN
PGND AVIN
PVIN
PVIN
INTB
SW connected to the Lout inductor with local mini planes
used on the top layer (green) and layer just below top layer
(yellow) with laser vias.
SDA
VSEL
Legend:
0603
In green are top layer planes and wires
In yellow are layer1 plane and wires (just below top layer)
Big circles gray are normal vias
4.7 uF
2.3 x 1.2 mm
Small circles gray are top to layer1 vias
S < 18.00 mm@
Figure 47. Layout Recommendation
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28
NCV6336
ORDERING INFORMATION
Device
†
Marking
Configuration
Package
Shipping
NCV6336BMFCCT1G
6336BM
5 A
WLCSP20 2.02 x 1.62 mm
(Pb–Free)
3000 / Tape & Reel
3000 / Tape & Reel
1.20 V
NCV6336CFCCT1G
6336CV
5 A
1.15 V
WLCSP20 2.02 x 1.62 mm
(Pb–Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Demo Board Available:
The NCP6336BGEVB/D evaluation board that configures the device in typical application to supply constant voltage.
www.onsemi.com
29
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP20, 1.62x2.02
CASE 568AG
ISSUE D
DATE 13 AUG 2013
SCALE 4:1
NOTES:
D
A
B
E
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
PIN A1
REFERENCE
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
MILLIMETERS
DIM
A
A1
A2
A3
b
D
E
e
MIN
−−−
0.17
0.33
0.02
0.24
MAX
0.60
0.23
0.39
0.04
0.28
A2
DIE COAT
(OPTIONAL)
A3
2X
0.10
0.10
C
1.62 BSC
2.02 BSC
0.40 BSC
2X
C
TOP VIEW
DETAIL A
A2
DETAIL A
GENERIC
0.10
C
MARKING DIAGRAM*
A
0.05
C
XXXXXX
AWLYWW
G
SEATING
PLANE
NOTE 3
C
A1
SIDE VIEW
e/2
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
20X
b
e
Y
0.05
0.03
C A B
E
C
e
G
= Pb−Free Package
D
C
B
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
A
1
2
3
4
RECOMMENDED
SOLDERING FOOTPRINT*
BOTTOM VIEW
A1
PACKAGE
OUTLINE
0.40
PITCH
20X
0.25
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON82918E
WLCSP20, 1.62X2.02
PAGE 1 OF 1
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