NCV6356QMTWTXG [ONSEMI]
同步降压转换器，处理器电源，I2C 编程，5.0 A;
| 型号： | NCV6356QMTWTXG |
| 厂家： | 
ONSEMI |
| 描述： | 同步降压转换器，处理器电源，I2C 编程，5.0 A 开关 光电二极管 转换器 |
| 文件： | 总34页 (文件大小：2368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV6356
AOT Step Down Converter,
Configurable
5.0 A
Description
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The NCV6356 is a synchronous AOT (Adaptive On−time) buck
converter optimized to supply the different sub systems of automotive
applications post regulation system up to 5 V input. The device is able
to deliver up to 5.0 A, with programmable output voltage from 0.6 V
to 1.4 V. Operation at up to 2.4 MHz switching frequency allows the
use of small components. Synchronous rectification and automatic
PFM Pseudo−PWM (PPWM) transitions improve overall solution
efficiency. The NCV6356 is in low profile 3.0 x 4.0 mm DFN−14
package.
1
WDFNW14 4x3, 0.5P
CASE 511CM
MARKING DIAGRAM
Features
6356
xx
AYWW
G
• Input Voltage Range from 2.5 V to 5.5 V : Battery, 3.3 V and 5.0 V
Rail Powered Applications
• Power Capability : 3.0 A Ta = 105°C − 5.0 A Ta = 85°C
• Programmable Output Voltage : 0.6 V to 1.4 V in 6.25 mV Steps
• Up to 2.4 MHz Switching Frequency with On Chip Oscillator
• Uses 330 nH Inductor and at least 22 mF Capacitors for Optimized
Footprint and Solution Thickness
6356
xx
= Specific Device Code
= C: 1.150 V / 1.150 V
= B: 1.200 V / 1.200 V
= Q: 0.875 V / 0.906 V
= Assembly Location
= Year
• PFM/PPWM Operation for Optimum Efficiency
A
Y
WW
G
• Low 60 mA Quiescent Current
= Work Week
= Pb−Free Package*
2
• I C Control Interface with Interrupt and Dynamic Voltage Scaling
Support
(Note: Microdot may be in either location)
• Enable / VSEL Pins, Power Good / Interrupt Signaling
• Thermal Protections and Temperature Management
• Transient Load Helper: Share the Same Rail with Another Rail
• 3.0 x 4.0 mm / 0.5 mm Pitch DFN 14 Package
• AEC−Q100 Qualified and PPAP Capable
Typical Applications
• Snap Dragon
• Automotive POL
• Instrumentation, Clusters
• Infotainment
• ADAS System (Vision, Radar)
(Top View)
14−Pin 0.50 mm pitch DFN
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 32 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
August, 2019 − Rev. 0
NCV6356/D
NCV6356
NCV6356
Supply Input
4.7 u F
AVIN
PVIN
SW
Supply Input
Core
AGND
10uF
Thermal
Protection
DCDC
5A
Enable Control
Input
EN
Operating
Mode
Modular
Driver
330nH
VSEL
Voltage Selection
Control
2x 22uF
PGND
FB
Output
PGND
Interrupt
Monitoring
INTB
DCDC
2.4MHz
Processor
Core
SDA
Sense
I@C
Processor I@C
Controller
SCL
Control Interface
Figure 1. Typical Application Circuit
PVIN
PVIN
POWER INPUT
SUPPLY INPUT
AVIN
Core
Thermal
ANALOG GROUND
AGND
SW
SW
SW
5.0 A
DC-DC
SWITCH NODE
Protection
Output Voltage
Monitoring
ENABLE CONTROL INPUT
EN
Up to 2.4 MHz
DC−DC converter
Controller
Operating
Mode Control
VOLTAGE SELECTION
VS EL
PGND
PGND
POWER GROUND
FEEDBACK
INTB
SCL
SDA
Logic Control
Interrupt
I2C
2
PROCESSOR I C
VOUT
Sense
CONTROL INTERFACE
Figure 2. Simplified Block Diagram
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2
NCV6356
Figure 3. Pin Out (Top View)
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Type
Description
REFERENCE
4
AVIN
AGND
Analog Input
Analog Supply. This pin is the device analog and digital supply. Could be connected di-
rectly to the VIN plane with a dedicated 4.7 mF ceramic capacitor. Must be equal to PVIN
15
Analog Ground
Analog Ground. Analog and digital modules ground. Must be connected to the system
ground.
CONTROL AND SERIAL INTERFACE
14
EN
Digital Input
Enable Control. Active high will enable the part. There is an internal pull down resistor on
this pin.
13
VSEL
Digital Input
Output voltage / Mode Selection. The level determines which of two programmable con-
figurations to utilize (operating mode / output voltage). There is an internal pull down resis-
tor on this pin; could be left open if not used.
3
1
INTB
SCL
Digital Output
Digital Input
Interrupt open drain output. Must be connected to the ground plane if not used.
2
I C interface Clock line. There is an internal pull down resistor on this pin; could be left
open if not used
2
12
SDA
Digital
Input/Output
I C interface Bi−directional Data line. There is an internal pull down resistor on this pin;
could be left open if not used
DC to DC CONVERTER
8, 9
PVIN
Power Input
Switch Supply. These pins must be decoupled to ground by at least a 10 mF ceramic
capacitor. It should be placed as close as possible to these pins. All pins must be used
with short heavy connections. Must be equal to AVIN
5, 6, 7
SW
Power Output
Switch Node. These pins supply drive power to the inductor. Typical application uses
0.33 mH inductor; refer to application section for more information.
All pins must be used with short heavy connections.
10, 11
PGND
VOUT
Power Ground
Analog Input
Switch Ground. This pin is the power ground and carries the high switching current. High
quality ground must be provided to prevent noise spikes. To avoid high−density current
flow in a limited PCB track, a local ground plane that connects all PGND pins together is
recommended. Analog and power grounds should only be connected together in one loca-
tion with a trace.
2
Feedback Voltage Input. Must be connected to the output capacitor positive terminal with
a trace, not to a plane. This is the positive input to the error amplifier.
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3
NCV6356
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Analog and power pins (Note 1):
V
A
V
AVIN, PVIN, SW, INTB, VOUT, DC non switching
PVIN−PGND pins, transient 3 ns – 2.4 MHz
−0.3 to +6.0
−0.3 to +7.5
2
I C pins: SDA, SCL
V 2
I C
−0.3 to +6.0
V
Digital pins : EN, VSEL
Input Voltage
V
DG
−0.3 to V +0.3 ≤ 6.0
V
A
Input Current
I
10
mA
DG
Human Body Model (HBM) ESD Rating (Note 2)
Charged Device Model (CDM) ESD Rating (Note 2)
ESD HBM
ESD CDM
2500
1000
V
V
Latch Up Current: (Note 3)
Digital Pins
I
LU
100
100
mA
All Other Pins
Storage Temperature Range
Maximum Junction Temperature
Moisture Sensitivity (Note 4)
T
−65 to +150
−40 to +150
Level 1
°C
°C
STG
T
JMAX
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM) 2.5 kV per JEDEC standard: JESD22*A114.
Charged Device Model (CDM) 1.0 kV per JEDEC standard: JESD22−C101 Class IV
3. Latch up Current per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
Table 3. OPERATING CONDITIONS
Symbol
AV PV
Parameter
Conditions
PV
Min
2.5
−40
−
Typ
Max
5.5
+125
−
Unit
V
Power Supply
AV
IN =
IN,
IN
IN
T
J
Junction Temperature Range (Note 6)
Thermal Resistance Junction to Ambient (Note 7)
Power Dissipation Rating (Note 8)
25
30
°C
R
DFN−14 on Demo−board
≤ 105°C,
°C/W
mW
q
JA
P
D
T
A
−
666
−
R
= 30°C/W
q
JA
T
R
≤ 85°C
−
−
1333
2000
−
−
mW
mW
A
= 30°C/W
q
JA
T = 65°C
A
R
= 30°C/W
q
JA
L
Inductor for DC to DC converter (Note 5)
0.15
15
0.33
−
0.47
200
−
mH
mF
mF
Co
Output Capacitor for DC to DC Converter (Note 5)
Input Capacitor for DC to DC Converter (Note 5)
Cin
Per 1.0 A of I
6.0
10.0
OUT
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Including de−ratings (Refer to the Application Information section of this document for further details)
6. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation
7. The R
is dependent of the PCB heat dissipation. Board used to drive this data was a NCV6356EVB board. It is a multilayer board with
q
JA
1−once internal power and ground planes and 2−once copper traces on top and bottom of the board
8. The maximum power dissipation (PD) is dependent on input voltage, maximum output current, pcb stack up and layout, and external
components selected.
125 * T
RqJA
+
A , by taking RqJA + 30oC
PD
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4
NCV6356
Table 4. ELECTRICAL CHARACTERISTICS (Note 9)
Min and Max Limits apply for T = −40°C to +125°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
J
Typical values are referenced to T = + 25°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply Current: Pins AVIN – PVINx
I
I
I
I
Operating quiescent current PPWM
Operating quiescent current PFM
Product sleep mode current
Product in off mode
DCDC active in Forced PPWM
no load
−
−
−
−
22
60
5
25
90
10
3
mA
mA
mA
mA
Q−PPWM
Q PFM
SLEEP
OFF
DCDC active in Auto mode
no load – minimal switching
Product in sleep mode
V
IN
= 5.5 V, T up to 85°C
J
EN, VSEL and Sleep_Mode low,
0.8
2
No I C pull up
V
IN
= 5.5 V, T up to 85°C
J
DC to DC Converter
PV
Input Voltage Range
Load Current Range
2.5
−
5.5
V
A
IN
I
NCV6356B and NCV6356C
(Note 11, 12)
OUT
Ipeak[1..0] = 00
Ipeak[1..0] = 01
Ipeak[1..0] = 10
Ipeak[1..0] = 11
0
0
0
0
−
−
−
−
3.5
4.0
4.5
5.0
NCV6356Q (Note 11, 12)
Ipeak[1..0] = 00
Ipeak[1..0] = 01
Ipeak[1..0] = 10
Ipeak[1..0] = 11
0
0
0
0
−
−
−
−
5.3
5.8
6.3
6.8
D
Output Voltage DC Error
Forced PPWM mode, V range,
No load
−1.5
−
−
−
1.5
%
VOUT
IN
Forced PPWM mode, V range,
−2
2
IN
I
up to I
(Note 11)
OUT
OUTMAX
Auto mode, V range,
−3
2
IN
(Note 11)
OUTMAX
I
up to I
OUT
F
Switching Frequency
2.16
2.4
38
2.64
50
MHz
SW
R
P−Channel MOSFET On Resistance
From PVIN to SW
= 5.0 V
−
mW
ONHS
V
IN
R
N−Channel MOSFET On Resistance
From SW to PGND
= 5.0 V
−
29
40
mW
ONLS
V
IN
I
PK
Peak Inductor Current
NCV6356B and NCV6356C
Open loop − Ipeak[1..0] = 00
Open loop − Ipeak[1..0] = 01
Open loop − Ipeak[1..0] = 10
Open loop − Ipeak[1..0] = 11
A
4.6
5.2
5.6
6.2
5.2
5.8
6.2
6.8
5.8
6.4
6.8
7.4
NCV6356QM
Open loop − Ipeak[1..0] = 00
Open loop − Ipeak[1..0] = 01
Open loop − Ipeak[1..0] = 10
Open loop − Ipeak[1..0] = 11
6.4
7.2
7.6
8.4
7.0
7.8
8.2
9.0
7.7
8.4
8.8
9.6
DC
DC
Load Regulation
Line Regulation
I
from 0 A to I (Note 11)
OUTMAX
−
5
−
mV
mV
LOAD
LINE
OUT
Forced PPWM mode
2.5 V ≤ V ≤ 5.5 V
−
6
−
IN
Forced PPWM mode
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NCV6356
Table 4. ELECTRICAL CHARACTERISTICS (Note 9)
Min and Max Limits apply for T = −40°C to +125°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
J
Typical values are referenced to T = + 25°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
A
Symbol
AC
Parameter
Conditions
t = t = 100 ns
Min
Typ
Max
Unit
Transient Load Response
−
20
−
mV
LOAD
r
f
Load step 1.5 A (Note 11)
NCV6356Q
−60
50
67
t = t = 200 ns, V = 1.0 V
OUT
r
f
L = 0.24 mH, C
= 4 x 47 mF
OUT
Load step 0.4A / 6.6 A (Note 11)
AC
D
Transient Line Response
t = t = 10 ms
Line step 3.3 V / 3.9 V (Note 11)
−
20
−
mV
LINE
r
f
Maximum Duty Cycle
Turn on time
−
−
100
100
−
%
t
Time from EN transitions from Low
to High to 90% of Output Voltage
130
Us
START
(DVS[1..0] = 00b)
R
DCDC Active Output Discharge
Vout = 1.15 V
−
12
20
W
DISDCDC
EN, VSEL
V
V
High input voltage
Low input voltage
Digital input X Filter
1.05
−
−
−
−
−
V
V
IH
0.4
4.5
IL
T
FTR
EN, VSEL rising and falling
DBN_Time = 01 (Note 11)
0.5
ms
I
Digital input X Pull−Down
For EN and VSEL pins
−
0.05
1.00
mA
PD
(input bias current)
INTB (Optional)
V
V
INTB low output voltage
INTB high output voltage
INTB leakage current
I
= 5 mA
0
−
−
−
−
−
0.2
5.5
100
INTBL
INTBH
INT
Open drain
INTB
3.6V at INTB pin when INTB valid
LK
2
I C
V 2
High level at SCL/SCA line
SCL, SDA low input voltage
SCL high input voltage
SDA high input voltage
SDA low output voltage
1.7
−
−
−
−
−
−
−
4.5
0.4
−
V
V
V
I CINT
V 2
I CIL
SCL, SDA pin (Note 10)
SCL pin (Note 10, 11)
SDA pin (Note 10, 11)
V 2
I CIH
1.6
1.2
−
−
V 2
I COL
I
= 3 mA
0.4
3.4
V
SINK
2
F
SCL
I C clock frequency
(note 11)
−
MHz
TOTAL DEVICE
V
V
Under Voltage Lockout
V
V
falling
rising
−
60
−
−
−
2.5
200
−
V
mV
°C
°C
°C
°C
°C
°C
UVLO
IN
Under Voltage Lockout Hysteresis
Thermal Shut Down Protection
Warning Rising Edge
UVLOH
SD
IN
T
T
T
T
T
T
150
135
105
30
15
6
−
−
WARNING
PWTH
2
Pre – Warning Threshold
I C default value
−
−
Thermal Shut Down Hysteresis
Thermal warning Hysteresis
Thermal pre−warning Hysteresis
−
−
SDH
−
−
WARNINGH
PWTH H
−
−
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Refer to the Application Information Section of this data sheet for more details.
2
10.Devices that use non−standard supply voltages which do not conform to the intent I C bus system levels must relate their input levels to the
V
voltage to which the pull−up resistors R are connected.
DD
P
11. Guaranteed by design and characterized.
12.Junction temperature must be maintained below 125°C. Output load current capability depends on the application thermal capability.
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NCV6356
Typical Operating Characteristics
AV = PV = 3.3 V, T =+25°C
IN
IN
J
DCDC=1.15 V, Ipeak =6.8 A (Unless otherwise noted). L=0.33 uH DFE252012F – Cout = 2 x 22uF 0603, Cin = 4.7 uF 0603.
Figure 5. Efficiency vs ILOAD and Temperature,
OUT = 1.39375 V, SPM5030 Inductor
Figure 4. Efficiency vs ILOAD and VIN,
OUT = 1.39375 V, SPM5030 Inductor
V
V
Figure 6. Efficiency vs ILOAD and VIN,
OUT = 1.15 V, SPM5030 Inductor
Figure 7. Efficiency vs ILOAD and Temperature,
OUT = 1.15 V, SPM5030 Inductor
V
V
Figure 8. Efficiency vs ILOAD and VIN,
VOUT = 0.60 V, SPM5030 Inductor
Figure 9. Efficiency vs ILOAD and Temperature,
OUT = 0.60 V, SPM5030 Inductor
V
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NCV6356
Figure 10. Efficiency vs ILOAD and VIN,
OUT = 1.150 V
Figure 11. Efficiency vs ILOAD and Temperature,
OUT = 1.150 V
V
V
Figure 12. Efficiency vs ILOAD and VIN,
OUT = 0.600 V
Figure 13. Efficiency vs ILOAD and Temperature,
OUT = 0.875 V, HEI201612A−R24M Inductor
V
V
Figure 14. Efficiency vs ILOAD and Temperature,
OUT = 0.906 V, HEI201612A−R24M Inductor
Figure 15. Efficiency vs ILOAD and Temperature,
OUT = 1.394 V
V
V
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NCV6356
Figure 16. VOUT Accuracy vs ILOAD and VIN,
OUT = 1.150 V
Figure 17. VOUT Accuracy vs VIN and Temperature,
OUT = 1.150 V
V
V
Figure 18. VOUT Accuracy vs ILOAD and VIN,
OUT = 0.600 V
Figure 19. VOUT Accuracy vs ILOAD and VIN,
VOUT = 0.875 V, HEI201612A−R24M Inductor
V
Figure 20. VOUT Accuracy vs ILOAD and VIN,
OUT = 0.906 V, HEI201612A−R24M Inductor
Figure 21. VOUT Accuracy vs ILOAD and VIN,
OUT = 1.394 V
V
V
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NCV6356
Figure 22. HSS RON vs VIN and Temperature
Figure 23. LSS RON vs VIN and Temperature
Figure 24. IOFF vs VIN and Temperature
Figure 25. ISLEEP vs VIN and Temperature
Figure 26. IQPFM vs VIN and Temperature
Figure 27. IQPPWM vs VIN and Temperature
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NCV6356
Figure 28. Switchover Point VOUT = 1.15 V
Figure 29. Switchover Point VOUT = 1.4 V
Figure 30. Switching Frequency vs ILOAD and VIN,
Figure 31. Switching Frequency vs ILOAD and
Temperature, VOUT = 1.150 V
V
OUT = 1.150 V
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NCV6356
Figure 32. Ripple
Figure 33. Normal Power Up, VOUT = 1.15 V,
DVS[1..0] = 00
Figure 34. Transient Load 0.4 to 6.6 A − Auto Mode,
VIN = 3.3 V − VOUT = 1.0 V − L = 0.24 uH − COUT = 4 x
47 uF
Figure 35. Transient Load 0.4 to 6.6 A − Forced
PPWM, VIN = 3.3 V − VOUT = 1.0 V − L = 0.24 uH −
OUT = 4 x 47 uF
C
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NCV6356
Figure 36. Transient Load 0.05 to 1.5 A,
Figure 37. Transient Load 0.05 to 1.5 A,
Transient Line 3.0 − 3.6 V Auto Mode
Transient Line 3.6 − 3.0 V Auto Mode
Figure 38. Transient Load 1 to 2.5 A,
Figure 39. Transient Load 1 to 2.5 A,
Transient Line 3.0 − 3.6 V Auto Mode
Transient Line 3.6 − 3.0 V Auto Mode
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NCV6356
DETAILED OPERATING DESCRIPTION
Output Stage
Detailed Descriptions
The NCV6356 is voltage mode stand−alone DC to DC
converter optimized to supply different sub systems of
automotive applications post regulation system up to 5 V
NCV6356 is a 3.5 A to 5.0 A output current capable DC
to DC converter with both high side and low side
(synchronous) switches integrated.
2
input. It can deliver up to 5 A at an I C selectable voltage
Inductor Peak Current Limitation / Short Protection
During normal operation, peak current limitation
monitors and limits the inductor current by checking the
current in the P−MOSFET switch. When this current
exceeds the Ipeak threshold, the P−MOSFET is immediately
opened.
To protect again excessive load or short circuit, the
number of consecutive Ipeak is counted. When the counter
reaches 16, the DCDC is powered down during about 2 ms
and the ISHORT interrupt is flagged. It will re−start
following the REARM bit in the LIMCONF register:
• If REARM = 0, then NCV6356 does not re−start
automatically, an EN pin toggle is required.
• If REARM = 1, NCV6356 re−starts automatically after
the 2 ms with register values set prior the fault
condition.
ranging from 0.6 V to 1.40 þV. The switching frequency up
to 2.4 MHz allows the use of small output filter components.
Power Good indicator and Interrupt management are
available. Operating modes, configuration, and output
power can be easily selected either by using digital I/O pins
2
or by programming a set of registers using an I C compatible
interface capable of operation up to 3.4 MHz.
2
Default I C settings are factory programmable.
DC to DC Converter Operation
The converter integrates both high side and low side
(synchronous) switches. Neither external transistors nor
diodes are required for NCV6356 operation. Feedback and
compensation network are also fully integrated.
It uses the AOT (Adaptive On−Time) control scheme and
can operate in two different modes: PFM and PPWM
(Pseudo−PWM). The transition between modes can occur
automatically or the switcher can be placed in forced PPWM
This current limitation is particularly useful to protect the
inductor. The peak current can be set by writing
IPEAK[1..0] bits in the LIMCONF register.
2
mode by I C programming (PPWMVSEL0 / PPWMVSEL1
bits of COMMAND register).
PPWM (Pseudo Pulse Width Modulation) Operating Mode
In medium and high load conditions, NCV6356 operates
in PPWM mode to regulate the desired output voltage. In
this mode, the inductor current is in CCM (Continuous
Conduction Mode) and the AOT guaranties a pseudo−fixed
frequency with 10% accuracy. The internal N−MOSFET
switch operates as synchronous rectifier and is driven
complementary to the P−MOSFET switch.
Table 5. IPEAK VALUES
OPN
IPEAK[1..0]
Inductor Peak Current (A)
5.2 – for 3.5 output current
5.8 – for 4.0 output current
6.2 – for 4.5 output current
6.8 – for 5.0 output current
7.0 – for 5.3 output current
7.7 – for 5.8 output current
8.2 – for 6.3 output current
8.8 – for 6.8 output current
NCV6356B
NCV6356C
00
01
10
11
00
01
10
11
NCV6356Q
PFM (Pulse Frequency Modulation) Operating Mode
In order to save power and improve efficiency at low
loads, the NCV6356 operates in PFM mode as the inductor
current drops into DCM (Discontinuous Conduction Mode).
The upper FET on−time is kept constant and the switching
frequency becomes proportional to the loading current. As
it does in PPWM mode, the internal N−MOSFET operates
as a synchronous rectifier after each P−MOSFET on−pulse
until there is no longer current in the coil.
Output Voltage
The output voltage is set internally by an integrated
resistor bridge and no extra components are needed to set the
output voltage. Writing in the VoutVSEL0[6..0] bits of the
PROGVSEL0 register or VoutVSEL1[6..0] bits of the
PROGVSEL1 register will change the output voltage. The
output voltage level can be programmed by 6.26 mV steps
between 0.6 V to 1.39375 V. The VSEL pin and VSELGT
bit will determine which register between PROGVSEL0
and PROGVSEL1 will set the output voltage.
• If VSELGT = 1 AND VSEL=0 ³ Output voltage is set
by VoutVSEL0[6..0] bits (PROGVSEL0 register)
• Else ³ Output voltage is set by VoutVSEL1[6..0] bits
(PROGVSEL1 register)
When the load increases and the current in the inductor
become continuous again, the controller automatically turns
back to PPWM mode.
Forced PPWM
The NCV6356 can be programmed to only use PPWM
and the transition to PFM can be disabled if so desired,
2
thanks to the PPWMVSEL0 or PPWMVSEL1 I C bits
(COMMAND register).
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14
NCV6356
Under Voltage Lock Out (UVLO)
Enabling
NCV6356 core does not operate for voltages below the
Under Voltage Lock Out (UVLO) level. Below the UVLO
threshold, all internal circuitry (both analog and digital) is
held in reset. NCV6356 operation is guaranteed down to
UVLO as the battery voltage is dropping off. To avoid erratic
on / off behavior, a maximum 200 mV hysteresis is
implemented. Restart is guaranteed at 2.7 V when the VBAT
voltage is recovering or rising.
The EN pin controls NCV6356 start up. EN pin Low to
High transition starts the power up sequencer. If EN is low,
the DC to DC converter is turned off and device enters:
2
• Sleep Mode if Sleep_Mode I C bit is high or VSEL is
2
high or I C pull up present,
2
• Off Mode if Sleep_Mode I C bit and VSEL are low and
2
no I C pull up.
When EN pin is set to a high level, the DC to DC converter
can be enabled / disabled by writing the ENVSEL0 or
ENVSEL1 bit of the PROGVSEL0 and PROGVSEL1
registers:
Thermal Management
Thermal Shut Down (TSD)
The thermal capability of the NCV6356 can be exceeded
due to the step down converter output stage power level. A
thermal protection circuitry with associated interrupt is
therefore implemented to prevent the IC from damage. This
protection circuitry is only activated when the core is in
active mode (output voltage is turned on). During thermal
shut down, output voltage is turned off.
2
• Enx I C bit is high, the DC to DC converter is
activated.
2
• Enx I C is low, the DC to DC converter is turned off
and the device enters in Sleep Mode.
A built in pull down resistor disables the device when this
pin is left unconnected or not driven. EN pin activity does
not generate any digital reset.
During thermal shut down, the output voltage is turned
off.
When NCV6356 returns from thermal shutdown, it can
re−start in 2 different configurations depending on the
REARM bit in the LIMCONF register (refer to the register
description section):
• If REARM = 0 then NCV6356 does not re−start after
TSD. To restart, an EN pin toggle is required.
• If REARM = 1, NCV6356 re−starts with register values
set prior to thermal shutdown.
Power Up Sequence (PUS)
In order to power up the circuit, the input voltage AVIN
has to rise above the VUVLO threshold. This triggers the
internal core circuitry power up which is the “Wake Up
Time” (including “Bias Time”)
This delay is internal and cannot be bypassed. EN pin
transition within this delay corresponds to the “Initial power
up sequence” (IPUS):
The thermal shut down threshold is set at 150°C (typical)
and a 30°C hysteresis is implemented in order to avoid
erratic on / off behavior. After a typical 150°C thermal shut
down, NCV6356 will resume to normal operation when the
die temperature cools to 120°C.
AVIN
UVLO
POR
EN
Thermal Warnings
In addition to the TSD, the die temperature monitoring
DELAY[2..0]
VOUT
~ 80 us
32 us
circuitry includes
a thermal warning and thermal
pre−warning sensor and interrupts. These sensors can
inform the processor that NCV6356 is close to its thermal
shutdown and preventive measures to cool down die
temperature can be taken by software.
Wake up
Time
Init DVS ramp
Time
Time
Figure 40. Initial Power Up Sequence
The Warning threshold is set by hardware to 135°C
typical. The Pre−Warning threshold is set by default to
105°C but it can be changed by setting the TPWTH[1..0] bits
in the LIMCONF register.
In addition a user programmable delay will also take place
between the Wake Up Time and the Init time: The
DELAY[2..0] bits of the TIME register will set this user
programmable delay with a 2 ms resolution. With default
delay of 0 ms, the NCV6356 IPUS takes roughly 100 ms, and
the DC to DC converter output voltage will be ready within
150 ms.
Active Output Discharge
To make sure that no residual voltage remains in the power
supply rail when disabled, an active discharge path can
ground the NCV6356 output voltage. For maximum
flexibility, this feature can be easily disabled or enabled with
the DISCHG bit in the PGOOD register. By default the
discharge path is enabled and is activated during the first
100 ms after battery insertion.
The power up output voltage is defined by the VSEL state.
2
NOTE: During the Wake Up time, the I C interface is
2
not active. Any I C request to the IC during this
time period will result in a NACK reply.
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15
NCV6356
Normal, Quick and Fast Power Up Sequence
In addition the delay set in DELAY[2..0] bits in TIME
register will apply only for the EN pins turn ON sequence
(NPUS and QPUS).
The previous description applies only when the EN
transitions during the internal core circuitry power up (Wake
up and calibration time). Otherwise 3 different cases are
possible:
• Enabling the part by setting the EN pin from Off Mode
will result in “Normal power up sequence” (NPUS,
with DELAY;[2..0]).
• Enabling the part by setting the EN pin from Sleep
Mode will result in “Quick power up sequence”
(QPUS, with DELAY;[2..0]).
• Enabling the DC to DC converter, whereas EN is
already high, either by setting the ENVSEL0 or
ENVSEL1 bits or by VSEL pin transition will results in
“Fast power up sequence” (FPUS, without
DELAY[2..0]).
The power up output voltage is defined by VSEL state.
DC to DC Converter Shut Down
When shutting down the device, no shut down sequence
is required. The output voltage is disabled and, depending on
the DISCHG bit state of the PGOOD register, the output may
be discharged.
DC to DC converter shutdown is initiated by either
grounding the EN pin (Hardware Shutdown) or, depending
on the VSEL internal signal level, by clearing the ENVSEL0
or ENVSEL1 bits (Software shutdown) in the PROGVSEL0
or PROGVSEL1 registers.
In hardware shutdown (EN = 0), the internal core is still
active and I C accessible.
The internal core of the NCV6356 shuts down when AVIN
falls below UVLO.
AVIN
UVLO
POR
Dynamic Voltage Scaling (DVS)
The NCV6356 supports dynamic voltage scaling (DVS)
allowing the output voltage to be reprogrammed via I C
EN
O
F
F
2
commands and provides the different voltages required by
the processor. The change between set points is managed in
a smooth fashion without disturbing the operation of the
processor.
When programming a higher voltage, the output raises
with controlled dV/dt defined by DVS[1..0] bits in the TIME
register. When programming a lower voltage the output
voltage will decrease accordingly. The DVS step is fixed and
the speed is programmable.
DELAY[2..0]
M
O
D
E
60 us
32 us
TFTR Bias
Time
Init
Time
DVS ramp
Time
Figure 41. Normal Power Up Sequence
AVIN
The DVS sequence is automatically initiated by changing
the output voltage settings. There are two ways to change
these settings:
UVLO
POR
S
EN
L
E
E
P
• Directly change the active setting register value
(VoutVSEL0[6..0] of the PROGVSEL0 register or
VoutVSEL1[6..0] of the PROGVSEL1 register) via an
DELAY[2..0]
M
O
D
E
10 us
32 us
2
I C command
TFTR Bias
Time
Init
Time
DVS ramp
Time
• Change the VSEL internal signal level by toggling the
VSEL pin.
Figure 42. Quick Power Up Sequence
2
The second method eliminates the I C latency and is
therefore faster.
AVIN
The DVS transition mode can be changed with the
DVSMODE bit in the COMMAND register:
• In forced PPWM mode when accurate output voltage
control is needed. Rise and fall time are controlled with
the DVS[1..0] bits.
UVLO
POR
S
L
E
E
P
VSEL
VOUT
M
O
D
E
32 us
T
Init
Time
DVS ramp
Time
Figure 43. Fast Power Up Sequence
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16
NCV6356
Internal
DVS ramp
V2
Internal
Reference
Output
Voltage
nV
V2
nt
V1
V1
DVS
up
DVS
down
Figure 44. DVS in Forced PPWM Mode Diagram
PG
• In Auto mode when the output voltage must not be
discharged. Rise time is controlled by the DVS[1..0],
and fall time depends of the load and cannot be faster
than the DVS[1..0] settings.
Figure 47. Power Good during DVS Transition
Digital IO Settings
Output
Voltage
V2
Internal
Reference
nV
VSEL Pin
nt
By changing VSEL pin levels, the user has a latency free
way to change NCV6356 configuration: operating mode
(Auto or PWM forced), the output voltage as well as enable.
V1
Figure 45. DVS in Auto Mode Diagram
Table 6. VSEL PIN PARAMETERS
Power Good Indicator
Parameter VSEL
Pin Can Set
REGISTER
VSEL = LOW
REGISTER
VSEL = HIGH
To indicate the output voltage level is established, a power
good signal is available. The power good signal is low when
the DC to DC converter is off. Once the output voltage
reaches 95% of the expected output level, the power good
logic signal becomes high (ACK_PG, SEN_PG bits).
During operation, when the output drops below 90% of
the programmed level, the power good logic signal goes low,
indicating a power failure. When the voltage rises again to
above 95%, the power good signal goes high again.
During a DVS sequence, the Power Good signal is set low
during the transition and goes back high once the transition
is completed.
ENABLE
ENVSEL0
ENVSEL1
PROGVSEL1[7]
PROGVSEL0[7]
VOUT
VoutVSEL0[6..0]
VoutVSEL1[6..0]
OPERATING MODE
(Auto / PPWM
Forced)
PWMVSEL0
COMMAND[7]
PWMVSEL1
COMMAND[6]
VSEL pin action can be masked by writing 0 to the
VSELGT bit in the COMMAND register. In that case I C bit
corresponding to VSEL high will be taken into account.
2
The Power Good signal during normal operation can be
disabled by clearing the PGDCDC bit in the PGOOD
register. The Power good operation during DVS can be
activated with PGDVS bit if the PGOOD register.
EN pin
The EN pin can be gated by writing the ENVSEL0 or
ENVSEL1 bits of the PROGVSEL0 and PROGVSEL1
registers, depending on which register is activated by the
VSEL internal signal.
DCDC_EN
Interrupt Pin (Optional)
95%
90%
32 us
The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when a
system status change is detected (dual edge monitoring).
DCDC
3.5−
14 us
3.5−
14 us
3.5 us
PG
Table 7. INTERRUPT SOURCES
Interrupt
Figure 46. Power Good Signal when PGDCDC = 1
Name
Description
TSD
Thermal Shut Down
TWARN
TPREW
UVLO
IDCDC
ISHORT
PG
Thermal Warning
Thermal Pre Warning
Under Voltage Lock Out
DC to DC converter Current Over / below limit
DC to DC converter Short−Circuit Protection
Power Good
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17
NCV6356
Individual bits generating interrupts will be set to 1 in the
INT_ACK register (I C read only registers), indicating the
TWARN
2
SEN_TWARN
MSK_TWARN
interrupt source. INT_ACK register is automatically reset
2
by an I C read. The INT_SEN register (read only register)
contains real time indicators of interrupt sources.
All interrupt sources can be masked by writing in the
register INT_MSK. Masked sources will never generate an
interrupt request on the INTB pin.
ACK_TWARN
INTB
I@C access on INT_ACK
read
read
read
read
The INTB pin is an open drain output. A non−masked
interrupt request will result in the INTB pin being driven
low.
When the host reads the INT_ACK registers the INTB pin
is released to high impedance and the interrupt register
INT_ACK is cleared.
Figure 48. TWARN Interrupt Operation Example
Configurations
Default output voltages, enables, DCDC modes, current
limit and other parameters can be factory programmed upon
request.
Figure 48 is an example of a TWARN event of the INTB
2
Below is the default configurations pre−defined:
pin with INT_SEN/INT_MSK/INT_ACK and an I C read
access behavior.
Table 8. NCV6356 CONFIGURATION
5.0 A
5.0 A
6.8 A
NCV6356CM
NCV6356BM
NCV6356QM
Configuration
2
Default I C address
ADD1 – 14h : 0010100R/W
ADD1 – 14h : 0010100R/W
ADD6 − 68h : 1101000R/W
PID product identification
RID revision identification
FID feature identification
20h
Metal
00h
20h
Metal
01h
20h
Metal
02h
Default VOUT – VSEL=1
Default VOUT – VSEL=0
Default MODE – VSEL=1
Default MODE – VSEL=0
Default IPEAK
1.15 V
1.15 V
1.20 V
1.20 V
0.90625 V
0.875 V
Forced PPWM
Auto mode
6.8 A
Forced PPWM
Auto mode
6.8 A
Forced PPWM
Forced PPWM
8.8 A
OPN
NCV6356CMTWTXG
6356C
NCV6356BMTWTXG
6356B
NCV6356QMTWTXG
6356Q
Marking
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18
NCV6356
I2C Compatible Interface
NCV6356 can support a subset of the I C protocol as
detailed below.
2
I2C Communication Description
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
READ OUT FROM PART
START
START
ACK
ACK
/ACK
STOP
IC ADDRESS
1
DATA 1
DATA n
1 à READ
/ACK
ACK
ACK
ACK
STOP
WRITE INSIDE PART
IC ADDRESS
0
DATA1
DATA n
If PART does not Acknoleg,ethe /NACK will be followed by a STOP or(Srerpeated star)t.
If PART Acknolege,sthe ACK can be followed by another data or Stop or Sr
à
0
WRITE
Figure 49. General Protocol Description
The first byte transmitted is the Chip address (with the
LSB bit set to 1 for a read operation, or set to 0 for a Write
operation). The following data will be:
• During a Write operation, the register address (@REG)
is written in followed by the data. The writing process
is auto−incremental, so the first data will be written in
@REG, the contents of @REG are incremented and the
next data byte is placed in the location pointed to by
@REG + 1 ..., etc.
last write operation. Like the writing process, the
reading process is auto−incremental.
Read Sequence
The Master will first make a “Pseudo Write” transaction
with no data to set the internal address register. Then, a stop
then start or a Repeated Start will initiate the read transaction
from the register address the initial write transaction has
pointed to:
• During a Read operation, the NCV6356 will output the
data from the last register that has been accessed by the
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
START
ACK
ACK
STOP
IC ADDRESS
0
REGISTER ADDRESS
à
0
WRITE
START
ACK
ACK
/ACK
STOP
IC ADDRESS
1
DATA1
DATA n
REGISTER ADDRESS
VALUE
REGISTER ADDRESS + (n − 1)
VALUE
n REGISTERS READ
à
1
READ
Figure 50. Read Sequence
The first WRITE sequence will set the internal pointer to
the register that is selected. Then the read transaction will
start at the address the write transaction has initiated.
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19
NCV6356
Write Sequence
Write operation will be achieved by only one transaction.
After chip address, the REG address has to be set, then
following data will be the data we want to write in REG,
REG + 1, REG + 2, ..., REG +n.
Write n Registers:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
WRITE VALUE IN
REGISTER REG0 + (n−1)
WRITE VALUE IN
REGISTER REG0
START
ACK
ACK
ACK
ACK
STOP
IC ADDRESS
0
REGISTER REG0 ADDRESS
REG VALUE
REG+ (n – 1) VALUE
n REGISTERS WRITE
à
0
WRITE
Figure 51. Write Sequence
Write then Read Sequence
With Stop Then Start
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
WRITE VALUE IN
REGISTER REG0 + (n−1)
WRITE VALUE IN
REGISTER REG0
START
ACK
ACK
ACK
ACK
STOP
IC ADDRESS
0
REGISTER REG0 ADDRESS
REG VALUE
REG + (n– 1) VALUE
n REGISTERS WRITE
à
0
WRITE
START
ACK
ACK
/ACK
STOP
IC ADDRESS
1
DATA 1
DATA k
REGISTER REG+ (n– 1)
VALUE
REGISTER ADDRESS + (n − 1) +
(k –1) VALUE
k REGISTERS READ
à
1
READ
Figure 52. Write Followed by Read Transaction
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20
NCV6356
I2C Address
settings can be generated upon request to
ON Semiconductor. See Table 8 (NCV6356 Configuration)
for the default I C address.
2
The NCV6356 has 8 available I C addresses selectable by
factory settings (ADD0 to ADD7). Different address
2
Table 9. I2C ADDRESS
2
I C Address
Hex
A7
A6
A5
A4
A3
A2
A1
A0
ADD0
W 0x20
R 0x21
0
0
1
0
0
0
0
R/W
Add
0x10
0
−
ADD1
ADD2
ADD3
ADD4
ADD5
ADD6
ADD7
W 0x28
R 0x29
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
Add
0x14
1
−
W 0x30
R 0x31
R/W
Add
0x18
1
−
W 0x38
R 0x39
R/W
Add
0x1C
0
−
W 0xC0
R 0xC1
R/W
Add
0x60
0
−
W 0xC8
R 0xC9
R/W
Add
0x64
1
−
W 0xD0
R 0xD1
R/W
Add
0x68
1
−
W 0xD8
R 0xD9
R/W
Add
0x6C
−
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21
NCV6356
Register Map
The tables below describe the I C registers.
2
Registers / bits Operations:
R
RC
Read only register
Read then Clear
RW
Read and Write register
Reserved
Spare
Address is reserved and register / bit is not physically designed
Address is reserved and register / bit is physically designed
Table 10. I2C REGISTERS MAP CONFIGURATION (NCV6356C)
Add.
00h
Register Name
INT_ACK
INT_SEN
INT_MSK
PID
Type
RC
R
Def.
00h
01h
FFh
20h
Metal
00h
−
Function
Interrupt register
01h
Sense register (real time status)
02h
RW
R
Mask register to enable or disable interrupt sources (trim)
Product Identification
03h
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 0Fh
10h
−
−
Reserved for future use
PROGVSEL1
PROGVSEL0
PGOOD
TIME
RW
RW
RW
RW
RW
−
D8h
D8h
10h
09h
43h
−
Output voltage settings and EN for VSEL pin = High (trim)
Output voltage settings and EN for VSEL pin = Low (trim)
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (trim)
Reserved for future use
11h
12h
13h
14h
COMMAND
−
15h
16h
LIMCONF
−
RW
−
E3h
−
Reset and limit configuration register (trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
Table 11. I2C REGISTERS MAP CONFIGURATION (NCV6356B)
Add.
00h
Register Name
INT_ACK
INT_SEN
INT_MSK
PID
Type
RC
R
Def.
00h
01h
FFh
20h
Metal
01h
−
Function
Interrupt register
01h
Sense register (real time status)
02h
RW
R
Mask register to enable or disable interrupt sources (trim)
Product Identification
03h
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 0Fh
10h
−
−
Reserved for future use
PROGVSEL1
PROGVSEL0
PGOOD
TIME
RW
RW
RW
RW
RW
−
E0h
E0h
10h
09h
43h
−
Output voltage settings and EN for VSEL pin = High (trim)
Output voltage settings and EN for VSEL pin = Low (trim)
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (trim)
Reserved for future use
11h
12h
13h
14h
COMMAND
−
15h
16h
LIMCONF
−
RW
−
E3h
−
Reset and limit configuration register (trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
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22
NCV6356
Table 12. I2C REGISTERS MAP CONFIGURATION (NCV6356Q)
Add.
00h
Register Name
INT_ACK
INT_SEN
INT_MSK
PID
Type
RC
R
Def.
00h
01h
FFh
20h
Metal
02h
−
Function
Interrupt register
01h
Sense register (real time status)
02h
RW
R
Mask register to enable or disable interrupt sources (trim)
Product Identification
03h
04h
RID
R
Revision Identification
05h
FID
R
Features Identification (trim)
06h to 0Fh
10h
−
−
Reserved for future use
PROGVSEL1
PROGVSEL0
PGOOD
TIME
RW
RW
RW
RW
RW
−
B1h
ACh
10h
09h
C3h
−
Output voltage settings and EN for VSEL pin = High (trim)
Output voltage settings and EN for VSEL pin = Low (trim)
Power good and active discharge settings (trim)
Enabling and DVS timings (trim)
Enabling and Operating mode Command register (trim)
Reserved for future use
11h
12h
13h
14h
COMMAND
−
15h
16h
LIMCONF
−
RW
−
E3h
−
Reset and limit configuration register (trim)
Reserved for future use
17h to 1Fh
20h to FFh
−
−
−
Reserved. Test Registers
Registers Description
Table 13. INTERRUPT ACKNOWLEDGE REGISTER
Name: INTACK
Address: 00h
Type: RC
Default: 00000000b (00h)
Trigger: Dual Edge [D7..D0]
D7
D6
D5
D4
D3
D2
D1
D0
ACK_TSD
ACK_TWARN
ACK_TPREW
Spare = 0
ACK_ISHORT
ACK_UVLO
ACK_IDCDC
ACK_PG
Bit
Bit Description
ACK_PG
ACK_IDCDC
ACK_UVLO
ACK_ISHORT
ACK_TPREW
ACK_TWARN
ACK_TSD
Power Good Sense Acknowledgement
0: Cleared
1: DCDC Power Good Event detected
DCDC Over Current Sense Acknowledgement
0: Cleared
1: DCDC Over Current Event detected
Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event detected
DCDC Short−Circuit Protection Sense Acknowledgement
0: Cleared
1: DCDC Short circuit protection detected
Thermal Pre Warning Sense Acknowledgement
0: Cleared
1: Thermal Pre Warning Event detected
Thermal Warning Sense Acknowledgement
0: Cleared
1: Thermal Warning Event detected
Thermal Shutdown Sense Acknowledgement
0: Cleared
1: Thermal Shutdown Event detected
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23
NCV6356
Table 14. INTERRUPT SENSE REGISTER
Name: INTSEN
Type: R
Address: 01h
Default: 00000000b (00h)
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
SEN_TSD
SEN_TWARN
SEN_TPREW
Spare = 0
SEN_ISHORT
SEN_UVLO
SEN_IDCDC
SEN_PG
Bit
Power Good Sense
0: DCDC Output Voltage below target
Bit Description
SEN_PG
1: DCDC Output Voltage within nominal range
SEN_IDCDC
SEN_UVLO
SEN_ISHORT
SEN_TPREW
SEN_TWARN
SEN_TSD
DCDC over current sense
0: DCDC output current is below limit
1: DCDC output current is over limit
Under Voltage Sense
0: Input Voltage higher than UVLO threshold
1: Input Voltage lower than UVLO threshold
DCDC Short−Circuit Protection Sense
0: Short−Circuit detected not detected
1: Short−Circuit not detected
Thermal Pre Warning Sense
0: Junction temperature below thermal pre−warning limit
1: Junction temperature over thermal pre−warning limit
Thermal Warning Sense
0: Junction temperature below thermal warning limit
1: Junction temperature over thermal warning limit
Thermal Shutdown Sense
0: Junction temperature below thermal shutdown limit
1: Junction temperature over thermal shutdown limit
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NCV6356
Table 15. INTERRUPT MASK REGISTER
Name: INTMSK
Type: RW
Address: 02h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
MSK_TSD
MSK_TWARN
MSK_TPREW
Spare = 1
MSK_ISHORT
MSK_UVLO
MSK_IDCDC
MASK_PG
Bit
Bit Description
MSK_PG
MSK_IDCDC
MSK_UVLO
MSK_ISHORT
MSK_TPREW
MSK_TWARN
MSK_TSD
Power Good interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
DCDC over current interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Under Voltage interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
DCDC Short−Circuit Protection source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Thermal Pre Warning interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Thermal Warning interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Thermal Shutdown interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Table 16. PRODUCT ID REGISTER
Name: PID
Type: R
Address: 03h
Default: 00011011b (20h)
Reset on N/A
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
PID_7
PID_6
PID_5
PID_4
PID_3
PID_2
PID_1
PID_0
Table 17. REVISION ID REGISTER
Name: RID
Type: R
Address: 04h
Default: Metal
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
RID_7
RID_6
RID_5
RID_4
RID_3
RID_2
RID_1
RID_0
Bit
RID[7..0]
Bit Description
Revision Identification
00000000: First Silicon
00000001: Final Silicon
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25
NCV6356
Table 18. FEATURE ID REGISTER
Name: FID
Type: R
Address: 05h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare
Spare
Spare
Spare
FID_3
FID_2
FID_1
FID_0
Bit
FID[3..0]
Bit Description
Feature Identification
00000000: NCV6356C 5.0 A, 1.15 V configuration
00000001: NCV6356B 5.0 A, 1.20 V configuration
00000010: NCV6356Q 6.8 A, 0.875 V − 0.906 V configuration
Table 19. DC TO DC VOLTAGE PROG (VSEL = 1) REGISTER
Name: PROGVSEL1
Type: RW
Trigger: N/A
D7
Address: 10h
Default: See Register map
D6
D5
D4
D3
VoutVSEL1[6..0]
Bit Description
D2
D1
D0
ENVSEL1
Bit
VoutVSEL1[6..0]
Sets the DC to DC converter output voltage when VSEL pin = 1 and VSEL pin function is enabled in register
COMMAND.D0, or when VSEL pin function is disabled in register COMMAND.D0
0000000b = 600 mV − 1111111b = 1393.75 mV (steps of 6.25 mV)
ENVSEL1
EN Pin Gating for VSEL internal signal = High
0: Disabled
1: Enabled
Table 20. DC TO DC VOLTAGE PROG (VSEL = 0) REGISTER
Name: PROGVSEL0
Type: RW
Trigger: N/A
D7
Address: 11h
Default: See Register map
D6
D5
D4
D3
D2
D1
D0
ENVSEL0
Bit
VoutVSEL0[6..0]
Bit Description
VoutVSEL0[6..0]
Sets the DC to DC converter output voltage when VSEL pin = 0 and VSEL pin function is enabled in regis-
ter COMMAND.D0
0000000b = 600 mV − 1111111b = 1393.75 mV (steps of 6.25 mV)
ENVSEL0
EN Pin Gating for VSEL internal signal = Low
0: Disabled
1: Enabled
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26
NCV6356
Table 21. POWER GOOD REGISTER
Name: PGOOD
Type: RW
Address: 12h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
Spare = 0
D2
D1
D0
Spare = 0
Bit
Spare = 0
Spare = 0
DISCHG
Spare = 0
PGDVS
PGDCDC
Bit Description
PGDCDC
Power Good Enabling
0 = Disabled
1 = Enabled
PGDVS
Power Good Active On DVS
0 = Disabled
1 = Enabled
DISCHG
Active discharge bit Enabling
0 = Discharge path disabled
1 = Discharge path enabled
Table 22. TIMING REGISTER
Name: TIME
Address: 13h
Default: See Register map
Type: RW
Trigger: N/A
D7
D6
D5
D4
D3
D2
Spare = 0
Bit Description
D1
D0
DELAY[2..0]
DVS[1..0]
DBN_Time[1..0]
Bit
DBN_Time[1..0]
DVS[1..0]
EN and VSEL debounce time
00 = No debounce
01 = 1−2 us
10 = 2−3 us
11 = 3−4 us
DVS Speed
00 = 6.25 mV step / 0.333 us
01 = 6.25 mV step / 0.666 us
10 = 6.25 mV step / 1.333 us
11 = 6.25 mV step / 2.666 us
DELAY[2..0]
Delay applied upon enabling (ms)
000b = 0 ms – 111b = 14 ms (Steps of 2 ms)
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27
NCV6356
Table 23. COMMAND REGISTER
Name: COMMAND
Type: RW
Address: 14h
Default: See Register map
Trigger: N/A
D7
PPWMVSEL0
Bit
D6
D5
D4
D3
D2
D1
D0
PPWMVSEL1
DVSMODE
Sleep_Mode
Spare = 0
Spare = 0
Spare
VSELGT
Bit Description
VSELGT
VSEL Pin Gating
0 = Disabled
1 = Enabled
Sleep_Mode
DVSMODE
Sleep mode
0 = Low Iq mode when EN and VSEL low
1 = Force product in sleep mode (when EN and VSEL are low)
DVS transition mode selection
0 = Auto
1 = Forced PPWM
PPWMVSEL1
PPWMVSEL0
Operating mode for MODE internal signal = High
0 = Auto
1 = Forced PPWM
Operating mode for MODE internal signal = Low
0 = Auto
1 = Forced PPWM
Table 24. LIMITS CONFIGURATION REGISTER
Name: LIMCONF
Type: RW
Address: 16h
Default: See Register map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
IPEAK[1..0]
Bit
TPWTH[1..0]
Spare = 0
FORCERST
RSTSTATUS
REARM
Bit Description
REARM
Rearming of device after TSD / ISHORT
0: No re−arming after TSD / ISHORT
2
1: Re−arming active after TSD / ISHORT with no reset of I C registers: new power−up sequence is initiat-
2
ed with previously programmed I C registers values
RSTSTATUS
FORCERST
TPWTH[1..0]
Reset Indicator Bit
0: Must be written to 0 after register reset
1: Default (loaded after Registers reset)
Force Reset Bit
0 = Default value. Self cleared to 0
1: Force reset of internal registers to default
Thermal pre−Warning threshold settings
00 = 83°C
01 = 94°C
10 = 105°C
11 = 116°C
IPEAK
Inductor peak current settings
00 = 5.2 A (for 3.5 A output current)
01 = 5.8 A (for 4.0 A output current)
10 = 6.2 A (for 4.5 A output current)
11 = 6.8 A (for 5.0 A output current)
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28
NCV6356
APPLICATION INFORMATION
NCV6356
Supply Input
4.7 uF
AVIN
PVIN
Supply Input
Core
AGND
10 uF
Thermal
Protection
DCDC
5 A
Enable Control EN
Input
SW
Operating
Mode
Control
330 nH
Modular
Driver
Voltage VSEL
Selection
2x 22uF
PGND
FB
Output
Monitoring
PGND
Interrupt
INTB
DCDC
2.4 MHz
Controller
Processor
Core
SDA
Sense
I@C
Processor I@C
Control Interface
SCL
Figure 53. Typical Application Schematic
Output Filter Considerations
The output filter introduces a double pole in the system at
a frequency of:
the FB pin to the system decoupling capacitor positive
terminal.
Components Selection
1
fLC
=
Inductor Selection
The inductance of the inductor is chosen such that the
2 ‧p ‧ L ‧C
peak−to−peak ripple current I
is approximately 20% to
L_PP
The NCV6356 internal compensation network is
optimized for a typical output filter comprising a 330 nH
inductor and 47 uF capacitor as describes in the basic
application schematic in Figure 53.
50% of the maximum output current I
. This
OUT_MAX
provides the best trade−off between transient response and
output ripple. The inductance corresponding to a given
current ripple is:
Voltage Sensing Considerations
(VIN − VOUT )‧VOUT
L =
In order to regulate the power supply rail, the NCV6356
must sense its output voltage. The IC can support two
sensing methods:
• Normal sensing: The FB pin should be connected to the
output capacitor positive terminal (voltage to regulate).
• Remote sensing: The power supply rail sense should be
made close to the system powered by the NCV6356.
The voltage to the system is more accurate, since the
PCB line impedance voltage drop is within the
VIN ‧ fSW ‧ IL _ PP
The selected inductor must have a saturation current
rating higher than the maximum peak current which is
calculated by:
IL _ PP
IL _ MAX = IOUT _ MAX
+
2
The inductor must also have a high enough current rating
to avoid self−heating. A low DCR is therefore preferred.
Refer to Table 25 for recommended inductors.
regulation loop. In this case, we recommend connecting
Table 25. INDUCTOR SELECTION
Value
Size (L x l x T)
(mm)
Saturation Current
Max (A)
DCR Max at 255C
(mW)
(uH)
0.33
0.33
0.33
Supplier
Cyntec
Cyntec
Cyntec
Part #
PIFE20161B−R33MS−11
PIFE25201B−R33MS−11
PIFE32251B−R33MS−11
2.0 x 1.6 x 1.2
2.5 x 2.0 x 1.2
3.2 x 2.5 x 1.2
4.0
5.2
6.5
33
17
14
www.onsemi.com
29
NCV6356
Table 25. INDUCTOR SELECTION
Value
(uH)
Size (L x l x T)
Saturation Current
Max (A)
DCR Max at 255C
(mW)
(mm)
Supplier
TOKO
TOKO
TOKO
TDK
Part #
DFE252012F−H−R33M
DFE201612E−H−R33M
FDSD0412−H−R33M
VLS252012HBX−R33M
SPM5030T−R35M
0.33
0.33
0.33
0.33
0.35
0.24
2.5 x 2.0 x 1.2
2.0 x 1.6 x 1.2
4.2 x 4.2 x 1.2
2.5 x 2.0 x 1.2
7.1 x 6.5 x 3.0
2.0 x 1.6 x 1.2
5.1
4.8
7.5
5.3
14.9
4.8
13
21
19
25
TDK
4
Chilisin
HEI201612A−R24M−AUDG
13.5
Output Capacitor Selection
The minimum input capacitance with respect to the input
The output capacitor selection is determined by output
voltage ripple and load transient response requirement. For
high transient load performance a high output capacitor
value must be used. For a given peak−to−peak ripple current
ripple voltage V
is
IN_PP
IOUT
‧ (D − D 2 )
VOUT
VIN
_ MAX
D =
C IN _ MIN
=
VIN _ PP ‧ fSW
Where
In addition, the input capacitor must be able to absorb the
input current, which has a RMS value of
I
in the inductor of the output filter, the output voltage
L_PP
ripple across the output capacitor is the sum of three
components as shown below.
IIN_RMS = IOUT_MAX ‧ D−D2
VOUT_PP [VOUT_PP(C) +VOUT_PP(ESR) +VOUT_PP(ESL)
,
The input capacitor also must be sufficient to protect the
device from over voltage spikes, and a 4.7 uF capacitor or
greater is required. The input capacitor should be located as
close as possible to the IC. All PGND pins must be
connected together to the ground terminal of the input cap
which then must be connected to the ground plane. All PVIN
pins must be connected together to the Vbat terminal of the
input cap which then connects to the Vbat plane.
With:
IL _ PP
VOUT _ PP (C )
=
8 ‧C ‧ fSW
VOUT _ PP(ESR) = IL_ PP ‧ESR
LESL
VOUT
=
‧VIN
Power Capability
The NCV6356’s power capability is driven by the
_ PP (ESL )
L
difference in temperature between the junction (T ) and
Where the peak−to−peak ripple current is given by
(VIN − VOUT )‧VOUT
J
ambient (T ), the junction−to−ambient thermal resistance
A
(Rq ), and the on−chip power dissipation (P ).
IL _ PP
=
JA
IC
VIN ‧ fSW ‧ L
The on−chip power dissipation P can be determined as
IC
P = P − P
In applications with all ceramic output capacitors, the
main ripple component of the output ripple is V
IC
T
L
with the total power losses P being
T
.
OUT_PP(C)
⎛
⎞
1
h
The minimum output capacitance can be calculated based on
P = VOUT ⋅ IOUT ⋅ ⎢ −1⎟
T
⎢
⎟
⎝
⎠
where h is the efficiency and P
a given output ripple requirement V
operation mode.
in PPWM
OUT_PP
L
P = ILOAD 2 ⋅ DCR
L
the simplified inductor power losses
.
I L _ PP
Now the junction temperature T can easily be calculated
J
CMIN
=
8 ‧VOUT
‧ fSW
_ PP
TJ = RqJA ⋅ P + TA
IC
as
Please note that the T should stay within the
recommended operating conditions.
J
Input Capacitor Selection
One of the input capacitor selection requirements is the
input voltage ripple. To minimize the input voltage ripple
and get better decoupling at the input power supply rail, a
ceramic capacitor is recommended due to low ESR and ESL.
The Rq is a function of the PCB layout (number of
JA
layers and copper and PCB size). For example, the
NCV6356 mounted on the EVB has a Rq about 30°C/W.
JA
www.onsemi.com
30
NCV6356
Layout Considerations
• AGND directly connected to the GND plane.
Electrical Rules
• PGND directly connected to Cin input capacitor, and
then connected to the GND plane: Local mini planes
used on the top layer (green) and the layer just below
the top layer (yellow) with laser vias.
Good electrical layout is key to proper operation, high
efficiency, and noise reduction. Electrical layout guidelines
are:
• Use wide and short traces for power paths (such as
PVIN, VOUT, SW, and PGND) to reduce parasitic
inductance and high−frequency loop area. It is also
good for efficiency improvement.
• The device should be well decoupled by input capacitor
and the input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission.
• SW track should be wide and short to reduce losses and
noise radiation.
• It is recommended to have separated ground planes for
PGND and AGND and connect the two planes at one
point. Try to avoid overlap of input ground loop and
output ground loop to prevent noise impact on output
regulation.
• Arrange a “quiet” path for output voltage sense, and
make it surrounded by a ground plane.
Thermal Rules
Good PCB layout improves the thermal performance and
thus allows for high power dissipation even with a small IC
package. Thermal layout guidelines are:
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
Figure 54. Placement Recommendation
• Use multiple vias around the IC to connect the inner
ground layers to reduce thermal impedance.
• Use a large and thick copper area especially in the top
layer for good thermal conduction and radiation.
• Use two layers or more for the high current paths
(PVIN, PGND, SW) in order to split current into
different paths and limit PCB copper self−heating.
Component Placement
• Input capacitor placed as close as possible to the IC.
• PVIN directly connected to Cin input capacitor, and
then connected to the Vin plane. Local mini planes used
on the top layer (green) and the layer just below the top
layer (yellow) with laser vias.
Figure 55. Demo Board Example (INTB not used)
• AVIN connected to the Vin plane just after the
capacitor.
www.onsemi.com
31
NCV6356
Table 26. ORDERING INFORMATION
†
OPN
Marking
Configuration
Package
Shipping
NCV6356CMTWTXG
6356C
6356B
6356Q
5.0 A
DFN 3.0 x 4.0 mm
3,000 Tape & Reel
3,000 Tape & Reel
3,000 Tape & Reel
1.150 V / 1.150 V
(Pb−Free)
NCV6356BMTWTXG
NCV6356QMTWTXG
5.0 A
1.200 V / 1.200 V
DFN 3.0 x 4.0 mm
(Pb−Free)
5.0 A
0.875 V / 0.906 V
DFN 3.0 x 4.0 mm
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
Demo board available:
• The NCV6356GEVB/D evaluation board that
configures the device in typical application to supply
constant voltage.
www.onsemi.com
32
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFNW14 4x3, 0.5P
CASE 511CM
ISSUE B
1
DATE 11 OCT 2019
SCALE 2:1
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
AYWWG
G
XXXXX = Specific Device Code
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
(*Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13091G
WDFNW14 4x3, 0.5P
PAGE 1 OF 1
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