NCV70514MW003BR2G_技术文档

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Micro-stepping Motor Driver

NCV70514

Description

The NCV70514 is a micro−stepping stepper motor driver for bipolar

stepper motors. The chip is connected through I/O pins and an SPI

interface with an external microcontroller. The NCV70514 contains

a current−translation table and takes the next micro−step depending on

the clock signal on the “NXT” input pin and the status of the “DIR”

(= direction) register or input pin. The chip provides an error message

if stall, an electrical error, an under−voltage or an elevated junction

temperature is detected. It is using a proprietary PWM algorithm

for reliable current control.

NCV70514 is fully compatible with the automotive voltage

requirements and is ideally suited for general−purpose stepper motor

applications in the automotive, industrial, medical, and marine

environment.

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MARKING

DIAGRAM

1

32

1

N70514−x

FAWLYYWW

G

QFN32, 5x5

CASE 488AM

Due to the technology, the device is especially suited for use

in applications with fluctuating battery supplies.

32

1

Features

QFNW32, 5x5

CASE 484AB

• Dual H−bridge for 2−phase Stepper Motors

• Programmable Peak−current up to 800 mA

• Low Temperature Boost Current

(available only for NCV70514MW007 device)

• On−chip Current Translator

N70514 = Specific Device Code

F

A

WL

YY

WW

G

= Fab Location

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

• SPI Interface with Daisy Chain Capability

• 7 Step Modes from Full−step up to 32 Micro−steps

• Fully Integrated Current−sensing and Current−regulation

• On Chip Stall Detection

ORDERING INFORMATION

See detailed ordering, marking and shipping information in the

package dimensions section on page 30 of this data sheet.

• PWM Current Control with Automatic Selection of Fast and Slow

Decay

• Fixed PWM Frequency

• Active Fly−back Diodes

• Full Output Protection and Diagnosis

• Thermal Warning and Shutdown

• Compatible with 3.3 V Microcontrollers, 5 V Tolerant Inputs, 5 V

Tolerant Open Drain Outputs

• Reset Function

• Overcurrent Protection

• Enhanced Under Voltage Management

• Step Mode Selection Inputs

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

Typical Applications

• Small Positioning Applications

• Automotive (headlamp alignment, HVAC, idle control, cruise control)

• Industrial Equipment (lighting, fluid control, labeling, process control, XYZ tables, robots)

• Building Automation (HVAC, surveillance, satellite dish, renewable energy systems)

1

Publication Order Number:

January, 2021 − Rev. 6

NCV70514/D

NCV70514

TYPICAL APPLICATION SCHEMATIC

The application schematic below shows typical connections for applications with low axis counts and/or with software SPI

implementation. For applications with many stepper motor drivers, some “minimal wiring” examples are shown at the last

sections of this datasheet.

D1

100 nF

C4

100 nF

C3

100 nF

C2

V_BAT

V_DD

C1

100 uF

R1

R2

VDD

VBB

DIR

NXT

DO

R3

R4

MOTXP

R11

R5

DI

NCV70514

C5

C6

CLK

MOTXN

uC

R6

CSB

M

R7

R8

MOTYP

MOTYN

STEP0

STEP1

ERRB

RHB

C7

C8

R9

R12

R10

TST1 TST2

GND

Figure 1. Typical Application Schematic

Table 1. EXTERNAL COMPONENTS

Component

C1

Function

Typ. Value

Max Tolerance

20%

Unit

mF

nF

kW

W

V

buffer capacitor (Note 1)

22 ... 100

BB

DD

C2, C3

decoupling capacitor (Note 2)

decoupling capacitor (Note 3)

100

20%

C4

100

20%

C5, C6, C7, C8

R1, R2

Optional EMC filtering capacitor (Note 4)

Pull up resistor

1 ... 3.3 max

20%

1..5

10%

R3 – R10

R11, R12

D1

Optional resistors

1

10%

Optional resistors (Note 5)

Optional reverse protection diode

100

10%

e.g. MURD530

1. Low ESR < 4 W, mounted as close as possible to the NCV70514. Total decoupling capacitance value has to be chosen properly to reduce

the supply voltage ripple and to avoid EM emission.

2. C2 and C3 must be close to pins VBB and coupled GND directly.

3. C4 must be a ceramic capacitor to assure low ESR.

4. Optional capacitors for improvement of EMC and system ESD performance. The slope times on motor pins can be longer than specified

in the AC table.

5. Value depends on characteristics of mC inputs for DO and ERRB signals.

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2

NCV70514

VDD

VBB

Internal voltage

regulator 3.3 V

Timebase

CLK

CSB

DI

STALL

EMC

MOTXP

MOTXN

P

W

M

T

TSD

SPI

R

A

N

S

L

A

T

O

R

I−sense

Open/

Short

DO

Logic &

Registers

NXT

DIR

EMC

MOTYP

MOTYN

P

W

M

OTP

POR

STEP0

STEP1

RHB

I−sense

NCV70514

UV

detect

Band−

gap

ERRB

GND

TST1

TST2

Figure 2. Block Diagram

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3

NCV70514

PACKAGE AND PIN DESCRIPTION

32

31

30

29

27

26

25

28

MOTYP

1

24

MOTXP

MOTYP

VBB

23

22

2

3

VBB

NC

21

20

19

18

4

QFN32 5x5

NC

5

6

7

DIR

STEP0

STEP1

CSB

RHB

NXT

17

8

10

11

12

13

14

15

16

9

Figure 3. Pin Connections – QFN32 5x5

Table 2. PIN DESCRIPTION

Pin No.

QFN32 5x5

Pin Name

MOTXP

VBB

Description

Positive end of phase X coil

Battery voltage supply

I/O Type

Driver output

Supply

1, 2

3, 4, 21, 22

5, 20

NC

Not Connected

6

STEP0

STEP1

CSB

Step mode selection input 0

Step mode selection input 1

SPI chip select input

Digital Input

Digital Output

Supply

7

8

9

DI

SPI data input

10

DO

SPI data output (Open Drain)

Error Output (Open Drain)

11

ERRB

VDD

12

Internal supply (needs external decoupling capacitor)

Ground

13

GND

Supply

14

TST1

TST2

CLK

Test pin input (to be tied to ground in normal operation)

SPI clock input

Digital Input

Driver output

Supply

15

16

17

NXT

Next micro−step input

18

RHB

Run/Hold Current selection input

Direction input

19

DIR

23, 24

25, 26, 31, 32

27, 28

29, 30

MOTYP

GNDP

MOTYN

MOTXN

Positive end of phase Y coil

Ground

Negative end of phase Y coil

Negative end of phase X coil

Driver output

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4

NCV70514

Table 3. ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Min

−0.3

−45

−55

−2

Max

+40

+6.0

+175

+160

+2

Unit

V

Supply voltage (Note 6)

V

BB

Digital input/outputs voltage

V

IO

V

Junction temperature range (Note 7)

Storage Temperature (Note 8)

T

j

°C

kV

T

strg

HBM Electrostatic discharge voltage (Note 9)

System Electrostatic discharge voltage (Note 10)

V

esd_hbm

V

−8

+8

syst_esd

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

6. V Max is +43 V for limited time <0.5 s.

BB

7. The circuit functionality is not guaranteed.

8. For limited time up to 100 hours. Otherwise the max storage temperature is 85°C.

9. HBM according to AEC−Q100: EIA−JESD22−A114−B (100 pF via 1.5 kW).

10.System ESD, 150 pF, 330 W, contact discharge on the connector pin, unpowered.

Operating ranges define the limits for functional

operation and parametric characteristics of the device. A

mission profile (Note 11) is a substantial part of the

operation conditions; hence the Customer must contact

ON Semiconductor in order to mutually agree in writing on

the allowed missions profile(s) in the application.

Table 4. RECOMMENDED OPERATING RANGES

Characteristic

Symbol

Min

+6

Typ

Max

+29

Unit

V

Battery Supply voltage

V

BB

Digital input/outputs voltage

V

0

+5.5

+145

+160

V

IO

Parametric operating junction temperature range (Notes 12, 14)

Functional operating junction temperature range (Notes 13, 14)

T

−40

°C

jp

T

jf

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

11. A mission profile describes the application specific conditions such as, but not limited to, the cumulative operating conditions over life time,

the system power dissipation, the system’s environmental conditions, the thermal design of the customer’s system, the modes, in which the

device is operated by the customer, etc. No more than 100 cumulated hours in life time above T .

tw

12.The parametric characteristics of the circuit are not guaranteed outside the Parametric operating junction temperature range.

13.The maximum functional operating temperature range can be limited by thermal shutdown T

.

tsd

14.The cold boost motor current shall be enabled only for ambient temperature below 25°C.

PACKAGE THERMAL CHARACTERISTIC

• PCB board copper area (via the device pins and

exposed pad)

The major thermal resistances of the device are the Rth

from the junction to the ambient (Rthja) and the Rth from the

junction to the exposed pad (Rthjp).

Using an exposed die pad on the bottom surface of the

package is mainly contributing to this performance. In order

to take full advantage of the exposed pad, it is most

important that the PCB has features to conduct heat away

from the package. In the table below, one can find the values

for the Rthja and Rthjp:

The NCV70514 is available in thermally optimized

QFN32 5x5 package. For the optimizations, the package has

an exposed thermal pad which has to be soldered to the PCB

ground plane. The ground plane needs thermal vias to

conduct the heat to the bottom layer.

For precise thermal cooling calculations the major

thermal resistances of the devices are given. The thermal

media to which the power of the devices has to be given are:

• Static environmental air (via the case)

Table 5. THERMAL RESISTANCE

Package

QFN32 5x5

15.The Rthja for 2S2P simulated for worst case power and following conditions:

Rth, Junction−to−Exposed Pad, Rthjp

Rth, Junction−to−Ambient, Rthja (Note 15)

15 K/W

39 K/W

•

A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used

Board thickness is 1.46 mm (FR4 PCB material)

2

All four layers: 30 um thick copper with an area of 2500 mm where:

− Top layer with 70% copper coverage in 20x20 mm around device, rest 40% copper coverage

− In layer 1 with 70% copper coverage

− In layer 2 with 98% copper coverage

− Bottom layer with 90% copper coverage

•

The 12 vias in Exposed Pad area, via diameter 0.4 mm

Gap−filler max 400 mm between PCB and heat sink non conductive with worst case thermal conductivity of 1.5 W/mK

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5

NCV70514

EQUIVALENT SCHEMATICS

The following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified

representations of the circuits used.

DIGITAL

OUT

DIGITAL

IN

ERRB,

DO

DI, CLK,

NXT, DIR,

RHB,

Ipd

STEP0,

STEP1,

(CSB)

MOT

OUT

VDD

VBB

MOTXP,

MOTXN,

MOTYN,

MOTYP

Figure 4. Input and Output Equivalent Diagrams

ELECTRICAL CHARACTERISTICS

DC PARAMETERS

The DC parameters are guaranteed over junction temperature from −40 to 145°C and VBB in the operating range from 6

to 29 V, unless otherwise specified. Convention: currents flowing into the circuit are defined as positive.

Table 6. DC PARAMETERS

Symbol

Pin(s)

Parameter

Test Conditions

Min

Typ

Max

Unit

MOTORDRIVER

I

-

MOTXP

MOTXN

MOTYP

MOTYN

Max current through motor coil in

normal operation

V

= 14 V

= 14 V,

800

mA

%

MS

BB

max,Peak

I

Absolute error on coil current

(Note 16)

−10

−7

10

7

MSabs

BB

T = 145°C

j

I

Matching of X & Y coil currents

(Note 16)

V

BB

= 14 V

%

MSrel

R

On resistance of High side + Low side

Driver at the highest current range

T ≤ 25°C

1.8

2.4

W

DS(on)

j

T = 145°C

j

R

Motor pin pull−down resistance

HiZ mode

70

kW

mpd

LOGIC INPUTS

V

DI, CLK,

NXT,

DIR,

RHB,

STEP0,

STEP1

Logic low input level, max

Logic high input level, min

Logic low input level, max

Logic high input level, max

T = 145°C

0.8

4

V

inL

inH

inL

j

V

T = 145°C

j

2.4

−1

1

I

T = 145°C

j

mA

I

T = 145°C

j

2

inH

16.Tested in production for 800 mA, 400 mA, 200 mA and 100 mA current settings for both X and Y coil.

17.CSB has an internal weak pull−up resistor of 100 kW.

18.Thermal warning is derived from thermal shutdown (T = T − 20°C).

tw

tsd

19.No more than 100 cumulated hours in life time above T .

tw

20.Parameter guaranteed by trimming relevant OTPs in production test at 160°C and V = 14 V.

BB

21.Dynamic current is with oscillator running, all analogue cells active. Coil currents 0 mA, SPI active, ERRB inactive, no floating inputs, TST

input tied to GND.

22.All analog cells in power down. Logic powered, no clocks running. All outputs unloaded, no floating inputs.

23.Pin VDD must not be used for any external supply.

24.The SPI registers content will not be altered above this voltage.

25.Maximum allowed drain current that the output can withstand without getting damaged. Not tested in production.

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6

NCV70514

Table 6. DC PARAMETERS

Symbol

Pin(s)

Parameter

Test Conditions

Min

Typ

Max

Unit

LOGIC INPUTS

V

CSB

Logic low input level, max

T = 145°C

0.8

V

inL

inH

inL

j

V

Logic high input level, min

T = 145°C

j

2.4

I

Logic low input level, max (Note 17)

Logic high input level, max (Note 17)

Internal pull−down resistor

T = 145°C

j

−50

−30

−10

1

mA

kW

I

T = 145°C

j

inH

R

TST1

3

9

pd

LOGIC OUTPUTS

V

DO,

ERRB

Output voltage when

8 mA sink current

0.4

5.5

12

V

OLmax

OHmax

OLmax

V

Maximum drain voltage

I

Maximum allowed drain current

(Note 25)

mA

THERMAL WARNING & SHUTDOWN

T

Thermal warning (Notes 18 and 19)

Thermal shutdown (Note 20)

136

156

145

165

154

174

°C

tw

T

tsd

SUPPLY AND VOLTAGE REGULATOR

UV

V

BB

H−Bridge off voltage low threshold

5.98

V

3

UV

Under voltage low threshold

UVxThr[3:0] = 0000

UVxThr[3:0] = 1111

1

2

10.96

0.33

UV

Under voltage low threshold step

Between two UVxThr

codes

1_STEP

2_STEP

UV

Under voltage low threshold accuracy

Under voltage hysteresis

−4

4

%

X_ACC

UV

I

30

150

4

310

15

mV

mA

X_HYST

I

Total current consumption (Note 21)

Unloaded outputs

bat

V

= 29 V

BB

Sleep mode current consumption

(Note 22)

V

BB

= 5.5 V & 18 V

90

150

mA

bat_s

V

DD

Regulated internal supply (Note 23)

5.5 V < V < 29 V

3.0

3.3

3.6

3.0

V

DD

BB

V

Digital supply reset level @ power

down (Note 24)

ddReset

I

Current limitation

Pin shorted to ground

80

mA

ddLim

V

= 14 V

BB

16.Tested in production for 800 mA, 400 mA, 200 mA and 100 mA current settings for both X and Y coil.

17.CSB has an internal weak pull−up resistor of 100 kW.

18.Thermal warning is derived from thermal shutdown (T = T − 20°C).

tw

tsd

19.No more than 100 cumulated hours in life time above T .

tw

20.Parameter guaranteed by trimming relevant OTPs in production test at 160°C and V = 14 V.

BB

21.Dynamic current is with oscillator running, all analogue cells active. Coil currents 0 mA, SPI active, ERRB inactive, no floating inputs, TST

input tied to GND.

22.All analog cells in power down. Logic powered, no clocks running. All outputs unloaded, no floating inputs.

23.Pin VDD must not be used for any external supply.

24.The SPI registers content will not be altered above this voltage.

25.Maximum allowed drain current that the output can withstand without getting damaged. Not tested in production.

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7

NCV70514

Figure 5. ON Resistance of High Side + Low Side Driver at the Highest Current Range

AC PARAMETERS

The AC parameters are guaranteed over junction temperature from −40 to 145°C and VBB in the operating range from 6

to 29 V, unless otherwise specified.

Table 7. AC PARAMETERS

Symbol

Pin(s)

Parameter

Frequency of internal oscillator

PWM frequency

Test Conditions

Min

7.2

Typ

Max

8.8

Unit

INTERNAL OSCILLATOR

f

V

BB

= 14 V

8

MHz

osc

MOTORDRIVER

f

MOTxx

(Note 26)

20.5

22.8

5

25.1

kHz

ms

pwm

t

Open coil detection with

PWM=100% (Note 26)

SPI bit OpenDet[1:0] = 00

SPI bit OpenDet [1:0] = 01

SPI bit OpenDet [1:0] = 10

SPI bit OpenDet [1:0] = 11

SPI bit EMC[1:0] = 00

SPI bit EMC[1:0] = 01

SPI bit EMC[1:0] = 10

SPI bit EMC[1:0] = 00

SPI bit EMC[1:0] = 01

SPI bit EMC[1:0] = 10

OCdet

25

50

200

80

t

Turn−on transient time, between

ns

brise

10% and 90%, I

BB

= 200 mA,

MD

120

190

70

V

= 14 V, 1 nF at motor pins

t

Turn−off transient time, between

10% and 90%, I = 200 mA,

bfall

MD

110

180

V

BB

= 14 V, 1 nF at motor pins

DIGITAL OUTPUTS

t

DO,

ERRB

Output fall−time (90% to 10%)

from V to V

Capacitive load 200 pF and

50

ns

H2L

pull−up 1.5 kW

InH

InL

HARD RESET FUNCTION

t

DIR

Hard reset trigger time (Note 26)

Hard reset DIR pulse width

RHB set−up time

See hard reset function

(Note 26)

20

2.5

5

200

ms

hr_trig

t

−2.5

hr_dir

hr_set

hr_trig

t

RHB

ERRB

CSB

(Note 26)

ms

t

Hard reset error indication

CSB wake−up low pulse width

Wake−up time

(Note 26)

2

hr_err

t

(Note 26)

1

150

csb_width

t

wu

See Sleep Mode

250

ms

26.Derived from the internal oscillator

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8

NCV70514

Table 7. AC PARAMETERS

Symbol

Pin(s)

Parameter

Test Conditions

Min

Typ

Max

Unit

NXT/DIR/STEP0/STEP1 INPUTS

t

NXT

NXT minimum, high pulse width

NXT minimum, low pulse width

NXT max repetition rate

2

ms

NXT_HI

t

NXT_LO

f

/2

kHz

ms

NXT

CSB_LO_WIDTH

PWM

t

NXT pin trigger after SPI NXT

command

1

t

NXT,

DIR,

STEP0,

STEP1

NXT hold time, following change

of DIR, STEP0 or STEP1

25

ms

DIR_SET

t

NXT hold time, before change of

DIR, STEP0 or STEP1

DIR_HOLD

26.Derived from the internal oscillator

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Table 8. SPI INTERFACE

Symbol

Parameter

Min

1

Typ

Max

Unit

ms

ns

ms

ns

ms

ns

t

SPI clock period

CLK

t

SPI clock high time

SPI clock rise time

SPI clock fall time

SPI clock low time

200

HI_CLK

t

1

CLKRISE

CLKFALL

t

200

50

LO_CLK

t

DI set up time, valid data before rising edge of CLK

DI hold time, hold data after rising edge of CLK

CSB high time

SET_DI

t

50

HOLD_DI

t

2.5

1

HI_CSB

SET_CSB_LO

t

CSB set up time, CSB low before rising edge of CLK (Note 27)

CSB set up time, CSB high after rising edge of CLK

DO delay time, DO settling time after CSB low (Note 28)

DO delay time, DO settling time after CLK low (Note 28)

t

200

CLK_CSB_HI

DEL_CSB_DO

t

250

100

t

DEL_CLK_DO

27.After leaving sleep mode an additional wait time of 250 ms is needed before pulling CSB low.

28.Specified for a capacitive load 10 pF and a pull−up resistor of 1.5 kW.

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NCV70514

0.8 Vcc

0.2 Vcc

CS

t_{HI_CSB}

t_{SET_CSB_LO}

t_CLKRISE

0.8 Vcc

t_CLK

T_{CLK_CSB_HI}

t_CLKFALL

CLK

0.2 Vcc

t_{LO_CLK}

t_{HI_CLK}

t_{HOLD _DI}

t_{SET_DI}

0.8 Vcc

DI

Valid

t_{DEL_CLK_DO}

t_{DEL_CSB_DO}

0.8 Vcc

DO

Valid

Figure 6. SPI Timing

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NCV70514

DETAILED OPERATING DESCRIPTION

H−Bridge Drivers with PWM Control

In order to reduce the radiated/conducted emission,

voltage slope control is implemented in the output switches.

Two bits in SPI control register 3 allow adjustment of the

voltage slopes.

A protection against shorts on motor lines is implemented.

When excessive voltage is sensed across a MOSFET for a

time longer than the required transition time, then the

MOSFET is switched−off.

Two H−bridges are integrated to drive a bipolar stepper

motor. Each H−bridge consists of two low−side N−type

MOSFET switches and two high−side P−type MOSFET

switches. One PWM current control loop with on−chip

current sensing is implemented for each H−bridge.

Depending on the desired current range and the micro−step

position at hand, the R

of the low−side transistors will

DS(on)

be adapted to maintain current−sense accuracy. A

comparator compares continuously the actual winding

current with the requested current and feeds back the

information to generate a PWM signal, which turns on/off

the H−bridge switches. The switching points of the PWM

duty−cycle are synchronized to the on−chip PWM clock. For

each output bridge the PWM duty cycle is measured and

stored in two appropriate status registers of the motor

controller.

The PWM frequency will not vary with changes in the

supply voltage. Also variations in motor−speed or load−

conditions of the motor have no effect. There are no external

components required to adjust the PWM frequency. In order

to avoid large currents through the H−bridge switches, it is

guaranteed that the top− and bottom−switches of the same

half−bridge are never conductive simultaneously (interlock

delay).

Motor Enable−Disable

The H−bridges and PWM control can be disabled

(high−impedance state) by means of a bit <MOTEN> in the

SPI control registers. <MOTEN>=0 will only disable the

drivers and will not impact the functions of NXT, DIR,

RHB, SPI bus, etc. The H−bridges will resume normal PWM

operation by writing <MOTEN>=1 in the SPI register.

PWM current control is then enabled again and will regulate

current in both coils corresponding with the position given

by the current translator.

Automatic Forward and Slow−Fast Decay

The PWM generation is in steady−state using a

combination of forward and slow−decay. For transition to

lower current levels, fast−decay is automatically activated to

allow high−speed response. The selection of fast or slow

decay is completely transparent for the user and no

additional parameters are required for operation.

Icoil

Set value

Actual value

t

0

t

pwm

Forward& Slow Decay

Fast Decay & Forward

Figure 7. Forward and Slow/Fast Decay PWM

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11

NCV70514

PWM Duty Cycle Measurement

For both motor windings the actual PWM duty cycle is

measured and stored in two status registers. The duty cycle

values are a representation of the applied average voltage to

the motor windings to achieve and maintain the actual set

point current. Figure 8 gives an example of the duty cycle

representation.

Set value

Icoil

0

PWM

Voltage

t

−48%

−38%

−40%

PWM Value

40%

Figure 8. PWM Duty Cycle Measurement

Automatic Duty Cycle Adaptation

If during regulation the set point current is not reached

completely automatic and requires no additional parameters

for operation. The state of the duty cycle adaptation mode is

represented in the T/B bits of the appropriate status registers

for both motor windings X and Y. Figure 9 gives a

representation of the duty cycle adaptation.

before 75% of t

, the duty cycle of the PWM is adapted

pwm

automatically to > 50% (top regulation) to maintain the

requested average current in the coils. This process is

|Icoil|

Duty Cycle

< 50%

Duty Cycle < 50%

Set value

Duty Cycle > 50%

Actual value

0

t

pwm

Bit T/B

Bottom reg. Bit T/B = 0

Top reg. Bit T/B = 1

Figure 9. Automatic Duty Cycle Adaptation

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12

NCV70514

Step Translator

Step Mode

The step translator provides the control of the motor

by means of SPI register step mode: SM[2:0], SPI bits DIRP,

RHBP and input pins STEP0, STEP1, DIR (direction of

rotation), RHB (run/hold of motor) and NXT (next pulse).

It is translating consecutive steps in corresponding currents

in both motor coils for a given step mode.

position are set to “0”. This means that the position in the

current table moves to the right and in the case that

micro−step position of desired new resolution does not

overlap the micro−step position of current resolution, the

closest value up or down in required column is set depending

on the direction of rotation.

One out of seven possible stepping modes can be selected

through SPI−bits SM[2:0] and pins STEP0, STEP1. Device

takes the value from SPI−bits SM[2:0] and increases

StepMode value with adding binary information from

STEP0, STEP1 pins. After power−on or hard reset, the

coil−current translator is set to the default to 1/32

micro−stepping at position ‘16*’. When remaining in the

default step mode, subsequent translator positions are all in

the same column and increased or decreased with 1. Table 9

lists the output current versus the translator position.

When the micro−step resolution is reduced, then the

corresponding least−significant bits of the translator

When the micro−step resolution is increased, then the

corresponding least−significant bits of the translator

position are added as “0”: the micro−step position moves to

the left on the same row.

In general any change of <SM[2:0]> SPI bits or STEP0

and STEP1 pins have no effect on current micro−step

position without consequent occurrence of NXT pulse or

<NXTP> SPI command. (see NXT input timing below).

When NXT pulse or <NXTP> SPI command arrives, the

motor moves into next micro−step position according to the

current <SM[2:0]> SPI bits value and STEP0, STEP1 pins

level set.

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13

NCV70514

Table 9. CIRCULAR TRANSLATOR TABLE

Step mode SM[2:0]

% of Imax

Step mode SM[2:0]

% of Imax

000

001

010

1/8

0

011

1/4

0

100

1/2

0

000

1/32

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

001

1/16

32

−

010

1/8

16

−

011

1/4

8

100

1/2

4

1/32 1/16

MSP[6:0]

000 0000

000 0001

000 0010

000 0011

000 0100

000 0101

000 0110

000 0111

000 1000

000 1001

000 1010

000 1011

000 1100

000 1101

000 1110

000 1111

Coil Y Coil X MSP[6:0]

Coil Y Coil X

0

1

0

−

0

100

99.9

99.5

98.9

98.1

97

100 0000

100 0001

100 0010

100 0011

100 0100

100 0101

100 0110

100 0111

100 1000

100 1001

100 1010

100 1011

100 1100

100 1101

100 1110

100 1111

101 0000

101 0001

101 0010

101 0011

101 0100

101 0101

101 0110

101 0111

101 1000

101 1001

101 1010

101 1011

101 1100

101 1101

101 1110

101 1111

110 0000

110 0001

110 0010

110 0011

110 0100

110 0101

110 0110

0

−100

−

1

−

1

−

1

4.9

−

5

−4.9 −99.9

−9.8 −99.5

−14.7 −98.9

−19.5 −98.1

2

1

9.8

33

−

3

−

14.7

19.5

24.3

29

−

4

2

34

−

17

−

5

−

2

−

−24.3

−97

6

3

95.7

94.2

92.4

90.4

88.2

85.8

83.1

80.3

77.3

74.1

70.7

67.2

63.4

59.6

55.6

51.4

47.1

42.8

38.3

33.7

29

35

−

−29 −95.7

−33.7 −94.2

−38.3 −92.4

−42.8 −90.4

−47.1 −88.2

−51.4 −85.8

−55.6 −83.1

−59.6 −80.3

−63.4 −77.3

−67.2 −74.1

−70.7 −70.7

−74.1 −67.2

−77.3 −63.4

−80.3 −59.6

−83.1 −55.6

−85.8 −51.4

−88.2 −47.1

−90.4 −42.8

−92.4 −38.3

−94.2 −33.7

7

−

33.7

38.3

42.8

47.1

51.4

55.6

59.6

63.4

67.2

70.7

74.1

77.3

80.3

83.1

85.8

88.2

90.4

92.4

94.2

95.7

97

−

8

4

36

−

18

−

9

−

3

−

2

−

10

11

12

13

14

15

5

37

−

6

38

−

19

−

4

−

7

39

−

001 0000 16(*)

8

40

−

20

−

10

−

001 0001

001 0010

001 0011

001 0100

001 0101

001 0110

001 0111

001 1000

001 1001

001 1010

001 1011

001 1100

001 1101

001 1110

001 1111

010 0000

010 0001

010 0010

010 0011

010 0100

010 0101

010 0110

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

−

5

−

3

−

2

−

6

9

41

−

10

−

42

−

21

−

6

−

11

−

43

−

12

−

44

−

22

−

11

−

7

−

4

13

−

45

−

−95.7

−29

24.3

19.5

14.7

9.8

−

−97 −24.3

−98.1 −19.5

−98.9 −14.7

14

−

98.1

98.9

99.5

99.9

100

46

−

23

−

8

−

15

−

47

−

−99.5

−99.9

−100

−99.9

−99.5

−98.9

−98.1

−97

−9.8

−4.9

0

4.9

−

16

−

0

48

−

24

−

12

−

9

−

99.9

99.5

−4.9

−9.8

−

4.9

17

−

49

−

9.8

98.9 −14.7

98.1 −19.5

−

14.7

19.5

24.3

29

18

−

50

−

25

−

97

−24.3

−29

−

19

95.7

51

−

−95.7

*Default position after reset of the translator position.

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14

NCV70514

Table 9. CIRCULAR TRANSLATOR TABLE

Step mode SM[2:0]

% of Imax

Step mode SM[2:0]

% of Imax

000

1/32

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

001

1/16

−

010

1/8

−

011

1/4

−

100

1/2

−

000

1/32

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

001

1/16

−

010

1/8

−

011

1/4

−

100

1/2

−

MSP[6:0]

010 0111

010 1000

010 1001

010 1010

010 1011

010 1100

010 1101

010 1110

010 1111

011 0000

011 0001

011 0010

011 0011

011 0100

011 0101

011 0110

011 0111

011 1000

011 1001

011 1010

011 1011

011 1100

011 1101

011 1110

011 1111

Coil Y Coil X

94.2 −33.7

92.4 −38.3

90.4 −42.8

88.2 −47.1

85.8 −51.4

83.1 −55.6

80.3 −59.6

77.3 −63.4

74.1 −67.2

70.7 −70.7

67.2 −74.1

63.4 −77.3

59.6 −80.3

55.6 −83.1

51.4 −85.8

47.1 −88.2

42.8 −90.4

38.3 −92.4

33.7 −94.2

MSP[6:0]

110 0111

110 1000

110 1001

110 1010

110 1011

110 1100

110 1101

110 1110

110 1111

111 0000

111 0001

111 0010

111 0011

111 0100

111 0101

111 0110

111 0111

111 1000

111 1001

111 1010

111 1011

111 1100

111 1101

111 1110

111 1111

Coil Y Coil X

−94.2

−92.4

−90.4

−88.2

−85.8

−83.1

−80.3

−77.3

−74.1

−70.7

−67.2

−63.4

−59.6

−55.6

−51.4

−47.1

−42.8

−38.3

−33.7

−29

33.7

38.3

42.8

47.1

51.4

55.6

59.6

63.4

67.2

70.7

74.1

77.3

80.3

83.1

85.8

88.2

90.4

92.4

94.2

95.7

97

20

−

10

−

5

−

52

−

26

−

13

−

21

−

53

−

22

−

11

−

54

−

27

−

23

−

55

−

24

−

12

−

6

3

56

−

28

−

14

−

7

−

25

−

57

−

26

−

13

−

58

−

29

−

27

−

59

−

28

−

14

−

7

−

60

−

30

−

15

−

29

−

29

−95.7

−97

61

−

24.3

−

−24.3

−19.5

−14.7

−9.8

30

−

15

−

19.5 −98.1

14.7 −98.9

9.8 −99.5

4.9 −99.9

62

−

31

−

98.1

98.9

99.5

99.9

−

31

−

63

−

−4.9

*Default position after reset of the translator position.

Besides the micro−step modes listed above, also two full

step modes are implemented. Full step mode 1 activates

always only one coil at a time, whereas mode 2 always keeps

2 coils active. The table below lists the output current versus

the translator positions for these cases and Figure 10 shows

the projection on a square.

modes. Changing from one full step mode to another full

step mode will always result in a “45deg step−back or

forward” depending on the DIR bit. For example: in the

table below, when changing full step mode (positioner is on

a particular row and full step column), then the new full step

location will be one row above or below in the adjacent “full

step column”. The step−back and forward is executed after

the NXT pulse.

Changing between micro−step mode and full step modes

follows a similar scheme as changes between micro−step

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15

NCV70514

Table 10. SQUARE TRANSLATOR TABLE FOR FULL STEP

Step mode ( SM[2:0] )

101 or 110

% of Imax

111

Full Step1

Full Step2

MSP[6:0]

000 0000

001 0000

010 0000

011 0000

100 0000

101 0000

110 0000

111 0000

Coil x

100

71

Coil y

0

−

1

−

2

−

3

−

0

−

1

−

2

−

3

71

0

100

71

−71

−100

−71

0

−71

−100

−71

71

I_y

1

3

2

1

2

0

3

I_x

2

0

3

1/4^thMicro−step

SM[2:0] = 011

Full Step 1

SM[2:0] = 101

Full Step 2

SM[2:0] = 111

Figure 10. Translator Table: Circular and Square

Translator Position

The translator position can be read in the SPI register

<MSP[6:0]>. This is a 7−bit number equivalent to the 1/32

micro−step from : Circular Translator Table. The translator

position is updated immediately following

micro−step trigger (see below).

Positive direction of rotation means counter−clockwise

rotation of electrical vector Ix + Iy. Also when the motor is

disabled (<MOTEN>=0), both the DIR pin and <DIRP>

will have an effect on the positioner. The logic state of the

DIR pin is visible as a flag in SPI status register.

th

a next

Next Micro−Step Trigger

Positive edges on the NXT input − or activation of the

“NXT pushbutton” <NXTP> in the SPI input register − will

move the motor current one step up/down in the translator

table. The <NXTP> bit in SPI is used to move positioner one

(micro−)step by means of only SPI commands. If the bit is

set to “1”, it is reset automatically to “0” after having

advanced the positioner with one micro−step.

NXT

Update

Translator Position

Update

Translator Position

Figure 11. Translator Position Timing Diagram

Direction

Trigger “Next micro−step” = (positive edge on NXT−pin) OR

(<NXTP>=1)

The direction of rotation is selected by means of input pin

DIR and its “polarity bit” <DIRP> (SPI register). The

polarity bit <DIRP> allows changing the direction of

rotation by means of only SPI commands instead of the

dedicated input pin.

• Also when the motor is disabled (<MOTEN>=0),

NXT/DIR/RHB functions will move the positioner

according to the logic.

• In order to be sure that both the NXT pin and the

<NXTP> SPI command are individually attended, the

following non overlapping zone has to be respected.

In this case it is guaranteed that both triggers will have

effect (2 steps are taken).

Direction = DIR−pin EXOR <DIRP>

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16

NCV70514

or <NXTP> SPI command only. On the other hand, the SPI

bits <DIRP>, <SM[2:0]> and <NXTP> can change state at

the same time in the same SPI command: the next

micro−step will be applied with the new settings.

0.8 V_CC

CSB

NXT

t_{CSB_LO_WIDTH}

IRUN, IHOLD and “Run / Not Hold” Mode

The RHB input pin and it’s “polarity bit” <RHBP> (SPI

register) allow to switch the driver between “Run Mode” and

“Hold Mode”.

0.2 V_CC

Figure 12. NXT Input Non Overlapping Zone with

the <NXTP> SPI Command

“Run Mode” = NOT(“Hold Mode”) = RHB−pin EXOR

<RHBP>

• In “Run mode”, the current translator table is stepped

through based on the “NXT & DIR” commands. The

amplitude of the motor current (=Imax) is set by SPI

control register <IRUN[3:0]>.

• In “Hold mode”, NXT & DIR will have no effect and

the position in the current translator table is maintained.

The motor current amplitude is set by SPI control

register <IHOLD[3:0]>.

t_{NXT_HI}

t_{NXT_LO}

0.5V_CC

NXT

t_{DIR_SET}

t_{DIR_HOLD}

By setting bit <Iboost> in NCV70514MW007 device in

SPI Control register 4A, the current table will be changed

from 800 mA peak current range to 1.1 A peak current range.

All currents will scale proportionally according to the

following table. The boost function can be activated at

temperatures below thermal warning temperature TW. Above

thermal warning temperature TW, the boost function is

automatically disabled and current is decreased to unboosted

level. Status of the boost function can be read in SPI <Iboost>

bit. Thermal profile and mission profile must be checked by

ON Semiconductor to guarantee the reliability.

DIR

VALID

STEPx

VALID

Figure 13. NXT Input Timing Diagram

For control by means of I/O’s, the NXT pin operation with

respect to DIR, STEP0 and STEP1 pins should be in a

non−overlapped way. See also the timing diagram below

(refer to the AC table for the timing values). The STEP0 and

STEP1 pins or <SM[2:0]> SPI bits setting, when changed,

is accepted upon the consequent either NXT pin rising edge

The run and hold current settings correspond to the

following current levels:

Table 11. IRUN AND IHOLD VALUES (4BIT)

Register

Value

Peak Motor

Current IRUN (mA)

Peak Motor

Current IRUN (mA)

Peak Motor

Current IHOLD (mA)

Peak Motor

Current IHOLD (mA)

I

= 0

I

= 1

I

= 0

I

= 1

boost

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

59

81

0

71

84

98

59

71

84

81

98

116

138

164

194

231

275

327

389

462

550

655

778

925

1100

100

119

141

168

200

238

283

336

400

476

566

673

800

116

138

164

194

231

275

327

389

462

550

655

778

925

100

119

141

168

200

238

283

336

400

476

566

673

NOTE: During hold with a hold current of 0 mA the stall and motion detection and the open coil detection are disabled. The PWM duty

cycle registers will present 0% duty cycle.

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17

NCV70514

Whenever <IRUN[3:0]> or <IHOLD[3:0]> is changed, the

new coil currents will be updated immediately at the next

PWM period.

Table 12. UV1/2 THRESHOLDS SETTINGS (4BIT)

UVxThr Index

UV1/2 Threshold Level (V)

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

5.98

6.31

6.65

6.98

7.31

7.64

7.97

8.31

8.64

8.97

9.3

In case the motor is disabled (<MOTEN>=0), the logic is

functional and both RHB pin and <RHBP> bit will have

effect on NXT/DIR operation (not on the H−bridges). When

the chip is in sleep mode, the logic is not functional and as

a result, the RHB pin will have no effect.

The logic state of the RHB pin is visible as a flag in SPI

status register.

Note: The hard−reset function is embedded in the “Hold

mode” by means of a special sequence on the DIR pin, see

also Hard−Reset Function chapter.

Under−voltage Detection

The NCV70514 has three UV threshold levels. Two

higher threshold levels are programmable over SPI register

UVxThr, third threshold level is fixed.

Each UV level has its own flag readable via SPI and can

create interrupt to microcontroller when dedicated bit of

interrupt enable register is set.

9.63

9.97

10.3

10.63

10.96

All interrupt sources UV’s, BEMF, etc. are grouped

into single interrupt line (pin) ERRB.

When supply voltage VBB drops under dedicated UVx

level, several actions are performed.

Stall and Motion Detection

Motion detection is based on the Back Electromotive

Force (BEMF or back emf) generated into the running

motor. When the motor is blocked, e.g. when it hits the

end−position, the velocity and as a result also the generated

back emf, is disturbed. The NCV70514 measures the back

emf during the current zero crossing phase and makes it

available in the SPI status register 4. The back emf voltage

is measured several times in each PWM cycle during zero

crossing phase. Samples taken during PWM ON phase of the

switches in the second coil are discarded not to add noise to

measurement (see Figure 14). Results are then converted

into a 5−bits word <Bemf[4:0]> with the following formula:

• UV1 level – no action inside device regarding to

H−bridges – only when UV1IntEn interrupt enable bit

is set, ERRB pin is pulled down. Microcontroller needs

to do action like Soft stop, etc based on this interrupt.

• UV2 level – when UV2IntEn interrupt enable bit is set,

ERRB pin is pulled down. When UV2MIntEn interrupt

enable bit is set, the ERRB pin is pulled down in the

moment NXP pulse comes, the device then stops

executing NXT pulses and starts counting them in Step

loss counter <Sl[6:0]>.

• UV3 level – device each time disables H−Bridge

drivers (<MOTEN> = 0). When UV3IntEn interrupt

enable bit is set, ERRB pin is pulled down. When

UV3MIntEn interrupt enable bit is set, the ERRB pin is

pulled down in the moment NXP pulse comes, the

device then stops executing NXT pulses and starts

counting them in Step loss counter <Sl[6:0]>.

BEMF_code(dec) +

2⁵

5

_{V_MOT_XorY_diff(V) @ Gain @}ǒ₄Ǔ_@_2.41

When the result is ready, it is indicated by <BemfRes> bit

in status register.

When using normal mode of back emf measurement

(<EnhBemfEn> = 0), last sample before end of current zero

crossing phase becomes available in <Bemf[4:0]> register

(see the red circle on Figure 14).

When the enhanced back emf measurement mode is set by

<EnhBemfEn> bit, all non discarded results are

continuously available in <Bemf[4:0]> register (see red and

all black circles on Figure 14). This allows microcontroller

Only if the <UV3>=0 the motor can be enabled again

by writing <MOTEN>=1 in the control register 1.

Note: The change of DIR and step mode will not be taken

into account in Step loss counter.

Step loss register range is 7 bits => 0 to 127 NXT pulses, no

overflow, keeping the counter at maximum value of 127 if

more than 127 NXT pulses are received.

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18

NCV70514

(when reading content of the register fast enough) to follow

stall bit cleared, the chip reacts on “Next Micro−step

Triggers” only after direction has changed its state at least

once.

back emf signal and its shape during zero crossing phase and

use more complex algorithms to optimize the work of driven

stepper motor.

An additional feature of the NCV70514 is the detection of

uncontrolled motion during Hold. If the stall detection is

enabled and the hold position is at full steps (full step mode1,

0°, 90°, 180°, 270°) with only excitation of one coil, the

NCV70514 is checking upon back emf voltages higher than

or equal to the <StThr[3:0]> threshold. If this voltage is

detected, it indicates there is a motor movement. The stall bit

in the SPI register is set and the ERRB pin is pulled down.

The motion detection during hold does not work for IHold

0 A.

I coil X

Ideal Coil Current

0

Real Coil Current

Current Decay

Zero crossing position

(0;64)

Notes:

t

NXT

1. Used stall detection is covered by patent US

8,058,894B2

2. As the stall threshold register <StThr[3:0]> is 4

bits wide, the 4 MSBs of 5−bit <Bemf[4:0]>

register are taken for comparison.

Pins MXP/MXN in HiZ state

V MXP/MXN

MXN MXN

MXP MXP MXP

VBB+ 0.6 V

Voltage Transient

VBEMF

Stall detection and Bemf measurement are performed

only when Speed register value <Sp[7:0]> is less than or

equal to Speed threshold register value <SpThr[7:0]>.

Range and resolution of Speed register and Speed

threshold register are 0 to 5100 ms and 20 ms/digit for half

stepping mode. Accuracy of speed (time) measurement is

given by the accuracy of the internal oscillator.

If measured back emf voltage has not expected polarity,

the back emf sign flag <Bemfs> is set. Motor pin, where

lower voltage is expected, is tied to GND by pull down

current. Sign is determined by comparator, which compares

the polarity of voltage measured over the coil with expected

polarity of voltage.

t

MYP MYP MYP MYP MYP MYP

V MYP/MYN

t

BEMF

sampling

Figure 14. Back emf Sampling

For slow speed or when a motion ends at a full step

position (there is an absence of next NXT trigger), the end

of the zero crossing is taking too long or is non−existing. In

this case, the back emf voltage is taken the latest at “stall

time−out” time and this value is used also for comparison

with <StThr[3:0]> stall threshold to detect stall situation in

run mode or movement in hold mode. The “stall time−out”

is set in SPI by means of <StTo[7:0]> register and is

H-bridge

HiZ state

VXP

VXN

VBEMF

NXT

expressed in counts of 4/f

(See AC Table), roughly

pwm

NXT

in steps of 0.2 ms. If <StTo[7:0]> = 0, time−out is not

active.

XP

XN

At the end of the current zero crossing phase the internal

circuitry compares measured back emf voltages with

<StThr[3:0]> register, which determines threshold for stall

detection. The last sample of back emf taken before end

of zero crossing phase is used for stall detection in normal

mode as well as in enhanced back emf mode. When

<StThr[3:0]> = 0 then stall detection is disabled. When

value of <StThr[3:0]> is different from 0 and measured back

emf signal is lower than <StThr[3:0]> threshold for 2

succeeding coil current zero−crossings (including both X

and Y coil), then the <STALL> bit in SPI status register 1 is

set, the current translator table goes 135 degrees in opposite

direction and the ERRB pin is pulled down, Irun is

maintained. The stall bit is cleared by reading the status

register 1, also the ERRB pin becomes inactive again. With

2 mA

BEMF polarity

XOR

Bemfs

Expected polarity

Figure 15. Back emf Sign Value

The last measured back emf value <Bemf[4:0]>, sign flag

<Bemfs> and coil where the last back emf sample was taken

<Bemfcoil> can be read out via SPI.

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19

NCV70514

Open & Short circuit Automatic Diagnostic

The auto−diagnostic is executed after each power up, or

when enabling the H−bridge (<MOTEN>=0

Table 13. STALL THRESHOLDS SETTINGS (4BIT)

StThr index

StThr Level (V)

BemfGain = 1

Disable

0.48

StThr Level (V)

BemfGain = 0

Disable

0.24

→

<MOTEN>=1) in case the <DIAGEN> bit would be

programmed to one (see SPI table, control register 0x03, bit 6).

During the auto−diagnostic sequence, the device makes

use of internal pull−ups and pull−downs (see Figure 16) to

test the connections at the XP, XN, YP, YN pins with weak

currents. This mechanism guarantees a very wide coverage;

however, some conditions are reported as multiple failure

source detections. This is due to the impossibility to discern

between the two cases from electrical point of view. Details

of failures combination coverage by the automatic

diagnostic for the X coil are shown in Figure 14. The same

is applicable for Y coil.

Any short circuit detection disables the output H−bridges

(<MOTEN> = 0) and does not allow the device

to automatically proceed to “normal mode”. To permit

entering normal mode, the registers involved must be

cleared out by SPI reading and the error condition removed

prior enabling again the outputs (<MOTEN> set to “1”).

The dead time for automatic diagnostic routine is

2 ms (*). The automatic diagnostic is interrupted when the

supply voltage drops below UV3 level.

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0.96

0.48

1.44

0.72

1.92

0.96

2.4

1.2

2.88

1.44

3.36

1.68

3.84

1.92

4.32

2.16

4.8

2.4

5.28

2.64

5.76

2.88

6.24

3.12

6.72

3.36

7.2

3.6

Note: (*): For a controlled start of the automatic diagnostics,

the user has to place the motor driver in high impedance state

by setting the <MOTEN> bit to ‘0’. After setting the

<MOTEN> bit to ‘1’, there is a need for an additional delay

time. This is needed for recirculation of the motor current.

An average time of approximately 2 ms is needed. This time

has to be taken into account by the user.

Warning, Error Detection and Diagnostics

Feedback

Open & Short Circuit Diagnostic

The NCV70514 stepper driver features an enhanced

diagnostic detection and feedback, to be read by the external

microcontroller unit (MCU). Among the main items of

interest for the application and typical failures, are open coil

and the short circuit condition, which may be to ground

(chassis), or to supply (battery line).

X or Y H-bridge

To serve this purpose two diagnostic modes are available

in the device. The first is called “Automatic Diagnostic” and

is executed after each power−up sequence. In addition, by a

specific bit setting, it can be enabled after any output

(H−bridge) activation. The other mode is defined as “User

Diagnostic” or “Normal Mode Diagnostic” and consists in

applying activation sequences directly from the MCU and

read back the consequent status via the proper device

registers.

NT

PT

P

N

PB

NB

ref.

Figure 16. Automatic Diagnostic

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20

NCV70514

Table 14. DIAGNOSTICS OPEN/SHORT DETECTION

SR1[5:4] =

{SHORT,

OPEN}

SR7A[6] =

SR7A[3] =

SR7A[2] =

SR7A[1] =

SR7A[0] =

{OPENX,L} {SHRTXPB} {SHRTXNB} {SHRTXPT} {SHRTXNT}

Fault condition

No short, No open coil – unique detection

0, 0

0

1

0

1

Short XP and/or XN top side, no open coil;

Short XP and XN top side and open coil

1, 0

Short XP and/or XN bottom side, no open coil;

Short XP and XN bottom side and open coil

1, 1

1

0

No short or short XN bottom side, open coil

Short XP top side, open coil

1, 1

1

0

1

0

1

0

1

Short XN top side and short XP bottom side,

open coil

Short XN top side, open coil

1, 1

1

0

1

Open & Short circuit User Diagnostic

H−bridges are disabled (<MOTEN>=0) in case of Open coil

detection. When <OpenDis> bit is set, drivers remain active

for both coils independently of <OpenHiZ> bit.

The short circuit detection monitors the load current in

each activated output stage. The current is measured in terms

When in normal mode, the device will continuously check

upon errors with respect to the expected behavior.

The open load condition is determined by the fact that the

PWM duty cycle keeps 100% value for a time longer than set

by <OpenDet[1:0]> register. This is valid of course only for

the X/Y coil where the current is supposed to circulate,

meaning that in full step positions (MSP[6:0] = {0; 32; 64;

96} (dec)) the open load can be detected only for one of the

coil at a time (respectively {X; Y; X; Y}). The same

reasoning applies for the short circuits detection.

of voltage drop over the MOSFETS’ R . If the load

DS(ON)

current exceeds the over−current detection threshold, then

the over−current flag <SHORT> is set and the drivers are

switched off to protect the integrated circuit. Each driver

stage has an individual detection bit for the N side and the

P side.

Due to the timeout value set by <OpenDet[1:0]>, the open

coil detection is dependent on the motor speed. In more

detail, there is a maximum speed at which it can be done.

Table 15 specifies these maxima for the different step

modes. For practical reasons, all values are given in full

steps per second.

When short circuit is detected, <MOTEN> is set to 0. The

positioner, the NXT, RHB, STEP0, STEP1 and DIR stay

operational. The flag <SHORT> (result of OR−ing the

latched flags: <SHRTXPT> OR <SHRTXPB> OR

<SHRTXNT> OR <SHRTYXNB> OR <SHRTYPT> OR

<SHRTYPB> OR <SHRTYNT> OR <SHRTYNB>) is reset

when the microcontroller reads out the short circuit status

flags in status registers 7A and 8A.

To enable the motor again after reading out of the status

flags, <MOTEN>=1 has to be written. Depending on the

<DIAGEN> bit, Automatic diagnostic can be performed

after enabling the outputs (H−bridges) prior to going

to normal mode operation.

Table 15.

MAXIMUM VELOCITIES FOR OPEN COIL DETECTION

Step Mode

Speed [FS/s] for given <OpenDet[1:0]>

00

200

01

40

10

20

11

5

Full Step1

Full Step2

1/2

400

80

40

10

Notes:

300

60

30

7.5

8.8

9.4

9.7

9.8

1. Successive reading of the <SHRTij> flags and

re−enabling the motor in case of a short circuit

condition may lead to damage of the drivers.

2. Example: SHRTXPT means: Short at X coil,

Positive output pin, Top transistor.

3. In case of the short from any stepper motor pin

to the top side during switching event from bottom

to top on motor pin, the flag “short to bottom side”

is set instead of the expected “short to top side”

flag.

1/4

350

70

35

1/8

375

75

37.5

38.8

39.4

1/16

387.5

393.8

77.5

78.8

1/32

When Open coil condition is detected, the appropriate bit

(<OPENX> or <OPENY>) together with <OPEN> bit in

the SPI status register are set. Reaction of the H−bridge to

Open coil condition depends on the settings of <OpenHiZ>

and <OpenDis> bits.

When both <OpenHiZ> and <OpenDis> bits are 0,

<MOTEN> bit stays in 1 and only H−bridge where open coil

is detected is disabled. When <OpenHiZ> bit is set, both

Thermal Warning and Shutdown

When junction temperature is above T , the thermal

tw

warning bit <TW> is set (SPI register) and the ERRB pin is

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21

NCV70514

pulled down (*). If junction temperature increases

above thermal shutdown level, then also the <TSD> flag is

set, the ERRB pin is pulled down, the motor is disabled

after a power−on or hard reset and can also be activated by

means of SPI bit <SLP>. In sleep−mode, all analog circuits

are suspended in low−power and all digital clocks are

stopped: SPI communication is impossible. The motor

driver is disabled (even if <MOTEN>=1), the content of all

logic registers is maintained (including <MOTEN>, <TSD>

and <TW>), all logic output pins are disabled (ERRB has no

function) and none of the input pins are functional with the

exception of pin CSB. Only this pin can wake−up the chip

to normal mode (i.e. clear bit <SLP>) by means of a

(<MOTEN> = 0) and the hardware reset is disabled. If T <

j

T

level and <TSD> bit has been read−out, the status

tw

of <TSD> is cleared and the ERRB pin is released.

Only if the <TSD>=<TW>=0, the motor can be enabled

again by writing <MOTEN>=1 in the control register 1.

During the over temperature condition the hardware reset

will not work until T < T and the <TSD> readout is done.

j

tw

In this way it is guaranteed that after a <TSD>=1 event,

“high−to−low voltage” transition. After wake−up, time t

wu

the die−temperature decreases back to the level of <TW>.

(see AC Table) is needed to restore analog and digital clocks

and to bring SPI communication within specification.

Note: (*): During the <TW> situation the motor is not

disabled while the ERRB is pulled down. To be informed

about other error situations it is recommended to poll the

status registers on a regular base (time base driven

by application software in the millisecond domain).

Notes:

• The hard−reset function is disabled in sleep mode.

• The thermal shutdown function will be “frozen” during

sleep mode and re−activated at wake−up. This is

important in case bit <TSD>=1 was cleared already by

the micro and <TW> was not “0” yet.

SPI Framing Error

The SPI transmission is continuously monitored

for correct amounts of incoming data bits. If within one

frame of data the number of SPI CLK high transitions is not

equal to a multiple of 16 (16,32,48,...), then the SPI error bit

in the status register is set and the ERRB pin goes low to

indicate this error to the micro controller. During this fault

condition the incoming data are not loaded into the internal

registers and the transmit shift register is not loaded with the

requested data.

The status of the SPI framing error is reset by an errorless

received frame requesting for the motor controller status

register 0. This request will reset the SPI error bit and

releases the ERRB pin (high).

• The CSB low pulse width has to be within t

,

csb_with

(see AC Table) to guarantee a correct wake−up.

Power−on Reset, Hard−Reset Function

After a power−on or a hard−reset, a flag <HR> in the SPI

status register is set and the ERRB is pulled low. The ERRB

stays low during this reset state. The typical power−on reset

time is given by t

(Table 7 −ACPARAMETERS). After

hr_err

the reset state the device enters sleep mode and the ERRB

pin goes high to indicate the motor controller is ready for

operation.

By means of a specific pattern on the DIR pin during the

“Hold Mode”, the complete digital part of driver can be reset

without a power−cycle. This hard−reset function is activated

when the input pin DIR changes logic state

Error Output

This is an open drain output to flag a problem to the

external microcontroller. The signal on this output is active

low and the logic combination of:

“0 → 1 → 0 → 1” within t

in five consecutive patterns

hr_trig

during “Hold Mode”. See figure below and Table 7 − AC

PARAMETERS. With the device NCV70514MW007, the

DIR change pattern can be alternatively created via the

<DIRP> bit in SPI control register 1.

The operation of all analog circuits is suspended during

the reset state of the digital. Similar as for a normal

power−on, the flag <HR> is set in the SPI register after a

NOT(ERRB) = (<SPI> OR <SHORT> OR <OPENX> OR

<OPENY> OR <TSD> OR <TW> OR <STALL> OR

(BemfIntEn AND BemfRes) OR (UV1IntEn AND UV1)

OR (UV2IntEn AND UV2) OR (UV2MIntEn AND UV2M)

OR (UV3IntEn AND UV3) OR (UV3MIntEn AND UV3M)

OR (*)reset state) AND not (**)sleep mode

hard−reset and the ERRB pin is pulled low during t

(Table 7 − AC PARAMETERS).

hr_err

Note: (*) reset state: After a power−on or a hard−reset, the

ERRB is pulled low during t

PARAMETERS).

(Table 7 − AC

hr_err

To enable the motor controller to perform a proper self

diagnosis, it is recommended that the motor is in “Hold

Mode” before the hard reset is generated. The minimum

Note: (**) sleep mode: In sleep mode the ERRB is always

inactive (high).

time (t ) between the beginning of “Hold Mode” and the

hr_set

first rising edge of the DIR pin is given in Table 7 − AC

PARAMETERS.

Sleep Mode

The motor driver can be put in a low−power consumption

mode (sleep mode). The sleep mode is entered automatically

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22

NCV70514

t_{hr_trig}

DIR

RHB

t_{hr_set}

t_{hr_dir}

HOLD MODE

t_{hr_err}

ERRB

Figure 17. Hard Reset Timing Diagram

SPI INTERFACE

DO and DI. The DO signal is the output from the Slave

(NCV70514), and the DI signal is the output from the

Master. A slave or chip select line (CSB) allows individual

selection of a slave SPI device in a time multiplexed

multiple−slave system.

The CSB line is active low. If an NCV70514 is not

selected, DO is in high impedance state and it does not

interfere with SPI bus activities. Since the NCV70514

always clocks data out on the falling edge and samples data

in on rising edge of clock, the MCU SPI port must be

configured to match this operation.

The serial peripheral interface (SPI) is used to allow

an external microcontroller (MCU) to communicate

with the device. NCV70514 acts always as a slave and it

cannot initiate any transmission. The operation of the device

is configured and controlled by means of SPI registers,

which are observable for read and/or write from the master.

The NCV70514 SPI transfer size is 16 bits.

During an SPI transfer, the data is simultaneously

transmitted (shifted out serially) and received (shifted in

serially). A serial clock line (CLK) synchronizes shifting

and sampling of the information on the two serial data lines:

BYTE 1

BYTE 2

DI Addr [3:0]

DI Addr [7:4]

DI Data [7:0]

CS

CLK

DI

MSB

6

5

4

3

2

1

LSB

MSB

6

5

4

3

2

1

LSB

DO

Figure 18. SPI Frame Structure

The implemented SPI allows connection to multiple slaves

by means of both time−multiplexing (CSB per slave) and

daisy−chain (CSB per group of slaves). Multi−axis

connections schemes are discussed in a separate chapter

below.

copied in the control register. The contents of the

addressed control register will be sent back by the

NCV70514 in the next SPI access.

• Reading from a control register is accomplished

by putting its address in the second half of the address

byte. The data byte has no function for this command.

• Reading from a status register is accomplished

by putting its address either in the first or in the second

half of the address byte. The data byte has no function

for this command.

SPI Transfer Format and Pin Signals

All SPI commands (to DI pin of NCV70514) from the

micro controller consist of one “address byte” and one “data

byte”. The address byte contains up to two addresses of each

4 bit long. These addresses are pointing to a command or

requested action in a SPI slave. Three command−types can

be distinguished: “Write to a control register”, “Read from

a control register” and “Read from a status register”.

• Writing to a control register is accomplished only if the

address of the target register appears in the first half of

the address byte. The contents of the data−byte will be

The response (from DO pin of NCV70514) on these

commands is always

2 bytes long. The possible

combinations of DI/DO and their use are summarized in the

following Table 16. Figure 19 gives examples of the data

streaming:

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NCV70514

Table 16. SPI COMMAND ADDRESS, DATA AND RESPONSE STRUCTURE

DI ADDR[7:4] DI ADDR[3:0] DI DATA[7:0]

DO BYTE1

DOCR1

DOSR1

00h

DO BYTE2

DOCR2

DOSR1

00h

Comment on Use

Control and Status of CR

Control and Status of SR

Control and no Status

Status of SR and CR

Status of SR and SR

Status of SR

ACR1

ASR1

Nop

ACR2

ASR1

Nop

DICR1

XXh

ACR1

ASR2

Nop

DOCR1

DOSR2

00h

XXh

ACR1

ASR1

Nop

XXh

DOCR1

DOSR1

00h

Status of CR

Nop

XXh

00h

Status of SR

Nop

XXh

00h

Dummy/Placeholder

With:

ACRx = Address of control register x

ASRx = Address of status register x

DICRx = Data input of Control Register x

DOxy = Data output of corresponding register contents transmitted in the next SPI access

Nop = Register address outside range : 0h

XXh = any byte

The contents of the previously addressed registers

are copied into the transmission shift registers at the

falling edge of CSB

The written control registers are updated

by the NCV70514 at the rising edge of CSB

CS

COMMAND

DATA

NEXT COMMAND

NEXT DATA

ACR1 −−− ACR2

DATA FOR ACR1

MASTER −> SLAVE

SLAVE −> MASTER

DATA FROM ACR1

DATA FROM ACR2

PREVIOUS DATA

This is the data from command

before or not valid after power up

EXAMPLE 1: WRITE CR1, READ CR1 and CR2

or reset

CS

COMMAND

DATA

NEXT COMMAND

NEXT DATA

DATA FOR ACR3

ACR3 −−− ASR5

MASTER −> SLAVE

SLAVE −> MASTER

DATA FROM ACR3

DATA FROM ASR5

PREVIOUS DATA

This is the data from command

before or not valid after power up

or reset

EXAMPLE 2: WRITE CR3, READ CR3 and SR5

CS

NEXT COMMAND

NEXT DATA

COMMAND

DATA

ASR5 −−− ASR7

DUMMY

MASTER −> SLAVE

SLAVE −> MASTER

DATA FROM ASR7

DATA FROM ASR5

PREVIOUS DATA

This is the data from command

before or not valid after power up

or reset

EXAMPLE 3: READ SR5 and SR7

Figure 19. Command and Data Streaming of SPI

SPI Control Registers (CR)

All SPI control registers have Read/Write access.

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NCV70514

Table 17. SPI CONTROL REGISTERS (CR)

4−bit

Default

Address

after Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h or 11h

(CR1)

DIRP

RHBP

NXTP

MOTEN

StThr3

StThr2

StThr1

StThr0

0000 0000

0010 0000

02h or 12h

(CR2)

Ihold3

Ihold2

Ihold1

EMC1

Ihold0

Irun3

SLP

Irun2

SM2

Irun1

SM1

Irun0

SM0

03h or 13h EnhBemf En DIAGEN

(CR3)

EMC0

04h (CR4)

StTo7

StTo6

StTo5

StTo4

StTo3

StTo2

StTo1

StTo0

0001 0000

0000 0000

05h or 15h

(CR5)

SpThr7

SpThr6

SpThr5

SpThr4

SpThr3

SpThr2

SpThr1

SpThr0

06h or 16h

(CR6)

UV1Thr3

AD4

UV1Thr2

BemfGain

NotUsed

UV1Thr1

UV1Thr0

UV1IntEn

Iboost

UV2Thr3

UV2Thr2

UV2Thr1

UV2Thr0

0000 0000

0000 0100

07h or 17h

(CR7)

Bemf

ResIntEn

UV2IntEn UV2MIntEn UV3IntEn UV3MIntEn

OpenDet1 OpenDet0 OpenDis OpenHiZ

14h (CR4A)

NotUsed

NCV70514 responds on every incoming byte by shifting out the data stored on the last address sent via the bus. After POR

the initial address is unknown, so the first data shifted out are undefined.

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NCV70514

Table 18. BIT DEFINITION

Symbol

MAP position

Description

DIRP

Bit 7 – ADDR_0x01 or 0x11 (CR1)

Polarity of DIR pin, which controls direction status; DIRP = 1 inverts the

logic polarity of the DIR pin)

RHBP

Bit 6 – ADDR_0x01 or 0x11 (CR1)

Polarity of RHB pin, which controls RUN/HOLD status; RHBP = 1 inverts

logic polarity of the RHB pin (Hold = NOT(RHB XOR <RHBP>))

NXTP

MOTEN

StThr[3:0]

Ihold[3:0]

Irun[3:0]

EnhBemfEn

DIAGEN

EMC[1:0]

SLP

Bit 5 – ADDR_0x01 or 0x11 (CR1)

Bit 4 – ADDR_0x01 or 0x11 (CR1)

Bits [3:0] – ADDR_0x01 or 0x11 (CR1)

Bits [7:4] – ADDR_0x02 or 0x12 (CR2)

Bits [3:0] – ADDR_0x02 or 0x12 (CR2)

Bit 7 – ADDR_0x03 or 0x13 (CR3)

Bit 6 – ADDR_0x03 or 0x13 (CR3)

Bits [5:4] – ADDR_0x03 or 0x13 (CR3)

Bit 3 – ADDR_0x03 or 0x13 (CR3)

Bits [2:0] – ADDR_0x03 or 0x13 (CR3)

Bits [7:0] – ADDR_0x04 (CR4)

Push button pin, generating next step in position table

Enables the H−bridges (motor activated in RUN or HOLD mode)

Threshold level for stall detection, when “0”, stall detection is disabled

Current amplitude in HOLD mode

Current amplitude in RUN mode

Enhanced BEMF measurement functionality is activated when bit is set

Enables automatic diagnostic at rising edge of <MOTEN> bit

Voltage slope defining bits for motor driver switching

Places device in sleep mode with low current consumption (when 1)

Step mode selection

SM[2:0]

StTo[7:0]

Max difference between two successive full step next pulse periods (time-

out), after this time the BEMF sample is taken to verify stall

SpThr[7:0]

Bits [7:0] – ADDR_0x05 or 0x15 (CR5)

Speed threshold register, BEMF measurement and stall detection is acti-

vated when Speed register value is less than or equal to <SpThr> value

UV1Thr[3:0]

UV2Thr[3:0]

AD4

Bits [7:4] – ADDR_0x06 or 0x16 (CR6)

Bits [3:0] – ADDR_0x06 or 0x16 (CR6)

Bit 7 – ADDR_0x07 or 0x17 (CR7)

Setting of under voltage level UV1. See chapter UV detection

Setting of under voltage level UV2. See chapter UV detection

Address selection bit, alternating register ”Banks”. When AD = 1, all

addresses will be interpreted with a ”1” in the first nibble (allowing to

access registers CR4A, SR7A, SR8A). When AD = 0, all addresses will be

interpreted with a ”0” in the first nibble (allowing to access registers CR4,

SR7, SR8).

BemfGain

BemfResIntEn

UV1IntEn

Bit 6 – ADDR_0x07 or 0x17 (CR7)

Bit 5 – ADDR_0x07 or 0x17 (CR7)

Bit 4 – ADDR_0x07 or 0x17 (CR7)

Bit 3 – ADDR_0x07 or 0x17 (CR7)

Bit 2 – ADDR_0x07 or 0x17 (CR7)

Bit 1 – ADDR_0x07 or 0x17 (CR7)

Bit 0 – ADDR_0x07 or 0x17 (CR7)

Bit 4 – ADDR_0x14 (CR4A)

Gain of BEMF measurement channel − “0”: gain 0.5, “1”: gain 0.25

BEMF result interrupt enable

Under voltage 1 detection interrupt enable

UV2IntEn

Under voltage 2 detection interrupt enable

UV2MIntEn

UV3IntEn

Under voltage 2 detection and Motion interrupt enable

Under voltage 3 detection interrupt enable

UV3MIntEn

Iboost

Under voltage 3 detection and Motion interrupt enable

Motor current boost function activation and status

OpenDet[1:0]

Bits [3:2] – ADDR_0x14 (CR4A)

Open Coil detection time setting bits (see Table 7 − AC PARAMETERS)

OpenDis

OpenHiZ

Bit 1 – ADDR_0x14 (CR4A)

Bit 0 – ADDR_0x04 (CR4A)

When bit is set, Open Coil detection status is flagged, but drivers control

remain active for both coils, <OpenDis> bit setting has higher priority than

<OpenHiZ> bit

When bit is set, during Open Coil detection both drivers are deactivated

(MOTEN=0)

www.onsemi.com

26

NCV70514

SPI Status Registers (SR)

All SPI status registers have Read Only Access, with the odd parity on Bit7. Parity bit makes the numbers of 1 in the byte odd.

Table 19. SPI STATUS REGISTERS (SR)

Default

after

4−bit

Address

Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Comment

08h or 18h

(SR1)

PAR

SPI,L

SHORT,R*

OPEN,R*

TSD,L

TW,R

STALL,L

HR,L

Errors

0xx 0001

101 1010

001 0000

x00 0000

1111 1111

000 0000

09h or 19h

(SR2)

PAR

ORErr, R

MSP6,R

BemfRes

MSP5,R

Bemfs, R

Sp5,R

UV1,L

MSP4,R

Bemf4, R

Sp4,R

UV2,L

MSP3,R

Bemf3, R

Sp3 ,R

Sl3,L

UV2M,L

MSP2,R

Bemf2, R

Sp2,R

UV3,L

MSP1,R

Bemf1, R

Sp1,R

UV3M,L

MSP0,R

Bemf0, R

Sp0,R

INTst

0Ah or 1Ah

(SR3)

Micro−step

position

0Bh or 1Bh

(SR4)

PAR BemfCoil, R

Bemf

Speed

0Ch or 1Ch Sp7,R

(SR5)

Sp6,R

Sl6,L

0Dh or 1Dh

(SR6)

PAR

Sl5,L

Sl4,L

Sl2,L

Sl1,L

Sl0,L

StepLoss

0Eh (SR7)

0Fh (SR8)

1Eh (SR7A)

PAR

T/BX,R

T/BY,R

SignX,R

SignY,R

PWMX4,R

PWMY4,R

PWMX3,R

PWMY3,R

PWMX2,R

PWMY2,R

SHRTXNB,L

PWMX1,R

PWMY1,R

SHRTXPT,L

PWMX0,R

PWMY0,R

SHRTXNT,L

PWMX

PWMY

000 0000

xxx 0000

OPENX,L STEP0pin,R STEP1pin,R SHRTXPB,L

Input pins

& ShortsX

1Fh (SR8A)

PAR

OPENY,L RHBpin,R DIRpin, R SHRTYPB,L

SHRTYNB,L

SHRTYPT,L

SHRTYNT,L

Input pins

& ShortsY

xxx 0000

Flags have “,L” for latched information or “,R” for real time information. All latched flags are “cleared upon read”.

X = value after reset is defined during reset phase (diagnostics)

R* = real time read out of values of other latches. Reading out this R* value does not reset the bit, and does not reset the values of the

latches this bit reads out.

Table 20. BIT DEFINITION

Symbol

PAR

MAP Position

Description

Bit 7 – ADDR_0x08 or 0x18 (SR1)

Bit 6 – ADDR_0x08 or 0x18 (SR1)

Parity bit for SR1

SPI

SPI error: no multiple of 16 rising clock edges between falling and rising

edge of CSB line

SHORT

OPEN

Bit 5 – ADDR_0x08 or 0x18 (SR1)

Bit 4 – ADDR_0x08 or 0x18 (SR1)

An over current detected (common: set if at least one of the SHORTij indi-

vidual bits is set)

Open Coil X or Y detected (common: set if at least one of the two specific

X/Y open coil bits is set)

TSD

TW

Bit 3 – ADDR_0x08 or 0x18 (SR1)

Bit 2 – ADDR_0x08 or 0x18 (SR1)

Bit 1 – ADDR_0x08 or 0x18 (SR1)

Bit 0 – ADDR_0x08 or 0x18 (SR1)

Bit 7 – ADDR_0x09 or 0x19 (SR2)

Bit 6 – ADDR_0x09 or 0x19 (SR2)

Bit 5 – ADDR_0x09 or 0x19 (SR2)

Bit 4 – ADDR_0x09 or 0x19 (SR2)

Bit 3 – ADDR_0x09 or 0x19 (SR2)

Bit 2 – ADDR_0x09 or 0x19 (SR2)

Bit 1 – ADDR_0x09 or 0x19 (SR2)

Bit 0 – ADDR_0x09 or 0x19 (SR2)

Bit 7 – ADDR_0x0A or 0x1A (SR3)

Thermal shutdown

Thermal warning

STALL

HR

Stall detected by the internal algorithm

Hard reset flag: 1 indicates a hard reset has occurred

Parity bit for SR2

PAR

ORErr

BemfRes

UV1

Logic OR of all bits of SR1 (Error bits)

BEMF result ready at <Bemf> register

Under voltage 1 detection

UV2

Under voltage 2 detection

UV2M

UV3

Under voltage 2 detection and NXT pulse arrive during UV2 state (Motion)

Under voltage 3 detection

UV3M

PAR

Under voltage 3 detection and NXT pulse arrive during UV3 state (Motion)

Parity bit for SR3

www.onsemi.com

27

NCV70514

Table 20. BIT DEFINITION

Symbol

MAP Position

Description

MSP[6:0]

PAR

Bits [6:0] – ADDR_0x0A or 0x1A (SR3)

Bit 7 – ADDR_0x0B or 0x1B (SR4)

Bit 6 – ADDR_0x0B or 0x1B (SR4)

Bit 5 – ADDR_0x0B or 0x1B (SR4)

Bits [4:0] – ADDR_0x0B or 0x1B (SR4)

Bits [7:0] – ADDR_0x0C or 0x1C (SR5)

Bit 7 – ADDR_0x0D or 0x1D (SR6)

Bits [6:0] – ADDR_0x0D or 0x1D (SR6)

Translator micro−step position

Parity bit for SR4

BemfCoil

Bemfs

Last BEMF measurement was done on coil: 0 = X, 1 = Y

BEMF measured voltage has expected polarity (Yes = 0, No = 1)

BEMF value measured during zero crossing

Speed register

Bemf[4:0]

Sp[7:0]

PAR

Parity bit for SR6

Sl[6:0]

Step loss register counts number of NXT pulses arrived after activation of

under−voltage event or other failure state when NXT pulses are ignored

(e.g. TSD, OVC, STALL). Counter keeps maximum value of 127 after more

pulses have been received (no overflow)

PAR

T/BX

Bit 7 – ADDR_0x0E (SR7)

Bit 6 – ADDR_0x0E (SR7)

Bit 5 – ADDR_0x0E (SR7)

Bits [4:0] – ADDR_0x0E (SR7)

Bit 7 – ADDR_0x0F (SR8)

Bit 6 – ADDR_0x0F (SR8)

Bit 5 – ADDR_0x0F (SR8)

Bits [4:0] – ADDR_0x0F (SR8)

Bit 7 – ADDR_0x1E (SR7A)

Bit 6 – ADDR_0x1E (SR7A)

Bit 5 – ADDR_0x1E (SR7A)

Bit 4 – ADDR_0x1E (SR7A)

Bit 3 – ADDR_0x1E (SR7A)

Bit 2 – ADDR_0x1E (SR7A)

Bit 1 – ADDR_0x1E (SR7A)

Bit 0 – ADDR_0x1E (SR7A)

Bit 7 – ADDR_0x1F (SR8A)

Bit 6 – ADDR_0x1F (SR8A)

Bit 5 – ADDR_0x1F (SR8A)

Bit 4 – ADDR_0x1F (SR8A)

Bit 3 – ADDR_0x1F (SR8A)

Bit 2 – ADDR_0x1F (SR8A)

Bit 1 – ADDR_0x1F (SR8A)

Bit 0 – ADDR_0x1F (SR8A)

Parity bit for SR7

PWM Regulation mode on X coil (Top = 1 or Bottom = 0 regulation)

PWM sign for X coil regulation (“0” = positive, “1” = negative)

Actual PWM duty cycle value for coil X

Parity bit for SR8

SignX

PWMX[4:0]

PAR

T/BY

PWM Regulation mode on Y coil (Top = 1 or Bottom = 0 regulation)

PWM sign for Y coil regulation (“0” = positive, “1” = negative)

Actual PWM duty cycle value for coil Y

Parity bit for SR7A

SignY

PWMY[4:0]

PAR

OPENX

STEP0pin

STEP1pin

SHRTXPB

SHRTXNB

SHRTXPT

SHRTXNT

PAR

Open Coil X detected

Read out of STEP0 pin logic status

Read out of STEP1 pin logic status

Short circuit detected at XP pin towards ground (Bottom)

Short circuit detected at XN pin towards ground (Bottom)

Short circuit detected at XP pin towards supply (Top)

Short circuit detected at XN pin towards supply (Top)

Parity bit for SR8A

OPENY

RHBpin

DIRpin

Open Coil Y detected

Read out of RHB pin logic status

Read out of DIR pin logic status

SHRTYPB

SHRTYNB

SHRTYPT

SHRTYNT

Short circuit detected at YP pin towards ground (Bottom)

Short circuit detected at YN pin towards ground (Bottom)

Short circuit detected at YP pin towards supply (Top)

Short circuit detected at YN pin towards supply (Top)

www.onsemi.com

28

NCV70514

APPLICATION EXAMPLES FOR MULTI−AXIS CONTROL

The wiring diagrams below show possible connections of

Further I/O reduction is accomplished in case the ERRB

is not connected. This would mean that the microcontroller

operates while polling the error flags of the slaves.

Ultimately, one can operate multiple slaves by means of only

4 SPI connections: even the NXT pin can be avoided if the

microcontroller operates the motors by means of the

“NXTP” bit.

multiple slaves to one microcontroller. In these examples,

all movements of the motors are synchronized by means of

a common NXT wire. The direction and Run/Hold

activation is controlled by means of an SPI bus.

Microcontroller

IC1 NCV70514

3

NXT

CSB/CLK/NXT

NXT

CSB1

DI/DO/CLK

CSB/CLK/NXT

DO

CSB

DI

3

DI/DO/CLK

DO

ERRB

3

IC2 NCV70514

3

NXT

CSB/CLK/NXT

CSB

DI

CSB2

“Daisy−Chained SPI”

DO

DI/DO/CLK

ERRB

“Multiplexed SPI”

IC3 NCV70514

3

IC3 NCV70514

NXT

CSB/CLK/NXT

CSB

DI

CSB3

DI/DO/CLK

ERRB

DO

DI

ERRB

Rpu

vcc

Figure 20. Examples of Wiring Diagrams for Multi−axis Control*

Microcontroller

IC1 NCV70514

2

CSB/CLK

DI

CSB/CLK

DO

IC2 NCV70514

2

CSB/CLK

DI

Full SPI, Minimal Wiring

DO

IC3 NCV70514

CSB/CLK

DI

DO

DI

Figure 21. Minimal Wiring Diagram for Multi−axis Control*

*This drawing does not present the Hard Reset interconnection. For the functionality of the Hard Reset function the RHB and DIR pins have

to be connected to the micro controller.

www.onsemi.com

29

NCV70514

ELECTRO MAGNETIC COMPATIBILITY

The NCV70514 has been developed using

Special care has to be taken into account with long wiring

to motors and inductors. A modern methodology to regulate

the current in inductors and motor windings is based on

controlling the motor voltage by PWM. This low frequency

switching of the battery voltage is present at the wiring

towards the motor or windings. To reduce possible radiated

transmission, it is advised to use twisted pair cable and/or

shielded cable.

state−of−the−art design techniques for EMC. The overall

system performance depends on multiple aspects of the

system (IC design & lay−out, PCB design and layout ...) of

which some are not solely under control of the IC

manufacturer. Therefore, meeting system EMC

requirements can only happen in collaboration with all

involved parties.

PCB LAYOUT RECOMMENDATIONS

Recommended PCB layout for the NCV70514 is shown

on the following figure. The VDD capacitor C4 must be

placed close to the device and with GND straight to the

device and not the common GND. This is crucial for

optimum EMC performance.

Figure 22. Recommended PCB Layout

ORDERING INFORMATION

Device

Boost

Peak

Current

Peak

Current

†

Marking

End Market/Version

Package*

Shipping

NCV70514MW003BR2G

NCV70514MW007R2G

NCV70514MW007AR2G**

N70514−3

N70514−7

800 mA

N.A.

QFNW32 5x5 with

step−cut wettable

flank (Pb−Free)

5000 / Tape & Reel

1100 mA

QFN32 5x5 with

wettable flanks

(Pb−Free)

5000 / Tape & Reel

Automotive

High Temperature

Version

QFNW32 5x5 with

step−cut wettable

flank (Pb−Free)

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

*Devices NCV70514MW003 and NCV70514MW007 have different package mold compound. Please contact ON Semiconductor for technical

details.

**NCV70514MW007A is recommended for new designs.

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

30

NCV70514

PACKAGE DIMENSIONS

QFNW32 5x5, 0.5P

CASE 484AB

ISSUE D

L3

L4

L3

L4

A

B

D

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.10 AND 0.20MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

L

REFERENCE

ALTERNATE

CONSTRUCTION

DETAIL A

E

A

MILLIMETERS

EXPOSED

COPPER

DIM MIN

NOM

0.90

−−−

0.20 REF

−−−

0.25

5.00

3.10

5.00

3.10

0.50 BSC

−−−

0.40

−−−

0.08 REF

MAX

1.00

0.05

A

A1

A3

A4

b

D

D2

E

E2

e

0.80

−−−

A4

A1

0.10

0.20

4.90

3.00

4.90

3.00

−−−

0.30

5.10

3.20

5.10

3.20

TOP VIEW

PLATING

A1

A4

ALTERNATE

CONSTRUCTION

DETAIL B

(A3)

0.10

0.08

C

L3

K

L

L3

L4

0.35

0.30

−−−

0.50

0.10

A3

A4

SEATING

PLANE

C

NOTE 4

SIDE VIEW

DETAIL A

PLATED

SURFACES

D2

9

SECTION C−C

17

8

32X

L

RECOMMENDED

SOLDERING FOOTPRINT*

E2

5.30

1

32X

0.63

3.35

32

25

K

32X

b

0.10

e

1

M

C A B

e/2

BOTTOM VIEW

M

NOTE 3

0.05

C

3.35

5.30

PACKAGE

OUTLINE

0.50

32X

0.30

PITCH

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

31

NCV70514

PACKAGE DIMENSIONS

QFN32 5x5, 0.5P

CASE 488AM

ISSUE A

A

B

D

NOTES:

L

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

LOCATION

L1

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

E

A

MILLIMETERS

DIM

A

A1

A3

b

D

D2

E

E2

e

K

L

MIN

0.80

−−−

MAX

1.00

0.05

0.15

C

0.20 REF

0.15

C

EXPOSED Cu

MOLD CMPD

0.18

2.95

0.30

5.00 BSC

TOP VIEW

3.25

5.00 BSC

DETAIL B

2.95

3.25

(A3)

A1

0.10

C

0.50 BSC

DETAIL B

0.20

0.30

−−−

0.50

0.15

ALTERNATE

CONSTRUCTION

0.08

L1

SEATING

PLANE

C

NOTE 4

SIDE VIEW

RECOMMENDED

SOLDERING FOOTPRINT*

DETAIL A

32X L

K

D2

9

5.30

32X

17

0.63

8

3.35

E2

1

3.35 5.30

32

25

32X

b

0.10

e

e/2

M

C A B

NOTE 3

0.05

C

BOTTOM VIEW

0.50

32X

0.30

PITCH

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

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32


型号：	NCV70514MW003BR2G
厂家：	ONSEMI
描述：	微步电机驱动器电机驱动驱动器
文件：	总33页 (文件大小：456K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV70514MW003BR2G [ONSEMI]

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