NCV7357 [ONSEMI]
CAN FD Transceiver, High Speed;型号: | NCV7357 |
厂家: | ONSEMI |
描述: | CAN FD Transceiver, High Speed |
文件: | 总15页 (文件大小:226K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NCV7357
CAN FD Transceiver, High
Speed
Description
The NCV7357 CAN transceiver is the interface between
a controller area network (CAN) protocol controller and the physical
bus. The transceiver provides differential transmit capability to the bus
and differential receive capability to the CAN controller.
The NCV7357 is an addition to the CAN high−speed transceiver
family complementing NCV7344 CAN stand−alone transceivers and
previous generations such as AMIS42665, AMIS3066x, etc.
The NCV7357 guarantees additional timing parameters to ensure
robust communication at data rates beyond 1 Mbps to cope with CAN
flexible data rate requirements (CAN FD). These features make the
NCV7357 an excellent choice for all types of HS−CAN networks, in
nodes that require only a basic CAN capability.
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SOIC−8
DFNW8
D SUFFIX
CASE 751AZ
MW SUFFIX
CASE 507AB
MARKING DIAGRAM
Features
8
1
• Compatible with ISO 11898−2:2016
NV7357−X
ALYWG
G
NV7357−X
ALYWG
G
• CAN FD Timing Specified up to 5 Mbps
• V Pin on NCV7357−3 Version Allowing Direct Interfacing with
IO
1
3 V to 5 V Microcontrollers
• Low Current, Listen Only Silent Mode
NV7357−X = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
• Low Electromagnetic Emission (EME) and High Electromagnetic
Immunity
Y
W
G
= Year
= Work Week
= Pb−Free Package
• Very Low EME without Common−mode (CM) Choke
• No Disturbance of the Bus Lines with an Unpowered Node
• Transmit Data (TxD) Dominant Timeout Function
• Under All Supply Conditions the Chip Behaves Predictably
• Very High ESD Robustness of Bus Pins, >8 kV System ESD Pulses
• Thermal Protection
PIN ASSIGNMENT
1
8
TxD
S
• Bus Pins Short Circuit Proof to Supply Voltage and Ground
GND
VCC
CANH
EP
• Bus Pins Protected Against Transients in an Automotive
CANL
Environment
RxD
NC (−0)
VIO (−3)
• These are Pb−free Devices
Quality
NCV7357D1x
(Top View)
• Wettable Flank Package for Enhanced Optical Inspection
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
1
8
S
TxD
2
3
4
7
GND
VCC
CANH
Typical Applications
6
5
• Automotive
• Industrial Networks
CANL
RxD
NC (−0)
VIO (−3)
NCV7357MWx
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
March, 2019 − Rev. 0
NCV7357/D
NCV7357
V
CC
NC
5
3
NCV7357−0
V
CC
7
6
CANH
CANL
Thermal
Shutdown
1
Timer
TxD
V
CC
Mode
Driver
8
4
control
control
S
2
RxD
GND
COMP
Figure 1. NCV7357−0 Block Diagram
V
IO
V
CC
5
3
NCV7357−3
V
IO
7
6
CANH
CANL
Thermal
Shutdown
1
TxD
Timer
V
IO
8
Mode
control
Driver
control
S
2
4
GND
RxD
COMP
Figure 2. NCV7357−3 Block Diagram
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2
NCV7357
VBAT
IN
OUT
5V −reg
VCC
NC
5
VCC
3
RLT = 60 W
CANH
7
S
8
1
4
CAN
BUS
Micro−
controller
TxD
RxD
CANL
RLT = 60 W
6
.
2
GND
GND
Figure 3. Application Diagram NCV7357−0
VBAT
IN
IN
OUT
OUT
5V −reg
3V −reg
VIO
VCC
5
3
RLT = 60 W
CANH
S
7
8
1
4
CAN
BUS
Micro−
controller
TxD
RxD
CANL
RLT = 60 W
6
.
2
GND
GND
Figure 4. Application Diagram NCV7357−3
Table 1. PIN FUNCTION DESCRIPTION
Pin
1
Name
TxD
Description
Transmit data input; low input Ù dominant driver; internal pull−up current
2
GND
Ground
3
V
CC
Supply voltage
4
RxD
Receive data output; dominant transmitter Ù low output
Not connected. On NCV7357−0 only
Digital Input / Output pins supply voltage. On NCV7357−3 only
5
5
NC
V
IO
6
7
8
CANL
CANH
S
Low−level CAN bus line (low in dominant mode)
High−level CAN bus line (high in dominant mode)
Silent mode control input; internal pull−up current
Exposed Pad. Recommended to connect to GND or left floating in application
(DFNW8 package only).
EP
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NCV7357
FUNCTIONAL DESCRIPTION
High speed CAN FD transceiver
NCV7357 implements high−speed physical layer CAN
FD transceiver compatible with ISO11898−2, implementing
following optional features or alternatives:
• Extended bus load range
• Transmit dominant timeout, long
• Support of bit rates up to 5 Mbps
• Normal Bus biasing
Operating Modes
NCV7357 provides two modes of operation as illustrated
in Table 2. These modes are selectable through pin S.
Table 2. OPERATING MODES
Pin S
Mode
Pin TxD
BUS
Pin RxD
0
1
Dominant
Recessive
0
1
Low
Normal
Dominant
(1)
X
X
0
1
High
Silent
Recessive
1. CAN BUS driven by another transceiver on the BUS
2. ’X’ = don’t care
Power−off
Overtemperature Detection
This virtual mode is entered as soon as the V or V
undervoltage condition is detected. The internal logic is
reset and the transceiver is disabled. CAN bus pins are kept
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
CC
IO
exceeds T
value. Because the transmitter dissipates most
J(sd)
floating. As soon as both V and V voltages rise above
of the power, the power dissipation and temperature of the
IC is reduced. All other IC functions continue to operate.
The transmitter off−state resets when the temperature
decreases below the shutdown threshold and pin TxD goes
high. The thermal protection circuit is particularly needed
when a bus line short circuits.
CC
IO
corresponding undervoltage recovery thresholds, the device
proceeds to Normal or Silent mode, depending on S pin
state.
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give low EME.
TxD Dominant Timeout Function
A TxD dominant timeout timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
Silent Mode
In the silent mode, the transmitter is disabled. The bus pins
are in recessive state independent of TxD input. Transceiver
listens to the bus and provides data to controller, but
controller is prevented from sending any data to the bus.
internal timer value t
, the transmitter is disabled,
dom(TxD)
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant timeout time t
minimum possible bit rate to 17 kbps.
defines the
dom(TxD)
Power−off
CAN: off (no bias)
RxD: High−Z
Any
UV
mode detected
Fail Safe Features
TxD, S: High−Z
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit
to either positive or negative supply voltage, although
power dissipation increases during this fault condition.
Detection of undervoltage on supply pin (V or V )
No UV
and S = Low
No UV
and S = High
Normal mode
Silent mode
S = High
CC
IO
causes switching off device. After supply voltage is
recovered TxD pin must be first released to high to allow
sending dominant bits again.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
S = Low
S = High
CAN: Tx/Rx
CAN bias: VCC/2
CAN: Rx only
CAN bias: VCC/2
S = Low
Notes:
NCV7357−0
UV detected: VCC < VUVDVCC
NCV7357−3
UV detected: VCC < VUVDVCC and/or VIO < VUVDVIO
No UV: VCC > VUVDVCC and VIO > VUVDVIO
No UV:
VCC > VUVDVCC
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4
NCV7357
Figure 7). Pins TxD and S are biased internally should the
between microcontroller and transceiver are properly
adjusted. See Figure 4.
input become disconnected. Pins TxD, S and RxD will be
floating, preventing reverse supply should the VCC supply
be removed.
Definitions
All voltages are referenced to GND (pin 2). Positive
currents flow into the IC. Sinking current means the current
is flowing into the pin; sourcing current means the current
is flowing out of the pin.
VIO Supply Pin
The V pin (available only on NCV7357−3 version)
IO
should be connected to microcontroller supply pin. By using
V
IO
supply pin shared with microcontroller the I/O levels
ABSOLUTE MAXIMUM RATINGS
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply voltage V , V
Conditions
Min.
−0.3
−42
−42
−42
−0.3
−6
Max.
+6.0
+42
+42
+42
+6.0
+6
Unit
V
V
SUP
CC
IO
V
CANH
DC voltage at pin CANH
0 < V < 5.5 V; no time limit
V
CC
V
DC voltage at pin CANL
0 < V < 5.5 V; no time limit
V
CANL
CANH − CANL
CC
V
DC voltage between CANH and CANL
DC voltage at pin TxD, RxD, S
V
V
I/O
V
V
Electrostatic discharge voltage at all
pins, Component HBM
(Note 3)
(Note 4)
(Note 5)
kV
esdHBM
V
Electrostatic discharge voltage at all
pins, Component CDM
esdCDM
−750
+750
+8
V
V
Electrostatic discharge voltage at pins
CANH and CANL,
System HBM (Note 6)
esdIEC
−8
kV
V
Voltage transients, pins CANH, CANL.
According to ISO7637−3, Class C
(Note 6)
test pulses 1
test pulses 2a
test pulses 3a
test pulses 3b
(Note 7)
−100
V
V
schaff
+75
−150
V
+100
150
V
Latch−up
Static latch−up at all pins
mA
°C
°C
−
T
Storage temperature
−55
−40
+150
+170
stg
T
J
Maximum junction temperature
Moisture sensitivity level for SOIC−8
Moisture sensitivity level for DFNW8
MSL
2
1
SOIC
MSL
−
DFN
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor
4. Standardized charged device model ESD pulses when tested according to AEC−Q100−011
5. System human body model electrostatic discharge (ESD) pulses in accordance to IEC 61000−4−2. Equivalent to discharging a 150 pF
capacitor through a 330 W resistor referenced to GND
6. Results were verified by external test house
7. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78
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NCV7357
Table 4. THERMAL CHARACTERISTICS
Parameter
Symbol
Value
Unit
Thermal characteristics SOIC−8 (Note 8)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 9)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 10)
R
R
131
81
°C/W
°C/W
q
JA
JA
q
Thermal characteristics DFNW8 (Note 8)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 9)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 10)
R
R
125
58
°C/W
°C/W
q
JA
JA
q
8. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters
9. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage
10.Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage
Table 5. ELECTRICAL CHARACTERISTICS (V = 4.75 V to 5.25 V; V = 2.8 V to 5.25 V; for typical values T = 25°C, for
CC
IO
A
min/max values T = −40 to +150°C; R = 60 W, C = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2).
J
LT
RxD
Positive currents flow into the respective pin; (Notes 11))
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY (Pin V
)
CC
V
Power supply voltage
(Note 12)
4.75
30
5.0
45
5.0
−
5.25
55
V
CC
CC
I
Supply current in Normal mode
Dominant; V
= Low
mA
mA
TxD
TxD
Recessive; V
= High
2.0
2.0
10
Normal mode, Dominant; V
= 0
TxD
V; one of bus wires shorted
−3 V ≤ (V , V ) ≤ +18 V
mA
mA
mA
V
105
1.3
CANH
CANL
I
Supply current in silent mode
NCV7357−3 version
0.1
0.1
3.5
−
−
CCS
Supply current in silent mode
NCV7357−0 version
1.5
4.3
V
Undervoltage detection on V pin
4.0
UVDVCC
CC
V
IO
SUPPLY VOLTAGE (Pin V ) Only for NCV7357−3 version
IO
V
Supply voltage on pin V
2.8
−
−
5.5
200
900
600
2.6
V
IO
IO
I
Supply current on pin V in silent mode
V = VIO
TxD
120
700
460
2.3
mA
IOS
IO
Dominant; V
Recessive; V
= Low
−
TxD
TxD
Supply current on pin V during normal
IO
I
mA
IONM
mode
= High
−
V
Undervoltage detection voltage on V
pin
2.0
V
UVDVIO
IO
TRANSMITTER DATA INPUT (Pin TxD)
V
High−level input voltage
Low−level input voltage
High−level input current
Low−level input current
Input capacitance
Output recessive
Output dominant
2.0
−0.3
−5.0
−300
−
−
−
−
V
IH
V
0.8
5.0
−75
10
V
IL
I
IH
V
TxD
= V V
CC / IO
0
mA
mA
pF
I
IL
V
TxD
= 0 V
−150
5
C
(Note 13)
i
TRANSMITTER DATA INPUT (Pin S)
V
High−level input voltage
Low−level input voltage
High−level input current
Low−level input current
Input capacitance
Silent mode
2.0
−0.3
−1.0
−15
−
−
−
0
−
5
−
V
IH
V
Normal mode
0.8
1.0
−1.0
10
V
IL
I
IH
V
S
= V / V
IO
mA
mA
pF
CC
I
IL
V = 0 V
S
C
(Note 13)
i
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NCV7357
Table 5. ELECTRICAL CHARACTERISTICS (V = 4.75 V to 5.25 V; V = 2.8 V to 5.25 V; for typical values T = 25°C, for
CC
IO
A
min/max values T = −40 to +150°C; R = 60 W, C = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2).
J
LT
RxD
Positive currents flow into the respective pin; (Notes 11))
RECEIVER DATA OUTPUT (Pin RxD)
I
High−level output current
Normal mode
−8.0
−3.0
−1.0
mA
mA
OH
V
RxD
= V / V – 0.4 V
CC
IO
I
Low−level output current
V
RxD
= 0.4 V
1.0
6.0
12
OL
CAN TRANSMITTER (PINS CANH AND CANL)
V
Dominant output voltage at pin CANH
Normal mode; V
dom(TxD)
= Low;
LT
o(dom)(CANH)
TxD
2.75
0.5
3.5
1.5
4.5
V
V
t < t
; 50 W < R < 65 W
V
Dominant output voltage at pin CANL
Normal mode; V
= Low;
LT
o(dom)(CANL)
TxD
2.25
t < t ; 50 W < R < 65 W
dom(TxD)
V
o(rec)
Recessive output voltage at pins CANH
and CANL
Normal or Silent mode;
= High
V
TxD
2.0
2.5
3.0
V
or V
= Low and t > t
no load
;
TxD
dom(TxD)
V
Differential dominant output voltage
Normal mode; V
dom(TxD)
= Low;
LT
o(dom)(diff)
TxD
1.5
1.5
2.25
3.0
5.0
V
V
(V
− V
)
t < t
; 45 W < R < 65 W
CANH
CANL
V
Normal mode; V
= Low;
o(dom)(diff)_ARB
TxD
t < t
; R = 2 240 W
−
dom(TxD)
LT
(Note 13)
V
Differential recessive output voltage
(V − V
Normal or Silent mode;
o(rec)(diff)
)
V
= High
CANH
CANL
TxD
−50
0
+50
mV
or V
= Low and t > t
;
dom(TxD)
TxD
no load
V
Dominant output voltage driver symmetry
= V
o(CANL)(dom)
TxD = square wave up to 1 MHz;
= 4.7 nF
o(dom)(sym)
V
+
C
ST
0.9
−100
−1.0
−5.0
1.0
−70
+70
−
1.1
V
CC
o(dom)(sym)
o(CANH)(dom)
V
I
Short circuit output current at pin CANH
in dominant
Normal mode; TxD = Low,
t < t ; −3 V ≤ V
o(sc)(CANH)
≤
≤
+1.0
+100
+5.0
mA
dom(TxD)
CANH
+18 V
I
Short circuit output current at pin CANL in
dominant
Normal mode; TxD = Low,
o(sc)(CANL)
t < t ; −3 V ≤ V
mA
mA
dom(TxD)
CANL
+36 V
I
Short circuit output current at pins CANH
and CANL in recessive
Normal or Silent mode;
TxD = High,
o(sc)(rec)
−27 V < V
, V
CANL
< + 32 V
CANH
CAN RECEIVER (Pins CANH and CANL)
I
Input leakage current
0 W < R(V to GND) < 1 MW
LEAK(off)
CC
−5.0
−5.0
0
0
+5.0
+5.0
mA
mA
V
= V
= 5 V
CANH
CANL
V
CANH
= V = 0 V
IO
CC
V
= V
= 5 V
CANL
V
Differential input voltage range
recessive state
Normal or Silent mode;
i(rec)(diff)_NM
−12 V ≤ V
, V
≤ +12 V;
−3.0
0.9
−
−
−
0.5
8.0
0.9
V
V
V
CANH
CANL
no load
V
Differential input voltage range
dominant state
Normal or Silent mode;
i(dom)(diff)_NM
−12 V ≤ V
, V
≤ +12 V;
CANH
CANL
no load
V
Differential receiver threshold voltage
voltage
Normal or Silent mode;
i(th)(diff)_NM
−12 V ≤ V
, V
≤ +12 V;
0.5
CANH
CANL
no load
V
Normal or Silent mode; extended,
i(th)(diff)_NM_E
−30 V ≤ V
, V
≤ +35 V;
0.4
15
−
1.0
37
V
CANH
CANL
no load
, V
CANL
R
Common−mode input resistance at pins
CANH and CANL
−2 V ≤ V
≤ +7 V
i(cm)
CANH
25
kW
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NCV7357
Table 5. ELECTRICAL CHARACTERISTICS (V = 4.75 V to 5.25 V; V = 2.8 V to 5.25 V; for typical values T = 25°C, for
CC
IO
A
min/max values T = −40 to +150°C; R = 60 W, C = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2).
J
LT
RxD
Positive currents flow into the respective pin; (Notes 11))
R
Matching between pin CANH and pin
CANL common mode input resistance
V
= V
= + 5 V
i(cm)(m)
CANH
CANL
−1
0
+1
75
%
R
Differential input resistance
R
= R
+
i(diff)
i(diff)
i(cm)(CANH)
R
25
50
kW
i(cm)(CANL)
−2 V ≤ V
, V
≤ + 7 V
CANH
CANL
C
Input capacitance at pins CANH and
CANL
V
= High; (Note 13)
= High; (Note 13)
i
TxD
−
−
7.5
20
10
pF
pF
C
Differential input capacitance
V
TxD
3.75
i(diff)
TIMING CHARACTERISTICS (see Figure 5, Figure 6 and Figure 8)
t
t
Propagation delay TxD to bus active
Propagation delay TxD to bus inactive
Propagation delay bus active to RxD
Propagation delay bus inactive to RxD
Normal mode (Note 14)
Normal mode (Note 14)
−
−
−
−
75
85
24
32
−
−
−
−
ns
ns
ns
ns
d(TxD−BUSon)
d(TxD−BUSoff)
d(BUSon−RxD)
d(BUSoff−RxD)
t
t
Normal or Silent mode (Note 14)
Normal or Silent mode (Note 14)
Normal mode (Note 14)
t
Propagation delay TxD to RxD dominant
to recessive transition
pd_dr
50
50
100
120
210
210
ns
ns
t
Propagation delay TxD to RxD recessive
to dominant transition
Normal mode (Note 14)
pd_rd
t
Operating mode change delay
TxD dominant timeout
Bit time on RxD pin
Silent mode to Normal mode
5.0
1.0
11
−
50
10
ms
ms
ns
ns
d(s−nm)
t
Normal mode; V
= Low
dom(TxD)
TxD
t
t
= 500 ns (Note 14)
= 200 ns (Note 14)
= 500 ns (Note 14)
400
120
−
550
220
bit(RxD)
bit(TxD)
−
t
bit(TxD)
t
Bit time on bus (CANH − CANL pin)
t
435
155
−
−
530
210
ns
ns
bit(Vi(diff))
bit(TxD)
bit(TxD)
t
= 200 ns (Note 14)
Receiver timing symmetry
t
= 500 ns (Note 14)
= 200 ns (Note 14)
−65
−45
−
−
40
15
ns
ns
bit(TxD)
Dt
rec
Δt
t
− t
rec = bit(RxD) bit(Vi(diff))
t
bit(TxD)
THERMAL SHUTDOWN
Shutdown junction temperature
T
J(sd)
Junction temperature rising
160
180
200
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C. Low
J
A
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
12.In the range between VUVDVCC and 4.75 V and from 5.25 V to 6 V the chip is fully functional; some parameters may be outside of the
specification
13.Values based on design and characterization, not tested in production
14.C = 100 pF, C not present, C = 15 pF
LT
ST
RxD
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NCV7357
MEASUREMENTS SETUPS AND DEFINITIONS
recessive
dominant
recessive
0.7 x VIO*
TxD
0.3 x VIO*
CANH
CANL
900 mV
Vi(diff)
=
V
CANH − V
CANL
500 mV
0.7 x VIO*
RxD
0.3 x VIO*
td(TxD−BUSon)
td(TxD−BUSoff)
td(BUSoff−RXD)
td(BUSon−RXD)
Edge length below 10 ns
*On NCV7357−0 version VIO is replaced by VCC
Figure 5. Transceiver Timing Diagram − Propagation Delays
0.7 x VIO*
TxD
0.3 x VIO*
0.3 x VIO*
tpd_rd
5 x tbit(TxD)
tbit(TxD)
Vi(diff)
VCANH − V
=
900 mV
CANL
500 mV
tbit(Vi(diff))
0.7 x VIO*
RxD
0.3 x VIO*
tpd_dr
tbit(RxD)
Edge length below 10 ns
*On NCV7357−0 version VIO is replaced by VCC
Figure 6. Transceiver Timing Diagram − Loop Delay and Recessive Bit Time
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9
NCV7357
+5 V
+5 V
100nF
100 nF
VCC
V
IO
VCC
VIO
3
5
3
5
CANH
CANH
7
6
7
TxD
1
TxD
1
RLT /2
1 nF
CLT
Transient
Generator
CST
RLT /2
100 pF
RxD
4
1 nF
CANL
RxD
4
6
CANL
2x 30 W
8
2
8
2
15 pF
S
GND
15 pF
S
GND
Figure 7. Test Circuit for Automotive Transients
Figure 8. Test Circuit for Timing Characteristics
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10
NCV7357
Table 6. ISO 11898−2:2016 Parameter Cross−Reference Table
ISO 11898−2:2016 Specification
NCV7357 Datasheet
Symbol
Parameter
Notation
DOMINANT OUTPUT CHARACTERISTICS
Single ended voltage on CAN_H
V
V
o(dom)(CANH)
CAN_H
Single ended voltage on CAN_L
V
CAN_L
V
o(dom)(CANL)
Differential voltage on normal bus load
Differential voltage on effective resistance during arbitration
Differential voltage on extended bus load range (optional)
DRIVER SYMMETRY
V
Diff
V
Diff
V
Diff
V
o(dom)(diff)
o(dom)(diff)_ARB
V
V
o(dom)(diff)
Driver symmetry
V
V
SYM
o(dom)(sym)
I
o(SC)(CANH)
DRIVER OUTPUT CURRENT
Absolute current on CAN_H
I
CAN_H
Absolute current on CAN_L
I
I
o(SC)(CANL)
CAN_L
RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING ACTIVE
Single ended output voltage on CAN_H
Single ended output voltage on CAN_L
Differential output voltage
V
NA
NA
NA
CAN_H
V
CAN_L
V
Diff
RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING INACTIVE
Single ended output voltage on CAN_H
Single ended output voltage on CAN_L
Differential output voltage
V
V
o(off) (CANH)
CAN_H
V
V
o(off) (CANL)
CAN_L
V
Diff
V
o(off) (diff)
OPTIONAL TRANSMIT DOMINANT TIMEOUT
Transmit dominant timeout, long
t
t
t
dom(TxD)
dom
Transmit dominant timeout, short
NA
dom
STATIC RECEIVER INPUT CHARACTERISTICS, BUS BIASING ACTIVE/ INACTIVE
Recessive state differential input voltage range
Dominant state differential input voltage range
RECEIVER INPUT RESISTANCE
V
V
V
i(rec)(diff)_NM
Diff
V
Diff
i(dom)(diff)_NM
Differential internal resistance
R
R
Diff
i(diff)
R
R
R
R
CAN_H
CAN_L
i(cm)
i(cm)
Single ended internal resistance
RECEIVER INPUT RESISTANCE MATCHING
Matching a of internal resistance
m
R
R
i(cm)(m)
IMPLEMENTATION LOOP DELAY REQUIREMENT
t
t
pd_rd
pd_dr
Loop delay
t
Loop
OPTIONAL IMPLEMENTATION DATA SIGNAL TIMING REQUIREMENTS FOR USE WITH BIT RATES ABOVE 1 MBIT/S AND UP
TO 2 MBIT/S
Transmitted recessive bit width @ 2 Mbit/s
Received recessive bit width @ 2 Mbit/s
Receiver timing symmetry @ 2 Mbit/s
t
t
bit(Vi(diff))
Bit(Bus)
t
t
bit(RxD)
Bit(RXD)
Dt
Rec
Dt
rec
OPTIONAL IMPLEMENTATION DATA SIGNAL TIMING REQUIREMENTS FOR USE WITH BIT RATES ABOVE 2 MBIT/S AND UP
TO 5 MBIT/S
Transmitted recessive bit width @ 5 Mbit/s
Transmitted recessive bit width @ 5 Mbit / s
t
t
bit(Vi(diff))
Bit(Bus)
t
t
bit(RxD)
Bit(RXD)
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11
NCV7357
Received recessive bit width @ 5 Mbit / s
Dt
Rec
Dt
rec
MAXIMUM RATINGS OF V
, V AND V
CAN_L DIFF
CAN_H
Maximum rating V
V
Diff
V
CANH − CANL
Diff
V
V
CANH
CANL
CAN_H
CAN_L
General maximum rating V
and V
CAN_L
CAN_H
V
V
V
CAN_H
CAN_L
Optional: Extended maximum rating V
and V
NA
CAN_H
CAN_L
V
MAXIMUM LEAKAGE CURRENTS ON CAN_H AND CAN_L, UNPOWERED
I
,
CAN_H
Leakage current on CAN_H, CAN_L
I
LEAK(off)
I
CAN_L
BUS BIASING CONTROL TIMINGS
CAN activity filter time, long
t
t
NA
NA
NA
NA
NA
NA
Filter
CAN activity filter time, short
Filter
Wake−up timeout, short
t
Wake
Wake
Wake−up timeout, long
t
Timeout for bus inactivity (Required for selective wake−up implementation only)
Bus Bias reaction time (Required for selective wake−up implementation only)
t
Silence
t
Bias
Table 7. ORDERING INFORMATION
Part Number
Description
Temperature Range
Package
Shipping
High Speed CAN FD
Transceiver
NCV7357D10R2G
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
SOIC 150 8 GREEN
(Matte Sn, JEDEC
MS−012) (Pb−Free)
−40°C to +150°C
High Speed CAN FD
NCV7357D13R2G
NCV7357MW0R2G
NCV7357MW3R2G
Transceiver with V pin
IO
High Speed CAN FD
Transceiver
DFNW8
Wettable Flank
(Pb−Free)
−40°C to +150°C
High Speed CAN FD
Transceiver with V pin
IO
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12
NCV7357
PACKAGE DIMENSIONS
SOIC−8
CASE 751AZ
ISSUE B
NOTES 4&5
0.10 C D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
455CHAMFER
D
h
NOTE 6
D
A
2X
H
8
5
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS
SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES
NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE.
5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT
TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER
MOST EXTREMES OF THE PLASTIC BODY AT DATUM H.
6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H.
7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP.
0.10 C D
NOTES 4&5
E
E1
L2
SEATING
L
C
PLANE
DETAIL A
1
4
0.20 C D
8X b
8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
B
M
0.25
C A-B D
NOTE 6
MILLIMETERS
TOP VIEW
NOTES 3&7
DIM MIN
MAX
1.75
0.25
---
DETAIL A
A
A1
A2
b
---
0.10
1.25
0.31
0.10
A2
NOcTE 7
0.10 C
0.51
0.25
c
D
4.90 BSC
A
E
6.00 BSC
3.90 BSC
1.27 BSC
e
END VIEW
SEATING
PLANE
E1
e
C
A1
SIDE VIEW
NOTE 8
h
0.25
0.40
0.41
1.27
L
0.25 BSC
L2
RECOMMENDED
SOLDERING FOOTPRINT*
GENERIC
MARKING DIAGRAM*
8X
0.76
8X
1.52
7.00
1
1.27
PITCH
DIMENSIONS: MILLIMETERS
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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13
NCV7357
DFNW8 3x3, 0.65P
CASE 507AB
ISSUE D
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L3
L3
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.10 AND
0.20mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. THIS DEVICE CONTAINS WETTABLE FLANK
DESIGN FEATURES TO AID IN FILLET FORMA-
TION ON THE LEADS DURING MOUNTING.
L
L
DETAIL A
ALTERNATE
CONSTRUCTION
E
A
PIN ONE
REFERENCE
EXPOSED
COPPER
MILLIMETERS
DIM MIN
NOM
0.85
−−−
MAX
0.90
0.05
A
A1
A3
A4
b
D
D2
E
E2
e
K
L
L3
0.80
−−−
0.20 REF
−−−
0.30
3.00
2.40
3.00
1.60
TOP VIEW
0.10
0.25
2.95
2.30
2.95
1.50
−−−
0.35
3.05
2.50
3.05
1.70
PLATING
A1
A4
DETAIL B
0.05
0.05
C
C
DETAIL B
A4
A3
C
C
C
0.65 BSC
0.30 REF
0.40
0.35
0.00
0.45
0.10
SEATING
PLANE
NOTE 4
SIDE VIEW
0.05
L3
PLATED
SURFACES
GENERIC
MARKING DIAGRAM*
D2
DETAIL A
SECTION C−C
1
4
5
8X
L
E2
K
8
8X b
e/2
e
0.10 C A B
NOTE 3
C
0.05
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present. Some products may
not follow the Generic Marking.
2.55
2.28
8X
0.75
8
5
4
3.30 1.76
PACKAGE
OUTLINE
1
0.65
PITCH
8X
0.33
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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14
NCV7357
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