NCV7450DB0R2G_技术文档

System Basis Chip with

CAN FD, LDO Regulator and

HS Driver

NCV7450

The system basis chip (SBC) NCV7450 integrates +5 V / 250 mA

LDO regulator with a high−speed CAN FD transceiver and one

high−side driver with diagnostics, directly controlled by dedicated

pins.

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Features

16

• 5 V 2% / 250 mA LDO

♦ Current Limitation with Fold−back

♦ Output Voltage Monitoring

1

TSSOP16−EP

CASE 948BV

• One High−Speed CAN FD Transceiver

♦ Current Limitation, Reverse Current Protected

♦ Compliant to ISO11898−2:2016

♦ CAN FD Timing Specified up to 5 Mbit/s

♦ TxDC Timeout

MARKING DIAGRAM

16

• One High−Side Driver

♦ Rdson = 300 mW @ 25°C

♦ Current Limitation

NCV

7450

ALYWG

♦ Diagnostic Output

♦ Overcurrent Protection

♦ Underload Detection

1

NCV7450

= Specific Device Code

A

L

Y

W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

• Direct Control

• Window Watchdog

• Two−level Thermal Shutdown Protection

• AEC−Q100 Qualified and PPAP Capable

• This Device is Pb−Free, Halogen Free/BFR Free and RoHS

Compliant

PIN CONNECTIONS

1

2

3

4

5

6

7

8

Typical Applications

• Automotive

• Industrial Networks

16

15

14

13

12

11

10

9

VS1

VR1

WD_EN

RSTN

VS2

HS

NCV

7450

GND

CANL

CANH

GND

CAN_EN

TxDC

HS_DIAG

RxDC

WDI

HS_EN

ORDERING INFORMATION

†

Device

Package

Shipping

NCV7450DB0R2G TSSOP16−EP 4000 / Tape &

(Pb−Free) Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

1

Publication Order Number:

November, 2019 − Rev. 1

NCV7450/D

NCV7450

Battery

Cbuf

100n

connection

VS1

VS2

References,

oscillator

VR1

5 V / 250 mA

4u7

VDD

RESET

RSTN

WD_EN

WDI

Watchdog

HS_EN

HS_DIAG

HS

High−Side

10n

MCU

Load

VR1

CAN_EN

TxDC

CANH

CANL

Termination,

Protection

CAN

CAN bus

CAN

RxDC

NCV7450

GND

Figure 1. Simplified Application Diagram

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2

NCV7450

VS1

16

VS2

15

1

3

VR1

UV

Internal

supply

RSTN

ref

References

LDO

VR1

Regulator

Thermal

Monitoring

Oscillator

2

7

WD_EN

WDI

Watchdog

OV

8

5

HS_EN

14

HS

Slope Control

Diagnosis

VR1

HS_DIAG

Thermal

Monitoring

High−Side Driver

9

CAN_EN

VR1

4

6

11

12

Tx

Timeout

TxDC

RxDC

CANH

CANL

VR1

CAN

10

13

GND

Figure 2. Block Diagram

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3

NCV7450

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VS1

VR1

WD_EN

RSTN

VS2

HS

NCV

7450

GND

CANL

CANH

GND

CAN_EN

TxDC

HS_DIAG

RxDC

WDI

HS_EN

Table 1. PIN DESCRIPTION

Pin Type

No.

(LV = Low Voltage; HV = High Voltage)

Pin Name

Description

1

VR1

LV supply output

Output of the 5 V / 250 mA low−drop regulator

Watchdog enable input

2

WD_EN

RSTN

TxDC

HS_DIAG

RxDC

WDI

LV digital input; internal pull−up current

LV digital output; open drain; internal pull−up

LV digital input; internal pull−up

LV digital output; push−pull

LV digital input; internal pull−down

Ground connection

3

Reset signal to the MCU

4

CAN transmitter data input

5

HS driver diagnostic output (active Low)

CAN receiver data output

6

7

Watchdog trigger input

8

HS_EN

CAN_EN

GND

HS driver enable input

9

CAN transceiver enable input

10

11

12

13

14

15

16

Ground supply (all GND pins have to be connected externally)

CANH line of the CAN bus

CANH

CANL

GND

CAN bus interface

CANL line of the CAN bus

Ground connection

Ground supply (all GND pins have to be connected externally)

High−side driver output

HS

HV output; high−side

VS2

HV supply input

Main supply input (HS Driver), keep floating if HS driver not used

Main supply input (VR1, logic)

VS1

HV supply input

EP

Exposed pad

Substrate (has to be connected to all GND pins externally)

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NCV7450

Table 2. MAXIMUM RATINGS

Symbol

Rating

Min

−0.3

Max

40

Unit

V

Vmax_VS1

DC Power Supply Voltage (Note 1)

DC High−side driver Voltage

DC voltage on digital pins

Vmax_VS2

40

V

Vmax_HS

VS2+0.3

VR1+0.3

V

Vmax_digIO

V

(CAN_EN, WD_EN, WDI, RSTN, RxDC, TxDC, HS_EN, HS_DIAG)

Vmax_CAN

Vmax_diff

DC voltage on pin CANH and CANL

−40

−0.3

40

V

Differential DC voltage between any two pins (incl. CANH and CANL)

LDO Supply pin output voltage

Vmax_VR1

6 or

VS1+0.3

(whichever

is lower)

Tj

Tstg

Junction Temperature Range

Storage Temperature Range

−40

−55

150

260

+5

°C

kV

Tsld

Peak Soldering Temperature (Note 3)

V_ESDHBM

ESD Capability, Device HBM (Note 2)

Pins VS1/2, CANH,

−5

CANL, HS

V_ESDHBM

V_ESDMM

V_ESDCDM

V_ESDIEC

V_SCHAF

ESD Capability, Device HBM (Note 2)

All other pins

−4

−250

−750

−6

+4

+250

+750

+6

kV

V

ESD Capability, Machine Model (Note 2)

ESD Capability, Charged Device Model (Note 2)

ESD Capability, System HBM (Note 2), pins VS1/2, CANH, CANL, HS

V

kV

V

Voltage transients per ISO7637*3, Class D, pins VS1/2,

Test pulse 1

Test pulse 2a

Test pulse 3a

Test pulse 3b

−100

−

CANH and CANL

+75

−

V

−150

−

V

+100

V

MSL

Moisture Sensitivity Level

2

−

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

2. This device series incorporates ESD protection and is tested by the following methods:

Device ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

Device ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)

Device ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)

System ESD Human Body Model tested per IEC61000−4−2 (150 pF, 330 W)

Latchup Current Maximum Rating: v150 mA per JEDEC standard: JESD78.

3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

Table 3. THERMAL CHARACTERISTICS

Symbol

Rating

Value

Unit

°C/W

Thermal Characteristics,

R

Thermal Resistance, Junction−to−Air (Note 4)

Thermal Resistance, Junction−to−Air (Note 5)

54

81

θJA

R

ψJA

°C/W

Thermal Characteristics,

Thermal Resistance, Junction−to−Case

R

10.5

θJC

4. Value based on test board according to JESD51−3 standard, signal layer with 10% trace coverage.

5. Value based on test board according to JESD51−7 standard, signal layers with 20% trace coverage, inner planes with 90% coverage.

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5

NCV7450

Table 4. RECOMMENDED OPERATING RANGES

Symbol

Rating

Min

5

Max

28

Unit

V

Functional supply voltage

VS1

Supply voltage for valid parameter specification

Functional supply voltage

6

18

V

4.3

6

24

V

VS2

Supply voltage for valid parameter specification

VR1 LDO output voltage

18

V

VR1

VdigIO

4.9

0

5.1

VR1

VS2

40

V

Digital inputs/outputs voltage

High−side driver voltage

V

HS

0

V

CANH, CANL

CAN bus pins voltage

−40

V

T

J

Junction Temperature

150

125

°C

T

A

Ambient Temperature

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Table 5. ELECTRICAL CHARACTERISTICS (6 V v Vs1 = Vs2 v 18 V; −40°C v Tj v 150°C; unless otherwise specified.)

Symbol

VS1, VS2 SUPPLY

VS_PORH

Parameter

Conditions

Min

Typ

Max Unit

VS1 POR threshold

VS1 rising

VS1 falling

3.4

2.0

−

4.1

3.5

−

V

VS_PORL

VS1 POR threshold

Is1_off

VS1 consumption, low−power

VS1 = VS2 = 14 V, VR1 on (not loaded), HS load

to GND, CAN bus recessive, CAN_EN = Low,

HS_EN = Low, WD_EN = Low, Tj v 85°C

VS1 = VS2 = 14 V, HS load to GND,

HS_EN = Low, Tj v 85°C

VS1 = VS2 = 14 V, VR1 on (loaded by 100 mA,

not included in Is_act), HS floating, CAN bus

recessive, CAN_EN = High, HS_EN = High,

WD_EN = High, TxDC = High

25

mA

Is2_off

Is_act

VS2 consumption, low−power

−

4

−

mA

VS1+VS2 consumption, active

10

20

mA

VS2_OV

VS2 overvoltage

HS_EN = High

VS2 rising

28

−

1

−

V

VS2_OV_hyst

tfilt_VS2_OV

VS2 overvoltage hysteresis

VS2 overvoltage filter time

60

105

ms

VR1 VOLTAGE REGULATOR

V_VR1

Regulator output voltage

0 mA v I(VR1) v 250 mA,

6 V v VS1 v 28 V

4.9

5.0

5.1

V

Iout_VR1

Ilim_VR1

Regulator output current

Maximum VR1 load current

−

250

mA

Regulator current limitation

Maximum VR1 overload current, VR1 >

RES_VR1

400

1000 mA

Ishort_VR1

Vdrop_VR1

Regulator short current

Dropout Voltage

Maximum VR1 short current, VR1 < RES_VR1

133

1/3 x

Ilim_VR1

333

mA

V

I(VR1) = 100 mA, VS1 = 5 V

·Tj v 150°C

−

0.2

−

0.4

−

0.2

·Tj v 40°C (Note 6)

·Tj = −40°C

I(VR1) = 100 mA, VS1 = 4.5 V

I(VR1) = 50 mA, VS1 = 4.5 V

1 mA v I(VR1) v 100 mA

−

0.5

0.4

50

30

−

Loadreg_VR1

Linereg_VR1

Cload_VR1

Load Regulation

Line Regulation

VR1 load capacity

−50

−30

1

−

mV

mF

I(VR1) v 100 mA

−

ESR < 200 mW, ceramic capacitor recommended

4.7

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NCV7450

Table 5. ELECTRICAL CHARACTERISTICS (6 V v Vs1 = Vs2 v 18 V; −40°C v Tj v 150°C; unless otherwise specified.)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

VR1 VOLTAGE REGULATOR

RES_VR1

RES_hyst_VR1

tfilt_RES_VR1

toff_VR1

VR1 Reset threshold

VR1 voltage decreasing

4.3

0.05

−

4.5

0.1

15

4.7

0.2

−

V

VR1 Reset threshold hysteresis

VR1 undervoltage filter time

VR1 off time after TSD

ms

s

−

1.0

−

Is_add_VR1

VS consumption adder of VR1

(Note 6)

−

0.02 x

I(VR1)

−

A

HS DRIVER

Ron_HS

On−resistance

Tj = 25°C (Note 6)

Tj = 125°C

−

0.3

−

W

0.6

Tj = 125°C, Vs2 = 4.3 V (Note 6)

Tj = 150°C

−

0.8

−

0.7

Ilim_HS

Ioc_HS

Current Limitation

−3.7

−40

−3

−2.7

−

−2.5

−1.7

−6.0

A

Overcurrent threshold

Underload detection threshold

Output leakage current

Iuld_HS

Ileak_HS

mA

HS off ; V(HS) = 0 V

Tj = 25°C (Note 6)

Tj = 150°C

−1

−5

−

td_on_HS

Output delay time

HS_EN = Low −> High;

ms

V(HS) = 0.1 x Vs2

·HS_EN was Low for more than 30 ms

·HS_EN was Low for less than 20 ms

−

140

40

−

td_off_HS

td_oc_HS

tdb_uld_HS

Output delay time

HS_EN = High −> Low; V(HS) = 0.9 x Vs2

−

40

−

ms

Overcurrent detection filter time

65

Underload detection blanking

delay

Timer started after driver activation and

V(HS) = Vs2 – 2 V

−

130

td_uld_HS

dVout_HS

Is_add_HS

Underload detection filter time

Slew rate

HS Driver active, tdb_uld_HS elapsed

HS load = 16 Ω to GND

−

70

−

ms

0.2

4.4

V/ms

mA

HS consumption from VS2

HS_EN = High; HS pin floating

2.0

8.0

WATCHDOG TIMING (see Figure 3)

twd_acc

t_wd_TO

Watchdog timing accuracy

−15

−

+15

%

Timeout watchdog period

After WD_EN low −> high transition or RSTN

pulse

−

65

−

ms

t_wd_CW

Window watchdog closed win-

dow

−

6

−

ms

t_wd_OW

t_RSTN

Window watchdog open window

−

100

8

−

ms

Reset pulse length after VR1 un-

dervoltage or watchdog failure

t_WDI

Minimum WDI pulse width ac-

cepted as a watchdog service

6.0

−

ms

DIGITAL OUTPUTS, RxDC, HS_DIAG

IoutL_pinx

IoutH_pinx

Low−level output driving current pinx is logical Low, forced V(pinx) = 0.4 V

1.0

6

12

mA

High−level output driving current pinx is logical High, forced V(pinx) = VR1 − 0.4 V −8.0

−3

−1.0

DIGITAL OUTPUT RSTN

IoutL_RSTN Low−level output driving current RSTN is active (logical Low), forced V(RSTN) =

2.0

5

12

mA

0.4 V

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NCV7450

Table 5. ELECTRICAL CHARACTERISTICS (6 V v Vs1 = Vs2 v 18 V; −40°C v Tj v 150°C; unless otherwise specified.)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

DIGITAL OUTPUT RSTN

VoutL_RSTN

Low−level output voltage, low

VR1/VS1

VR1 > 4.7 V, I(RSTN) = 0.7 mA

−

0.4

V

VR1 > 2 V, VS1 < VR1, I(RSTN) = 0.1 mA

VS1 > 2 V, I(RSTN) = 0.3 mA

−

0.4

19

Rpullup_RSTN

Internal pull−up resistor to VR1

5.0

10

kW

DIGITAL INPUTS TxDC, CAN_EN, WD_EN, HS_EN, WDI

VinL_pinx

Low−level input voltage (logical

0

−

0.8

V

“Low”)

VinH_pinx

High−level input voltage (logical

“High”)

2.0

VR1

Vin_hys_pinx

Rpullup_pinx

Input voltage hysteresis

100

55

−

500

185

mV

Internal pull−up resistor to VR1;

pin TxDC

100

kΩ

Rpulldown_pinx

Ipullup_WD_EN

Internal pull−down resistor to

ground;

55

100

185

kΩ

pins CAN_EN, HS_EN, WDI

Internal pull−up current to VR1, V(WD_EN) = 0 V, pull−up current source active

pin WD_EN

50

−

100

610

5.0

200

−

mA

ms

tper_pullup_WDEN WD_EN pull−up current source WD_EN = CAN_EN = HS_EN = Low

activation period

ton_pullup_WDEN WD_EN pull−up current source WD_EN = CAN_EN = HS_EN = Low

activation on−time

−

THERMAL PROTECTION

Tsd1

Thermal shutdown level 1

Temperature increasing; HS switched off conse-

quently

145

165

135

155

175

145

165

185

155

°C

Tsd2

Thermal shutdown level 2

Temperature increasing; VR1 and CAN switched

off consequently

Tsd1_off

Thermal shutdown recovery

temperature

Temperature decreasing; HS switched on

6. Not tested in production, guaranteed by design.

Reset or previous

WD service

nominal t _wd_TO

Timeout WD

Safe trigger of timeout WD

WD expired

period

t_wd_TO

tolerance

nominal t_wd_OW

t_wd_trig

nominal t _wd_CW

Closed window

(WD trigger would be too early )

Window WD

period

Safe trigger of window WD

OK20121113 .01

t_wd_CW

tolerance

t_wd_OW

tolerance

recommended

WD trigger

Figure 3. Watchdog modes timing

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NCV7450

Table 6. ELECTRICAL CHARACTERISTICS (CONTINUED)

(VR1 = 4.75 V to 5.25 V; T = −40°C to +150°C; R = 60 W, C = 100 pF, C not used unless specified otherwise.)

J

LT

1

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CAN BUS LINES (Pins CANH and CANL)

I

Recessive output current at pins CANH

and CANL

CAN enabled;

−27 V < V

−5.0

−

+5.0

mA

o(rec)

< +32 V

CANH/L

I

LI

Input leakage current

0 < R(VR1 to GND) < 1 MW

0

mA

V

CANH

= V

= 5 V

CANH

V

Recessive output voltage at pin CANH

Recessive output voltage at pin CANL

Recessive output voltage at pin CANH

Recessive output voltage at pin CANL

Differential bus output voltage in off

CAN enabled; V

CAN disabled

= VR1

2.0

2.5

0

3.0

0.1

0.2

V

o(rec) (CANH)

TxDC

V

o(rec) (CANL)

TxDC

V

−0.1

−0.2

o(off) (CANH)

V

0

o(off) (CANL)

V

0

o(off) (diff)

mode (V

− V

)

CANH

CANL

V

Dominant output voltage at pin CANH

Dominant output voltage at pin CANL

Dominant output CANH/CANL drivers

50 Ω < R < 65 Ω; V

= 0 V;

2.75

0.5

3.5

1.5

4.5

2.25

1.1

V

o(dom) (CANH)

LT

dom(TxDC)

TxDC

t < t

V

50 Ω < R < 65 Ω; V

= 0 V;

o(dom) (CANL)

LT

dom(TxDC)

TxDC

t < t

V

R

= 60 Ω; C = 4.7 nF;

0.9

VR1

o(dom)(sym)

LT

1

symmetry (V

+ V

)

CANH

CANL

TxDC driven by square wave up

to 1 MHz

V

Differential bus output voltage

(V − V

V

= 0 V; dominant;

1.5

−50

2.25

3.0

5.0

V

o(dom) (diff)

TxDC

)

CANL

CANH

45 Ω < R < 65 Ω

LT

V

Differential bus output voltage during ar-

bitration (V − V

V

TxDC

= 0 V; dominant;

= 2240 Ω; (Note 7)

o(dom) (diff)_arb

)

CANL

CANH

R

LT

V

Differential bus output voltage

(V − V

V

TxDC

= VR1; recessive;

0

−70

70

−

+50

mV

mA

V

o(rec) (diff)

)

CANL

CANH

no load

= −3 V; V = 0 V

TxDC

I

Short circuit output current at pin CANH

Short circuit output current at pin CANL

V

CANH

−100

−40

1.0

o(sc) (CANH)

−3 V ≤ V

≤ +18 V

CANH

I

V

CANL

= 36 V; V = 0 V

TxDC

40

−1.0

100

o(sc) (CANL)

−3 V ≤ V

≤ +18 V

CANL

V

Differential receiver threshold voltage in

normal mode

CAN enabled;

−12 V ≤ V

0.5

−3.0

0.9

0.5

8.0

1.05

0.4

8.0

37

i(th)(diff)_NORM

≤ +12 V;

≤ +12 V

CANH

CANL

V

Differential receiver input voltage for re-

cessive state in normal mode

CAN enabled;

−12 V ≤ V

−

V

i(rec)(diff)_NORM

≤ +12 V;

≤ +12 V

CANH

CANL

V

Differential receiver input voltage for

dominant state in normal mode

CAN enabled;

−12 V ≤ V

i(dom)(diff)_NORM

≤ +12 V;

≤ +12 V

CANH

CANL

V

Differential receiver threshold voltage in

wakeup−detection mode

CAN in wakeup−detection mode;

−12 V ≤ V

0.4

−

V

i(th)(diff)_WU

≤ +12 V;

≤ +12 V

CANH

CANL

V

Differential receiver input voltage for re-

cessive state in wakeup−detection mode

CAN in wakeup−detection mode;

−12 V ≤ V

−3.0

1.05

15

−

V

i(rec)(diff) _WU

≤ +12 V;

≤ +12 V

CANH

CANL

V

Differential receiver input voltage for

dominant state in wakeup−detection

mode

CAN in wakeup−detection mode;

−12 V ≤ V

−

V

i(dom)(diff)_WU

≤ +12 V;

≤ +12 V

CANH

CANL

R

Common−mode input resistance at pin

CANH

−2 V ≤ V

≤ +7 V;

≤ +7 V

25

kΩ

i(cm) (CANH)

CANH

CANL

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NCV7450

Table 6. ELECTRICAL CHARACTERISTICS (CONTINUED)

(VR1 = 4.75 V to 5.25 V; T = −40°C to +150°C; R = 60 W, C = 100 pF, C not used unless specified otherwise.)

J

LT

1

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CAN BUS LINES (Pins CANH and CANL)

R

Common−mode input resistance at pin

CANL

−2 V ≤ V

≤ +7 V;

≤ +7 V

15

25

37

kΩ

i(cm) (CANL)

CANH

CANL

R

Matching between pin CANH and pin

CANL common mode input resistance

V

= V = 5 V

CANL

−1.0

0

+1.0

75

%

i(cm) (m)

CANH

R

Differential input resistance

−2 V ≤ V

≤ +7 V;

≤ +7 V

25

50

kΩ

i(diff)

CANH

CANL

C

Input capacitance at pin CANH

Input capacitance at pin CANL

Differential input capacitance

V

TxDC

V

TxDC

V

TxDC

= VR1; (Note 7)

−

7.5

20

10

pF

i(CANH)

C

i(CANL)

C

3.75

i(diff)

TIMING CHARACTERISTICS (see Figure 4 and Figure 5)

t

Delay TxDC to bus dominant

Delay TxDC to bus recessive

Delay bus dominant to RxDC

Delay bus recessive to RxDC

−

65

90

−

ns

d(TxDC−BUSon)

d(TxDC−BUSoff)

d(BUSon−RxDC)

d(BUSoff−RxDC)

t

−

60

−

65

−

t

Propagation delay TxDC to RxDC domi-

nant to recessive transition

50

100

210

pd_dr

t

Propagation delay TxDC to RxDC reces-

sive to dominant transition

50

120

25

210

47

ns

pd_rd

t

Delay wake−up detection mode to nor-

mal mode

7.0

ms

d(stb−nm)

t

Dominant time for wake−up via bus

CAN_EN = low

0.15

0.5

−

1.8

10

ms

wake_filt

t

Delay to flag wake event (recessive to

dominant transitions)

Valid bus wake−up event

dwakerd

t

Delay to flag wake event (dominant to

recessive transitions)

Valid bus wake−up event

0.5

−

10

ms

dwakedr

t

Bus time for wake−up timeout

TxDC dominant time for timeout

Bit time on RxDC pin

CAN_EN = low

1.0

−

10

ms

ns

wake_to

t

CAN_EN = high; V

= 0 V

dom(TxDC)

TxDC

t

= 500 ns

= 200 ns

= 500 ns

= 200 ns

= 500 ns

= 200 ns

400

120

435

155

−65

−45

550

220

530

210

40

Bit(RxDC)

Bit(TxDC)

t

Bit time on bus (CANH – CANL pin)

Receiver timing symmetry

Bit(Vi(diff))

Dt

Rec

Dt

t

Rec = Bit(RxDC) − Bit(Vi(diff))

15

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

7. Not tested in production, guaranteed by design.

www.onsemi.com

10

NCV7450

6-18 V

100 nF

VS1

VS2

CANH

VR1

2.2 uF

R_LT

C_LT

NCV7450

CAN_EN

TxDC

100 pF

60 W

CANL

RxDC

15 pF

GND

Figure 4. Test Circuit for Timing Characteristics

0.7 x VR1

TxDC

0.3 x VR1

t_{pd_rd}

t_Bit(TxDC)

t_{d(TxDC−BUSon )}

5 x t_Bit(TxDC)

t_{d(BUSon −RxDC )}

900 mV

V_i(diff)= V_CANH− V

CANL

500 mV

t_{Bit(Vi(diff ))}

t_{d(TxDC−BUSoff )}

d(BUSoff −RxDC))

t_{pd_dr}

0.7 x VR1

RxDC

0.3 x VR1

t_{Bit(RxDC )}

Figure 5. CAN Transceiver Timing Diagram

www.onsemi.com

11

NCV7450

FUNCTIONAL DESCRIPTION

Supply Concept

V(VR1)

The device has two independent supply pins VS1 and

VS2. While VR1 regulator and logic control are supplied

from VS1, High−side driver is supplied from VS2. Both

supply lines have to be properly decoupled by filtration

capacitors close to the device pins.

V_VR1

RES_hys_VR1

RES_VR1

As long as VS1 < VS_POR level, all the blocks are in

power−down mode.

VR1 Low−drop Regulator

Ishort _VR1

Ilim_VR1

I(VR1)

VR1 is a low−drop output regulator providing 5 V voltage

derived from the VS1 main supply. It is able to deliver up to

250 mA and is primarily intended to supply the on−chip

CAN transceiver, the application microcontroller unit

(MCU) and related 5 V loads (e.g. its own MCU−related

digital inputs/outputs). An external capacitor needs to be

connected on VR1 pin in order to ensure the regulator’s

stability and to filter the disturbances caused by the

connected loads.

VR1 voltage is supplying all the digital low−voltage

input/output pins.

The protection and monitoring of the VR1 regulator

consist of the following features:

Figure 7. VR1 current fold−back

CAN Transceiver

The SBC contains one high−speed CAN transceiver

compliant with ISO11898−2:2016, supporting bit rates up to

5 Mbit/s. The transceiver consists of the following

sub−blocks: transmitter, receiver, and wakeup detector.

If enabled (CAN_EN = High), the CAN transceiver is

ready to provide the full−speed interface between the bus

and a CAN controller connected on pins RxDC (received

data) and TxDC (data to transmit). The bus lines are biased

to VR1 / 2.

In order to prevent a faulty node from blocking the bus

traffic, the maximum length of the transmitted dominant

symbol is limited by a timeout counter to tdom(TxDC). In

case the TxDC Low signal exceeds the timeout value, the

transmitter returns automatically to the recessive state. The

transmission is again de−blocked when TxDC pin returns to

high (recessive) state.

If the CAN block is disabled (CAN_EN = Low) or RSTN

pin active (Low) due to failed watchdog service or VR1

undervoltage, the CAN transceiver is in its wake−up

detection state. The bus lines are biased to ground. Logical

level on TxDC is ignored and pin RxDC is kept high until a

CAN bus wake−up is detected. The CAN bus wake−up

corresponds to a pattern consisting of dominant – recessive

♦ VR1 Current Limitation – the two−level current

limitation controlled by VR1 reset comparator to

reduce the power dissipation in case of shorts to

ground by the current fold−back (see Figure 7)

♦ VR1 Reset Comparator – the VR1 regulator output

is compared with a reset level RES_VR1. If the VR1

level drops below this level for longer than

tflt_RES_VR1, a reset towards the MCU is generated

through the RSTN pin and peripherals (CAN

transceiver and HS driver) disabled.

♦ Temperature (see Figure 14)

V(VS)

V(VR1)

Vdrop_VR1

V_VR1

RES_VR1

VS_PORH

VS_PORL

– dominant symbols of at least t

each. The RxDC

wake_filt

starts following the CAN bus afterwards. The pattern must

be received within t to be recognized as a valid

wake−up event, otherwise internal wake−up logic is reset.

tfilt_VR1_RES

t_RSTN

tfilt_VR1_RES

wake_to

<tfilt_VR1_RES

RSTN

t_RSTN

Reset

EN_CAN

Off

Reset

Normal functionality

Norm. R Off

Mode

t_{wake_filt}

Figure 6. VR1 monitoring

CANH

CANL

< t_{wake_to}

t_dwakerd

RxDC

Figure 8. CAN wakeup pattern

www.onsemi.com

12

NCV7450

HS Driver

features are limited by td_oc_HS in case of an overcurrent

and (VS2 / dVout_HS) + td_uld_HS in case of an underload.

The HS driver is designed to drive resistive loads.

Therefore only a limited clamping energy (W < 1 mJ) can be

dissipated by the device. For inductive loads (L > 100 mH)

an external freewheeling diode connected between GND

and the HS pin is required.

HS high−side driver is intended to drive an external load.

Its state is directly controlled via HS_EN pin and diagnostics

are flagged on HS_DIAG pin (see Table 7).

When the driver is enabled (HS_EN = High), it is

protected against an excessive current and temperature and

diagnosed on Underload condition.

In case the HS driver is controlled by a PWM signal

through HS_EN with very low duty−cycle, the diagnostic

Table 7. HS Driver Diagnostics

Event

HS_EN

Low

Failure condition

HS status

HS_DIAG

High

Recovery condition

−

Off

On

Off

−

Normal operation (no failure)

High

−

High

−

Overcurrent

High

I(HS) > Ioc_HS

Low

HS_EN = Low

Underload

High

I(HS) < Iuld_HS

On

Low

I(HS) > Iuld_HS

Short−to−battery

Over−temperature

VS2 Overvoltage

RSTN active

High

Tj > Tsd1

VS2 > VS2_OV

RSTN = Low

Off

Low

Tj < Tsd1_off

VS2 < VS2_OV

RSTN = High

Vs < Vs_PORL

Vs > Vs_PORH

Unpowered

Reset

No trigger

within t_wd_OW

No trigger

within

WD_EN = high

Trigger

t_wd_TO

Trigger

WD_EN = low

WD_EN = high

Closed

Window

Open

Disabled

Timeout

Window

t_wd_CW

elapsed

Trigger

Figure 9. Watchdog operating modes

WD Enable

Watchdog

The on−chip watchdog requires that the MCU software

“triggers” or “services” the watchdog in a specified time

frame. A correct watchdog service consists of high−to−low

transition on the WDI input. The watchdog timer restarts

immediately after a successful trigger is received.

WD_EN

WDI

Service

After any Reset event (power−up, watchdog failure, VR1

undervoltage, thermal shutdown 2) or watchdog enable

(WD_EN = Low −> High), the watchdog always starts in a

timeout mode. The MCU software must serve the watchdog

any time before the timeout expiration. After the watchdog

is triggered for the first time, it starts working in a window

mode operation: the watchdog time is split to two distinct

parts – a closed window, where the watchdog may not be

triggered, is followed by an open window where the MCU

must send a valid watchdog trigger (see Figure 10).

RSTN

Closed

Open

Closed

window window window window

Open

Timeout

WD status off

<t_wd_TO

t_wd_CW <t_wd_OW

t_wd_trig

Figure 10. Correct watchdog services

www.onsemi.com

13

NCV7450

In case the watchdog is not triggered before the timeout or

To ensure the High level is correctly detected if the pin

becomes floating, external WD_EN capacity should stay

below 50 pF.

After the rising edge on WD_EN pin, the MCU should

wait tper_pullup_WDEN before the first watchdog service.

open window elapses (Figure 11, Figure 12), or trigger is

sent within the closed window (Figure 13), RSTN signal is

generated and then watchdog restarted in the timeout mode

again.

WD Enable

WD_EN

sampled

WD_EN

sampled

WD_EN

sampled

WD_EN

WDI

Timeout elapsed

Ipullup_WD_EN

Pull-up current

tper_pullup_WDEN

ton_pullup_WDEN

Enabled

(timeout )

Enabled

Disabled

WD status

RSTN

Figure 14. WD_EN pull−up current source activation

Closed

window

Open

win.

Reset

Timeout

off

Timeout

t_wd_TO

WD status

t_RSTN

t_wd_CW

Thermal Protection

The device junction temperature is monitored in order to

avoid permanent degradation or damage. Two distinct

junction temperature levels are provided − thermal

shutdown level 1 Tsd1 (typ. 155°C) and thermal shutdown

level 2 Tsd2 (typ. 175°C).

When the junction temperature exceeds the first thermal

shutdown level, the high−side driver is disabled while VR1

and CAN transceiver keeps running so that the MCU can

still take appropriate actions. The junction temperature

above the second shutdown level leads to complete device

de−activation, VR1 included; the device recovers

automatically after the junction temperature drops below

Tsd1 level and toff_VR1 (typ. 1 second) elapses. HS driver

functionality is recovered when the junction temperature

drops below Tsd1_off.

Figure 11. Missed watchdog in Timeout mode

WD_EN

WDI

Open Window elapsed

RSTN

Closed Open

window window

Closed Open

window window

Reset

Timeout

WD status

t_wd_CW t_wd_OW t_RSTN

t_wd_CW

Figure 12. Missed watchdog in Window mode

The details of the thermal protection handling are shown

in Figure 15.

Trigger in

Closed Window

WD_EN

WDI

Normal operation

VR1: on

CAN: per CAN _EN

HS: per HS _EN

Watchdog: per WD _EN

RSTN: High

RSTN

Closed

Reset

win.

Closed Open Closed Open

window win. window win.

Timeout

WD status

Tj < Tsd1_off

<t_wd_CW t_RSTN

t_wd_CW

Thermal Shutdown 1

Figure 13. Watchdog service during closed window

VR1: on

CAN: per CAN _EN

HS: off

Watchdog: per WD _EN

RSTN: High

The WD_EN pin has an integrated pull−up source to

enable the watchdog in case the pin is disconnected from the

application. To reduce the power consumption in the

low−power mode (watchdog, CAN and HS driver disabled),

the WD_EN pull−up current source is switched on for

Thermal Shutdown 2

Cool-down

ton_pullup_WDEN

time

with

period

of

tper_pullup_WDEN. The pin state is sampled in the end of

the current source activation. Once High level is detected on

the WD_EN pin, the current source is activated

permanently.

VR1: off

CAN: off

HS: off

Watchdog: off

RSTN: Low

VR1: off

CAN: off

HS: off

Watchdog: off

RSTN: Low

Tj < Tsd1

Figure 15. Thermal monitoring flow chart

www.onsemi.com

14

NCV7450

Table 8. ISO11898−2:2016 PARAMETER CROSS−REFERENCE TABLE

ISO 11898−2:2016 Specification

NCV7450 Datasheet

Symbol

Parameter

Notation

DOMINANT OUTPUT CHARACTERISTICS

Single ended voltage on CAN_H

V

o(dom)(CANH)

CAN_H

Single ended voltage on CAN_L

V

CAN_L

V

o(dom)(CANL)

Differential voltage on normal bus load

Differential voltage on effective resistance during arbitration

Optional: Differential voltage on extended bus load range

DRIVER SYMMETRY

V

Diff

V

Diff

V

Diff

V

o(dom)(diff)

V

o(dom)(diff)_arb

V

o(dom)(diff)

Driver symmetry

V

SYM

o(dom)(sym)

I

o(SC)(CANH)

DRIVER OUTPUT CURRENT

Absolute current on CAN_H

I

CAN_H

Absolute current on CAN_L

I

o(SC)(CANL)

CAN_L

RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING ACTIVE

Single ended output voltage on CAN_H

Single ended output voltage on CAN_L

Differential output voltage

V

o(rec)(CANH)

CAN_H

V

o(rec)(CANL)

CAN_L

V

Diff

V

o(rec)(diff)

RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING INACTIVE

Single ended output voltage on CAN_H

Single ended output voltage on CAN_L

Differential output voltage

V

o(off)(CANH)

CAN_H

V

o(off)(CANL)

CAN_L

V

Diff

V

o(off)(dif)

OPTIONAL TRANSMIT DOMINANT TIMEOUT

Transmit dominant timeout, long

t

dom(TxDC)

dom

Transmit dominant timeout, short

NA

dom

STATIC RECEIVER INPUT CHARACTERISTICS, BUS BIASING ACTIVE

Recessive state differential input voltage range

Dominant state differential input voltage range

STATIC RECEIVER INPUT CHARACTERISTICS, BUS BIASING INACTIVE

Recessive state differential input voltage range

Dominant state differential input voltage range

RECEIVER INPUT RESISTANCE

V

i(rec)(diff) _ NORM

Diff

V

Diff

i(dom)(diff) _ NORM

V

i(rec)(diff) _ WU

Diff

V

Diff

i(dom)(diff) _ WU

Differential internal resistance

R

Diff

i(diff)

R

i(cm)(CANH)

Single ended internal resistance

R

CAN_H

R

i(cm)(CANL)

CAN_L

RECEIVER INPUT RESISTANCE MATCHING

Matching a of internal resistance

IMPLEMENTATION LOOP DELAY REQUIREMENT

Loop delay

m

R

i(cm)(m)

R

t

Loop

pd_rd

t

pd_dr

OPTIONAL IMPLEMENTATION DATA SIGNAL TIMING REQUIREMENTS for use with bit rates above 1 Mbit/s and up to 2 Mbit/s

Transmitted recessive bit width @ 2 Mbit/s

Received recessive bit width @ 2 Mbit/s

Receiver timing symmetry @ 2 Mbit/s

t

Bit(Vi(diff))

Bit(Bus)

t

Bit(RxD)

Bit(RXD)

Dt

Rec

Dt

Rec

www.onsemi.com

15

NCV7450

Table 8. ISO11898−2:2016 PARAMETER CROSS−REFERENCE TABLE

ISO 11898−2:2016 Specification

NCV7450 Datasheet

Symbol

Parameter

Notation

OPTIONAL IMPLEMENTATION DATA SIGNAL TIMING REQUIREMENTS for use with bit rates above 2 Mbit/s and up to 5 Mbit/s

Transmitted recessive bit width @ 5 Mbit/s

Transmitted recessive bit width @ 5 Mbit / s

Received recessive bit width @ 5 Mbit / s

t

Bit(Vi(diff))

Bit(Bus)

t

Bit(RxD)

Bit(RXD)

Dt

Rec

Dt

Rec

MAXIMUM RATINGS OF V

, V AND V

CAN_L DIFF

CAN_H

Maximum rating V

V

Diff

Vmax_diff

Diff

General maximum rating V

and V

V

CANH

CAN_H

CAN_L

CAN_H

V

CAN_L

V

CANL

Optional: Extended maximum rating V

and V

V

NA

CAN_H

CAN_L

CAN_H

V

CAN_L

MAXIMUM LEAKAGE CURRENTS ON CAN_H AND CAN_L, UNPOWERED

Leakage current on CAN_H, CAN_L

I

,

I

LI

CAN_H

I

CAN_L

BUS BIASING CONTROL TIMINGS

CAN activity filter time, long

t

NA

Filter

CAN activity filter time, short

t

wake_filt

Filter

Optional: Wake−up timeout, short

t

wake_to

Wake

Optional: Wake−up timeout, long

t

wake_to

Timeout for bus inactivity (Required for selective wake−up implementation only)

Bus Bias reaction time (Required for selective wake−up implementation only)

t

NA

Silence

t

NA

Bias

www.onsemi.com

16

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

TSSOP16, 4.4x5 EXPOSED PAD

CASE 948BV

ISSUE O

DATE 22 JUN 2017

TOP VIEW

END VIEW

BOTTOM VIEW

SIDE VIEW

MIN

SYMBOL

NOM

MAX

A

A1

A2

b

c

D

1.10

0.15

0.95

0.30

0.20

5.10

6.50

4.50

0.05

0.85

0.19

0.13

4.90

6.30

4.30

E

E1

e

L

0.65 BSC

1.00 REF

L1

N

P

R

S

0.45

0.90

6.50

4.60

0.37

0.75

1.00

6.70

4.80

0.47

LAND PATTERN

0º

8º

θ

X

Y

Notes:

3.33 REF

2.76 REF

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153 variations ABT.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON65408G

TSSOP16, 4.4X5 EXPOSED PAD

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

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


型号：	NCV7450DB0R2G
厂家：	ONSEMI
描述：	具有 CAN FD、LDO 稳压器和 HS 驱动器的系统基础芯片驱动驱动器稳压器
文件：	总18页 (文件大小：317K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV7450DB0R2G [ONSEMI]

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