NCV7512FTR2G [ONSEMI]
FLEXMOS Quad Low-Side Pre-Driver; FLEXMOS四路低端预驱动器
| 型号： | NCV7512FTR2G |
| 厂家： | 
ONSEMI |
| 描述： | FLEXMOS Quad Low-Side Pre-Driver |
| 文件： | 总25页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV7512
FLEXMOSt Quad Low-Side
Pre-Driver
The NCV7512 programmable four channel low−side MOSFET
driver is one of a family of FLEXMOSTM automotive grade products
used for driving logic−level MOSFETs. The product is controllable
by any combination of SPI (Serial Peripheral Interface) or parallel
inputs.
Programmable features include optional fault recovery, shorted
load detection threshold, fault retry timing, and fault masking mode.
The programmable refresh time allows operation in a
power−limiting PWM mode.
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MARKING
DIAGRAM
The device offers 3.3 V / 5 V compatible logic inputs and the serial
output driver can be powered from either 3.3 V or 5 V supplies.
Power−on reset of the supply pin provides for a controlled power up
and power down. Two enable inputs are supplied. ENA1 provides a
global on/off control with a reset function for internal circuitry.
ENA2 controls the output stage (during initialization).
Each channel independently monitors its external MOSFET’s
drain voltage for fault conditions. Shorted load fault detection
thresholds are fully programmable using an externally programmed
reference voltage and a combination of four discrete internal ratio
values. The ratio values are SPI selectable and allow different
detection thresholds for each pair of output channels. Open load fault
detection threshold is a function of a percentage of the power supply
voltage (VCC1). Fault information for each channel is 2−bit encoded
by fault type and is available through SPI communication.
32 LEAD LQFP
FT SUFFIX
CASE 873A
NCV7512
AWLYYWWG
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
The FLEXMOS family of products offers application scalability
through choice of external MOSFETs.
NCV7512FTG
LQFP
(Pb−Free)
250 Units/Tray
Features
NCV7512FTR2G
LQFP
2000 Tape & Reel
(Pb−Free)
• 16−Bit SPI with Frame Error Detection
• 3.3 V/5 V Compatible Parallel and Serial Control Inputs
• 3.3 V/5 V Compatible Serial Output Driver
• Two Enable Inputs
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Open−Drain Fault and Status Flags
• Programmable
− Shorted Load Fault Detection Thresholds
− Fault Recovery Mode
− Fault Retry Timer
− Flag Masking
• Load Diagnostics with Latched Unique Fault Type Data
− Shorted Load
− Open Load
− Short to GND
• Scalable to Load by Choice of External MOSFET
• These are Pb−Free Devices*
• NCV Prefix for Automotive
−Site and Change Control
−AEC−Q100 Qualified
*For additional information on our Pb−Free strategy and soldering details, please
downloadthe ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
December, 2008 − Rev. 2
NCV7512/D
NCV7512
IN3 IN2 IN1 IN0
ENA2
VCC2
NCV7512
CHANNEL 1
Quad Low−Side Pre−Driver
DRN1
GAT1
DRN2
FAULT
DETECT
POWER ON RESET
VCC1
ENA1
VSS
VCC2
&
BIAS
DRIVER
VSS
GATE SELECT
FLAG MASK
ENA ENA
DRN
VCC2
VCC2
VCC2
CHANNEL 2
DISABLE MODE
REFRESH/REF
1
2
REF
DISABLE
PARALLEL
SERIAL
GAT2
DRN3
VSS
CSB
SCLK
SI
6
ENA ENA
DRN
CHANNEL 3
VCC
1
2
REF
POR
CSB
SCLK
SI
DISABLE
PARALLEL
SERIAL
GAT3
DRN4
VSS
SPI
16 BIT
ENA ENA
DRN
CHANNEL 4
1
2
REF
VDD
SO
DISABLE
PARALLEL
SERIAL
GAT4
VSS
VSS
DRIVER
VSS
SO
VCC1
8
VCC1
FAULT BITS
CH
1−2
FAULT
REFERENCE
GENERATOR
FLTREF
+
FLTB
GND
OA
−
CH
3−4
FAULT LOGIC
&
REFRESH TIMER
4
2
ENA
1
DRN 1:4
CLOCK
DRAIN
FEEDBACK
MONITOR
MASK 1:4
STAB
POR
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Figure 1. Block Diagram
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NCV7512
V
LOAD
M
+5V
RFILT
POWER−ON
RESET
CB1
VCC1
FLTREF
ENA1
ENA2
N/C
VCC2
DRN1
GAT1
DRN2
GAT2
DRN3
GAT3
DRN4
GAT4
N/C
+5V OR
+3.3V
RD1
RD2
RD3
RD4
NID9N05CL
NID9N05CL
NID9N05CL
RST
5
IN1
IN2
CB2
IN3
NID9N05CL
IN4
4
N/C
IRQ
I/O
FLTB
CSB
SCLK
SI
N/C
N/C
N/C
RFPU
VDD
SO
STAB
GND
RSPU
VSS
Figure 2. Application Diagram
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NCV7512
PIN FUNCTION DESCRIPTION
PIN Number
Symbol
N/C*
IN1
Description
1
No Connection.
2
Channel 1 Input Parallel Control. Active High.
3
IN2
Channel 2 Input Parallel Control. Active High.
4
IN3
Channel 3 Input Parallel Control. Active High.
5
IN4
Channel 4 Input Parallel Control. Active High.
6
N/C*
ENA2
ENA1
FLTB
CSB
No Connection.
7
Enable 2 Input. Active High. Output Driver Control and Diagnostic Circuitry.
8
Enable 1 Input. Active High. Output Driver Control with System Reset.
9
Fault Bar Flag. Open−Drain Output. Goes Low with any Channel Open or Short Condition.**
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Chip Select Bar (SPI Control).
SCLK
SI
Serial Clock (SPI Control).
Serial Input (SPI Control).
SO
Serial Output (SPI Control).
VDD
STAB
VSS
Power Supply − Serial Output Driver.
Status Bar Flag. Open−Drain Output. Goes Low when any DRNx is Low (FET is On).**
Power Return (Ground) for VCC2, VDD, Drain Clamps. Isolated from GND by a Diode.
N/C*
N/C*
GAT4
DRN4
GAT3
DRN3
GAT2
DRN2
GAT1
DRN1
N/C*
N/C*
VCC2
VCC1
FLTREF
GND
No Connection.
No Connection.
Gate Drive.
Drain Feedback.
Gate Drive.
Drain Feedback.
Gate Drive.
Drain Feedback.
Gate Drive.
Drain Feedback.
No Connection.
No Connection.
Power Supply for Gate Drivers.
Power Supply. Logic and Low Power Device.
Fault Detection Voltage Threshold.
Ground. Power Return for VCC1. Includes Device Substrate.
*True no connect. PC board traces allowable.
** Unless masked out.
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NCV7512
24 23 22 21 20 19 18 17
GAT1
DRN1
N/C
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
STAB
VDD
SO
N/C
NCV7512
VCC2
VCC1
FLTREF
GND
SI
SCLK
CSB
FLTB
1
2
3
4
5
6
7
8
Figure 3. 32 Pin LQFP Pinout (Top View)
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NCV7512
MAXIMUM RATINGS (Voltages are with respect to device substrate.)
Rating
Value
−0.3 to 6.5
"0.3
Unit
V
DC Supply (V
, V
, V
)
CC1 CC2 DD
Difference Between V
and V
V
CC1
CC2
Difference Between GND (Substrate) and V
Output Voltage (GATx, STAB, FLTB, SO)
"0.3
V
SS
−0.3 to 6.5
−0.3 to 40
10
V
Drain Feedback Clamp Voltage (DRNx) (Note 1)
Drain Feedback Clamp Current (DRNx) (Note 1)
Input Voltage (ENAx, SCLK, SI, FLTREF, Inx)
V
mA
V
−0.3 to 6.5
−40 to 150
−65 to 150
260 peak
Junction Temperature, T
°C
°C
°C
J
Storage Temperature, T
STG
Peak Reflow Soldering Temperature: Lead−Free
60 to 150 seconds at 217°C (Note 2)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. An external series resistor must be connected between the MOSFET drain and the feedback input in the application. Total clamp power
dissipationis limited by the maximum junction temperature, the application environment temperature, and the package thermal resistances.
2. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D, and
ApplicationNote AND8003/D.
3. Values represent still air steady−state thermal performance on a 4 layer (42 x 42 x 1.5 mm) PCB with 1 oz. copper on an FR4 substrate, using
2
a minimum width signal trace pattern (384 mm trace area).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
V
CC1
V
CC2
Main Power Supply Voltage
4.75
5.25
Gate Drivers Power Supply Voltage
Serial Output Driver Power Supply Voltage
Logic Input High Voltage
V
− 0.3
V
+ 0.3
V
CC1
CC1
V
DD
3.0
2.0
0
V
V
V
CC1
V
IN
High
V
CC1
V
IN
Low
Logic Input Low Voltage
0.8
V
T
A
Ambient Still−Air Operating Temperature
−40
125
°C
ATTRIBUTES
Characteristic
Value
ESD Capability
Human Body Model
Machine Model
w " 2.0 kV
w " 200 V
Moisture Sensitivity (Note 2)
MSL3
Package Thermal Resistance (Note 3)
Junction–to–Ambient, R
86.0 °C/W
58.5 °C/W
q
JA
Junction–to–Pin, R
Y
JL
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NCV7512
ELECTRICAL CHARACTERISTICS (4.75 VvV
v5.25 V, V = V
, −40°CvT v125°C, unless otherwise specified.) (Note 4)
CCX J
CCX
DD
Characteristic
Conditions
Min
Typ
Max
Unit
V
CC1
Supply
Operating Current
V
= 5.25 V, V
= 1.0 V
,
mA
CC1
FLTREF
ENA = 0
–
–
−2.3
−2.5
5.0
5.0
X
ENA = ENA = V
1
2
CC1
V
DRNX
= 0 V, GAT drivers off
X
ENA = ENA = V ,
–
−2.0
5.0
1
2
CC1
GAT drivers on
X
Power−On Reset Threshold
Power−On Reset Hysteresis
V
CC1
Rising
3.65
4.20
4.60
–
V
V
−
0.150
0.385
Digital I/O
V
V
V
High
ENA , IN , SI, SCLK, CSB
2.0
–
–
–
0.8
500
–
V
V
IN
IN
IN
X
X
Low
ENA , IN , SI, SCLK, CSB
–
X
X
Hysteresis
ENA , IN , SI, SCLK, CSB
100
−25
–
330
−10
10
mV
mA
mA
kW
V
X
X
Input Pullup Current
Input Pulldown Current
Input Pulldown Resistance
SO Low Voltage
CSB V = 0 V
IN
ENA2, IN , SI, SCLK, V = V
25
X
IN
CC1
ENA1
100
–
150
0.11
200
0.25
–
V
DD
V
DD
= 3.3 V, I
= 5 mA
SINK
SO High Voltage
= 3.3 V, I
= 5 mA
V
− 0.25
V − 0.11
DD
V
SOURCE
DD
SO Output Resistance
SO Tri−State Leakage Current
STAB Low Voltage
Output High or Low
CSB = 3.3 V
–
−10
–
22
–
–
W
10
mA
V
STAB Active, I
= 1.25 mA
0.1
–
0.25
10
STAB
STAB Leakage Current
FLTB Low Voltage
V
STAB
= V
–
mA
V
CC1
FLTB Active, I
= 1.25 mA
–
0.1
–
0.25
10
FLTB
FLTB Leakage Current
V
FLTB
= V
–
mA
CC1
Fault Detection – GAT ON
X
FLTREF Input Current
V
= 0 V
−1.0
0
–
–
–
–
mA
V
FLTREF
FLTREF Input Linear Range
Guaranteed by Design
Guaranteed by Design
V
− 2.0
CC1
FLTREF Op−amp V
PSRR
30
–
dB
V
CC1
DRN Clamp Voltage
I
I
= 10 mA
27
–
32
33.6
–
37
X
DRNX
DRNX
= I
CL(MAX)
= 10 mA
DRN Shorted Load Threshold
GAT Output High, V
= 1.0 V
= 1.0 V
= 1.0 V
= 1.0 V
20
25
50
75
100
–
30
%
X
X
FLTREF
Register 2: R = 0, R = 0 or
V
V
V
V
1
0
FLTREF
R = 0, R = 0
4
3
GAT Output High, V
45
55
%
X
FLTREF
Register 2: R = 0, R = 1 or
1
0
FLTREF
R = 0, R = 1
4
3
GAT Output High, V
70
80
%
X
FLTREF
Register 2: R = 1, R = 0 or
1
0
FLTREF
R = 1, R = 0
4
3
GAT Output High, V
95
105
1.0
%
X
FLTREF
Register 2: R = 1, R = 1 or
1
0
FLTREF
R = 1, R = 1
4
3
DRN Input Leakage Current
V
CC1
= V
= V = 5.0 V, ENA = IN = 0 V,
−1.0
mA
X
CC2
DD
X
X
V
DRNX
= V
CL(MIN)
V
CC1
= V = V = 0 V, ENA = IN
CC2 DD X X
= 0 V, V
= V
CL(MIN)
DRNX
4. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100%
parametrically tested in production.
5. Guaranteed by design.
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NCV7512
ELECTRICAL CHARACTERISTICS (continued) (4.75 VvV
v5.25 V, V = V
, −40°CvT v125°C, unless otherwise
CCX J
CCX
DD
specified.) (Note 4)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
Fault Detection – GAT OFF
X
DRN Diagnostic Current
I
Short to GND Detection,
= 0.30 V
−27
−20
−10
mA
mA
X
SG
V
DRNX
CC1
I
Open Load Detection,
= 0.75 V
30
60
80
OL
V
DRNX
CC1
DRN Fault Threshold Voltage
V
Short to GND Detection
Open Load Detection
−
27
72
–
30
75
50
33
78
–
%V
X
SG
CC1
CC1
CC1
V
%V
%V
OL
DRN Off State Bias Voltage
V
CTR
X
Gate Driver Outputs
GAT Output Resistance
Output High or Low
1.0
−5.25
1.9
1.80
–
2.5
kW
X
GAT High Output Current
V
= 0 V
−1.9
5.25
mA
mA
ms
X
GATX
GATX
GAT Low Output Current
V
= V
–
X
CC2
Turn−On Propagation Delay
Turn−Off Propagation Delay
Output Rise Time
t
P(ON)
IN to GAT (Figure 4)
X
X
–
–
1.0
CSB to GAT (Figure 5)
X
t
ms
ms
IN to GAT (Figure 4)
P(OFF)
X
X
–
–
–
–
1.0
CSB to GAT (Figure 5)
X
t
R
20% to 80% of V
,
1.40
CC2
C
LOAD
= 400 pF
(Figure 4, Note 5)
80% to 20% of V
Output Fall Time
t
F
,
–
–
1.40
ms
CC2
C
LOAD
= 400 pF
(Figure 4, Note 5)
Fault Timers
Channel Fault Blanking Timer
t
V
= 5.0 V; IN rising to
30
90
45
60
ms
ms
BL(ON)
DRNX
X
FLTB falling (Figure 6)
t
V
DRNX
= 0 V; IN falling to
120
150
BL(OFF)
X
FLTB falling (Figure 6)
Channel Fault Filter Timer
t
t
Figure 7
7.0
7.5
30
–
12
10
17
12.5
50
ms
ms
ms
kHz
FF
Global Fault Refresh Timer
(Auto−retry Mode)
Register 2: Bit R = 0 or R = 0
FR
2
5
Register 2: Bit R = 1 or R = 1
40
2
5
Timer Clock
ENA1 = High
500
–
Serial Peripheral Interface (Figure 9) V
= 5.0 V, V = 3.3 V, F
= 4.0 MHz, C
= 200 pF
ccx
DD
SCLK
LOAD
SO Supply Voltage
V
DD
3.3 V Interface
5 V Interface
3.0
4.5
–
3.3
5.0
250
–
3.6
5.5
–
V
V
SCLK Clock Period
Maximum Input Capacitance
SCLK High Time
−
ns
pF
ns
ns
ns
Sl, SCLK (Note 5)
–
25
–
SCLK = 2.0 V to 2.0 V
SCLK = 0.8 V to 0.8 V
Sl = 0.8 V/2.0 V to
125
125
25
–
SCLK Low Time
–
–
Sl Setup Time
–
–
SCLK = 2.0 V (Note 5)
Sl Hold Time
SCLK = 2.0 V to
25
–
–
ns
Sl = 0.8 V/2.0 V (Note 5)
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NCV7512
ELECTRICAL CHARACTERISTICS (continued) (4.75 VvV
v5.25 V, V = V
, −40°CvT v125°C, unless otherwise
CCX J
CCX
DD
specified.) (Note 4)
Characteristic
Symbol
Conditions
Min
Typ
= 200 pF
Max
Unit
Serial Peripheral Interface (continued) (Figure 9) V
= 5.0 V, V = 3.3 V, F
= 4.0 MHz, C
ccx
DD
SCLK
LOAD
SO Rise Time
(20% V to 80% V
)
–
25
50
50
–
ns
ns
ns
ns
ns
ns
ms
SO
DD
C
LOAD
= 200 pF (Note 5)
SO Fall Time
(80% V to 20% V
)
–
60
75
–
–
SO
DD
C
LOAD
= 200 pF (Note 5)
CSB Setup Time
CSB Hold Time
CSB to SO Time
SO Delay Time
Transfer Delay Time
CSB = 0.8 V to SCLK = 2.0 V
(Note 5)
–
SCLK = 0.8 V to CSB = 2.0 V
(Note 5)
–
–
CSB = 0.8 V to SO Data Valid
(Note 5)
65
65
–
125
125
–
SCLK = 0.8 V to SO Data Valid
(Note 5)
–
CSB Rising Edge to Next
Falling Edge (Note 5)
1.0
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NCV7512
Open
Load
Threshold
DRNx
Shorted
Load
Threshold
50%
INX
tP(OFF)
tR
tF
80%
20%
50%
GATX
tP(ON)
Figure 4. Gate Driver Timing Diagram – Parallel Input
50%
CSB
GX
tP(OFF)
50%
GATX
tP(ON)
Figure 5. Gate Driver Timing Diagram – Serial Input
DRNX
50%
INX
tBL(ON)
tBL(OFF)
50%
50%
FLTB
Figure 6. Blanking Timing Diagram
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NCV7512
OPEN LOAD
THRESHOLD
SHORTED
LOAD
THRESHOLD
DRNX
INX
tFF
tFF
50%
50%
FLTB
Figure 7. Filter Timing Diagram
GATX
tBL(ON)
tFR
tFF
tFR
tBL(ON)
tFR
DRNX
INX
SHORTED LOAD THRESHOLD (FLTREF)
Figure 8. Fault Refresh Timing Diagram
CSB
SETUP
TRANSFER
DELAY
CSB
SI
SETUP
CSB
HOLD
SCLK
1
16
SI
HOLD
BITS 14...1
SI
MSB IN
LSB IN
SO
DELAY
SO
RISE,FALL
CSB to
SO VALID
80% VDD
20% VDD
SEE
NOTE
BITS 14...1
SO
LSB OUT
MSB OUT
Note: Not defined but usually MSB of data just received.
Figure 9. SPI Timing Diagram
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NCV7512
DETAILED OPERATING DESCRIPTION
General
The active−low CSB chip select bar input has a pull−up
current source. The SI and SCLK inputs have pull−down
current sources. The recommended idle state for SCLK is
low. The tri−state SO line driver can operate in 3.3V or 5V
systems. Power (3.3V or 5V) to the SO driver is applied via
The NCV7512 is a four channel general−purpose
low−side pre−driver for controlling and protecting N−type
logic level MOSFETs. While specifically designed for
driving MOSFETs with resistive, inductive or lamp loads
in automotive applications, the device is also suitable for
industrial and commercial applications. Programmable
fault detection and protection modes allow the NCV7512
to accommodate a wide range of external MOSFETs and
loads providing the user with flexible application solutions.
Separate power supply pins are provided for low and high
current paths to improve analog accuracy and digital signal
integrity. ON Semiconductor’s SmartDiscretest such as
the NID9N05CL, clamp MOSFETs, and are recommended
when driving unclamped inductive loads.
the device’s V and V pins.
DD
SS
The NCV7512 employs frame error detection. Integer
multiples of 16 SCLK cycles during each CSB
high−low−high cycle (valid communication frame) is
required for the device to recognize a command. A frame
error does not affect error flag reporting.
The CSB input controls SPI data transfer and initializes
the selected device’s frame error and fault reporting logic.
The host initiates communication when a selected
device’s CSB pin goes low. The master’s SCLK signal
shifts Output (fault) data MSB first from the SO pin while
input (command) data is received MSB first at the SI pin
(Figure 10).
Fault data changes on the falling edge of SCLK and is
guaranteed valid before the next rising edge of SCLK.
Command data received must be valid before the rising
edge of SCLK.
When CSB goes low, frame error detection is initialized,
latched fault data is transferred to the SPI, and the FLTB
flag is disabled and reset if previously set. Faults while CSB
is low are ignored, but will be captured if still present after
CSB goes high.
If a valid frame has been received when CSB goes high,
the last multiple of 16 bits received is decoded into
command data, and FLTB is re−enabled. Latched
(previous) fault data is cleared and current fault data is
captured. The FLTB flag will be set if a fault is detected.
If a frame error is detected when CSB goes high, new
command data is ignored, and previous fault data remains
latched and available for retrieval during the next valid
frame. The FLTB flag will be set if a fault is detected.
Frame errors are ignored. They are not reported by FLTB.
Power Up/Down Control
The NCV7512’s power−up/down control prevents
spurious output operation by monitoring the V
supply voltage. An internal Power−On Reset (POR) circuit
power
CC1
holds all GAT outputs low until sufficient voltage is
X
available to allow proper control of the device. All internal
registers are initialized to their default states, fault data is
cleared, and the open−drain fault (FLTB) and status flags
(STAB) are disabled during a POR event.
When V
exceeds the POR threshold, the device is
CC1
ready to accept input data, outputs are allowed to turn on,
and fault and status reporting are accurate. When V
falls below the POR threshold during power down, fault
flags are reset and reporting is disabled. All GAT outputs
CC1
X
are held low. Operation below V =0.7V is not specified.
CC1
SPI Communication
The NCV7512 is a 16−bit SPI slave device. SPI
communication between the host and the NCV7512 may
either be directly addressed through CSB or daisy−chained
through other devices using a compatible SPI protocol.
CSB
MSB
LSB
4 − 13
B12 − B3
B12 − B3
1
2
3
14
15
16
SCLK
SI
X
B15
B14
B14
B13
B13
B2
B2
B1
B1
B0
B0
X
Z
SO
UKN
B15
Z
Note: X=Don’t Care, Z=Tri−State, UKN=Unknown Data
Figure 10. SPI Communications Frame Format
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NCV7512
Serial Data and Register Structure
The 16−bit data received (SI) is decoded into a 4−bit
address and a 6−bit data word (Figure 11). The upper four
bits, beginning with the received MSB, are fully decoded
to address one of four programmable registers and the
lower six bits are decoded into data for the addressed
register. Bit B15 must always be set to zero. Valid register
addresses are shown in Table 1.
The 16−bit data sent (SO) by the NCV7512 is encoded
8−bit fault information. The upper 6 bits are forced to zero
and lower 2 bits are forced to zero (Figure 12).
REGISTER SELECT
COMMAND INPUT DATA
MSB
LSB
B15
0
B14
A2
B13
A1
B12
A0
B11
X
B10
X
B9
X
B8
X
B7
X
B6
X
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
Figure 11. SPI Input Data
MSB
B15
LSB
B0
B14
0
B13
0
B12
0
B11
0
B10
0
B9
B8
B7
B6
B5
B4
B3
B2
B1
0
0
CH4
CH3
CH2
CH1
0
CHANNEL FAULT OUTPUT DATA
Figure 12. SPI Output Data
Table 1. Register Address Definitions
FUNCTION TABLE
ADDRESS
6−BIT INPUT DATA
D3 D2
A2
0
A1
0
A0
0
D5
D4
D1
D0
Gate Select
0
0
1
Disable Mode
Refresh & Reference
Mask
0
1
0
0
1
1
1
0
0
Null
OUTPUT DATA
8−bit Fault Data
X
X
X
Gate Select – Register 0
Each GAT output is turned on/off by programming its
Disable Mode – Register 1
The disable mode for shorted load faults is controlled by
each channel’s respective MX bit (Table 3). Setting a bit to
1 causes the selected GATX output to latch−off when a fault
is detected. Setting a bit to 0 causes the selected GATX
output to auto−retry when a fault is detected.
At power−up, each bit is set to 0 (all outputs in auto−retry
mode.)
X
respective G bit (Table 2). Setting a bit to 1 causes the
X
selected GAT output to drive its external MOSFET’s gate
X
to V
(ON.) Setting a bit to 0 causes the selected GAT
CC2
X
output to drive its external MOSFET’s gate to V (OFF.)
SS
Note that the actual state of the output depends on POR,
ENA and shorted load fault states as later defined by
X
Equation 1. At power−up, each bit is set to 0 (all outputs OFF.)
Table 3. Disable Mode Register
Table 2. Gate Select Register
A
2
A
1
A
0
D
5
D
4
D
3
D
2
D
1
D
0
A
2
A
1
A
0
D
5
D
4
D
3
D
2
D
1
D
0
0
0
1
M
4
M
3
M
2
M
1
0
0
0
G
G
G
G
1
4
3
2
0 = AUTO−RETRY
1 = LATCH OFF
0 = GAT OFF
X
1 = GAT ON
X
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NCV7512
Refresh and Reference – Register 2
and the fault reference for channels 2−1 is programmed by
RX bits 2−1 (Table 4).
At power−up, each bit is set to 0 (VFLT = 25%
VFLTREF, tFR = 10 ms.)
Refresh time (auto−retry mode) and shorted load fault
detection references are programmable in two groups of
two channels. Refresh time and the fault reference for
channels 4−3 is programmed by RX bits 4−3. Refresh time
Table 4. Refresh and Reference Register
A2
0
A1
1
A0
0
D5
R5
D4
D3
R3
D2
R2
D1
D0
R0
R4
R1
CHANNELS 4−3
CHANNELS 2−1
25% VFLTREF
50% VFLTREF
75% VFLTREF
VFLTREF
X
X
X
X
X
X
0
0
0
0
1
X
X
X
X
0
0
0
0
1
1
0
1
0
1
1
1
1
tFR = 10 ms
tFR = 40 ms
tFR = 10 ms
tFR = 40 ms
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
1
Flag / STAB Mask – Register 3
Table 6. Null Register
Using the mask feature, allows the user to disable the
FLTB and STAB flag reporting on a channel by channel
basis. No allowance is made to segregate control of
masking Flag and Status reporting.
A
A
A
D
D
D
D
D
D
0
2
1
0
5
4
3
2
1
1
X
X
X
X
X
X
X
X
Gate Driver Control and Enable
Each GAT output may be turned on by either its
respective parallel IN input or SPI control of the internal
The drain feedback from each channel’s DRN input is
X
X
combined with the channel’s K mask bit (Table 5.) When
X
X
K =1, a channel’s mask is cleared and its feedback to the
X
G
X
(Gate Select) register bit.
FLTB and STAB flags is enabled.
At power−up, each bit is set to 0 (all masks set.)
The device’s common ENA enable inputs can be used
X
to implement global control functions, such as system
reset, over−voltage or input override by a watchdog
controller. Each parallel input (Inx) and the ENA2 input
have individual internal pull−down current sources. The
ENA1 input has an internal pull−down resistor. Unused
parallel inputs should be connected to GND and unused
Table 5. Flag Mask Register
A
2
A
1
A
0
D
5
D
4
D
3
D
2
D
1
D
0
0
1
1
K
4
K
3
K
2
K
1
0 = MASK SET
1 = MASK CLEAR
enable inputs should be connected to V
.
CC1
Input signal frequency of PWM Inx signals should be
kept less than 2 kHz.
The STAB flag is influenced when a mask bit changes
CLR→SET after one valid SPI frame. FLTB is influenced
after two valid SPI frames. This is correct behavior for
FLTB since, while a fault persists, the FLTB will be set
when CSB goes LO→HI at the end of a SPI frame. The
mask instruction is decoded after CSB goes LO→HI so
FLTB will only reflect the mask bit change after the next
SPI frame. Both FLTB and STAB require only one valid
SPI frame when a mask bit changes SET→CLR.
When ENA1 is brought low, all GAT outputs, the timer
X
clock, and the flags are disabled. The fault and gate
registers are cleared and the flags are reset. New serial G
X
data is ignored while ENA1 is low but other registers can
be programmed. ENA1 provides global on/off control and
provides a soft reset.
ENA2 disables all GAT outputs and diagnostic circuitry
X
when brought low. SPI control and Parallel (Inx) inputs are
still recognized when ENA2 is low. ENA2 provides local
on/off control and can be used to disable the GAT outputs
Null Register – Register 4
X
during initialization of the NCV7512. ENA2 can also be
used to PWM all outputs simultaneously at low
frequencies.
The null register (Table 6) provides a way to retrieve
fault information without actively changing an input
command (i.e. modifying D ). Fault information is always
X
returned when any register is addressed.
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NCV7512
When both the ENA1 and ENA2 inputs are high, the
Diagnostics are disabled when ENA1 or ENA2 is low.
When both ENA1 and ENA2 are high, diagnostics are
enabled.
Shorted load faults are detected when a driver is on. Open
load or short to GND faults are detected when a driver is off.
On−state faults will initiate MOSFET protection
behavior. The FLTB flag will be set and the respective
channel’s DX fault bit is latched.
outputs will reflect the current parallel and serial input
states. Turning on a channel is an OR’d function of the
parallel and serial inputs.
The IN input state and the G register bit data are
X
X
logically combined with the internal (active low)
power−on reset signal (POR), the ENA input states, and
X
the shorted load state (SHRT ) to control the
X
corresponding GAT output such that:
Off−state faults will simply set the FLTB flag and the
channel’s DX bits.
X
GAT + POR · ENA1 · ENA2 · SHRT · (IN ) G )
X
x
x
x
Fault types are encoded in a 2−bit per channel format.
Fault information for all channels is simultaneously
retrieved by a SPI read (Figure 11). Table 8 shows the
fault−encoding scheme for channel 0. The remaining
channels are identically encoded.
(eq. 1)
The GAT state truth table is given in Table 7.
X
Table 7. Gate Driver Truth Table
POR
0
ENA1
ENA2
SHRT
IN
G
GAT
L
X
X
X
X
X
0
X
X
X
X
X
1
X
X
X
X
0
X
Table 8. Fault Data Encoding
1
0
X
X
L
CHANNEL 0
1
0
1
0
L
D
1
D
0
STATUS
1
1
X
L
0
0
NO FAULT
1
1
1
0
L
0
1
1
1
0
1
OPEN LOAD
SHORT TO GND
SHORTED LOAD
1
1
1
1
1
X
H
H
L
1
1
1
1
X
X
X
X
0
1
1
1
1
0
X
1
1→0
1
1
X
X
X
→0
→L
→L
Fault Blanking and Fault Filter Timers
1
1→0
0→1
G
G
X
X
Fault Blanking timers are used to allow drain feedback
to stabilize after a channel is commanded to change states.
Fault Filter timers are used to suppress glitches while a
channel is in a stable state.
1
1
→G
X
Gate Drivers
Each channels non−inverting GAT drivers are resistive
X
A turn−on blanking timer is started when a channel is
switches (1.80 kW typ.) to V
and V . On−chip
CC2
SS
commanded on. Drain feedback is sampled after t
.
BL(ON)
matching of drivers insures equivalent channel capability.
Load current switching matching is more dependent on the
characteristics of the external MOSFET and load.
Figure 12 shows the gate driver block diagram.
A turn−off blanking timer is started when a channel is
commanded off. Drain feedback is sampled after t
.
BL(OFF)
Blanking timers for all channels are started when both
ENA1 and ENA2 go high or when either ENA goes high
X
while the other is high.
A filter timer is started when a channel is in a stable state
and a fault detection threshold associated with that state has
been crossed. Drain feedback is sampled after t .
Each channel has independent blanking and filter timers.
FILTER
TIMER
DX0
ENCODING
LOGIC
FAULT
DETECTION
50
DX1
DRNX
GATX
BLANKING
TIMER
FF
VSS
S
tFR
R | R5
MX
LATCH OFF /
2
AUTO RE−TRY
_
R
SHRT
X
VCC2
The parameters for the t
identical for all channels.
, t
, and t times are
BL(ON) BL(OFF) FF
EN
1800
INX
GX
DRIVER
VSS
ENA1
ENA2
POR
Shorted Load Detection
An external reference voltage (applied to the FLTREF
input) serves as a common reference for all channels
(Figure 13) in detecting shorted load conditions. The
FLTREF voltage must be within the range of 0 to
Figure 13. Gate Driver Channel
Fault Diagnostics and Behavior
V
CC1
−2.0V. The part is designed to be used with a voltage
Each channel has independent fault diagnostics and
employs both blanking and filter timers to suppress false
faults. An external MOSFET is monitored for fault
conditions by connecting its drain to a channel’s DRNX
feedback input through an external series resistor.
divider between V
Shorted load detection thresholds can be programmed
via the SPI port in four 25% increments that are ratiometric
and GND.
CC1
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15
NCV7512
to the applied FLTREF voltage. Separate thresholds can be
selected for channels 1−2 and for channels 3−4 (Table 4).
A shorted load fault is detected when a channel’s DRN
feedback is greater than its programmed fault reference
(after the turn−on blanking or the fault filter has timed out).
Fault Recovery Refresh Time
Refresh time for shorted load faults is SPI programmable
to one of two values (10ms or 40ms) for channels 1−2
(register bit R2) and for channels 3−4 (register bit R5) via
the Refresh and Reference register (Table 4).
X
A global refresh timer is used for auto−retry timing. The
first faulted channel triggers the timer and the full refresh
period is guaranteed for that channel. An additional faulted
channel may initially retry immediately after its turn−on
blanking time, but subsequent retries will have the full
refresh time period.
If all channels in a group (e.g. channels 1−2) become
faulted, they will become synchronized to the selected
refresh period for that group. If all channels become faulted
and are set for the same refresh time, all will become
synchronized to the refresh period.
VCC1
CHANNELS 1−2
FLTREF
4
3
2
1
VCC1
2 X 4
DECODER
0 − 3V
RX1
+
100%
OA
RX2
R
R
R
R
−
R1
R2
75%
50%
25%
KELVIN
REGISTER 2
BITS
R4
R3
2 X 4
DECODER
4
3
2
1
CHANNELS 3−4
Open Load and Short to GND Detection
Figure 14. Shorted Load Reference Generator
A
window comparator with fixed references
proportional to V along with a pair of bias currents is
used to detect open load or short to GND faults when a
CC1
Shorted Load Fault Recovery
Each channel is SPI programmable for shorted load
channel is off. Each channel’s DRN feedback is compared
X
response. The M bits in the device’s Disable Mode
X
to the references after either the turn−off blanking or the
register (Table 3) control the channels to latch−off during
a fault or auto−retry.
When latch−off mode is selected the corresponding
filter has timed out. Figure 14 shows the DRN fault
X
detection zones. Note, the diagnostics are disabled and the
bias currents are turned off when ENA is low.
X
GAT output is turned off upon detection of a fault. Fault
X
No fault is detected if the feedback voltage at DRN is
X
recovery is initiated by toggling (ON→OFF→ON) the
greater than the V open load reference. If the feedback
OL
channel’s respective IN parallel input, serial G bit, or
X
X
is less than the V short to GND reference, a short to GND
SG
ENA2.
When auto−retry mode is selected (default mode) the
corresponding GAT output is turned off for the duration
fault is detected. If the feedback is less than V
and
OL
greater than V , an open load fault is detected.
SG
X
of the programmed fault refresh time (t ) upon detection
FR
IDRNX
of a fault. The output is automatically turned back on (if
still commanded on) when the refresh time ends. The
Short to
GND
Open
Load
No
Fault
channel’s DRN feedback is re−sampled after the turn−on
X
IOL
blanking time. The output will automatically turn off if a
fault is again detected. This behavior will continue for as
long as the channel is commanded on and the fault persists.
In either mode, a fault may exist at turn−on or may occur
some time afterward. To be detected, the fault must exist
longer than either the channel fault blanking timer
0
−I
SG
(t
) at turn−on or longer than the channel fault filter
BL(ON)
timer (t )some time after turn−on. The length of time that
a MOSFET stays on during a shorted load fault is thus
FF
VDRNX
VSG
VCTR
VOL
limited to either t
In auto−retry mode, a persistent shorted load fault will
result in a low duty cycle (t /t ) for the
or t .
BL(ON)
FF
Figure 15. DRNX Bias and Fault Detection Zones
t
FD
BL(ON) FR
[
affected channel and help prevent thermal failure of the
Figure 16 shows the simplified detection circuitry. Bias
channel’s MOSFET.
currents I and I are applied to a bridge along with bias
SG
OL
voltage V
(50% V
typ.).
CTR
CC1
CAUTION − CONTINUOUS INPUT TOGGLING VIA
IN , G or ENA2 WILL OVERRIDE EITHER DISABLE
X
X
MODE. Care should be taken to service a shorted load fault
quickly.
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NCV7512
the dynamic behavior of the short to GND/ open load
VCC1
diagnostic are provided in the Applications Information
section of this data sheet.
ISG
(20 uA)
VLOAD
RLOAD
Status Flag (STAB)
The open−drain active−low status flag output reports the
state of the channels DRN feedback. Feedback from all
channels is logically OR’d to the flag (Figure 16). STAB
goes low when any DRNx is low. STAB does not report
masked channels. The STAB outputs from several devices
can be wire−OR’d to a common pull−up resistor connected
VOL
−
D3
D1
CMP1
A
B
1600
DRNX
RDX
+
50
X
VX
DZ1
+
CMP2
−
RSG
(VCL
)
D4
D2
VSG
+VOS
+
_
VCTR
I
OL (60 uA)
to the controller’s 3.3 or 5 V V supply.
DD
When ENA1 is high, the drain feedback from a channel’s
V
SG
= 30% V
V
= 75% V
cc1, OL cc1
DRN input is compared to the V reference and reported
X
OL
without regard to ENA2 or the commanded state of the
channel’s driver. The status flag is reset and disabled when
ENA1 is low or when all mask bits are set. See Table 9 for
additional details.
Figure 16. Short to GND/Open−Load Detection
Normal Operation − When a channel is off and V
LOAD
and R
DRNX
are present, R
is absent, and
LOAD
SG (short to ground)
is supplied
OL (open load)
The status flag is set (low) when the feedback voltage is
V
>> V , bias current I
CTR
less than V , and the channel’s mask bit (Table 5) is
OL
from V
to ground through external resistors R
LOAD
LOAD
cleared. The flag is reset (hi−Z) when the feedback voltage
and R , and through the internal 1650W resistance and
DX
is greater than V , and the channel’s mask bit is cleared.
OL
bridge diode D2. Bias current I is supplied from V
to
SG
CC1
V
through D3. No fault is detected if the feedback
CTR
OTHER
CHANNELS
voltage (V
minus the total voltage drop caused by I
LOAD
SG
STAB
KX
and the resistance in the path) on CMP1 is greater than V
(and the voltage on CMP2 is greater than V [it will be
since RSG is absent]).
OL
VOL
D
−
SG
CMP1
Q
A
DRNX
ENA1
+
500 kHz
CLR
Open Fault − When either V
or R
and R
LOAD, SG
LOAD
POR
are absent, the bridge will self−bias so that the voltage at
DRN will settle to about V . An open load fault will
X
CTR
be detected since the feedback voltage to CMP1 and CMP2
is between V and V
Figure 17. STAB Flag Logic
.
OL
SG
Short to GND − Detection can tolerate an offset (V
)
OS
Fault Flag (FLTB)
between the NCV7512’s GND and the short. The value of
the functional offset is determined by the RDX resistor
value and the user defined acceptable threshold shift.
The open−drain active−low fault flag output can be used
to provide immediate fault notification to a host controller.
Fault detection from all channels is logically ORed to the
flag (Figure 17). The FLTB outputs from several devices
can be wire−ORed to a common pull−up resistor connected
to the controller’s 3.3 or 5 V V supply.
The flag is set (low) when a channel detects any fault, the
channel’s mask bit (Table 5) is cleared, and both ENA and
When R is present and V
<< V , bias current I
CTR SG
SG
DRNX
is supplied from V
to V through D1, the internal
CC1
OS
1650W, and the external R
and R resistances. Bias
SG
DX
DD
current I is supplied from V
to ground through D4.
OL
CTR
A “weak” short to GND can be detected when either
or R is absent and the feedback (V plus the
X
V
LOAD
LOAD
OS
CSB are high. The Fault Flag is reset (hi−Z) and disabled
when either ENA1 or CSB is low. See Table 9 for additional
details.
total voltage rise caused by I and the resistance in the
OL
path) is less than V . The NCV7512 does not distinguish
OL
between “weak” shorts and “hard” shorts.
When V
between V
and R
are present, a voltage divider
LOAD
LOAD
OTHER
CHANNELS
and V is formed by R
and R . A
LOAD SG
LOAD
OS
KX
FLTB
“hard” short to GND may be detected in this case
depending on the ratio of R and R and the values of
FAULTX
S
R
ENA2
ENA1
LOAD
SG
Q
R
, V
DX
, and V
.
LOAD
OS
Note that the comparators see a voltage drop or rise due
only to the 50W internal resistance and the bias currents.
This produces a small difference in the comparison to the
POR
(RESET DOMINANT)
CSB
actual feedback voltage at the DRN input.
X
Figure 18. FLTB Flag Logic
Several equations for choosing R and for predicting
DX
open load or short to GND resistances, and a discussion of
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17
NCV7512
Fault Detection and Capture
can be captured and identified, and that the device cannot
be inadvertently re−programmed by a communication
error.
The NCV7512 latches a fault when it is detected, and
frame error detection will not allow any register to accept
data if an invalid frame occurred.
When a fault has been detected, the FLTB flag is set and
fault data is latched into a channel’s fault latch. The latch
captures and holds the fault data and ignores subsequent
fault data for that channel until a valid SPI frame occurs.
Fault data from all channels is transferred from each
channel’s fault latch into the SPI shift register and the FLTB
flag is reset when CSB goes low at the start of the SPI
frame. Fault latches are cleared and re−armed when CSB
goes high at the end of the SPI frame only if a valid frame
has occurred; otherwise the latches retain the detected fault
data until a valid frame occurs. The FLTB flag will be set
if a fault is still present.
Each channel of the NCV7512 is capable of detecting
shorted load faults when the channel is on, and short to
ground or open load faults when the channel is off.
Each fault type is uniquely encoded into two−bit per
channel fault data. A drain feedback input for each channel
compares the voltage at the drain of the channel’s external
MOSFET to several internal reference voltages. Separate
detection references are used to distinguish the three fault
types and blanking and filter timers are used respectively
to allow for output state transition settling and for glitch
suppression.
Fault diagnostics are disabled when either enable input
is low. When both enable inputs are high, each channel’s
drain feedback input is continuously compared to
references appropriate to the channel’s input state to detect
faults, but the comparison result is only latched at the end
of either a blanking or filter timer event.
Blanking timers for all channels are triggered when
either ENx input changes state from low to high while the
other enable input is high, or when both enable inputs go
high simultaneously. A single channel’s blanking timer is
triggered when its input state changes. If the comparison of
the feedback to a reference indicates an abnormal condition
when the blanking time ends, a fault has been detected and
the fault data is latched into the channel’s fault latch.
A channel’s filter timer is triggered when its drain
feedback comparison state changes. If the change indicates
an abnormal condition when the filter time ends, a fault has
been detected and the fault data is latched into the channel’s
fault latch.
Fault latches for all channels and the FLTB flag can also
be cleared and re−armed by toggling ENA1 H−L−H. A full
I/O truth table is given in Table 9.
Fault Data Readback Examples
Several examples are shown to illustrate fault detection,
capture and SPI read−back of fault data for one channel. A
normal SPI frame returns 16 bits of data but only the two
bits of serial data for the single channel are shown for
clarity.
The examples assume:
The NCV7512 is configured as in Figure 2;
Both enable inputs are high;
The channel’s flag mask bit is cleared ;
Disable mode is set to auto−retry;
The parallel input commands the channel;
SPI frame is always valid.
Thus, a state change of the inputs (ENA , IN or G ) or
X
X
X
a state change of an individual channel’s feedback (DRN )
X
comparison must occur for a timer to be triggered and a
detected fault to be captured.
Fault Capture, SPI Communication, and SPI
Frame Error Detection
The fault capture and frame error detection strategies of
the NCV7512 combine to ensure that intermittent faults
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18
NCV7512
Shorted Load Detected
Refer to Figure 18. The channel is commanded on when
IN goes high. GAT goes high and the timers are started.
A SPI frame sent soon after “B” returns data indicating
“shorted load”.
The FLTB flag is reset when CSB goes low (“F”). At “C”
when CSB goes high at the end of the frame, the fault latch
X
X
At “A”, the STAB flag is set as the DRN feedback falls
X
through the V threshold.
is cleared and re−armed. Since IN and the DRN
OL
X X
A SPI frame sent soon after the IN command returns
feedback are unchanged, FLTB and the fault latch are set
X
data indicating “no fault”.
and the fault is re−captured (“G”).
The blanking time ends, and the filter timer is triggered
When the auto−retry timer ends at “D”, GAT goes high
X
as DRN rises (a shorted load fault occurs) through the
and the blanking and filter timers are started. Since IN and
X
X
FLTREF threshold. The STAB flag is reset as DRN passes
DRN are unchanged, GAT goes low when the blanking
X
X X
through the V threshold. DRN is nearly at V when
the filter time ends at “B”. A shorted load fault is detected
time ends at “E” and the auto−retry timer is started.
Read−back data continues to indicate a “shorted load” and
the FLTB flag continues to be set while the fault persists.
OL
X
LOAD
and captured by the fault latch, GAT goes low, the FLTB
X
flag is set, and the auto−retry timer is started.
1
INx
0
FAULT DETECTED
1
0
GATx
VLOAD
VOL
FLTREF
0
1
0
A
STAB
D
E
B
1
0
1
0
1
0
1
0
1
0
1
0
BLANK
TIMER
tFR
tFR
tBL(ON)
tBL(ON)
INTERNAL
SIGNALS
C
FILTER
TIMER
tFF
FAULT
LATCH
00
00
11
11
11
11
11
CSB
SO
11
11
11
11
11
G
FLTB
F
Data bits in the fault latch (00 & 11) represent single channel encoded fault data as described in Table 8.
Figure 19. Shorted Load Detected
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19
NCV7512
Shorted Load Recovery
Figure 19 is a continuation of Figure 18. IN is high
latched data has not yet been read, the data remains
unchanged.
X
when the auto−retry timer ends. GAT goes high and the
blanking and filter timers are started. The fault is removed
The SPI frame sent after the blanking time ends returns
a “shorted load” fault because the previous frame occurred
during the blanking time.
X
before the blanking timer ends, and DRN starts to fall. As
X
DRN passes through the V threshold at “A”, the STAB
Since the channel’s fault bits indicate “no fault”, FLTB
is reset and the fault latch is updated at “C” when CSB goes
high.
X
OL
flag is set. DRN continues to fall and settles below the
X
FLTREF threshold.
A SPI frame is sent during the blanking time and returns
data indicating a “shorted load” fault.
If another SPI frame is sent before “D”, the returned data
will indicate “no fault”.
Although the fault is removed, updates to the fault
latches are suppressed while a blanking or filter timer is
active. The same fault is captured again and FLTB is set
when CSB goes high. At “B” the blanking time ends and the
channel’s fault bits will indicate “no fault” but because the
The channel is commanded off at “D”. GAT goes low
X
and the timers are started. DRN starts to rise and the STAB
X
flag is reset as DRN passes through the V threshold.
X
OL
The SPI frame sent at “E” returns data indicating “no
fault”.
1
INx
0
D
1
GATx
0
FAULT REMOVED
VLOAD
A
VOL
FLTREF
0
1
STAB
0
B
1
0
1
0
1
0
1
0
1
0
1
0
BLANK
TIMER
tFR
tBL(OFF)
tBL(ON)
INTERNAL
SIGNALS
FILTER
TIMER
tFF
tFF
FAULT
LATCH
11
11
11
00
CSB
SO
C
E
11
11
11
00
FLTB
Data bits in the fault latch (00 & 11) represent single channel encoded fault data as described in Table 8.
Figure 20. Shorted Load Recovery
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20
NCV7512
Short to GND/Open Load
Figure 20 illustrates turn−off with an open or high
resistance load when some capacitance is present at DRN .
A SPI frame sent shortly after “B” returns data indicating
“short to GND” and the fault latch is updated at “C” when
CSB goes high.
X
In the case of an open load, DRN rises and settles to V
The next three SPI frames sent after “C” return data
indicating an “open load”.
X
CTR
(shown as the solid DRNx waveform). In the case of a high
resistance load, DRN may continue to rise and may
The STAB flag is reset at “D” as DRN passes through
X
X
eventually settle to V
.
the V threshold. Note that the filter timer is not triggered
LOAD
OL
Timing diagram description: The channel is commanded
as DRN passes from a fault state to a good state. The
X
off. GAT goes low and the timers are started. DRN starts
channel’s fault bits will indicate “no fault” but because the
latched data has not yet been read, the data remains
unchanged.
The fault latch is updated at “E” when CSB goes high and
the FLTB flag remains reset.
X
X
to rise and is below the V threshold when the blanking
SG
time ends at “A”. A short to GND fault is detected and
captured by the fault latch, and the FLTB flag is set.
DRN continues to rise and as it passes through the V
X
SG
threshold at “B”, the filter timer is triggered. At the end of
the filter time, the channel’s fault bits will indicate an
“open load” but because the latched data has not yet been
read, the data remains unchanged.
The next SPI frame sent returns data indicating “no
fault”.
1
INx
0
1
GATx
0
VLOAD
VOL
VCTR
VSG
0
D
1
A
B
C
STAB
0
1
0
1
0
1
0
1
0
1
0
1
0
BLANK
TIMER
tBL(OFF)
tFF
INTERNAL
SIGNALS
E
FILTER
TIMER
tFF
FAULT
LATCH
00
10
01
01
01
00
CSB
SO
00
10
01
01
01
00
FLTB
Data bits in the fault latch (00, 01 & 10) represent single channel encoded fault data as described in Table 8.
Figure 21. Short to GND/Open Load
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21
NCV7512
Table 9. I/O Truth Table
POR ENA1 ENA2 CSB
Inputs
Outputs*
K
IN
G
DRN
X
GAT
FLTB
→Z
Z
STAB
→Z
Z
D D
X1 X0
COMMENT
POR RESET
ENA1
X
→0
X
X
X
X
X
0
1
1
1
1
1
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
→0
→L
L
→00
X
X
00
1
0
K
X
K
X
K
X
G
X
L
FLTB
→Z
FLTB
Z
STAB
→Z
STAB
Z
D D
X1 X0
ENA2
X
1→0
1
1
→0
X
→L
→L
L
→00
ENA1 RESET
ENA2 DISABLE
FLAGS MASKED
1→0
X
G
X
D D
X1 X0
X
1
0
X
X
−
1
1
1
1
1
1
1
1
0
0
0
0
X
X
X
X
1
X
X
X
X
X
X
X
X
> V
< V
< V
< V
L
L
L
L
−
−
−
−
Z
−
−
−
−
STAB RESET
STAB SET
OL
OL
OL
OL
1
L
1→0
0→1
L→Z
Z→L
STAB RESET
STAB SET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
> V
L
L
L
L
L
L
L
L
L
L
L
Z
L
Z
L
00
01
01
01
01
01
10
10
10
10
10
FLAGS RESET
FLAGS SET
STAB RESET
STAB SET
OL
V
V
V
V
V
<V<V
SG
<V<V
SG
<V<V
SG
<V<V
SG
<V<V
SG
OL
OL
OL
OL
OL
X
1→0
0→1
1
L
L→Z
X
L
1→0
0→1
1
L→Z
Z→L
L
L
L
FLTB RESET
FLTB SET
1
1
< V
L
FLAGS SET
STAB RESET
STAB SET
SG
SG
SG
SG
SG
X
1→0
0→1
1
< V
L
L→Z
Z→L
L
X
< V
< V
< V
L
1→0
0→1
L→Z
Z→L
FLTB RESET
FLTB SET
1
L
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1
1
1
1
X
X
X
X
X
X
X
1
< V
H
L
L
L
L
L
L
H
L
L
L
L
L
L
Z
L
00
11
11
11
11
11
11
00
11
11
11
11
11
11
STAB SET
FLTREF
1
1→0
0→1
1
V
V
V
V
V
<V<V
<V<V
<V<V
<V<V
<V<V
L
L
L
L→Z
Z→L
L
FLAGS SET
STAB RESET
STAB SET
FLTREF
FLTREF
FLTREF
FLTREF
FLTREF
OL
OL
OL
OL
OL
X
1
X
1
L
1→0
0→1
1
1
L→Z
Z→L
L
FLTB RESET
FLTB SET
1
1
L
1
1
> V
Z
STAB RESET
STAB SET
OL
FLTREF
X
1
X
X
X
X
X
X
X
< V
Z
L
1
1
1
V
V
V
V
V
<V<V
<V<V
<V<V
<V<V
<V<V
L
L
FLAGS SET
STAB RESET
STAB SET
FLTREF
FLTREF
FLTREF
FLTREF
FLTREF
OL
OL
OL
OL
OL
X
1→0
0→1
1
1
L
L→Z
Z→L
L
X
1
L
1→0
0→1
1
1
L→Z
Z→L
L
FLTB RESET
FLTB SET
1
1
L
1
1
> V
Z
STAB RESET
OL
* Output states after blanking and filter timers end and when channel is set to latch−off mode.
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22
NCV7512
APPLICATION GUIDELINES
General
Unused DRN inputs should be connected to V
To limit power in the DRN input clamps and to ensure
X
to
proper open load or short to GND detection, the R
X
CC1
DX
prevent false open load faults. Unused parallel inputs
should be connected to GND and unused enable inputs
resistor must be dimensioned according to the following
constraint equations:
should be connected to V
.
CC1
V
−V
PK CL(MIN)
I
(eq. 2)
R
+
The mask bit for each unused channel should be ‘set’ (see
Table 5) to prevent activation of the flags and the user’s
software should be designed to ignore fault information for
unused channels.
DX(MIN)
CL(MAX)
|
|
V
− V
SG OS
(eq. 3)
R
+
DX(MAX)
|
|
I
SG
For best shorted−load detection accuracy, the external
MOSFET source terminals should be star−connected. The
NCV7512’s GND pin and the lower resistor in the fault
reference voltage divider should be Kelvin connected to
the star (See Figures 2 and 13).
Auto−retry fault recovery behavior is a necessary
consideration from a power dissipation viewpoint (for both
the NCV7512 and the MOSFETs). EMI should also be
evaluated during auto−retry.
Driver slew rate and turn−on/off symmetry can be
adjusted externally to the NCV7512 in each channel’s gate
circuit by adding a gate series resistor. Resistors and diodes
can be added for channel symmetry. Any benefit of EMI
reduction by this method comes at the expense of increased
switching losses in the MOSFETs.
The channel fault blanking timers must be considered
when choosing external components (MOSFETs, slew
control resistors, etc.) to avoid false faults. Component
choices must ensure that gate circuit charge/discharge
times stay within the turn−on/turn−off blanking times.
The NCV7512 does not have integral drain−gate flyback
clamps. Clamp MOSFETs, such as ON Semiconductor’s
NID9N05CL, are recommended when driving unclamped
inductive loads. This flexibility allows choice of MOSFET
clamp voltages suitable to each application.
Where:
• V is the peak transient drain voltage
PK
• V is the DRN input clamp voltage
CL
X
• I
is the input clamp current
CL(MAX)
• V short to GND fault detection voltage
SG
• I short to GND diagnostic current
SG
• V is the allowable offset (1V max) between the
OS
NCV7512’s GND and the short.
Once R
is chosen, the open load and short to GND
DX
detection resistances in the application can be predicted:
Once R is chosen, the open load and short to GND
detection resistances in the application can be predicted:
DX
V
−V
LOAD OL
(eq. 4)
(eq. 5)
R
w
* R
DX
OL
I
OL
|
|
R
R
(V
" V − I
)
LOAD SG
OS SG DX
R
SG
v
|
|
V
−V
) I
(R
) R
)
LOAD SG
SG DX
LOAD
Using the data sheet values for V
= 27 V, I
= 10 mA,
CL(MIN)
CL(MAX)
and choosing V = 55 V as an example, Equation 2 evaluates to
PK
2.8 kW minimum.
Choosing V
= 5.0 V and using the typical data sheet values for
CC1
V
SG
= 30%V
, I = 20 mA, and choosing V = 0, Equation 3
CC1 SG OS
evaluates to 75 kW maximum.
DRN Feedback Resistor
X
Selecting R = 6.8 kW "5%, V
= 5.0 V, V
= 12.0 V, V
OS
DX
CC1
LOAD
Each DRN feedback input has a clamp to keep the
X
= 0 V, R
OL OL SG
resistance of 130.7 kW.
= 555 W, and using the typical data sheet values for
LOAD
applied voltage below the breakdown voltage of the
V
, I , V , and I , Equation 4 predicts an open load detection
SG
NCV7512. An external series resistor (R ) is required
DX
between each DRN input and MOSFET drain. Channels
Equation 5 predicts a short to GND detection resistance of 71.1 W.
X
may be clamped sequentially or simultaneously but total
clamp power is limited by the maximum allowable
junction temperature.
When R and the data sheet values are taken to their extremes,
DX
the open load detection range is 94.1 kW v R v 273.5 kW, and
OL
the short to GND detection range is 59.2 W v R v 84.4 W.
SG
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23
NCV7512
APPLICATIONS DRAWINGS
Daisy Chain
SO pin when the CSB pin transitions from a high to a low
will be the Diagnostic Output Data. These are the bits
representing the status of the IC and are detailed in
Figure 22. Additional programming bits should be clocked
in which follow the Diagnostic Output bits.
The NCV7512 is capable of being setup in a daisy chain
configuration with other similar devices which include
additional NCV7512 devices as well as the NCV7513 Hex
Low−Side Predriver. Particular attention should be focused
on the fact that the first 16 bits which are clocked out of the
CSB SCLK
NCV7512
CSB SCLK
CSB SCLK
NCV7513
CSB SCLK
Any IC
using SPI
protocol
NCV7512
SO
SO
SO
SO
SI
SI
SI
SI
Figure 22. Daisy Chain
Parallel Control (time consideration)
for the last device in the serial string must first pass through
all the previous devices. The parallel control setup
eliminates that requirement, but at the cost of additional
control pins from the microprocessor for each individual
CSB (chip select bar) pin for each controllable device.
Serial data is only recognized by the device that is activated
through its’ respective CSB pin.
A more efficient way to control multiple SPI compatible
devices is to connect them in a parallel fashion and allow
each device to be controlled in a multiplex mode. Figure 23
shows a typical connection between the microprocessor or
microcontroller and multiple SPI compatible devices. In a
daisy chain configuration, the programming information
NCV7512
SI
SI
SCLK
SCLK
CSB
SO
OUT1
OUT2
OUT3
SO
CSB
chip1
NCV7512
SI
CSB
SCLK
CSB
SO
chip2
OUT1
OUT2
OUT3
CSB
chip3
NCV7512
SI
SCLK
CSB
SO
OUT1
OUT2
OUT3
Figure 23. SPI Parallel Control Setup
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24
NCV7512
PACKAGE DIMENSIONS
32 LEAD LQFP
FT SUFFIX
CASE 873A−02
ISSUE C
4X
A
A1
0.20 (0.008) AB T-U
Z
32
25
AE
AE
1
P
−U−
−T−
BASE
METAL
B
V
N
B1
DETAIL Y
DETAIL Y
V1
17
8
F
D
9
4X
−Z−
0.20 (0.008) AC T-U
Z
9
J
S1
_
8X M
S
R
SECTION AE−AE
DETAIL AD
G
−AB−
−AC−
E
C
SEATING
PLANE
0.10 (0.004) AC
W
_
Q
H
K
NOTES:
MILLIMETERS
DIM MIN MAX
7.000 BSC
3.500 BSC
INCHES
MIN MAX
0.276 BSC
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
X
A
A1
B
2. CONTROLLING DIMENSION:
MILLIMETER.
0.138 BSC
0.276 BSC
0.138 BSC
DETAIL AD
7.000 BSC
3.500 BSC
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
B1
C
1.400
1.600
0.450
1.450
0.400
0.055
0.063
0.018
0.057
0.016
D
0.300
1.350
0.300
0.012
0.053
0.012
E
F
G
H
0.800 BSC
0.031 BSC
0.050
0.090
0.450
0.150
0.200
0.750
0.002
0.004
0.018
0.006
0.008
0.030
J
K
_
12 REF
_
12 REF
M
N
0.090
0.160
0.004
0.006
P
0.400 BSC
1_
0.016 BSC
1_
Q
R
5_
5 _
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
0.150
0.250
0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
V1
W
X
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
FLEXMOS and SMARTDISCRETES are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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