NCV7544MWTXG [ONSEMI]
FLEXMOS™ Four Channel Half-Bridge MOSFET Pre-Driver for Motor Control Application;型号: | NCV7544MWTXG |
厂家: | ONSEMI |
描述: | FLEXMOS™ Four Channel Half-Bridge MOSFET Pre-Driver for Motor Control Application |
文件: | 总40页 (文件大小:374K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NCV7544
FLEXMOSt Quad Half-Bridge
MOSFET Pre-driver
The NCV7544 programmable four channel half−bridge MOSFET
pre−driver is one of a family of FLEXMOS automotive grade products
for driving logic−level NMOS FETs. The product is controllable by a
combination of serial SPI and CMOS−compatible parallel inputs. An
internal power−on reset provides controlled power up. A reset input
allows external re−initialization and a failsafe input allows the device
to be safely disabled in the event of system upset.
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Each channel independently monitors its external MOSFETs’
drain−source voltages for fault conditions. Overload detection
thresholds are SPI−selectable and the product allows different
detection thresholds for each channel.
The FLEXMOS family of products offers application scalability
through choice of external MOSFETs.
QFN32 5x5, 0.5P (PUNCHED)
CASE 485CZ
MARKING DIAGRAM
Features
• Supports Functional Safety Compliance
• 4 Half−bridge Pre−drivers for External Logic−level NMOS FETs
1
ON
NCV7544
AWLYYWW
• Integrated Charge Pump for:
♦ High−side Gate Drive
♦ Switched Reverse Battery Protection
G
NCV7544 = Specific Device Code
• 5 V CMOS Compatible I/O:
♦ 16−bit SPI Interface for Control and Diagnosis
♦ Reset and Failsafe Inputs
♦ 2 PWM Control Inputs
A
= Assembly Location
= Wafer Lot
WL
YY
WW
G
= Year
= Work Week
= Pb−Free Package
• Programmable:
♦ Slew Rate Control
♦ Overload Protection Thresholds
ORDERING INFORMATION
• Low Quiescent Current
• Wettable Flanks Pb−free Packaging
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
†
Device
NCV7544MWTXG
Package
Shipping
QFN−32
(Pb−Free)
5000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Benefits
• Scalable to Load by Choice of External MOSFET
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
October, 2018 − Rev. 0
NCV7544/D
NCV7544
VCC VS
CP CPSW
CSB
SCLK
SI
C1A
C1B
C2A
C2B
POWER
SUPPLY
CHARGE
PUMP
SPI
SO
SFL
N/C
RSTB
FSM
PWM1
PWM2
NCV7544
CP SFL
SFL CP
LOGIC
CORE
PDH
PDH
GH1
HB1
GL1
GH2
HB2
GL2
HB1
HB2
PDL
PDL
PGND
PGND
CP SFL
SFL CP
PDH
PDH
GH3
HB3
GL3
GH4
HB4
GL4
WATCH
DOG
HB3
HB4
PDL
PDL
FAILSAFE
PGND
PGND
{2018.06.25}
AGND DGND PGND
Figure 1. Block Diagram
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2
NCV7544
REVERSE
PROTECT
SECURITY
SWITCH
VBAT
VBAT_P
WD_EN
VS
CP
CPSW
C1A
C1B
C2A
C2B
VCC
GH1
HB1
GL1
OPTIONAL
14V
LIMITER
5V
M
M
NCV7544
GH2
HB2
GL2
VCC
CSB
SCLK
SI
SO
GH3
HB3
GL3
RSTB
PWM1
PWM2
M
GH4
HB4
GL4
WATCHDOG
FSM
AGND PGND DGND
A/D
3−5
3−5
mW
mW
{2018.06.25}
Figure 2. Application Diagram
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3
NCV7544
PACKAGE PIN DESCRIPTION
32 Pin QFN Exposed Pad Package
Pin
Label
Function
Description
29
VS
Main Power Supply
Main high−power device supply (battery) input; VDS sense reference node for the
half−bridge high−side drivers. An external ceramic bypass capacitor shall be connect-
ed between VS and GND close to the pin.
24
VCC
Logic Supply
SPI block and internal logic and low power (analog) supply input. An external ceramic
bypass capacitor shall be connected between VCC and GND close to the pin.
27
26
31
AGND
DGND
PGND
Signal Ground
Digital Ground
Power Ground
Low power return path; reference for the analog circuitry.
Low power return path; reference for the digital circuitry.
High power return path; reference for the half−bridge drivers; VDS sense reference
node for the half−bridge low−side drivers.
1
32
3
C1A
C1B
C2A
C2B
CP
Charge Pump Switch Switching nodes for external ceramic charge pumping capacitors 1 & 2.
Node
4
2
Charge Pump Output Charge pump output; an external ceramic buffer capacitor shall be connected between
CP and VS to provide stable output voltage during transient noise on VS.
30
17
CPSW
RSTB
Charge Pump
Switched Output
Switched charge pump output; activates external reverse battery and security power
MOSFET switches via SPI.
Wake Input
Digital input with falling edge digital de−glitch and pull−down resistor; active low master
reset; the device is in wake state when the pin is high.
18
19
20
21
22
23
CSB
SCLK
SI
SPI Chip Select
SPI Clock
Digital input with pull−up resistor; active low chip select.
Digital input with pull−down resistor.
SPI Serial Input
PWM Inputs
Digital input with pull−down resistor.
PWM2
PWM1
FSM
Digital inputs with symmetrical adaptive digital de−glitch and pull−down resistor; pro-
vide PWM signals to the half−bridge pre−drivers.
Fail−safe Input
Digital input with symmetrical digital de−glitch and pull−down resistor; the active high
fail−safe mode (can be set via an external watchdog circuit).
25
SO
SPI Serial Output
Digital tri−state output with high−side path protection to prevent VCC back−bias in the
event of an external voltage regulator failure or short to VS.
6
9
GH1
GH2
GH3
GH4
HB1
HB2
HB3
HB4
GL1
GL2
GL3
GL4
N/C
High−side Pre−driver High−side pre−drivers with pull−down resistor to HBx switch nodes; gate drive for ex-
Output
ternal logic−level N−MOS FETs.
12
15
7
Half−bridge Switch
Node
Monitoring inputs for external half−bridge switches; high−side MOSFET source node;
low−side MOSFET drain node.
10
13
16
5
Low−side Pre−driver Low−side pre−drivers with pull−down resistor to PGND;
Output
gate drive for external logic−level N−MOS FETs.
8
11
14
28
–
No Connection
Exposed Pad
Unused pin
EP
Connect to GND.
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4
NCV7544
Exposed Pad
(EP)
32 31 30 29 28 27 26 25
C1A
CP
1
2
3
4
5
6
7
8
24 VCC
23
FSM
C2A
C2B
GL1
GH1
HB1
GL2
22 PWM1
21 PWM2
20 SI
NCV7544
19 SCLK
18 CSB
17 RSTB
9 10 11 12 13 14 15 16
{2018.06.25}
Figure 3. 32 Pin 5 x 5 mm Exposed Pad Pin−out (Top View)
MAXIMUM RATINGS
(Except as noted, voltages are with respect to AGND = DGND = PGND = GND.)
Rating
Symbol
Value
Unit
VS Supply
DC: 2 min @ 25°C
AC: ISO7637 Pulse 5b, 400 ms @ 25°C
VS
−0.3 to 28
40
V
MAX
VCC Supply
VCC
−0.3 to 7.0
V
V
MAX
Output Voltage:
CP, CPSW
SO
V_OUT
V_SO
−0.3 to 40
−0.3 to 20
MAX
MAX
Input Voltage:
FSM, C1A, C1B, C2A, C2B
V_IN
V_IN
V_IN
I_IN
T
−0.3 to 40
−1.0 to 40
−0.3 to 20
5.0
V
V
MAX1
MAX2
MAX3
MAX
J
Input Voltage (Clamped):
HBx
Input Voltage: CSB, SCLK, SI, RSTB, PWMx
V
Input Current (Clamped): CSB, SCLK, SI, RSTB, FSM, PWMx, GHx, GLx
Junction Temperature
mA
°C
°C
°C
−40 to 150
−55 to 150
260
Storage Temperature
T
STG
Peak Reflow Soldering Temperature: Lead−free 60 to 150 seconds at 217°C (Note 1)
T
PK
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. See or download ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
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5
NCV7544
ATTRIBUTES
Characteristic
Symbol
Value
Unit
ESD Capability:
Human Body Model per AEC−Q100−002
V
kV
ESD_HBM
All pins
≥
≥
2.0
4.0
VS, HBx
Charged Device Model per AEC−Q100−011
V
V
ESD_CDM
All Pins
≥
≥
500
750
Corner Pins
Moisture Sensitivity (Note 1)
Package Thermal Resistance – Still−air, P = 1 W (Uniform Power Density)
MSL
3
–
°C/W
IN
Junction–to–Ambient, Rq
(Note 2)
(Note 3)
Rq
Rq
68.0
27.4
1.7
JA
JA
JA
Junction–to–Exposed Pad, RY
RY
JPAD
JPAD
2
2. 2S0P 2−layer PCB based on JESD51−3, 80 x 80 x 1.6 mm FR4, 20 thermal vias, 1 oz. signal, 1 oz. 400 mm bottom spreader.
2
3. S2P 4−layer PCB based on JESD51−7, 80 x 80 x 1.6 mm FR4, 20 thermal vias, 1 oz. signal, 1 oz. 6400 mm internal spreaders.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VS
Min
7.0
4.5
3.5
0
Max
18.0
5.5
Unit
V
Main Power Supply Voltage
Logic Power Supply Voltage
Logic High Input Voltage
OP
VCC
V
OP
IN_HIGH
V
VCC
V
OP
Logic Low Input Voltage
V
1.5
25
V
IN_LOW
Half−bridge Output PWM Rate
f
–
kHz
nF
MHz
ms
PWM
Charge Pump Capacitors (C1, C2, CCP)
SPI Clock Frequency
−
220
0.1
–
4700
2.5
f
SCLK
Startup Delay at VCC Power−On Reset (POR) (Note 4)
Ambient Still−Air Operating Temperature
t
200
125
RESET
T
A
−40
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Minimum wait time until device is ready to accept serial input data.
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6
NCV7544
PARAMETRIC TABLES
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
VS Supply
Symbol
Conditions
Min
Typ
Max
Unit
mA
VS = 12.0V, 0 v VCC v 5.5 V, RSTB = 0,
Standby Current
Operating Current
I
–
–
5.0
VS_SBY
T = 25°C
A
VCC = 5.0 V , RSTB = 1, T = 25 °C
A
Default Settings at POR, SPI Inactive
CR1.D[10]=0
0.9
5.0
mA
–
–
I
I
VS_OP0
CR1.D[10]=1
13.4
5.0
25.0
5.5
mA
V
VS_OP1
Under−voltage Lockout
VS
VS decreasing, SR0.D[5] ³ 1
SR0.D[5] ³ 0
4.5
UVLO
UVHY
Under−voltage Hysteresis
VS
100
200
–
mV
(after read status if VS > VS
)
UVLO+UVHY
Under−voltage Filter Time
Over−voltage Shutdown
t
VS decreasing
4.0
5.0
6.0
ms
V
UVDGL
VS
VS increasing, SR0.D[4] ³ 1
VS decreasing, SR0.D[4] ³ 0
SR0.D[4] ³ 0
19.0
18.0
20.0
19.0
21.0
20.0
OVSDR
OVSDF
VS
V
Over−voltage Hysteresis
VS
–
0.9
–
V
OVHY
(after read status if VS < VS
)
OV – OVHY
Over−voltage Filter Time
VS PWM Threshold
t
VS increasing
4.0
5.0
6.0
ms
OVDGL
VS
VS decreasing, SR0.D[7] ³ 1
8.90
9.45
10.0
V
PWM
SR0.D[7] ³ 0 and/or SR0.D[6] ³ 0
VS PWM Hysteresis
VCC Supply
VS
−
–
100
–
–
mV
PWM_HY
(after read status if VS > VS
)
PWM +PWM_HY
VS = 12.0V, VCC = 5.5 V , RSTB = 0, T = 25 °C
Default Settings at POR, SPI Inactive
A
Standby Current
I
5.0
mA
VCC_SBY
Operating Current
I
VS = 12.0V, RSTB = 1, T = 25 °C
–
8.0
12.0
4.49
4.20
mA
V
VCC_OP
A
Power−On Reset Threshold
VCC
VCC Increasing
VCC Decreasing
3.71
3.50
4.10
3.85
PORR
PORF
VCC
V
Charge Pump
C1 = C2 = 470 nF; CCP = 1000 nF
Switching Frequency
Regulation Voltage
f
Single−stage, complementary−phase topology
1.04
8.3
1.25
8.9
1.56
9.5
MHz
V
CP
CP
V(CP, VS), VS > VS
, 0 v I(CP) v 10 mA
REG
PWM
VS = 13V, I(CP) = no load
C1 = C2 = 470 nF, CCP = 1000 nF
(Note 6.)
Startup Delay
CP
–
–
500
ms
DLY
Dropout Voltage
V(VS) − V(CP, VS), I(CP) = 10 mA,
VS=9.4
CP
–
–
–
–
1.50
1.75
DROP0
DROP1
V
V(VS) − V(CP, VS), I(CP) = 10 mA,
VS=10V and SR0.D[7] = 0
CP
–
–
8.0
–
1.90
8.8
–
T w 125 °C
J
Charge Pump Low Detection
CP
CP
V(CP, VS) decreasing, VS > VS
, SR0.D[7] ³ 1
7.3
300
V
LOW0
PWM
Detection margin, CP
= CP
− CP
LOW0
mV
LOW1
LOW1
REG
Charge Pump Low Detection
Filter Time
t
120
150
180
ms
CPL_DGL
SR0.D[7] ³ 0
(after read status if V(CP,VS) > CP
Charge Pump Low Hysteresis
Charge Pump Fail Detection
CP
–
100
5.375
150
–
mV
V
LOW_HY
)
LOW+LOW_HY
CP
V(CP, VS) decreasing, SR0.D[6] ³ 1
4.925
120
5.750
180
FAIL
Charge Pump Fail Detection
Filter Time
t
ms
CPF_DGL
SR0.D[6] ³ 0
(after read status if V(CP,VS) > CP
Charge Pump Fail Hysteresis
CP
–
100
–
mV
FAIL_HY
)
FAIL+FAIL_HY
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7
NCV7544
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
Charge Pump Over−voltage
Detection
CP
VS increasing
28.0
30.25
32.5
V
OV
Charge Pump Over−voltage
Hysteresis
CP
0.5
–
1.0
1.5
2.0
–
V
OV_HYS
*Guaranteed by Simulation*
CP Switch Resistance
R
W
CPTOT
8x CP switches in parallel, T = 25°C
A
Switched CP Output Resis-
tance
R
CR1.D[9] = 1, I(CPSW) = 5 mA
–
–
0
100
1.0
W
CPSW_ON
Switched CP Output Leakage
CP
CR1.D[9] = 0
−1.0
uA
SW_LKG
Digital I/O
V
V
High
Low
V
CSB, SCLK, SI, RSTB, FSM, PWMx
CSB, SCLK, SI, RSTB, FSM, PWMx
3.5
–
–
–
V
V
IN_X
IN_X
INHX
V
–
1.5
130
130
INLX
Input Pull−down Resistance
Input Pull−up Resistance
R
SCLK, SI, RSTB, FSM, PWMx, V
= VCC
70
70
100
100
kW
kW
PDX
INX
R
CSB, V = 0V
IN
PU
V
V
= 5.5V: SCLK, SI, RSTB, FSM, PWMx
= 0V: CSB
–
−80
80
–
INX
INX
Input Current
Input Leakage
I
0
0
mA
mA
INX
V
INX
V
INX
= 0V: SCLK, SI, RSTB, FSM, PWMx
= VCC: CSB
I
−1.0
1.0
IN_LKG
Input Filter Time
t
FSM input
8.0
8.0
–
10
–
12
–
ms
ms
ms
V
IN_DGL
Reset De−glitch Time
Reset Assert Time
SO Low Voltage
t
Minimum RSTB pulse (H ³ L ³ H) detected
Minimum RSTB hold after H ³ L transition
RST_DGL
t
11
–
15
0.4
WRST
V
SOL
I
= 1.0 mA
–
SINK
VCC –
0.4
SO High Voltage
V
I
= 1.0 mA
–
–
–
V
SOH
SOURCE
SO Tri−State Leakage Current
SO
CSB = VCC, SO = VCC/2
−1.0
1.0
mA
LKG
Serial Peripheral Interface (See Figure 4)
VCC = 5.0V, FSCLK = 2.5 MHz, CLOAD = 80 pF, all timing is at 30% and 70% VCC unless otherwise specified.
SCLK Clock Period
SCLK High Time
SCLK Low Time
Maximum Input Capacitance
Sl Setup Time
t
400
200
200
–
–
–
–
–
ns
ns
ns
pF
ns
ns
ns
ns
ns
ns
SCLK
CLKH
t
SCLK = 70% VCC to 70% VCC
SCLK = 30% VCC to 30% VCC
SCLK, Sl
t
–
–
CLKL
C
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
–
15
–
INX
SISU
SIHD
t
Sl = 30%|70% to SCLK = 70% VCC
SCLK = 30% to Sl = 30%|70% VCC
25
25
–
–
Sl Hold Time
t
–
–
SO Rise Time
t
(20% V to 80% VCC)
25
–
50
50
–
SOR
SO
SO Fall Time
t
(80% V to 20% VCC)
–
SOF
SO
CSB Setup Time
CSB Hold Time
t
CSB = 30% to SCLK = 30% VCC
SCLK = 30% to CSB = 70% VCC
60
75
–
CSBSU
CSBHD
t
–
–
CSB = 30% VCC to SO = 30%|70% VCC
RLOAD = 5 kW
CSB to SO Assert Time
CSB to SO Release Time
t
–
–
65
–
125
350
ns
ns
SO_A
(Note 6)
CSB = 70% VCC to SO = 20%|80% VCC/2
t
SO_R
RLOAD = 5 kW
(Note 6)
SO Delay Time
SO
CS
SCLK = 70% VCC to SO = 30%|70%
CSB rising edge to next falling edge.
(Note 6)
(Note 6)
–
–
65
–
125
1.0
ns
DLY
Transfer Delay Time
Watchdog Timer
Watchdog Timeout
ms
DLY
CR1.D[8] = 0
CR1.D[8] = 1
20
400
25
500
30
600
t
ms
WD
Core Clock Oscillator
f
–
40
–
MHz
CORE
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8
NCV7544
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
Half−Bridge Pre−Driver Outputs
VS > VS
PWM
On−state Drive Voltage
High−side, V
No External Load
= H = V(GHx, HBx),
PDHX
V
8.3
8.1
–
–
–
–
–
–
9.5
9.8
V
V
V
V
V
V
PDHX
Low−side, V
= H =V(GLx, PGND),
PDLX
V
PDLX
No External Load
High−side driver Gate−source
Clamp Positive Voltage
V(GHx, HBx),
V
14.0
−20.0
11.5
−1.0
18.0
−16.0
15.0
–
GSX_CLPH
I
= 3.0 mA
CLMP
High−side driver Source−gate
Clamp Negative Voltage
V(HBx, GHx),
= −2.0 mA
V
SGX_CLPH
I
CLMP
Low−side driver Gate−source
Clamp Positive Voltage
V(GLx, PGND),
V
GSX_CLPL
I
= 10 mA
CLMP
Low−side driver Gate−source
Clamp Negative Voltage
V(GLx, PGND),
V
GSX_CLN
I
= −1.0 mA
CLMP
Gate Drive Timeout
t
I
v I
16
20
24
ms
TIMEOUT
GHx
GHx_SS
Gate Drive Timeout Current
I
V(GHx, HBx) = 0 V , t > t
−1.2
−1.0
−0.8
mA
GHx_SS
TIMEOUT
Gate−source Pull−down
Resistor
R
R(GHx, HBx), R(GLx, PGND)
BLANKx[1:0] = 0x00
70
–
130
kW
ms
GSX
Cross Conduction Blank Time
0.8
1.6
2.4
3.2
1.0
2.0
3.0
4.0
1.2
2.4
3.6
4.8
BLANKx[1:0] = 0x01
BLANKx[1:0] = 0x02
BLANKx[1:0] = 0x03
t
BLANKX
GHx, GLx
Pre−Driver Slope Control
VS > VS
PWM
High−side Pre−charge Time
GHx Rising and Falling Slope
T_PCx[1:0] = 0x00
T_PCx[1:0] = 0x01
T_PCx[1:0] = 0x02
T_PCx[1:0] = 0x03
I_PCRx[2:0] = 0x00
I_PCRx[2:0] = 0x01
I_PCRx[2:0] = 0x02
I_PCRx[2:0] = 0x03
I_PCRx[2:0] = 0x04
I_PCRx[2:0] = 0x05
I_PCRx[2:0] = 0x06
I_PCRx[2:0] = 0x07
I_PCFx[2:0] = 0x00
I_PCFx[2:0] = 0x01
I_PCFx[2:0] = 0x02
I_PCFx[2:0] = 0x03
I_PCFx[2:0] = 0x04
I_PCFx[2:0] = 0x05
I_PCFx[2:0] = 0x06
I_PCFx[2:0] = 0x07
80
100
200
120
240
160
t
ns
PRCX
240
300
360
320
400
480
High−side Pre−charge Current
GHx Rising Slope
1.23
1.50
1.77
4.52
5.25
5.99
V(GHx) = 3.5 V
7.42
8.63
9.84
10.65
14.19
17.42
20.64
24.19
24.84
30.64
36.12
41.61
47.41
52.89
58.38
64.18
12.38
16.50
20.25
24.00
28.13
28.88
35.63
42.00
48.38
55.13
61.50
67.88
74.63
14.11
18.81
23.09
27.36
32.07
32.92
40.62
47.88
55.15
62.85
70.11
77.38
85.08
I
mA
PRCX_R
High−side Pre−charge Current
GHx Falling Slope
V(GHx) = (VS + 3.5) V
I
mA
PRCX_F
www.onsemi.com
9
NCV7544
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
Symbol
Conditions
Min
1.23
Typ
1.50
Max
1.77
Unit
High−side Slew Current
SR_CTRLx[2:0] = 0x00
SR_CTRLx[2:0] = 0x01
SR_CTRLx[2:0] = 0x02
SR_CTRLx[2:0] = 0x03
SR_CTRLx[2:0] = 0x04
SR_CTRLx[2:0] = 0x05
SR_CTRLx[2:0] = 0x06
SR_CTRLx[2:0] = 0x07
SR_CTRLx[2:0] = 0x00
SR_CTRLx[2:0] = 0x01
SR_CTRLx[2:0] = 0x02
SR_CTRLx[2:0] = 0x03
SR_CTRLx[2:0] = 0x04
SR_CTRLx[2:0] = 0x05
SR_CTRLx[2:0] = 0x06
SR_CTRLx[2:0] = 0x07
GHx Rising and Falling Slope
1.94
2.25
2.57
Rising: V(GHx) = (VS + 3.5) V
Falling: V(GHx) = 3.5 V
2.91
3.38
3.85
4.52
5.25
5.99
I
mA
SRX
6.78
7.88
8.98
10.00
14.84
21.93
5.16
11.63
17.25
25.50
6.00
13.26
19.67
29.07
6.84
Low−side Drive Current
GLx Rising and Falling slope
7.74
9.00
10.26
15.41
23.94
35.93
53.03
78.66
11.63
18.06
27.11
40.01
59.34
87.72
13.52
21.00
31.52
46.52
69.00
V(GLx) = 3.5 V
I
mA
LSX
102.00 116.28
Slope Control Calibration Unit
Slope Calibration Comparator
Window Thresholds
V
Falling slope window lower threshold
Falling slope window upper threshold
Rising slope window lower threshold
Rising slope window upper threshold
3.0
13
82
92
–
5.0
15
7.0
17
88
98
100
–
CALF_L
CALF_U
CALR_L
CALR_U
CAL_PD
V
V
% VS
85
V
95
Comparator Propagation Delay
Sample Synchronization Delay
Calibration Pre−charge Time
t
62
ns
ns
t
t
= 2/f
CORE
–
50
SYNC
SYNC
CAL_PC[3:0] = 0x00
CAL_PC[3:0] = 0x01
CAL_PC[3:0] = 0x02
CAL_PC[3:0] = 0x03
CAL_PC[3:0] = 0x04
CAL_PC[3:0] = 0x05
CAL_PC[3:0] = 0x06
CAL_PC[3:0] = 0x07
CAL_PC[3:0] = 0x08
CAL_PC[3:0] = 0x09
CAL_PC[3:0] = 0x0A
CAL_PC[3:0] = 0x0B
CAL_PC[3:0] = 0x0C
CAL_PC[3:0] = 0x0D
CAL_PC[3:0] = 0x0E
CAL_PC[3:0] = 0x0F
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
1450
1550
HBx Rising & Falling Slope
t
(Note 7)
(Note 7)
ns
CAL_PCx
www.onsemi.com
10
NCV7544
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
Symbol
Conditions
Min
Typ
0.35
0.55
0.75
0.95
1.15
1.35
1.55
1.75
1.95
2.15
2.35
2.55
2.75
2.95
3.15
3.35
Max
Unit
Calibration Delay Time
CAL_DLY[3:0] = 0x00
CAL_DLY[3:0] = 0x01
CAL_DLY[3:0] = 0x02
CAL_DLY[3:0] = 0x03
CAL_DLY[3:0] = 0x04
CAL_DLY[3:0] = 0x05
CAL_DLY[3:0] = 0x06
CAL_DLY[3:0] = 0x07
CAL_DLY[3:0] = 0x08
CAL_DLY[3:0] = 0x09
CAL_DLY[3:0] = 0x0A
CAL_DLY[3:0] = 0x0B
CAL_DLY[3:0] = 0x0C
CAL_DLY[3:0] = 0x0D
CAL_DLY[3:0] = 0x0E
CAL_DLY[3:0] = 0x0F
HBx Rising & Falling Slope
t
(Note 7)
(Note 7)
ms
CAL_DLYx
Half−Bridge Diagnostics
Static VDS Monitor Thresholds
VDSx[2:0] = 0x00
VDSx[2:0] = 0x01
VDSx[2:0] = 0x02
VDSx[2:0] = 0x03
VDSx[2:0] = 0x04
VDSx[2:0] = 0x05
VDSx[2:0] = 0x06
VDSx[2:0] = 0x07
267
356
445
534
623
712
801
890
300
400
500
600
700
800
900
1000
333
444
555
666
777
888
999
1110
VDS = V(VS, HBx)
− or−
VDS
mV
THR_S
VDS = V(HBx, GND)
Static VDS Monitor
Filter Time
t
0.92
–
1.15
550
1.38
750
ms
DGL_STAT
Static VDS Monitor
Propagation Delay
t
ns
VDSS_PD
Dynamic VDS Monitor
Thresholds
VDS
VDS
77.0
17.0
80.0
20.0
83.0
23.0
% VS
% VS
THR_R
THR_F
www.onsemi.com
11
NCV7544
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
Symbol
Conditions
Min
Typ
0.35
0.55
0.75
0.95
1.15
1.35
1.55
1.75
1.95
2.15
2.35
2.55
2.75
2.95
3.15
3.35
Max
Unit
Dynamic VDS Detection
Delay Time
T_DLYX[3:0] = 0x00
T_DLYX[3:0] = 0x01
T_DLYX[3:0] = 0x02
T_DLYX[3:0] = 0x03
T_DLYX[3:0] = 0x04
T_DLYX[3:0] = 0x05
T_DLYX[3:0] = 0x06
T_DLYX[3:0] = 0x07
T_DLYX[3:0] = 0x08
T_DLYX[3:0] = 0x09
T_DLYX[3:0] = 0x0A
T_DLYX[3:0] = 0x0B
T_DLYX[3:0] = 0x0C
T_DLYX[3:0] = 0x0D
T_DLYX[3:0] = 0x0E
T_DLYX[3:0] = 0x0F
Rising or Falling Slope
t
(Note 7)
(Note 7)
ms
DLYX
Dynamic VDS Monitor
Filter Time
t
t
231
–
330
59
429
100
ns
ns
DGL_DYN
Dynamic VDS Monitor
Propagation Delay
VDSD_PD
HBx Monitor Threshold
VHB
45
–
50
55
% VS
THR
HBx Monitor Propagation Delay
t
1.0
2.0
ms
HBX_PD
CR0.HB_ENx = 0, HB1, HB3
source or sink, 10V v VS v 16V
HBx Monitor Test Currents
I
6.0
7.5
9.0
mA
TST
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Min/Max values are valid for the stated temperature range unless noted otherwise. Min/Max values are guaranteed by test, design or
statistical correlation
6. No production test
7. These values, measured in production via test mode, result in values that are t
longer than the stated values. The specification limits
SYNC
shall therefore be: (t
Typ + t
Typ) 20%, (t
Typ + t
Typ) 20%, and (t
Typ + t
Typ) 20%.
CAL_PCx
SYNC
CAL_DLYx
SYNC
DLYX
SYNC
www.onsemi.com
12
NCV7544
TRANSFER
DELAY
CSB
SETUP
70%
CSB
SCLK
SI
30%
SCLK PERIOD
CSB
HOLD
SCLK
HIGH
SCLK
LOW
70%
1
16
30%
70%
SI
SI
SETUP
HOLD
X
BITS 14...1
LSB IN
MSB IN
30%
CSB to SO
ASSERT
SO
DELAY
SO
RISE,FALL
CSB to SO
RELEASE
70%
30%
80%
20%
SO
BITS 14...1
LSB OUT
X
MSB OUT
{05/20/16}
Figure 4. SPI Timing
www.onsemi.com
13
NCV7544
DETAILED OPERATING DESCRIPTION
Power Supply
The power supply block provides:
• all internal supply and reference voltages;
• all internal bias and reference currents;
• VCC power−on reset (POR) and VS
under/over−voltage lockout signals.
Table 1 gives suggested values for the external pump and
buffer capacitors to support the charge pump DC loading
while maintaining good transient response and regulation
stability.
Table 1. SUGGESTED CHARGE PUMP
CAPACITORS
The analog and power portions of the device (reference
voltages/currents, charge pump, low−side gate drivers, etc.)
are supplied from the VS terminal. Each of the low−side gate
driver outputs (GLx) is supplied from VS via an individual
buffer (source follower) with voltage limit functionality.
The high−side gate driver outputs (GHx) are supplied from
a regulated charge pump.
DC Load
(mA)
Pump Capacitors
C1, C2 (nF)
Buffer Capacitor
CCP (nF)
1.0
7.5
100
220
470
220
470
15.0
1000
The device is initialized at power−up into a reduced power
state and the charge pump disabled. The charge pump is
controlled by SPI command via the CR1.DRV_EN bit (see
Table 7) and the charge pump is:
• disabled when CR1.DRV_EN=0;
• enabled when CR1.DRV_EN=1.
The logic core and the SPI communication interface are
supplied from the VCC terminal in order to achieve a high
frequency operation by use of external bypass capacitors. In
case of breakdown of the external voltage regulator, the
device can be protected by use of an external voltage limiter,
which must limit the maximum voltage at the VCC terminal
to VCC
(see § MAXIMUM RATINGS).
MAX
The outputs are disabled during device initialization at
The optional external reverse protection and security
switches are connected to the charge pump buffer capacitor
through the switched charge pump (CPSW) output. The
output is controlled by SPI command via the CR1.CP_SW
bit (see Table 7). The CPSW output is:
• disabled (the reverse and security MOSFETs are turned
OFF) when CR1.CP_SW=0;
power−up via an interlock between VS and VCC and such
(
that no control is available until after VCC > VCC
see
PORR
§ Electrical Characteristics: VCC Supply). Reverse battery
protection for VS and the VCC regulator is provided
externally by the application (see Figure 2).
The device is initialized at power−up into a reduced power
state (CR1.DRV_EN = 0, see § SPI Control Set):
• the charge pump is disabled;
• enabled (the reverse and security MOSFETs are turned
ON) when CR1.CP_SW=1.
• all gate drive currents are disabled;
• gate pull−down structures are enabled;
The charge pump is internally monitored to ensure safe
operation of the charge pump circuit and the high−side
driver outputs (see § Protection and Diagnosis − Charge
Pump Monitoring). Due to the single stage configuration the
charge pump provides the following output characteristics
(see Figure 5, Figure 6, § SPI Diagnosis Set and § Electrical
Characteristics: Charge Pump):
• HBx diagnostic test currents are available (see
§ OFF−state Monitoring of Half−bridge Drivers).
The device is placed into a full power state when
CR1.DRV_EN = 1.
Multiple GND pins are used in order to avoid loss of GND
due to a single−point failure, to improve ESD capability, and
to improve the VDS overload protection performance of the
device.
• V(CP, VS) < CP
FAIL
SR0.CPF → 1
the GHx and GLx outputs are shut down to prevent
damage to the external power MOSFETs;
Charge Pump
• VS < VS
PWM
SR0.CPL → 1
A regulated charge pump circuit in single−stage /
complementary−phase configuration is implemented. The
charge pump is sized to drive up 2 high−side drivers in PWM
the CP output voltage follows the VS voltage (the
regulation saturates) with a maximum drop voltage per
≤
(
.
operation f
25 kHz)
PWM
the equation V(CP, VS) = VS − CP
;
DROP
The topology utilizes 2 external pump capacitors and an
external buffer capacitor (see Figure 2) to supply:
• the high−side gate driver outputs (GHx);
• an optional external reverse protection power
MOSFET;
• CP
< V(CP, VS) < CP
LOW
FAIL
SR0.CPL → 1
• VS ≤ VS ≤ VS
PWM
OVSDR
the charge pump delivers a regulated output voltage
V(CP, VS) = CP and PWM operation of the GHx
REG
• an optional external security switch power MOSFET.
outputs is allowed;
www.onsemi.com
14
NCV7544
In the case of VS overvoltage, the charge pump
automatically resumes normal operation when the VS
• VS
< VS < VS(CP
the charge pump including the CPSW output is
functional, but the GHx outputs are shut down;
)
OVSDF
OV
.
voltage returns to below CP − CP
In the case of
it should be
OV
OV_HYS
VS < VS
or V(CP, VS) < CP
PWM
LOW
• VS > VS(CP
)
OV
considered for the microcontroller to adopt a PWM duty
ratio management schema in order to minimize charge pump
loading while ensuring smooth motor operation.
the charge pump is disabled and the charge pump buffer
capacitor is discharged to VS in order to protect the
device from destruction.
V(CP, VS)
CP In Regulation
CPREG
CPLOW
(MIN)
CP Low OR VS < VSPWM
SR0.D[7] → 1
CPFAIL
(MIN)
CP Fail
GHx → L
GLx → L
SR0.D[6] → 1
V(VS)
VSOVSD
(MIN)
VSPWM
(MAX)
CPDROP
{02/16/2018}
Figure 5. Charge Pump Characteristics
V
Load Dump Rise Time
(per ISO7637 Pulse 5b)
V(VSMAX
)
)
V(CPOV
CPREG
V(CP)
V(VS)
CPREG
t
CP Oscillator Stopped
Buffer Cap Discharged to VS
{04/07/2014}
Figure 6. Charge Pump Overvoltage Behavior
www.onsemi.com
15
NCV7544
SPI Interface
Watchdog Timer) in order to facilitate module boot loader
programming. The timeout setting is controlled by the
CR1.WD_CFG bit:
A full−duplex synchronous serial data transfer interface
(SPI) is used to control the device and provide diagnosis
during normal operation. Daisy chain capability of the
interface is implemented in order to minimize circuit
expenditure and communication efforts. The SPI protocol
utilizes 16−bit data words (B15 = MSB). The idle state of
SCLK is low and the SI data must be stable before the falling
edge of SCLK (“legacy mode 1”: CPOL=0, CPHA=1).
The interface consists of 4 I/O lines with 5V CMOS logic
levels and termination resistors (see Figure 7, Figure 2):
• when CR1.WD_CFG=0 (default setting) the WD
timeout is t
= 25 ms;
WD
• when CR1.WD_CFG=1 the WD timeout is t
=
WD
500 ms.
The first WD bit value sent after VCC POR or wake−up
must be WD = 0 in the first frame, then WD = 1 in the next.
A correct communication is reported when bit SR0.SPIF
= 0 and the device is in NORMAL MODE (NM) when bit
SRx.NM = 1. The device enters FAILSAFE MODE
immediately in the event of an SPI communication error(see
§ Operating Modes).
• the active−low CSB enables the SPI interface;
• the SCLK pin clocks the internal shift registers of the
device;
• the SI pin receives data of the input shift registers MSB
first;
Serial Data and SPI Register Structures
• the SO pin sends data of the output shift registers MSB
The input and output message formats of the implemented
SPI protocol are as shown in the following tables. In the
descriptions in the following sections, it is implied that the
frame length is correct and that the WD bit has been properly
toggled when sending and receiving SPI messages. Please
also note that the SPI hardware protocol is a “frame−behind”
response type, i.e. the requested data is delivered in the next
frame.
first.
The device offers the following SPI communication error
checks in order to protect the application from unintended
motor activation:
• protocol length error (modulo 16);
• no edges on SCLK during a CSB period;
• an undefined SPI command (not used bits must be set
to logic 0);
• watchdog (WD) toggle (the internal watchdog bit
(CRx.WD) must be toggled with each SPI message);
• WD timeout (the WD bit must be toggled before the
internal watchdog timeout is reached).
SPI Control Set
The first 4 bits (D15 ... D12) serve as address bits, while
12 bits (D11 ... D0) are used as data bits. The D11 bit is the
WD toggle bit: A SPI fail is detected if the bit is not toggled
within the WD timeout. The D10 bit may be used as an
extended address in some messages.
All Control Register (CRx) bits are initialized to logic 0
after a reset. The predefined value is off / inactive unless
otherwise noted. The SPI control set (input data map) and
input data structure prototype are shown in the following
tables.
An SI pin stuck−at condition during a CSB period is
detected by a WD toggle error. A VCC under−voltage
condition is directly blocking the complete SPI functionality
via the VCC
signal.
PORF
The length of the watchdog timeout is SPI programmable
(see § SPI Control Set and § Electrical Characteristics:
TOGGLE
CSB
SAMPLE
4 − 13
1
2
3
14
15
16
SCLK
SI
X
B15
MSB
B15
B14
B14
B13
B13
B12 − B3
B12 − B3
B2
B2
B1
B1
B0
LSB
B0
Z
SO
X
Z
Note: SPI Legacy Mode 1; X=Don’t Care, Z=Tri−State
Figure 7. SPI Communication Frame Format
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16
NCV7544
Table 2. SPI INPUT DATA FORMAT
Command Input Message Format
MSB
LSB
B0
D0
B15
A3
B14
A2
B13
A1
B12
A0
B11
WD
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
4−bit REGISTER ADDRESS
WATCH
DOG
11−bit INPUT DATA
Table 3. INPUT DATA STRUCTURE PROTOTYPE
Input Data Prototype
WD
?
D10
?
D9
?
D8
?
D7
?
D6
?
D5
?
D4
?
D3
?
D2
?
D1
?
D0
CRx
?
Table 4. SPI INPUT REGISTER DEFINITIONS
Defined Command Input Registers (CRx)
D15
A3
0
D14
A2
0
D13
D12
A0
0
D11
D10
Register Name
Status Output Mode & HBx Enable
HBx Mode
Alias
CR0
A1
0
WD
D10
D10
D10
0
CR1
0
0
0
1
HBx PWM Control
HBx PWM Mode
HBx Calibration Control
HB1 Configuration A
HB1 Configuration B
HB2 Configuration A
HB2 Configuration B
HB3 Configuration A
HB3 Configuration B
HB4 Configuration A
HB4 Configuration B
Not Used
CR2
0
0
1
0
CR3
0
0
1
1
0
CR4
0
1
0
0
D10
0
CR5A
CR5B
CR6A
CR6B
CR7A
CR7B
CR8A
CR8B
CR9
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
WD
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
X
Not Used
CR10
CR11
CR12
CR13
CR14
CR15
X
Not Used
X
HBx Diagnosis
0
Not Used
0
HBx PWM De−glitch
Test Mode
0
D10
NOTE: Half−bridge gate drive settings must only be changed when HBx is in tri−state (HB_ENx = 0);
Gate drive pre−charge time settings must only be changed in single increments (i.e. 00 to 01, 01 to 10 etc.).
Table 5. CR0: STATUS OUTPUT MODE & HBx ENABLE REGISTER
WD
WD
D10
D9
D8
D7
D6
X
D5
X
D4
X
D3
D2
D1
D0
CR0
SRA_MODE
SRA[2:0]
HB_EN4 … HB_EN1
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17
NCV7544
Table 6. CR0 INSTRUCTION DEFINITIONS
Mnemonic
Value
Comment
SRA_MODE
The Status Register Address selected via CR0.SRA [2:0] will be used for a single read command. The address
always points to SR0 after the read (default state).
0
The Status Register Address selected via SRA [2:0] will be used for the next and all further read commands
until a new address is selected.
1
SRA[2:0]
000
001
010
011
100
101
110
111
0
SR0 data is returned in the next frame (default state).
SR1 data is returned in the next frame.
SR2 data is returned in the next frame.
SR3 data is returned in the next frame.
SR4 data is returned in the next frame.
SR5 data is returned in the next frame.
SR6 data is returned in the next frame.
SR7 data is returned in the next frame.
HBx output disabled (default state).
HBx output enabled.
HB_ENx
1
Table 7. CR1: HBx MODE CONTROL REGISTER
WD
D10
D9
D8
D7
X
D6
X
D5
X
D4
X
D3
D2
D1
D0
CR1
HB_MODE4 … HB_MODE1
WD
DRV_EN
CP_SW
WD_CFG
Table 8. CR1 INSTRUCTION DEFINITIONS
Mnemonic
Value
Comment
0
1
0
1
0
1
0
1
Charge pump and gate drive currents are disabled (default state).
Charge pump and gate drive currents are enabled.
Charge pump switched output is OFF: CPSW = Hi−Z (default state).
Charge pump switched output is ON: CPSW = V(CP−VS).
Watch dog timeout = 25 ms (default state).
DRV_EN
CP_SW
WD_CFG
HB_MODEx
Watch dog timeout = 500 ms.
Low−side pre−driver active (default state).
High−side pre−driver active.
Table 9. CR2: HBx PWM CONTROL REGISTER
WD
WD
D10
0
D9
0
D8
0
D7
0
D6
X
D5
X
D4
X
D3
D2
D1
D0
CR2
HB_PWM4 … HB_PWM1
Table 10. CR2 INSTRUCTION DEFINITIONS
Mnemonic
Value
Comment
0
1
Output is in 100% ON mode (default).
Output is in PWM mode.
HB_PWMx
Table 11. CR3: HBx PWM MODE CONTROL REGISTER
WD
WD
D10
X
D9
X
D8
X
D7
X
D6
D5
D4
D3
X
D2
D1
X
D0
PWM10
CR3
PWM40
X
PWM30
PWM20
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NCV7544
Table 12. CR3 INSTRUCTION DEFINITIONS
Mnemonic
Value
Comment
0
1
Output PWM source is input PWM1 (default).
Output PWM source is input PWM2.
PWMx0
Table 13. CR4: HBx CALIBRATION CONTROL REGISTER
WD
WD
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CR4
CAL_DLY[3:0]
CAL_PC[3:0]
CAL_SEL[2:0]
Table 14. CR4 INSTRUCTION DEFINITIONS
Mnemonic
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Comment
CAL_DLY[3:0]
Delay time: end of rising|falling slope 0.35 ms (default).
Delay time: end of rising|falling slope 0.55 ms.
Delay time: end of rising|falling slope 0.75 ms.
Delay time: end of rising|falling slope 0.95 ms.
Delay time: end of rising|falling slope 1.15 ms.
Delay time: end of rising|falling slope 1.35 ms.
Delay time: end of rising|falling slope 1.55 ms.
Delay time: end of rising|falling slope 1.75 ms.
Delay time: end of rising|falling slope 1.95 ms.
Delay time: end of rising|falling slope 2.15 ms.
Delay time: end of rising|falling slope 2.35 ms.
Delay time: end of rising|falling slope 2.55 ms.
Delay time: end of rising|falling slope 2.75 ms.
Delay time: end of rising|falling slope 2.95 ms.
Delay time: end of rising|falling slope 3.15 ms.
Delay time: end of rising|falling slope 3.35 ms.
Pre−charge time: start of rising|falling slope 50 ns (default).
Pre−charge time: start of rising|falling slope 150 ns.
Pre−charge time: start of rising|falling slope 250 ns.
Pre−charge time: start of rising|falling slope 350 ns.
Pre−charge time: start of rising|falling slope 450 ns.
Pre−charge time: start of rising|falling slope 550 ns.
Pre−charge time: start of rising|falling slope 650 ns.
Pre−charge time: start of rising|falling slope 750 ns.
Pre−charge time: start of rising|falling slope 850 ns.
Pre−charge time: start of rising|falling slope 950 ns.
Pre−charge time: start of rising|falling slope 1050 ns.
Pre−charge time: start of rising|falling slope 1150 ns.
Pre−charge time: start of rising|falling slope 1250 ns.
Pre−charge time: start of rising|falling slope 1350 ns.
Pre−charge time: start of rising|falling slope 1450 ns.
Pre−charge time: start of rising|falling slope 1550 ns.
CAL_PC[3:0]
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NCV7544
Table 14. CR4 INSTRUCTION DEFINITIONS
Mnemonic
Value
000
001
010
011
100
101
110
111
Comment
CAL_SEL[2:0]
Calibration unit disabled (default).
Select output HB1.
Select output HB2.
Select output HB3.
Select output HB4.
Calibration unit disabled
Calibration unit disabled
Calibration unit disabled
Table 15. CR5A − CR8A: HBx CONFIGURATION A REGISTER
CR5A – CR8A
WD
WD
D10
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BLANKx[1:0]
I_PCFx[2:0]
I_PCRx[2:0]
T_PCx[1:0]
Table 16. CR5A − CR8A INSTRUCTION DEFINITIONS
Mnemonic
Value
00
Comment
Select cross−conduction blanking time 1 ms (default).
BLANKx[1:0]
01
Select cross−conduction blanking time 2 ms.
10
Select cross−conduction blanking time 3 ms.
11
Select cross−conduction blanking time 4 ms.
I_PCFx[2:0]
I_PCRx[2:0]
T_PCx[1:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
00
Select falling slope pre−charge current 28.88mA (default).
Select falling slope pre−charge current 35.63 mA.
Select falling slope pre−charge current 42.00 mA.
Select falling slope pre−charge current 48.38 mA.
Select falling slope pre−charge current 55.13mA.
Select falling slope pre−charge current 61.50 mA.
Select falling slope pre−charge current 67.88 mA.
Select falling slope pre−charge current 74.63 mA.
Select rising slope pre−charge current 1.50 mA (default).
Select rising slope pre−charge current 5.25 mA.
Select rising slope pre−charge current 8.63 mA.
Select rising slope pre−charge current 12.38 mA.
Select rising slope pre−charge current 16.50 mA.
Select rising slope pre−charge current 20.25 mA.
Select rising slope pre−charge current 24.00 mA.
Select rising slope pre−charge current 28.13 mA.
Select rising/falling slope pre−charge time 100 ns (default).
Select rising/falling slope pre−charge time 200 ns.
Select rising/falling slope pre−charge time 300 ns.
Select rising/falling slope pre−charge time 400 ns.
01
10
11
Table 17. CR5B − CR8B: HBx CONFIGURATION B REGISTER
CR5B – CR8B
WD
WD
D10
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VDSx[2:0]
T_DLY[3:0]
SR_CTRL[2:0]
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NCV7544
Table 18. CR5B − CR8B INSTRUCTION DEFINITIONS
Mnemonic
Value
000
Comment
VDSx[2:0]
Select static VDS sense threshold 300 mV (default).
001
Select static VDS sense threshold 400 mV.
010
Select static VDS sense threshold 500 mV.
011
Select static VDS sense threshold 600 mV.
100
Select static VDS sense threshold 700 mV.
101
Select static VDS sense threshold 800 mV.
110
Select static VDS sense threshold 900 mV.
111
Select static VDS sense threshold 1000 mV.
T_DLY[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
000
Select rising/falling slope dynamic overload detect delay 0.35 ms (default).
Select rising/falling slope dynamic overload detect delay 0.55 ms.
Select rising/falling slope dynamic overload detect delay 0.75 ms.
Select rising/falling slope dynamic overload detect delay 0.95 ms.
Select rising/falling slope dynamic overload detect delay 1.15 ms.
Select rising/falling slope dynamic overload detect delay 1.35 ms.
Select rising/falling slope dynamic overload detect delay 1.55 ms.
Select rising/falling slope dynamic overload detect delay 1.75 ms.
Select rising/falling slope dynamic overload detect delay 1.95 ms.
Select rising/falling slope dynamic overload detect delay 2.15 ms.
Select rising/falling slope dynamic overload detect delay 2.35 ms.
Select rising/falling slope dynamic overload detect delay 2.55 ms.
Select rising/falling slope dynamic overload detect delay 2.75 ms.
Select rising/falling slope dynamic overload detect delay 2.95 ms.
Select rising/falling slope dynamic overload detect delay 3.15 ms.
Select rising/falling slope dynamic overload detect delay 3.35 ms.
Select rising/falling slope slew phase current 1.5 mA (default).
Select rising/falling slope slew phase current 2.25 mA.
Select rising/falling slope slew phase current 3.38 mA.
Select rising/falling slope slew phase current 5.25 mA.
Select rising/falling slope slew phase current 7.88 mA.
Select rising/falling slope slew phase current 11.63 mA.
Select rising/falling slope slew phase current 17.25 mA.
Select rising/falling slope slew phase current 25.50 mA.
SR_CTRL[2:0]
001
010
011
100
101
110
111
Table 19. CR12: HBx DIAGNOSIS CONTROL REGISTER
CR12
WD
WD
D10
0
D9
0
D8
0
D7
X
D6
X
D5
D4
D3
X
D2
X
D1
D0
TST_LS3 TST_LS1
TST_HS3 TST_HS1
Table 20. CR12 INSTRUCTION DEFINITIONS
Mnemonic
Value
Comment
0
1
0
1
Disable low−side test current (default).
Enable low−side test current.
TST_LSx
Disable high−side test current (default).
Enable high−side test current.
TST_HSx
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NCV7544
Table 21. CR14: HBx PWM DE−GLITCH
CR14
WD
WD
D10
0
D9
0
D8
0
D7
D6
X
D5
X
D4
X
D3
D2
D1
D0
0
DGL4
DGL3
DGL2
DGL1
Table 22. CR14 INSTRUCTION DEFINITIONS
Mnemonic
Value
Comment
0
1
Type 1 de−glitch: t
Type 2 de−glitch: t
= t
+ t
+ t
DLYx
(default).
PWM_DGL
BLANKx
PRCx
DGLx
= t
PRCx
+ t
DLYx
PWM_DGL
Table 23. CR15: TEST MODE REGISTER
CR15
WD
WD
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Factory Use Only
SPI Diagnosis Set
The first 3 bits D[15:13] serve as address bits, while the
13 bits D[12:0] are used as data bits. Output data for “not
used” register adresses is D[11:0] = 0. The address of the
Status Register (SRx) accessed for status information to be
retrieved via a subsequent SPI frame is selected by the
control register bits CR0.SRA_MODE and CR0.SRA[2:0]
(see Table 5, Table 6).
Two different reading modes are provided depending on
the SRA_MODE bit:
• when CR0.SRA_MODE = 0, the SRx address selected
via bits CR0.SRA[1:0] will be used for a single status
read command and the SR address returns to SR0
(device status register, default state) after reading;
All status diagnosis bits are initialized to logic 0 after a reset
event and in normal operation except:
• the NORMAL MODE (NM) bit indicates NORMAL MODE
when SRx.NM = 1;
• the Register Clear Flag (RCF) bit is set (SR0.RCF = 1)
after a mode change to NORMAL MODE
(see § Operating Modes).
The RCF bit indicates that all input and output registers
were initialized; the bit is cleared after SR0 is read.
All status diagnosis bits are latched with the exception of
the SR5.D[3:0] bits (see § Output Status Monitoring). To
de−latch a diagnosis:
• the referring failure has to be removed;
• when CR0.SRA_MODE = 1, the SRx address selected
via bits CR0.SRA[1:0] will be used for the next and all
further status read commands until a new address or
mode is selected.
• the referring failure bit has to be read by SPI diagnosis.
Refer to § Protection and Diagnosis to restart the outputs
after a fault condition. The SPI diagnosis set (output data
map) and output data structure prototype are shown in the
following tables.
The default reading mode and address after VCC POR or
wake−up is CR0.SRA_MODE = 0, CR0.SRA[1:0] = 00.
Table 24. SPI OUTPUT DATA FORMAT
Status Output Message Format
MSB
B15
A2
LSB
B14
A1
B13
A0
B12
NM
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D5
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
3−bit REGISTER
ADDRESS
NORMAL
MODE
12−bit OUTPUT DATA
Table 25. OUTPUT DATA STRUCTURE PROTOTYPE
Output Data Prototype
NM
NM
D11
?
D10
?
D9
?
D8
?
D7
?
D6
?
D5
?
D4
?
D3
?
D2
?
D1
D0
?
SRx
?
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NCV7544
Table 26. SPI OUTPUT REGISTER DEFINITIONS
Defined Status Output Registers (SRx)
D15
A2
0
D14
A1
0
D13
A0
0
D12
Register Name
Device Status
Alias
SR0
SR1
SR2
SR3
SR4
SR5
SR6
SR7
NM
HB 1…4 Status Monitor
Not Used
0
0
1
0
1
0
NM
HB 1…4 VDS Monitor
HB 1…4 Calibration Result
HB 1…4 Output Status
Not Used
0
1
1
1
0
0
1
0
1
1
1
0
Device ID/Test Mode
1
1
1
Table 27. SR0: DEVICE STATUS REGISTER
NM
NM
D11
TM
D10
D9
D8
D7
D6
D5
D4
OVF
D3
0
D2
0
D1
D0
0
SR0
RCF
FSM
SPIF
CPL
CPF
UVF
HB_QSB
Table 28. SR0 RESPONSE DEFINITIONS
Mnemonic
Value
Comment
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
Test mode inactive (default).
Test mode active.
TM
Registers not cleared (command input and status output registers).
Registers cleared (after mode change to “NORMAL”).
FSM input pin = 0 (FSM not asserted).
FSM input pin = 1 (FSM asserted).
SPI message correct.
RCF
FSM
SPIF
CPL
CPF
UVF
OVF
SPI message failure.
Charge pump in regulation
V(CP, VS) < CP
−OR− VS < VSPWM (Charge Pump Low).
LOW
Half bridge high−side pre−driver activation allowed.
Half bridge high−side pre−driver activation not allowed (Charge Pump Fail).
VS supply in normal range.
VS supply below normal range.
VS supply in normal range.
VS supply above normal range.
D3
D2
Not used.
Not used.
VDS normal − no static or dynamic overload detected.
VDS failure – static or dynamic overload detected (VDS_Hx or VDS_Lx).
Not used.
HB_QSB
D0
Table 29. SR1: HBx STATUS MONITOR REGISTER
NM
NM
D11
0
D10
0
D9
0
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
SR1
SWH4
SWL4
SWH3
SWL3
SWH2
SWL2
SWH1
SWL1
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NCV7544
Table 30. SR1 RESPONSE DEFINITIONS
Mnemonic
Value
Comment
0
1
0
1
GHx output is “low” (default).
GHx output is “high”.
SWHx
GLx output is “low” (default).
GLx output is “high”.
SWLx
Table 31. SR3: HBx VDS MONITOR REGISTER
NM
NM
D11
0
D10
0
D9
0
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
SR3
VDS_H4 VDS_L4 VDS_H3 VDS_L3 VDS_H2 VDS_L2 VDS_H1 VDS_L1
Table 32. SR3 RESPONSE DEFINITIONS
Mnemonic
Value
Comment
0
1
0
1
HBx high−side power switch normal – no static or dynamic overload detected (default).
HBx high−side power switch failure – static or dynamic overload detected.
HBx low−side power switch normal – no static or dynamic overload detected (default).
HBx low−side power switch failure – static or dynamic overload detected.
VDS_Hx
VDS_Lx
Table 33. SR4: HBx CALIBRATION RESULT REGISTER
NM
NM
D11
0
D10
0
D9
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
SR4
CAL_READY CAL_DLY_R[1:0]
CAL_PC_R[1:0]
CAL_DLY F[1:0]
CAL_PC _F[1:0]
Table 34. SR4 RESPONSE DEFINITIONS
Mnemonic
Value
Comment
0
Calibration result not ready or has been read via SPI (default).
CAL_READY
Calibration is successfully performed with a valid result (the bit is reset after SPI read command).
1
00
01
10
11
Rising slope result: VHBx < 15% (default).
Rising slope result: 15% < VHBx < 85%.
Rising slope result: 85% < VHBx < 95 %.
Rising slope result: VHBx >95%.
CAL_DLY_R[1:0]
CAL_PC_R[1:0]
CAL_DLY_F[1:0]
CAL_PC _F[1:0]
00
01
10
11
Rising slope result: VHBx < 5% (default).
Rising slope result: 5% < VHBx < 15%.
Rising slope result: 15% < VHBx < 85 %.
Rising slope result: VHBx > 85%.
00
01
10
11
Falling slope result: VHBx > 85% (default).
Falling slope result: 85% > VHBx > 15%.
Falling slope result: 15% > VHBx > 5%.
Falling slope result: VHBx < 5%.
00
01
10
11
Falling slope result: VHBx > 95% (default).
Falling slope result: 95% > VHBx > 85%.
Falling slope result: 85% > VHBx > 15%.
Falling slope result: VHBx < 15%.
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NCV7544
Table 35. SR5: HBx OUTPUT STATUS REGISTER
NM
NM
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
SR5
HB_OUT4 … HB_OUT1
Table 36. SR5 RESPONSE DEFINITIONS
Mnemonic
Value
Comment
0
1
Output < VHB
Output > VHB
(default).
THR
HB_OUTx
THR.
Table 37. SR7: TEST MODE STATUS REGISTER − SR0.TM = 1: TEST MODE FORMAT
NM
NM
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D0
SR7
Factory Use Only
Table 38. SR7: DEVICE ID/TEST MODE STATUS REGISTER − SR0.TM = 0: DEVICE ID FORMAT
NM
NM
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
SR7
DEV_ID[11:9]
DEV_ID[8:6]
DEV_ID[5:3]
DEV_ID[2:0]
Table 39. SR7 RESPONSE DEFINITIONS: DEVICE ID FORMAT
Mnemonic
ID Type
Value
Comment
000
001
NCV7547
NCV7544
NCV7546
etc.
DEV_ID[11:9]
Device Name
010
011−111
000
001−110
111
Generation 0
DEV_ID[8:6]
DEV_ID[5:3]
DEV_ID[2:0]
Generation
Silicon Revision
Mask Revision
Generation 1 etc.
Generation 0 (NCV7547)
000
001
First Silicon (REV_n.m)
Second Silicon (REV_n+1.m)
etc.
010−111
000
001
Initial Mask Revision (REV_n.m)
First Mask Revision (REV_n.m+1)
etc.
010−111
When not in test mode (SR0.TM = 0), a status request via
CR0.D[10:7] returns SR7.D[11:0] = DEV_ID[11:0] as
defined in Table 39. The default content of SR7 after VCC
POR or wake−up is SR7.D[11:0] = 0.
digital core changed (isolation pocket changed or
unchanged);
• mask revision: interconnect changed (metal and/or
polysilicon/contact/via).
The DEV_ID[5:0] revision value may be changed based
on whether the entire die (silicon) or intermediate layer
(mask) is affected. The revisions can be e.g. classified
accordingly:
The mask revision value is set to DEV_ID[2:0] = 000
whenever the die revision is incremented. Table 40 shows
how the value encoding scheme is used to indicate the device
revision level.
• silicon revision: defined area changed (isolation pocket
or other boundary, bond pad etc. changed/moved) or
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NCV7544
Table 40. DEVICE REVISION LEVEL ENCODING
The CR1.HB_MODEx bits are used to control the polarity
Silicon Revision
DEV_ID[5:3] LEVEL
Mask Revision
DEV_ID[2:0] LEVEL
of the selected half−bridge:
• when CR1.HB_MODEx=0, the low−side driver (PDL)
is in an ON state (i.e. GLx = VGS ≈ V
, see
000
001
010
011
100
101
110
111
A
B
C
D
E
F
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
PDLX
§ Electrical Characteristics: Half−Bridge Pre−Driver
Outputs);
• when CR1.HB_MODEx=1, the high−side driver (PDH)
is in an ON state (i.e. GHx = VGS ≈ V
, see
PDHX
§ Electrical Characteristics: Half−Bridge Pre−Driver
Outputs).
G
H
The CR2.HB_PWMx bits are used to enable PWM mode
control of the selected half−bridge:
• when CR2.HB_PWMx=0, an output is in 100% ON
state according to its CR1.HB_MODEx bit;
Half−bridge Gate Drivers
The half−bridge drivers are used to control the gates of
external logic−level NMOS power switches. The device is
initialized at power−up into a reduced power state
(CR1.DRV_EN = 0, see Table 7, Table 8):
• when CR2.HB_PWMx=1, an output is in PWM with
state according to its CR1.HB_MODEx bit.
The application of a PWM mode selected via the
CR2.HB_PWMx bits to the corresponding output is
performed asynchronous to the PWMx input (i.e. a change
is applied after the rising edge of the CSB signal). Each
half−bridge can be controlled in PWM mode by one of the
PWMx inputs as selected via the CR3.PWMx[1:0] bits
according to Table 41 (see also Table 11, Table 12):
• the charge pump is disabled;
• all gate drive currents are disabled.
• HBx diagnostic test currents are available (see
§ Monitoring of Half−bridge Drivers in OFF−state).
The device is placed into a full power state when
CR1.DRV_EN = 1. The half−bridges are held in
high−impedance state (external NMOS are off) via gate
pull−down structures which are activated during power−up,
while in reduced power state, or when in sleep mode.
Table 41. CR3A/CR3B: PWM SOURCE SELECTION
PWMx0
PWM Source Selection
0
1
Output PWM source is input PWM1
Output PWM source is input PWM2
Control of Half−bridge Drivers
The operation of the drivers is controlled by SPI
configuration individually for each driver. All half−bridges
can be operated in 100% “ON” mode as well as in PWM
mode.
The control schema is shown in Table 42 (see also § SPI
Control Set):
The CR0.HB_ENx bits are used to enable the operation of
the selected half−bridges and to re−start the drivers after a
fault condition:
The application of a selected PWMx input signal routing
to the corresponding output is performed asynchronous to
the PWMx input (i.e. a change is applied after the rising edge
of the CSB signal).
The selected output is controlled via the selected
positive−logic PWMx input (see Figure 8):
• when input PWMx=0, the driver defined by its
HB_MODEx bit is turned OFF (i.e. VGS ≈ 0 V) and its
complementary gate driver is turned ON (i.e. VGS ≈
• when CR0.HB_ENx=0, the GHx and GLx outputs are
V
PDHX
or VGS ≈ V
);
PDLX
disabled (i.e. VGS ≈ 0 V);
• when CR0.HB_ENx=1, the GHx and GLx outputs are
enabled.
Table 42. HBx DRIVER CONTROL
CR0
CR1
CR2
Output
HB_ENx
HB_MODEx
HB_PWMx
Comment
Power Switches Operation Mode
HBx “OFF”
0
1
1
1
1
X
0
1
0
1
X
0
0
1
1
Disable
Low−side “ON”
100% “ON”
PWM Mode
HB1 … HB4
High−side “ON”
Low−side PWM
High−side PWM
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NCV7544
Switching Behavior of Half−bridge Drivers
• when input PWMx=1, the driver defined by its
HB_MODEx bit is turned ON (i.e. VGS ≈ V
The external high−side NMOS switches are controlled
with gate pre−charge and slew phases, while the external
low−side switches are controlled via simple drive stages
supplying a nominal 4x multiple of the selected high−side
driver slew current (see Figure 9 and § Electrical
Characteristics: Pre−driver Slope Control). The timing for
the gate drivers is provided by the digital logic, where the
key parameters can be programmed via SPI in order to adapt
different MOSFET types and application switching speeds.
Each individual half−bridge can be programmed via three
configuration registers, e.g. CR5A and CR5B for HB1, and
CR14 (see § SPI Control Set, Table 15 − Table 17 and
Table 21, summarized in Table 43):
or
PDHX
V
) and its complementary gate driver is turned
PDLX
OFF (i.e. VGS ≈ 0 V).
When multiple PWMx inputs are needed to be active, the
scheduled PWM signals should be offset in time to avoid
degradation of the VDS overload detection due to crosstalk
(see § Overload Protection). The minimum offset should be
based on the t
times appropriate for the respective
PWM_DGL
channels (see § Switching Behavior of Half−bridge Drivers,
Figure 10 and Figure 11).
NOTE: The PWM source selection logic does not
prevent more than one half−bridge output to be
controlled by the same PWMx input.
Table 43. HALF−BRIDGE CONFIGURATION REGISTERS
D0
T_PCx[1:0]
WD
WD
D10
0
D9
D8
D7
D6
D5
D5
D4
D3
D2
D2
D2
D1
CR5A – CR8A
CR5B – CR8B
CR14
BLANKx[1:0]
I_PCFx[2:0]
I_PCRx[2:0]
WD
WD
D10
1
D9
D8
D7
D6
D4
D3
D1
D0
VDSx[2:0]
T_DLY[3:0]
SR_CTRL[2:0]
WD
WD
D10
0
D9
0
D8
0
D7
0
D6
X
D5
X
D4
D3
D1
D0
X
DGL4
DGL3
DGL2
DGL1
GHx
GLx
0
time
PWMx
HB_PWMx
Low-side
ON
High-side
ON
High-side PWM
Low-side PWM
HB_MODEx
HB_ENx
0
time
{02/06/18}
Note 1. GLx and GHx are for the same HBx output control (e.g. HB1: GL1, GH1).
Note 2. GLx and GHx time offset from PWMx via adaptive PWM input de-glitch not shown.
Figure 8. Gate Drive Operation in PWM Mode
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NCV7544
For each individual half−bridge:
• cross−conduction blanking time is selected via the
BLANKx[1:0] bits;
Please refer to § Electrical Characteristics for defined
blanking (t ), pre−charge (t ,
PRCX_R
,
I
BLANKX
PRCX
I
), slew (I
PRCX_F
), delay (t
) and VDS threshold
DLYX
SRX
• pre−charge current is selected via the I_PCRx[2:0]
bits for the rising slope and via the I_PCFx[2:0]
bits for the falling slope;
(VDS
) parametric values.
THRX
NOTE: A proper initial switching parameter set (e.g.
VDS , t , I , I ) for a
I
THRX PRCX PRCX_R SRX, PRCX_F
• pre−charge time for both slopes is selected via the
chosen MOSFET has to be evaluated for a
desired switching speed (see also § Overload
Protection).
T_PCx[1:0] bits;
• slew current for both slopes is selected via the
SR_CTRLx[2:0] bits – this parameter controls the
external NMOS switches’ rise/fall times to adopt proper
EMC performance and minimize switching losses;
When operated in PWM mode, the PWMx input signals
are each provided with a symmetrical de−glitch within a
)
half− bridge’s control logic. The de−glitch time (t
PWM_DGL
• VDS overload detection delay is selected via the
T_DLYx[3:0] bits – this parameter controls when the
VDS overload detection is performed (see § Overload
Protection);
,
,
is adapted to the SPI settings t
t
t
and
BLANKX PRCX DLYX
DGLx as selected for each channel (see § Electrical
Characteristics: Half−Bridge Pre−Driver Outputs &
Pre−driver Slope Control).
• VDS overload detection threshold is selected via the
VDSx[2:0] bits – this parameter controls the VDS
monitoring comparator threshold (see Table 17, Table
18);
The adapted t
avoids mistreatment of the
PWM_DGL
half−bridge drivers by ensuring that a complete turn−on or
turn−off sequence is executed (erratic pulse widths are
thereby avoided) and assures correct operation of the VDS
overload protection (see § Overload Protection)
• adaptive PWM input de−glitch construction when in
half−bridge configuration is selected by DGLx[6:0] bits
(see Figure 10, Figure 11, Table 21 and Table 22).
PWMx_DGL
1
< DEGLITCHED INTERNAL SIGNAL >
time
0
tBLANK
tBLANK
tBLANK
I(GHx)
tPRCx
tPRCx
tTIMEOUT
−I
PRCX_R
−I
SRX
−I
GHx_SS
0
time
+ISRX
+IPRCX_F
I(GLx)
−I
LSX
0
time
+ILSX
{02/06/2018}
Figure 9. Gate Drive Current Evolution
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NCV7544
In order to not overload the charge pump circuit in case of
loss of VS or in case of a disconnected security switch, the
Type 2 de−glitch is selected when CR14.DGLx = 1 (see
Figure 11) and the adapted time is given by:
steady state output current of the high−side gate drivers is
tPWM_DGL + tPRCX ) tDLYX
(eq. 2)
(
limited to I
after t
see I(GHx) in Figure 12
GHX_SS
TIMEOUT
and § Electrical Characteristics: Half−Bridge Pre−Driver
Outputs).
NOTE: To avoid synchronization issues, the de−glitch
type must be selected before beginning PWM of
a load.
Once a switching parameter set for EMC optimization and
stable VDS overload detection has been chosen, the
allowable duty ratio (D) is bounded by the selected adaptive
de−glitch type and PWM frequency such that:
NOTE: Driver turn−ON/OFF via SPI (i.e.
CR1.HB_MODEx bits) includes both the
pre−charge and slew phases, but adapted
de−glitch strategy is not applied.
When operating in PWM mode, type 1 de−glitch is
selected when CR14.DGLx = 0 (see Figure 10) and the
adapted time is given by:
ǒ
Ǔ
fPWM tPWM v D v 1 * fPWM tPWM
DGL
DGL
(eq. 3)
When operating in PWM mode, the timing of the gate
drivers is according to Figure 12.
tPWM_DGL + tBLANKX ) tPRCX ) tDLYX
(eq. 1)
PWMx
1
0
time
tPRCx
tDLYx
tPRCx
tDLYx
tBLANKX
tBLANKX
tPWM_DGL
tPWM_DGL
PWMx_DGL
1
0
< DEGLITCHED INTERNAL SIGNAL >
time
Type 1 PWM De−glitch
PWM_DGL = tBLANKX + tPRCX + tDLYX
t
{03/06/15}
Figure 10. Type 1 PWMx Input De−glitch − CR14.DGLx = 0
PWMx
1
0
time
tPRCx
tDLYx
tPRCx
tDLYx
tPWM_DGL
tPWM_DGL
PWMx_DGL
1
0
< DEGLITCHED INTERNAL SIGNAL >
time
Type 2 PWM De−glitch
tPWM_DGL = tPRCX + tDLYX
{03/06/15}
Figure 11. Type 2 PWMx Input De−glitch − CR14.DGLx = 1
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NCV7544
PWMx_DGL
1
0
< DEGLITCHED INTERNAL SIGNAL >
time
tBLANK
tPRCx
tBLANK
tPRCx
V(GHx)
VPDHX
VGSP
V(HBx)
V(GLx)
VPDLX
time
PGND
V(HBx)
time
tDLYx
tBLANK
tDLYx
VS
0.9 VS
0.5 VS
VHBTHR
0.1 VS
GND
time
High−side
VDS Overload
Detection
Low−side
VDS Overload
Detection
{02/08/2018}
Figure 12. HBx Output Switching in Half−Bridge Configuration
In the pre−charge phase (V
< V ) the GHx output
parameter set and to verify proper setting of the high−side
gate drivers (GHx). The calibration assists optimizing EMC
performance and alignment of the GHx switching slopes
with the VDS overload detection delay time and threshold
to assure stable behavior of the protection strategy (see
§ Overload Protection).
GHX
GSP
delivers the selected rise (I
) or fall (I ) current
PRCX_F
PRCX_R
for the selected time (t
), and in the slew phase (V
≤
PRCx
GSP
VGHX ≤ VPDHX) the GHx output delivers the selected current
(I ) for up to the gate drive timeout time (t ).
SRX
TIMEOUT
After t , the GHx output delivers the timeout current
TIMEOUT
(I
). The GLx output always delivers a multiple (I
)
A calibration detection unit, consisting of 4 multiplexed
high−speed comparators, samples the voltage at the desired
GHx_SS
LSX
of the selected slew current (see Figure 9 and § Electrical
Characteristics: Half− Bridge Pre−Driver Outputs,
HBx input at a selected calibration sample time (see
,
Pre−driver Slope Control)
t
t
in § Electrical Characteristics: Slope
.
CAL_PCx CAL_DLYx
Control Calibration Unit). A complete calibration cycle
consists of sampling both the rising and falling switching
slopes, and the encoded calibration result is stored in the
device’s calibration register (SR4).
Slope Control Calibration Unit
A slope control calibration unit is implemented in order to
allow adjustments to a selected MOSFET’s initial switching
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30
NCV7544
Calibration is enabled when the calibration register (CR4)
and falling edges are completed (see Figure 13). The
detection results are stored in the calibration result register
SR4 (summary Table 44 − see also Table 33):
is written (summary Table 44 − see also Table 13):
• the desired HBx input is selected by the
CR4.CAL_SEL[2:0] bits where the resulting binary
code refers directly to the selected half−bridge
(e.g. 100 = HB4);
The CAL_READY bit indicates that when:
• SR4.CAL_READY = 0, calibration has not been
executed OR the calibration result has been read;
• SR4.CAL_READY = 1, successful detection was
performed for both slopes AND a valid comparator
output state is delivered.
• the detection pre−charge and delay sample times
(t
and t
) for calibration of the desired
CAL_PCx
CAL_DLYx
input are selected individually by the
CR4.CAL_PC[3:0] bits and by the
CR4.CAL_DLY[3:0] bits for both the rising and falling
slopes.
As long as the CAL_READY bit is not set (≠ 1), the
calibration of a particular slope for the selected channel may
be repeated. Calibration may be terminated by sending
CR4.CAL_SEL[2:0] = 000.
The calibration result is encoded in the SR4.
CAL_PC_R[1:0] bits and the SR4.CAL_DLY_R[1:0] bits
for the rising slope and in the SR4. CAL_PC_F[1:0] bits and
the SR4.CAL_DLY_F[1:0] bits for the falling slope
according to Table 45.
The calibration unit is turned off when
CR4.CAL_SEL[2:0] = 000 (POR default) is selected (see
also Table 14).
Detection is started with the next edge of a routed PWMx
input signal (see § Control of Half−bridge Drivers) on the
selected channel and detection is finished when both rising
Table 44. HBx CALIBRATION CONTROL AND RESULT REGISTERS
WD
WD
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CR4
CAL_DLY[3:0]
CAL_PC[3:0]
CAL_SEL[2:0]
NM
NM
D11
0
D10
D9
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
SR4
0
CAL_READY CAL_DLY_R[1:0]
CAL_PC_R[1:0]
CAL_DLY F[1:0]
CAL_PC _F[1:0]
Table 45. CALIBRATION RESULT RELATIVE TO HBx SAMPLE TIME
Relative HBx Level Detected
at Selected Sample Times
Mnemonic
Value
Comment
Start of Rising Slope
00
01
10
11
VHBx < 5%
5% < VHBx < 15%
15% < VHBx < 85%
VHBx > 85%
Pre−charge too low.
Pre−charge within target.
Pre−charge too high.
CAL_PC_R[1:0]
Pre−charge far too high.
End of Rising Slope
CAL_DLY_R[1:0]
00
01
10
11
VHBx < 15%
15% < VHBx < 85%
85% < VHBx < 95 %
VHBx >95%
Transition far too slow.
Transition slightly too slow.
Gate drive setting correct.
Transition too fast.
Start of Falling Slope
CAL_PC _F[1:0]
00
01
10
11
VHBx > 95%
95% > VHBx > 85%
85% > VHBx > 15%
VHBx < 15%
Pre−charge too low.
Pre−charge within target.
Pre−charge too high.
Pre−charge far too high.
End of Falling Slope
CAL_DLY_F[1:0]
00
01
10
11
VHBx > 85%
85% > VHBx > 15%
15% > VHBx > 5%
VHBx < 5%
Transition far too slow.
Transition slightly too slow.
Gate drive setting correct.
Transition too fast.
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31
NCV7544
The temporal position (see Figure 13) of the target
transition detection point (e.g. 10%, 90%) with respect to
or t (or in normal operation, t ) of
• the I
slew phase current setting.
SRX
Calibration may be performed at the application level
during module end−of−line (EOL) test where the (adjusted)
settings may be stored in a microcontroller’s EEPROM. In
order to maintain stable function and proper EMC
performance with temperature drift and output load
variations, the calibration can be verified/updated on a
sample basis during normal application operation.
t
CAL_PCx
CAL_DLYx
DLYX
the channel selected for calibration is dependent upon:
• the PWMx_DGL resulting from the channel’s operating
configuration (see § Switching Behavior of Half−bridge
Drivers, Figure 10 and Figure 11);
• the t
cross−conduction blank time setting as
BLANKX
applicable;
• the t , I
and I
pre−charge phase time
PRCX PRCX_R
and current settings;
PRCX_F
PWMx_DGL
< DEGLITCHED INTERNAL SIGNAL >
PWMx_DGL
BLANK
tBLANKx
tBLANKx tBLANKx
tPRCx
tPRCx
PRE−CHARGE
SLEW
tDLYx
tDLYx
(High−side Overload)
(Low−side Overload)
time
V(HBx)
VCALR_U
90%
VCALR_L
95%
85%
RISING
SLOPE
FALLING
SLOPE
VCALF_U
15%
10%
VCALF_L
5%
time
CALx
tCAL_PCx
tCAL_PCx
CAL PRE−CHARGE
CAL SLEW
tCAL_DLYx
tCAL_DLYx
CAL_PC_R[1:0]
CAL_DLY_R[1:0]
CAL_PC_F[1:0]
CAL_DLY_F[1:0]
“01”
“10”
“01”
“10”
“1”
CAL_READY
time
{02/07/2018}
Figure 13. HBx Slope Control Calibration
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NCV7544
OVERLOAD PROTECTION
Static Overload Protection
delay, CMP2 and CMP3 in Figure 14). A single detection
)
A static VDS monitoring technique is used to protect the
external MOS power switches in case of overload resulting
from short circuit conditions applied after activation of the
power switches (“short circuit 2” condition).
delay time (t
is used during switching of each of the
DLYX
high−side and the low−side external MOS. The detection
delay at each input is selected individually by the
T_DLY[3:0] bits in the HBx configuration “B” registers (see
The thresholds of the VDS monitoring comparators
(CMP1 and CMP4 in Figure 14) are SPI programmable (see
§ Electrical Characteristics: Half−Bridge Diagnostics) for
each individual half−bridge via the VDSx[2:0] bits in the
HBx configuration “B” registers (see Table 17, Table 18).
§ SPI Control Set). The detection delay t
is chosen
DLYX
based on the value of t
for the rising slope of the
CAL_R
high−side MOS as determined from the calibration result
(seeCAL_DLYR[3:0] in § Slope Control Calibration Unit).
The appropriate latch is set (after the adapted t
PWM_DGL
When a switch is in the ON−state (t > t
the pre−charge phase) and its drain−source voltage exceeds
the programmed VDS threshold:
after end of
− see Figure 10 and Figure 11) at the start of the switch
activation (see V(HBx) in Figure 12). In the case of the
DLYx
high−side MOS, the delay time t
is started at the end of
DLYX
the pre−charge time (t
MOS, the delay time t
). In the case of the low−side
is started concurrent with the
• the corresponding half−bridge’s GHx and GLx drivers
PRCX
(
are latched off immediately after a de−glitch time see
DLYX
GLx turn−on current (see I(GLx) in Figure 11). At the end
of time t the switching node voltage is compared with
t
in § Electrical Characteristics: Half−Bridge
DGL_STAT
);
Diagnostics
DLYX
the appropriate VDS
detection threshold (see § Electrical Characteristics:
Half−Bridge Diagnostics).
or VDS
overload
THR_R
THR_F
• the SR0.HB_QSB Quick Status Bits and the
appropriate VDS_Hx or VDS_Lx bit is latched in the
corresponding VDS monitor status register
(see Table 31 and Table 32)
When a switch is being activated and:
• the output voltage has not crossed the appropriate
Please refer to § Output Fault (Local) Protection to restart
the half−bridge drivers after a shutdown event.
threshold by the end of t
, the latch is reset after the
and both high and low−side
DLYX
de−glitch time t
DGL_DYN
power switches are deactivated and the appropriate
status bit (see § SPI Diagnosis Set) is latched in the
corresponding VDS monitor register (overload
detected);
NOTE: Additional protection via use of current sensing
in the low−side path of the power MOSFETs
(see Figure 2) may be necessary in order to
avoid destruction due to soft short condition.
• the output voltage has crossed the appropriate threshold
Dynamic Overload Protection
by the end of t
, the latch stays in set condition and
DLYX
A dynamic switching slope monitoring technique is used
to protect the external MOS power switches in case of
overload resulting from short circuit conditions applied
before or during activation of the power switches (“short
circuit 1” condition).
the power switches remain activated (no overload
detected).
Please refer to § Output Fault (Local) Protection to restart
the half−bridge drivers after a shutdown event.
The output voltage at the switching nodes (HBx) is
monitored during each of the GHx and the GLx turn−on
phases by a high speed comparator (< 100 ns propagation
NOTE: The same VDS_Hx and VDS_Lx status bits in
register SR3 are used to report either static or
dynamic overload condition.
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NCV7544
HBx Diagnostic & Overload Protection
VDSTHR_S
CR1.D[3:0]
STATIC VDS
HB_MODEx
+
CMP1
tDGL_STAT
3 x tDLY
tDLY
−
VDSTHR_R
VS
+
tDGL_DYN
CMP2
SECURITY
SWITCH
−
DYNAMIC VDS
VBAT_P
GHx
(reset dominant)
R
Q
PDH
LATCH
Q
S
VDS_HX
HBx
LOAD
SR3.D[7:0]
VDS_LX
S
Q
Q
GLx
PDL
LATCH
R
(reset dominant)
DYNAMIC VDS
3−5
m
+
PGND
CMP3
tDGL_DYN
tDLY
3 x tDLY
tDGL_STAT
−
VDSTHR_F
+
CMP4
−
STATIC VDS
VDSTHR_S
SR5.D[3:0]
HB_OUTx
+
CMP5
VHBTHR
−
TRANSPARENT VS/2
= INDIRECT PATH
{08/12/2015}
Figure 14. HBx Diagnostic and Overload Protection
Gate Protection Features
OFF−state Monitoring of Half−bridge Drivers
The half−bridge gate drivers provide integrated gate
protection features for the external power MOSFETs:
In order to support functional safety and to avoid
unintended motor activation, the status of each of the
half−bridge gate drivers can be monitored by SPI diagnosis
(see § Gate Driver Status Monitoring). The switch nodes
(i.e. HBx) status can be monitored by SPI communication
via the half−bridge output status register (SR5.D[7:0] − see
Table 35, Table 36). The system response depends on the
load configuration; the test procedure has to be provided by
the supervising microcontroller.
• a passive pull−down resistor R
keeps the MOSFET
GSX
in OFF−state, when no control of the device is available
(see § Package Pin Description and § Electrical
Characteristics: Half−Bridge Pre−Driver Outputs);
• a clamping structure limits the gate−source voltage to
+V
or to −V
in order to protect the
GSX_CLP
GSX_CLN
power MOSFETs from destruction via e.g. gate oxide
failure (see § Electrical Characteristics: Half−Bridge
Pre−Driver Outputs).
Several test current sources (I
– see § Electrical
TST
Characteristics:
Half−Bridge
Diagnostics)
and
comparators are implemented in order to provide OFF−state
diagnosis of the power MOSFET half−bridges.
The resistors and clamping structures are available in all
operating modes, including SLEEP MODE and in case of loss
of supply voltage.
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NCV7544
Operating Modes
The diagnostic consists of (see Figure 14 and Figure 15):
• a high−side and a low−side test current source at each
odd−numbered HBx feedback input;
The operating modes of the device are shown in the
diagram of Figure 16. The logic input pin pull up / pull down
resistors and the integrated gate protection pull−down
resistors and clamping structures (see § Gate Protection
Features) are available in all operating modes.
• a comparator (CMP5) at each HBx feedback input.
Provided the device is in NORMAL MODE (see §Operating
Modes) and no global failure (see § Device Fault (Global)
Protection) has been detected, the test current sources can be
activated individually by the TST_HSx and TST_LSx bits
in the HB diagnosis register (CR12.D[5:0] − see Table 19,
Table 20). Active pull−down current sources are disabled in
all GHx when any test current is activated via CR12. Passive
pull−down structures are always present.
The SLEEP MODE is the default mode after applying VCC
(VCC < VCC ) and while VCC > VCC
PORF
(power−on
PORR
reset) prior to wake−up of the device. During SLEEP MODE:
• the device is inactive and all outputs are disabled.
The device enters NORMAL MODE after applying the
wake−up signal (i.e. RSTB 0 → 1). During NORMAL MODE:
• the device is active (RSTB = 1);
• the entire device functionality is available;
• the SPI can be used to provide control and diagnosis of
the device.
NOTE: Both TST_HSx and TST_LSx test currents can
be turned on simultaneously.
HBx OFF−State Diagnostic
When the device enters NORMAL MODE the internal
registers and settings are cleared to default values and the
SR0.RCF bit inside the device status register is set (see
Table 27, Table 28).
The device enters FAILSAFE MODE when the device is
active and either a SPI failure condition is detected or the
external fail input (FSM) is activated i.e. FAILSAFE =
(RSTB = 1) AND [(SPIF=1) –OR– (FSM=1)].
VS
ITST
HB1, HB3
R
CR12.TST_HSx
SR5.D[3:0]
HB1 ... HB4
+
HB_OUTx
CMP5
In FAILSAFE MODE:
-
ITST
HB1, HB3
• the half−bridge gate drive outputs (GHx, GLx) are
disabled immediately;
R
VHBTHR
CR12.TST_LSx
• the HBx test currents (see § OFF−state Monitoring of
Half−bridge Drivers) are disabled immediately;
• the CPSW output is deactivated (the external MOS
half−bridge switches may be locked additionally by an
optional external security switch which can be under
control of a separate supervisory microcontroller (see
“WD_EN” in Figure 2) in order to support functional
safety even in case of logic issues/single point failures);
• the charge pump is disabled;
PGND
AGND
= INDIRECT PATH
{08/07/2018}
Figure 15. Half−bridge OFF−state Diagnostic
• SPI control is not possible.
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NCV7544
VCC < VCCPOR
VCC > 0
SLEEP
MODE
VCC < VCC POR
−OR−
VCC < VCCPOR
−OR−
RSTB = 0
RSTB = 0
VCC>VCC POR
−AND−
RSTB=1
FAILSAFE
MODE
NORMAL
MODE
FSM = 0
−AND−
SPIF = 0
SRx.NM = 0
SRx.NM = 1
FSM = 1 −OR− SPIF = 1
Figure 16. Operating Modes State Diagram
Although SPI control of the outputs is not possible in
FAILSAFE MODE, the status registers are not cleared during
the transition from NORMAL MODE to FAILSAFE MODE. The
device status therefore is accessible in FAILSAFE MODE as
long as the SPI interface is available (i.e. as long as VCC is
present). The SPI can thus be used in FAILSAFE MODE to
provide limited diagnosis of the device (CR0.SRA_MODE,
CR0.SRA[2;0]) and to re−enter NORMAL MODE.
Re−entering NORMAL MODE after FAILSAFE MODE is
achieved by toggling the WD bit while FSM = 0. After this
mode change the internal registers and settings are cleared
and the SR0.RCF bit inside the device status register is set
(see Table 27, Table 28).
PROTECTION AND DIAGNOSIS
NOTE: An external aluminum electrolytic capacitor at
the VS terminal is necessary to handle the
turn−off energy of the motors in emergency
condition.
again and the restart will not be successful. The restart will
be only successful after the error condition is removed. It is
recommended to use OFF state diagnosis (see § OFF−state
Monitoring of Half−bridge Drivers) to check the HBx node
for any failure condition before restarting the output.
Output Fault (Local) Protection
The external power MOSFET switches are protected
against overload condition (see § Overload Protection) in
NORMAL MODE by VDS monitoring. In case of a VDS
overload failure, the corresponding pre−driver outputs are
latched off (GHx = L AND GLx = L) after a de−glitch time
and the status is reported in the VDS monitor register SR3
(see Table 32).
Device Fault (Global) Protection
The device is protected against all relevant failure
conditions inside the automotive application. In case of a
fault condition, the affected outputs are latched off
immediately after a de−glitch time and the status is reported
the device status register (SR0 − see Table 27, Table 28).
To restart the device:
To restart a faulted half−bridge:
• the diagnosis has to be de−latched by reading the
corresponding failure flag;
• the diagnosis has to be de−latched by reading the
corresponding failure flag (see § SPI Diagnosis Set);
• the functionality has to be restarted by use of the
corresponding control bit (see § SPI Control Set).
• the output has to be restarted via the corresponding bits
in the CR0.HB_ENx register (see § SPI Control Set).
Charge Pump Monitoring
As long as a failure flag is not de−latched via SPI status
read, a faulted output cannot be turned back on. If the failure
condition is still present at a restart, the error flag will be set
The high−side pre−driver outputs are protected by charge
pump monitoring (see § Charge Pump, Figure 5 and
Figure 6):
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36
NCV7544
• when the battery supply voltage VS is below the
minimum supply voltage for a regulated charge pump
voltage OR V(CP,VS) drops below the minimum
• GH pull−down current is reduced to 1 mA
X
typ.(register contents are not changed − the current will
revert to its prior value after VS over−voltage is
resolved);
output voltage CP
this status is reported by the
LOW
SR0.CPL bit in the device status register immediately
after a de−glitch time t (see Table 27,
• the HBx test currents (see § OFF−state Monitoring of
Half−bridge Drivers) are disabled immediately.
CPL_DGL
Table 28). During this condition it should be considered
for the microcontroller to adopt a PWM duty ratio
management schema in order to minimize charge pump
loading while ensuring smooth motor operation.
The VS over−voltage condition is reported by the
SR0.OVF bit in the device status register (see Table 27,
Table 28). When the battery supply voltage is in
over−voltage condition VS > VS
the SR0.CPF bit is
OVSDR
• when the charge pump output voltage V(CP, VS) drops
masked. Please refer to § Device Fault (Global) Protection
to restart the outputs after a shutdown event.
A VCC overvoltage condition can occur during
breakdown of the external voltage regulator. Please refer to
§ Failure of External Voltage Regulator for details.
below the charge pump fail threshold CP , the half
FAIL
bridge high−side and low−side gate drivers are latched
off immediately after a de−glitch time t and the
CPF_DGL
status is reported by the SR0.CPF bit in the device
status register (see Table 27, Table 28).
• when the battery supply voltage VS is in the nominal
Under Voltage Condition
operation range VS
< VS < VS
the full
PWM
OVSDR
In case of VS under voltage condition:
• all outputs (GHx, GLx) are disabled immediately after
PWM operation of the GHx and GLx outputs is
allowed;
the de−glitch time t
and the condition is reported
UVDGL
• when the battery supply voltage is in over−voltage
by the SR0.UVF bit in the device status register (see
Table 27, Table 28);
condition VS > VS , the SR0.CPF bit is masked;
OVSDR
• when the battery supply voltage is in over−voltage
• the charge pump circuit and the switched charge pump
output (CPSW) are still functional in order to keep the
optional reverse battery and security switches active.
condition VS < VS < CP the charge pump
OVSDF
OV
− including the CPSW output − is functional but the
GHx outputs are shut down;
Please refer to § Device Fault (Global) Protection to
restart the outputs after a shutdown event.
In case of VCC under voltage condition (power−on reset
• when the battery supply voltage exceeds the maximum
supply voltage for the charge pump VS > CP the
OV
charge pump is disabled and the charge pump buffer
capacitor is discharged to VS in order to protect the
device from destruction.
condition, VCC < VCC
):
POR
• the device enters SLEEP MODE immediately without
de−glitch time;
Please refer to § Device Fault (Global) Protection to
restart the outputs after a shutdown event.
• logic input pull−up/down resistors, GHx & GLx output
pull−down resistors, and VCC under voltage lockout
assure safe operating states for all outputs.
Over−voltage Condition
During VS over−voltage, the behavior of the gate drivers
(GHx and GLx) depends on the programmed operation
mode:
To restart the device after this condition a wake−up
sequence is necessary (see § Operating Modes).
• the high side gate drivers (GHx) are latched off
Logic I/O Plausibility Check
The logic I/O pins are protected against mistreatment by
input de−glitch circuits. The de−glitch circuits are
implemented digitally, refer to § Electrical Characteristics:
Digital I/O for values.
immediately after de−glitch time t
(see
OVDGL
§ Electrical Characteristics: VS Supply) in order to
protect the application from over load condition; while
the low−side gate driver outputs (GLx) are operable in
order to provide controlled braking (e.g. for lift gate
motors);
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37
NCV7544
FUNCTIONAL SAFETY SUPPORT STRATEGY
The device uses a closed−loop verification strategy in
microcontroller by means of the SPI communication (see
Figure 14 and § SPI Diagnosis Set):
order to avoid mistreatment of the outputs and to support
functional safety. The verification strategy is implemented
based on the features in the following sections.
The output voltage levels of the half−bridge switches are
monitored by the transparent VS/2 comparators. The
comparator states are not latched and the current node states
are indicated by the HB_OUTx bits in the SR5 half−bridge
output status register. The controller can use the motor status
information for correlation of the operating mode, OFF state
diagnosis, or for controlled brake activation.
SPI Communication Monitoring
The SPI is protected against communication errors by use
of the WD toggle bit and protocol check features (see § SPI
Interface). In case of SPI communication error the device
enters FAILSAFE MODE immediately (see § Operating
Modes). A correct communication is reported in the NM bit
(see § SPI Diagnosis Set).
External Fail Mode Activation
The FAILSAFE MODE can be also activated by an external
signal (e.g. watchdog circuitry) via the FSM input. In case
of a malfunction of the microcontroller, an external
watchdog can cause the device to enter FAILSAFE MODE (see
§ Operating Modes).
Gate Driver Status Monitoring
The correct activation of the half−bridge drivers can be
monitored by the microcontroller by means of SPI
communication (see § SPI Diagnosis Set). The switching
status of the output drivers is indicated by the SWLx and
SWHx bits in the half− bridge status monitor register SR1.
The bit value corresponds to the logic status of the driver. In
PWM mode, both SWHx = 1 and SWLx = 1.
Failure of External Voltage Regulator
In case of breakdown of the external voltage regulator, the
device and the application’s VCC node may be protected
against overload by use of an optional external voltage
In case of a discrepancy between control data and status
information from the device, the microcontroller has to
drive the device into FAILSAFE MODE in order to avoid
mistreatment of the motor drives, then transition the device
to NORMAL MODE for reprogramming.
limiter circuit which must limit the voltage to VCC
Figure 2 and § MAXIMUM RATINGS).
The SPI port’s SO pin is protected against reverse biasing
by use of a back−to−back switch. The reverse voltage for this
(see
MAX
condition is limited to V_SO
(see § MAXIMUM
MAX
RATINGS).
Output Status Monitoring
The status of the MOS switches and the motor connection
lines can be monitored during NORMAL MODE by the
FLEXMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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38
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P (PUNCHED)
CASE 485CZ
ISSUE A
DATE 29 JUL 2013
SCALE 2:1
NOTES:
L
D
A B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
L
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
DIM MIN
MAX
0.90
0.05
0.15
C
A
A1
A3
b
0.80
−−−
0.20 REF
0.20
0.15
C
TOP VIEW
0.30
D
D2
E
5.00 BSC
3.20
3.40
(0.15)
(0.10)
(A3)
A
5.00 BSC
DETAIL B
0.10
C
C
E2
e
L
3.20
0.50 BSC
0.30
3.40
DETAIL B
ALTERNATE
0.50
CONSTRUCTION
0.08
A1
SEATING
PLANE
NOTE 4
C
SIDE VIEW
GENERIC
MARKING DIAGRAM*
M
0.10
C A B
1
D2
DETAIL A
32X L
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
9
8
E2
b
1
24
32X
XXXXX = Specific Device Code
M
0.10
C A B
32
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
e
WL
YY
WW
G
M
0.10
C A B
e/2
NOTE 3
M
0.05
C
BOTTOM VIEW
(Note: Microdot may be in either location)
RECOMMENDED
*This information is generic. Please refer
to device data sheet for actual part
marking.
SOLDERING FOOTPRINT
5.30
3.60
32X
0.62
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
5.30
3.60
PKG
OUTLINE
32X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON87072E
QFN32 5x5, 0.5P (PUNCHED)
PAGE 1 OF 1
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相关型号:
NCV7546MWTXG
FLEXMOS™ Six Channel Half-Bridge MOSFET Pre-Driver for Motor Control Application
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