NCV7547MWTXG [ONSEMI]
七沟道半桥 MOSFET 预驱动器,用于电机控制应用;型号: | NCV7547MWTXG |
厂家: | ONSEMI |
描述: | 七沟道半桥 MOSFET 预驱动器,用于电机控制应用 电动机控制 电机 驱动 驱动器 |
文件: | 总42页 (文件大小:522K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NCV7547
FLEXMOSt 7x Half-bridge
MOSFET Pre-driver
The NCV7547 programmable seven channel half−bridge MOSFET
pre−driver is one of a family of FLEXMOS automotive grade products
for driving logic−level NMOS FETs. The product is controllable by a
combination of serial SPI and CMOS−compatible parallel inputs. An
internal power−on reset provides controlled power up. A reset input
allows external re−initialization and a failsafe input allows the device
to be safely disabled in the event of system upset.
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Each channel independently monitors its external MOSFETs’
drain−source voltages for fault conditions. Overload detection
thresholds are SPI−selectable and the product allows different
detection thresholds for each channel.
The FLEXMOS family of products offers application scalability
through choice of external MOSFETs.
1
48
QFNW48
7x7, 0.5P
CASE 484AJ
Features
MARKING DIAGRAM
• Supports Functional Safety Compliance
• 7 Half−bridge Pre−drivers for External Logic−level NMOS FETs
♦ One Channel with Separated High−side & Low−side Pre−drivers
Configurable as a Half−bridge or as Independent Pre−drivers
1
ON
NCV7547
• Integrated Charge Pump for:
AWLYYWW
G
♦ High−side Gate Drive
♦ Switched Reverse Battery Protection
• 5 V CMOS Compatible I/O:
♦ 16−bit SPI Interface for Control and Diagnosis
♦ Reset and Failsafe Inputs
NCV7547 = Specific Device Code
A
= Assembly Location
= Wafer Lot
WL
YY
WW
G
= Year
= Work Week
= Pb−Free Package
♦ 4 PWM Control Inputs
• Programmable:
♦ Slew Rate Control
♦ Overload Protection Thresholds
ORDERING INFORMATION
• Low Quiescent Current
†
Device
NCV7547MWTXG
Package
Shipping
• Wettable Flanks Pb−free Packaging
QFN−48
(Pb−Free)
2500 / Tape &
Reel
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Benefits
• Scalable to Load by Choice of External MOSFET
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
February, 2019 − Rev. 1
NCV7547/D
NCV7547
VCC VS
CP CPSW
CSB
SCLK
SI
C1A
C1B
C2A
C2B
POWER
SUPPLY
CHARGE
PUMP
SPI
SO
RSTB
FSM
SFL
PWM1
PWM2
PWM3
PWM4
NCV7547
N/C
N/C
N/C
N/C
N/C
CP SFL
PDH
GH1
HB1
GL1
HB1
PDL
SFL CP
PDH
PGND
CP SFL
GH7
SH7
DL7
GL7
LOGIC
CORE
PDH
GH2
HB2
GL2
HB7
HB2
PDL
PDL
PGND
PGND
CP SFL
SFL CP
PDH
PDH
GH3
HB3
GL3
GH6
HB6
GL6
HB3
HB6
PDL
PDL
PGND
PGND
CP SFL
SFL CP
WATCH
DOG
PDH
PDH
GH4
HB4
GL4
GH5
HB5
GL5
HB4
HB5
FAILSAFE
PDL
PDL
PGND
PGND
AGND DGND PGND
Figure 1. Block Diagram
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2
NCV7547
REVERSE
PROTECT
SECURITY
SWITCH
VBAT
VBAT _P
WD_EN
VS
CP CPSW
C1A
C1B
C2A
C2B
GH1
HB1
GL1
OPTIONAL
14V
LIMITER
VCC
5V
M
M
NCV7547
VCC
GH2
HB2
GL2
CSB
SCLK
SI
SO
RSTB
PWM1
PWM2
PWM3
PWM4
GH3
HB3
GL3
M
M
M
GH4
HB4
GL4
WATCHDOG
FSM
N/C
N/C
N/C
N/C
N/C
GH5
HB5
GL5
GH7
SH7
DL7
GL7
GH6
HB6
GL6
AGND PGND DGND
A/D
3−5
3−5
3−5
mW
mW
mW
Figure 2. Application Diagram
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3
NCV7547
PACKAGE PIN DESCRIPTION
Pin
Label
Function
Description
48 PIN QFN EXPOSED PAD PACKAGE
42
36
VS
Main Power Supply
Logic Supply
Main high−power device supply (battery) input; VDS sense reference node for the half−
bridge high−side drivers. An external ceramic bypass capacitor shall be connected be-
tween VS and GND close to the pin.
VCC
SPI block and internal logic and low power (analog) supply input. An external ceramic
bypass capacitor shall be connected between VCC and GND close to the pin.
24
25
13
AGND
DGND
PGND
Signal Ground
Digital Ground
Power Ground
Low power return path; reference for the analog circuitry.
Low power return path; reference for the digital circuitry.
High power return path; reference for the half−bridge drivers; VDS sense reference node
for the half−bridge low−side drivers.
45
46
47
48
43
C1A
C1B
C2A
C2B
CP
Charge Pump
Switch Node
Switching nodes for external ceramic charge pumping capacitors 1 & 2.
Charge Pump
Output
Charge pump output; an external ceramic buffer capacitor shall be connected between
CP and VS to provide stable output voltage during transient noise on VS.
44
29
34
CPSW
RSTB
FSM
Charge Pump
Switched charge pump output; activates external reverse battery and security power
MOSFET switches via SPI.
Switched Output
Wake Input
Fail−safe Input
PWM Inputs
Digital input with falling edge digital de−glitch and pull−down resistor; active low master
reset; the device is in wake state when the pin is high.
Digital input with symmetrical digital de−glitch and pull−down resistor; active high fail−safe
mode (can be set via an external watchdog circuit).
33
32
31
30
26
27
28
35
PWM1
PWM2
PWM3
PWM4
CSB
Digital inputs with symmetrical adaptive digital de−glitch and pull−down resistor; provide
PWM signals to the half−bridge pre−drivers.
SPI Chip Select
SPI Clock
Digital input with pull−up resistor; active low chip select.
Digital input with pull−down resistor.
SCLK
SI
SPI Serial Input
SPI Serial Output
Digital input with pull−down resistor.
SO
Digital tri−state output with high−side path protection to prevent VCC back−bias in the
event of an external voltage regulator failure or short to VS.
2
5
GH1
GH2
GH3
GH4
GH5
GH6
HB1
HB2
HB3
HB4
HB5
HB6
High−side
Pre−driver
Output
High−side pre−drivers with pull−down resistor to HBx switch nodes; gate drive for external
logic−level N−MOS FETs.
8
11
15
18
3
Half−bridge
Switch Node
Monitoring inputs for external half−bridge switches 1:6 with pull−down resistor to AGND;
high−side MOSFET source node; low−side MOSFET drain node.
6
9
12
16
19
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4
NCV7547
PACKAGE PIN DESCRIPTION
Pin
Label
Function
Description
48 PIN QFN EXPOSED PAD PACKAGE
1
4
GL1
GL2
GL3
GL4
GL5
GL6
GH7
Low−side
Pre−driver
Output
Low−side pre−drivers with pull−down resistor to PGND;
gate drive for external logic−level N−MOS FETs.
7
10
14
17
22
High−side Pre−driver High−side pre−driver with pull−down resistor to SH7 input; gate drive for external logic−
Output
level N−MOS FETs.
23
21
20
SH7
DL7
GL7
High−side
Monitoring input for external high−side switch 7 with pull−down resistor to AGND; high−
Source Node
side MOSFET source node.
Low−side
Drain Node
Monitoring input for external low−side switch 7 with pull−down resistor to AGND; low−side
MOSFET drain node.
Low−side Pre−driver Low−side pre−driver with pull−down resistor to PGND;
Output
gate drive for external logic−level N−MOS FETs.
41
40
39
38
37
N/C
N/C
N/C
N/C
N/C
EP
–
No internal connection.
Exposed Pad
Connect to GND.
Exposed Pad
(EP)
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
32
31
30
29
28
27
26
25
GL1
GH1
HB1
GL2
GH2
HB2
GL3
GH3
HB3
GL4
GH4
HB4
VCC
SO
3
FSM
4
PWM1
PWM2
PWM3
PWM4
RSTB
SI
5
6
NCV7547
7
8
9
10
11
12
SCLK
CSB
DGND
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. 32 Pin 5 x 5 mm Exposed Pad Pin−out (Top View)
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5
NCV7547
MAXIMUM RATINGS (Except as noted, voltages are with respect to AGND = DGND = PGND = GND.)
Rating
Symbol
VS
Value
Unit
VS Supply
DC: 2 min @ 25°C
−0.3 to 28
V
MAX
AC: ISO7637 Pulse 5b, 400 ms @ 25°C
40
VCC Supply
VCC
−0.3 to 7.0
V
V
MAX
Output Voltage:
CP, CPSW
SO
V_OUT
V_SO
−0.3 to 40
−0.3 to 20
MAX
MAX
Input Voltage:
FSM, C1A, C1B, C2A, C2B
V_IN
V_IN
V_IN
I_IN
T
−0.3 to 40
−1.0 to 40
−0.3 to 20
5.0
V
V
MAX1
MAX2
MAX3
MAX
J
Input Voltage (Clamped):
HBx, SH7, DL7
Input Voltage: CSB, SCLK, SI, RSTB, PWMx
V
Input Current (Clamped): CSB, SCLK, SI, RSTB, FSM, PWMx, GHx, GLx
Junction Temperature
mA
°C
°C
°C
−40 to 150
−55 to 150
260
Storage Temperature
T
STG
Peak Reflow Soldering Temperature: Lead−free 60 to 150 seconds at 217°C (Note 1)
T
PK
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. See or download ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
ATTRIBUTES
Characteristic
Symbol
Value
Unit
ESD Capability:
V
ESD_HBM
Human Body Model per AEC−Q100−002
All pins
≥
≥
2.0
4.0
kV
kV
VS, HBx, SH7, DL7
Charged Device Model per AEC−Q100−011
All Pins
V
ESD_CDM
≥
≥
500
750
V
V
Corner Pins
Moisture Sensitivity (Note 1)
Package Thermal Resistance – Still−air, P = 1 W (Uniform Power Density)
MSL
1
–
°C/W
IN
Junction–to–Ambient, Rq
(Note 2)
(Note 3)
Rq
Rq
RY
JPAD
61.7
37.5
10.8
JA
JA
JA
Junction–to–Exposed Pad, RY
JPAD
2. Based on JESD51−3, 1.2 mm thick FR4, 2S0P PCB, 1 oz. signal, 4 thermal vias to 28 x 28 mm 1 oz. spreader on bottom layer.
3. Based on JESD51−7, 1.2 mm thick FR4, 1S2P PCB, 1 oz. signal, 4 thermal vias to 76 x 76 mm 1 oz. internal spreader planes.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VS
Min
7.0
4.5
3.5
0
Max
18.0
5.5
Unit
V
Main Power Supply Voltage
Logic Power Supply Voltage
Logic High Input Voltage
OP
VCC
V
OP
IN_HIGH
V
VCC
V
OP
Logic Low Input Voltage
V
1.5
25
V
IN_LOW
Half−bridge Output PWM Rate
f
–
kHz
nF
MHz
ms
PWM
Charge Pump Capacitors (C1, C2, CCP)
SPI Clock Frequency
−
220
0.1
–
4700
2.5
f
SCLK
Startup Delay at VCC Power−On Reset (POR) (Note 4)
Ambient Still−Air Operating Temperature
t
200
125
RESET
T
A
−40
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Minimum wait time until device is ready to accept serial input data.
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6
NCV7547
PARAMETRIC TABLES
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
VS SUPPLY
Symbol
Conditions
Min
Typ
Max
Unit
Standby Current
VS = 12.0V, 0 v VCC v 5.5 V, RSTB = 0,
A
–
–
5.0
I
mA
VS_SBY
T = 25°C
Operating Current
VCC = 5.0 V , RSTB = 1, T = 25°C
A
Default Settings at POR, SPI Inactive
CR1.D[10]=0
1.6
5.0
I
I
mA
VS_OP0
–
–
CR1.D[10]=1
20.3
5.0
25.0
5.5
–
mA
V
VS_OP1
Under−voltage Lockout
VS
VS decreasing, SR0.D[5] ³ 1
SR0.D[5] ³ 0
4.5
100
UVLO
UVHY
Under−voltage Hysteresis
200
VS
mV
(after read status if VS > VS
)
UVLO+UVHY
Under−voltage Filter Time
Over−voltage Shutdown
t
VS decreasing
4.0
19.0
18.0
–
5.0
20.0
19.0
0.9
6.0
21.0
20.0
–
ms
V
UVDGL
VS
VS increasing, SR0.D[4] ³ 1
VS decreasing, SR0.D[4] ³ 0
SR0.D[4] ³ 0
OVSDR
OVSDF
VS
V
Over−voltage Hysteresis
VS
V
OVHY
(after read status if VS < VS
)
OV – OVHY
Over−voltage Filter Time
VS PWM Threshold
VS PWM Hysteresis
t
VS increasing
4.0
8.90
−
5.0
9.45
100
6.0
10.0
–
ms
OVDGL
VS
VS decreasing, SR0.D[7] ³ 1
V
PWM
SR0.D[7] ³ 0 and/or SR0.D[6] ³ 0
(after read status if VS > VS
VS
mV
PWM_HY
)
PWM +PWM_HY
VCC SUPPLY
Standby Current
VS = 12.0V, VCC = 5.5 V , RSTB = 0, T = 25°C
–
–
5.0
A
I
mA
VCC_SBY
Default Settings at POR, SPI Inactive
Operating Current
I
VS = 12.0V, RSTB = 1, T = 25°C
–
8.0
12.0
4.49
4.20
mA
V
VCC_OP
A
Power−On Reset Threshold
VCC
VCC Increasing
VCC Decreasing
3.71
3.50
4.10
3.85
PORR
PORF
VCC
V
CHARGE PUMP
C1 = C2 = 470 nF; CCP = 1000 nF
Single−stage, complementary−phase topology
(Note 6)
Switching Frequency
f
0.75
1.10
1.45
MHz
CP
Spread Spectrum
Modulation Depth
Modulation Rate
CP
CPMOD
−
−
15.0
45.6
−
−
%
kHz
MOD
f
Regulation Voltage
Startup Delay
CP
V(CP, VS), VS > VS
, 0 v I(CP) v 15 mA
8.3
–
8.9
–
9.5
V
REG
PWM
VS = 13V, I(CP) = no load
C1 = C2 = 470 nF, CCP = 1000 nF
(Note 6)
500
CP
ms
DLY
Dropout Voltage
CP
CP
V(VS) − V(CP, VS), I(CP) = 10 mA, VS=9.4
V(VS) − V(CP, VS), I(CP) = 15 mA,
–
–
–
–
1.50
1.75
1.90
8.8
DROP0
DROP1
V
VS=10V and SR0.D[7] = 0
T w 125°C
J
–
–
Charge Pump Low Detection
CP
CP
V(CP, VS) decreasing, VS > VS
, SR0.D[7] ³ 1
7.3
300
120
8.0
–
V
LOW0
PWM
Detection margin, CP
= CP
− CP
LOW0
–
mV
LOW1
LOW1
REG
Charge Pump Low Detection
Filter Time
150
180
t
ms
CPL_DGL
Charge Pump Low Hysteresis
SR0.D[7] ³ 0
(after read status if V(CP,VS) > CP
–
100
–
CP
mV
LOW_HY
)
LOW+LOW_HY
5. Min/Max values are valid for the stated temperature range unless noted otherwise. Min/Max values are guaranteed by test, design or statis-
tical correlation
6. No production test
7. These values, measured in production via test mode, result in values that are t
longer than the stated values. The specification limits
SYNC
shall therefore be: (t
Typ + t
Typ) 20%, (t
Typ + t
Typ) 20%, and (t
Typ + t
Typ) 20%.
CAL_PCx
SYNC
CAL_DLYx
SYNC
DLYX
SYNC
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NCV7547
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
CHARGE PUMP
Symbol
Conditions
Min
Typ
Max
Unit
Charge Pump Fail Detection
CP
V(CP, VS) decreasing, SR0.D[6] ³ 1
4.925
120
5.375
150
5.750
180
V
FAIL
Charge Pump Fail Detection
Filter Time
t
ms
CPF_DGL
Charge Pump Fail Hysteresis
SR0.D[6] ³ 0
–
28.0
0.5
–
100
30.25
1.0
1.5
–
–
32.5
2.0
–
CP
mV
V
FAIL_HY
(after read status if V(CP,VS) > CP
)
FAIL+FAIL_HY
Charge Pump Over−voltage
Detection
VS increasing
CP
OV
Charge Pump Over−voltage
Hysteresis
CP
V
OV_HYS
CPTOT
CP Switch Resistance
*Guaranteed by Simulation*
8x CP switches in parallel, T = 25°C
R
W
A
Switched CP Output Resis-
tance
CR1.D[9] = 1, I(CPSW) = 5 mA
CR1.D[9] = 0
–
100
1.0
R
W
CPSW_ON
Switched CP Output Leakage
CP
−1.0
0
uA
SW_LKG
DIGITAL I/O
V
High
Low
V
CSB, SCLK, SI, RSTB, FSM, PWMx
CSB, SCLK, SI, RSTB, FSM, PWMx
3.5
–
–
–
–
V
V
IN_X
IN_X
INHX
V
V
1.5
130
130
INLX
Input Pull−down Resistance
Input Pull−up Resistance
Input Current
R
SCLK, SI, RSTB, FSM, PWMx, V
= VCC
70
70
100
100
0
kW
kW
PDX
INX
R
CSB, V = 0V
IN
PU
V
INX
V
INX
= 5.5V: SCLK, SI, RSTB, FSM, PWMx
= 0V: CSB
–
−80
80
–
I
mA
mA
INX
Input Leakage
V
INX
V
INX
= 0V: SCLK, SI, RSTB, FSM, PWMx
= VCC: CSB
−1.0
0
1.0
I
IN_LKG
Input Filter Time
Reset De−glitch Time
Reset Assert Time
SO Low Voltage
t
FSM input
8.0
8.0
–
10
–
12
–
ms
ms
ms
V
IN_DGL
t
Minimum RSTB pulse (H ³ L ³ H) detected
Minimum RSTB hold after H ³ L transition
RST_DGL
t
11
–
15
0.4
–
WRST
V
SOL
I
I
= 1.0 mA
–
SINK
SO High Voltage
= 1.0 mA
VCC –
0.4
–
SOURCE
V
SOH
V
SO Tri−State Leakage Current
SO
CSB = VCC, SO = VCC/2
−1.0
–
1.0
mA
LKG
SERIAL PERIPHERAL INTERFACE (See Figure 4)
VCC = 5.0V, FSCLK = 2.5 MHz, CLOAD = 80 pF, all timing is at 30% and 70% VCC unless otherwise specified.
SCLK Clock Period
SCLK High Time
SCLK Low Time
Maximum Input Capacitance
Sl Setup Time
t
400
200
200
–
–
–
–
–
ns
ns
ns
pF
ns
ns
ns
ns
ns
ns
SCLK
CLKH
t
SCLK = 70% VCC to 70% VCC
SCLK = 30% VCC to 30% VCC
SCLK, Sl
t
–
–
CLKL
C
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
–
15
–
INX
SISU
SIHD
t
Sl = 30%|70% to SCLK = 70% VCC
SCLK = 30% to Sl = 30%|70% VCC
25
25
–
–
Sl Hold Time
t
–
–
SO Rise Time
t
(20% V to 80% VCC)
25
–
50
50
–
SOR
SO
SO Fall Time
t
(80% V to 20% VCC)
–
SOF
SO
CSB Setup Time
CSB Hold Time
t
CSB = 30% to SCLK = 30% VCC
SCLK = 30% to CSB = 70% VCC
60
75
–
CSBSU
CSBHD
t
–
–
5. Min/Max values are valid for the stated temperature range unless noted otherwise. Min/Max values are guaranteed by test, design or statis-
tical correlation
6. No production test
7. These values, measured in production via test mode, result in values that are t
longer than the stated values. The specification limits
SYNC
shall therefore be: (t
Typ + t
Typ) 20%, (t
Typ + t
Typ) 20%, and (t
Typ + t
Typ) 20%.
CAL_PCx
SYNC
CAL_DLYx
SYNC
DLYX
SYNC
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NCV7547
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
SERIAL PERIPHERAL INTERFACE (See Figure 4)
CSB to SO Assert Time
CSB to SO Release Time
CSB = 30% VCC to SO = 30%|70% VCC
RLOAD = 5 kW
–
–
65
–
125
350
t
ns
ns
SO_A
(Note 6)
CSB = 70% VCC to SO = 20%|80% VCC/2
RLOAD = 5 kW
t
SO_R
(Note 6)
(Note 6)
SO Delay Time
SO
CS
SCLK = 70% VCC to SO = 30%|70%
–
–
65
–
125
1.0
ns
DLY
Transfer Delay Time
CSB rising edge to next falling edge.
(Note 6)
ms
DLY
HALF−BRIDGE PRE−DRIVER OUTPUTS
VS > VS
PWM
On−state Drive Voltage
High−side, V
= H = V(GHx, HBx) or V(GHX,
8.3
8.1
–
–
–
–
–
–
9.5
9.8
PDHX
V
V
V
V
V
V
V
PDHX
SH7), No External Load
Low−side, V = H =V(GLx, PGND),
PDLX
V
PDLX
No External Load
High−side driver Gate−source
Clamp Positive Voltage
V(GHx, HBx), V(GH7, SH7), I
= 3.0 mA
14.0
−20.0
11.5
−1.0
18.0
−16.0
15.0
–
CLMP
CLMP
V
V
GSX_CLPH
High−side driver Source−gate
Clamp Negative Voltage
V(HBx, GHx), V(SH7, GH7), I
= −2.0 mA
SGX_CLPH
Low−side driver Gate−source
Clamp Positive Voltage
V(GLx, PGND), I
V(GLx, PGND), I
= 10 mA
CLMP
V
GSX_CLPL
Low−side driver Gate−source
Clamp Negative Voltage
= −1.0 mA
CLMP
V
GSX_CLN
Gate Drive Timeout
t
I
v I
16
−1.2
70
20
−1.0
–
24
ms
TIMEOUT
GHx
GHx_SS
Gate Drive Timeout Current
I
V(GHx, HBx) or V(GHx, SH7) = 0 V, t > t
−0.8
130
mA
GHx_SS
TIMEOUT
Gate−source Pull−down
Resistor
R(GHx, HBx), R(GHx, SH7), R(GLx, PGND)
R
kW
ms
GSX
Cross Conduction Blank Time
BLANKx[1:0] = 0x00
BLANKx[1:0] = 0x01
BLANKx[1:0] = 0x02
BLANKx[1:0] = 0x03
0.8
1.6
2.4
3.2
1.0
2.0
3.0
4.0
1.2
2.4
3.6
4.8
t
GHx, GLx
BLANKX
PRE−DRIVER SLOPE CONTROL
VS > VS
PWM
High−side Pre−charge Time
GHx Rising and Falling Slope
T_PCx[1:0] = 0x00
T_PCx[1:0] = 0x01
T_PCx[1:0] = 0x02
T_PCx[1:0] = 0x03
I_PCRx[2:0] = 0x00
I_PCRx[2:0] = 0x01
I_PCRx[2:0] = 0x02
I_PCRx[2:0] = 0x03
I_PCRx[2:0] = 0x04
I_PCRx[2:0] = 0x05
I_PCRx[2:0] = 0x06
I_PCRx[2:0] = 0x07
80
100
200
120
240
160
t
ns
PRCX
240
300
360
320
400
480
High−side Pre−charge Current
GHx Rising Slope
1.23
4.52
7.42
10.65
14.19
17.42
20.64
24.19
1.50
5.25
8.63
12.38
16.50
20.25
24.00
28.13
1.77
5.99
9.84
14.11
18.81
23.09
27.36
32.07
V(GHx) = 3.5 V
I
mA
PRCX_R
5. Min/Max values are valid for the stated temperature range unless noted otherwise. Min/Max values are guaranteed by test, design or statis-
tical correlation
6. No production test
7. These values, measured in production via test mode, result in values that are t
longer than the stated values. The specification limits
SYNC
shall therefore be: (t
Typ + t
Typ) 20%, (t
Typ + t
Typ) 20%, and (t
Typ + t
Typ) 20%.
CAL_PCx
SYNC
CAL_DLYx
SYNC
DLYX
SYNC
www.onsemi.com
9
NCV7547
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
PRE−DRIVER SLOPE CONTROL
High−side Pre−charge Current
GHx Falling Slope
I_PCFx[2:0] = 0x00
I_PCFx[2:0] = 0x01
24.84
30.64
36.12
41.61
47.41
52.89
58.38
64.18
1.23
28.88
35.63
42.00
48.38
55.13
61.50
67.88
74.63
1.50
32.92
40.62
47.88
55.15
62.85
70.11
77.38
85.08
1.77
V(GHx) = (VS + 3.5) V
I_PCFx[2:0] = 0x02
I_PCFx[2:0] = 0x03
I
mA
PRCX_F
I_PCFx[2:0] = 0x04
I_PCFx[2:0] = 0x05
I_PCFx[2:0] = 0x06
I_PCFx[2:0] = 0x07
High−side Slew Current
SR_CTRLx[2:0] = 0x00
SR_CTRLx[2:0] = 0x01
SR_CTRLx[2:0] = 0x02
SR_CTRLx[2:0] = 0x03
SR_CTRLx[2:0] = 0x04
SR_CTRLx[2:0] = 0x05
SR_CTRLx[2:0] = 0x06
SR_CTRLx[2:0] = 0x07
SR_CTRLx[2:0] = 0x00
SR_CTRLx[2:0] = 0x01
SR_CTRLx[2:0] = 0x02
SR_CTRLx[2:0] = 0x03
SR_CTRLx[2:0] = 0x04
SR_CTRLx[2:0] = 0x05
SR_CTRLx[2:0] = 0x06
SR_CTRLx[2:0] = 0x07
GHx Rising and Falling Slope
1.94
2.25
2.57
Rising: V(GHx) = (VS + 3.5) V
Falling: V(GHx) = 3.5 V
2.91
3.38
3.85
4.52
5.25
5.99
I
mA
SRX
6.78
7.88
8.98
10.00
14.84
21.93
5.16
11.63
17.25
25.50
6.00
13.26
19.67
29.07
6.84
Low−side Drive Current
GLx Rising and Falling slope
7.74
9.00
10.26
15.41
23.94
35.93
53.03
78.66
11.63
18.06
27.11
40.01
59.34
87.72
13.52
21.00
31.52
46.52
69.00
V(GLx) = 3.5 V
I
mA
LSX
102.00 116.28
SLOPE CONTROL CALIBRATION UNIT
Slope Calibration Comparator
Window Thresholds
V
Falling slope window lower threshold
Falling slope window upper threshold
Rising slope window lower threshold
Rising slope window upper threshold
3.0
13
82
92
–
5.0
15
7.0
17
88
98
100
–
CALF_L
CALF_U
CALR_L
CALR_U
CAL_PD
V
V
% VS
85
V
95
Comparator Propagation Delay
Sample Synchronization Delay
Calibration Pre−charge Time
t
62
ns
ns
t
t
= 2/f
CORE
–
50
SYNC
SYNC
CAL_PC[3:0] = 0x00
50
CAL_PC[3:0] = 0x01
CAL_PC[3:0] = 0x02
CAL_PC[3:0] = 0x03
CAL_PC[3:0] = 0x04
CAL_PC[3:0] = 0x05
150
250
350
450
550
HBx Rising & Falling Slope
t
(Note 7)
(Note 7)
ns
CAL_PCx
5. Min/Max values are valid for the stated temperature range unless noted otherwise. Min/Max values are guaranteed by test, design or statis-
tical correlation
6. No production test
7. These values, measured in production via test mode, result in values that are t
longer than the stated values. The specification limits
SYNC
shall therefore be: (t
Typ + t
Typ) 20%, (t
Typ + t
Typ) 20%, and (t
Typ + t
Typ) 20%.
CAL_PCx
SYNC
CAL_DLYx
SYNC
DLYX
SYNC
www.onsemi.com
10
NCV7547
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
SLOPE CONTROL CALIBRATION UNIT
Calibration Pre−charge Time
CAL_PC[3:0] = 0x06
CAL_PC[3:0] = 0x07
CAL_PC[3:0] = 0x08
CAL_PC[3:0] = 0x09
CAL_PC[3:0] = 0x0A
CAL_PC[3:0] = 0x0B
CAL_PC[3:0] = 0x0C
CAL_PC[3:0] = 0x0D
CAL_PC[3:0] = 0x0E
CAL_PC[3:0] = 0x0F
CAL_DLY[3:0] = 0x00
CAL_DLY[3:0] = 0x01
CAL_DLY[3:0] = 0x02
CAL_DLY[3:0] = 0x03
CAL_DLY[3:0] = 0x04
CAL_DLY[3:0] = 0x05
CAL_DLY[3:0] = 0x06
CAL_DLY[3:0] = 0x07
CAL_DLY[3:0] = 0x08
CAL_DLY[3:0] = 0x09
CAL_DLY[3:0] = 0x0A
CAL_DLY[3:0] = 0x0B
CAL_DLY[3:0] = 0x0C
CAL_DLY[3:0] = 0x0D
CAL_DLY[3:0] = 0x0E
CAL_DLY[3:0] = 0x0F
650
750
HBx Rising & Falling Slope
850
950
1050
1150
1250
1350
1450
1550
0.35
0.55
0.75
0.95
1.15
1.35
1.55
1.75
1.95
2.15
2.35
2.55
2.75
2.95
3.15
3.35
t
(Note 7)
(Note 7)
ns
CAL_PCx
Calibration Delay Time
HBx Rising & Falling Slope
t
(Note 7)
(Note 7)
ms
CAL_DLYx
HALF−BRIDGE DIAGNOSTICS
VDS Monitor Thresholds
VDSx[2:0] = 0x00
VDSx[2:0] = 0x01
VDSx[2:0] = 0x02
VDSx[2:0] = 0x03
VDSx[2:0] = 0x04
VDSx[2:0] = 0x05
VDSx[2:0] = 0x06
VDSx[2:0] = 0x07
263
356
445
534
623
712
801
890
0.92
–
300
400
500
600
700
800
900
1000
1.15
550
337
444
555
666
777
888
999
1110
1.38
750
VDS = V(VS, HBx)
− or−
VDS
mV
THRX
VDS = V(HBx, GND)
VDS Monitor Filter Time
t
ms
DGL_STAT
VDS Monitor Propagation Delay
t
ns
VDSS_PD
5. Min/Max values are valid for the stated temperature range unless noted otherwise. Min/Max values are guaranteed by test, design or statis-
tical correlation
6. No production test
7. These values, measured in production via test mode, result in values that are t
longer than the stated values. The specification limits
SYNC
shall therefore be: (t
Typ + t
Typ) 20%, (t
Typ + t
Typ) 20%, and (t
Typ + t
Typ) 20%.
CAL_PCx
SYNC
CAL_DLYx
SYNC
DLYX
SYNC
www.onsemi.com
11
NCV7547
ELECTRICAL CHARACTERISTICS
(4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VS ≤ 18 V, RSTB = VCC, CR1.D[10] = 1, −40°C ≤ T ≤ 150°C, unless otherwise specified.) (Note 5)
J
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
HALF−BRIDGE DIAGNOSTICS
VDS Overload Detection
Delay Time
T_DLYX[3:0] = 0x00
T_DLYX[3:0] = 0x01
1.05
1.65
2.25
2.85
3.45
4.05
4.65
5.25
5.85
6.45
7.05
7.65
8.25
8.85
9.45
10.05
26
T_DLYX[3:0] = 0x02
Rising or Falling Slope
T_DLYX[3:0] = 0x03
T_DLYX[3:0] = 0x04
T_DLYX[3:0] = 0x05
T_DLYX[3:0] = 0x06
T_DLYX[3:0] = 0x07
t
(Note 7)
(Note 7)
ms
DLYX
T_DLYX[3:0] = 0x08
T_DLYX[3:0] = 0x09
T_DLYX[3:0] = 0x0A
T_DLYX[3:0] = 0x0B
T_DLYX[3:0] = 0x0C
T_DLYX[3:0] = 0x0D
T_DLYX[3:0] = 0x0E
T_DLYX[3:0] = 0x0F
HBx, SH7, DL7 − Pull−down to AGND
HBx Input Resistance
R
−
−
kW
% VS
ms
HBX
HBx Monitor Threshold
VHB
45
–
50
55
2.0
9.0
THR
HBx Monitor Propagation Delay
HBx Monitor Test Currents
t
1.0
HBX_PD
CR0.HB_ENx = 0, HB1, HB3
source or sink, 10V v VS v 16V
6.0
7.5
I
mA
TST
WATCHDOG TIMER
Watchdog Timeout
CR1.D[8] = 0
CR1.D[8] = 1
20
400
25
500
30
600
t
ms
WD
Core Clock Oscillator
THERMAL OVERLOAD (Note 6)
Warning Threshold
f
–
40
–
MHz
CORE
T
T increasing, SR0.D[3] → 1
110
–
125
20
140
–
°C
°C
°C
°C
ms
OTW
J
Warning Hysteresis
SR0.D[3] → 0
T
T
OTW_HY
(after read status if T < T
)
J
OTW – OTW_HY
Shutdown Threshold
Shutdown Hysteresis
T
T increasing, SR0.D[2] → 1, all outputs → OFF
J
150
–
170
20
190
–
OTS
SR0.D[2] → 0
OTS_HY
(after read status if T < T
)
J
OTS – OTS_HY
Shutdown Filter Time
t
–
11.9
–
OTDGL
5. Min/Max values are valid for the stated temperature range unless noted otherwise. Min/Max values are guaranteed by test, design or statis-
tical correlation
6. No production test
7. These values, measured in production via test mode, result in values that are t
longer than the stated values. The specification limits
SYNC
shall therefore be: (t
Typ + t
Typ) 20%, (t
Typ + t
Typ) 20%, and (t
Typ + t
Typ) 20%.
CAL_PCx
SYNC
CAL_DLYx
SYNC
DLYX
SYNC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
12
NCV7547
TRANSFER
DELAY
CSB
SETUP
70%
CSB
SCLK
SI
30%
SCLK PERIOD
CSB
HOLD
SCLK
HIGH
SCLK
LOW
70%
1
16
30%
70%
SI
SETUP
SI
HOLD
X
BITS 14...1
LSB IN
MSB IN
30%
CSB to SO
ASSERT
SO
DELAY
SO
RISE,FALL
CSB to SO
RELEASE
70%
30%
80%
20%
SO
BITS 14...1
LSB OUT
X
MSB OUT
Figure 4. SPI Timing
www.onsemi.com
13
NCV7547
DETAILED OPERATING DESCRIPTION
Power Supply
The power supply block provides:
• all internal supply and reference voltages;
• all internal bias and reference currents;
• VCC power−on reset (POR) and VS
under/over−voltage lockout signals.
Table 1 gives suggested values for the external pump and
buffer capacitors to support the charge pump DC loading
while maintaining good transient response and regulation
stability.
Table 1. SUGGESTED CHARGE PUMP CAPACITORS
DC Load
(mA)
Pump Capacitors
C1, C2 (nF)
Buffer Capacitor
CCP (nF)
The analog and power portions of the device (reference
voltages/currents, charge pump, low−side gate drivers, etc.)
are supplied from the VS terminal. Each of the low−side gate
driver outputs (GLx) is supplied from VS via an individual
buffer (source follower) with voltage limit functionality.
The high−side gate driver outputs (GHx) are supplied from
a regulated charge pump.
The logic core and the SPI communication interface are
supplied from the VCC terminal in order to achieve a high
frequency operation by use of external bypass capacitors. In
case of breakdown of the external voltage regulator, the
device can be protected by use of an external voltage limiter,
which must limit the maximum voltage at the VCC terminal
1.0
7.5
100
220
470
220
470
15.0
1000
The device is initialized at power−up into a reduced power
state and the charge pump disabled. The charge pump is
controlled by SPI command via the CR1.DRV_EN bit (see
Table 7) and the charge pump is:
• disabled when CR1.DRV_EN=0;
• enabled when CR1.DRV_EN=1.
The optional external reverse protection and security
switches are connected to the charge pump buffer capacitor
through the switched charge pump (CPSW) output. The
output is controlled by SPI command via the CR1.CP_SW
bit (see Table 7). The CPSW output is:
• disabled (the reverse and security MOSFETs are turned
OFF) when CR1.CP_SW=0;
to VCC
(see § MAXIMUM RATINGS).
MAX
The outputs are disabled during device initialization at
power−up via an interlock between VS and VCC and such
that no control is available until after VCC > VCC
§ Electrical Characteristics: VCC Supply). Reverse battery
protection for VS and the VCC regulator is provided
externally by the application (see Figure 2).
(
see
PORR
• enabled (the reverse and security MOSFETs are turned
ON) when CR1.CP_SW=1.
The device is initialized at power−up into a reduced power
state (CR1.DRV_EN = 0, see § SPI Control Set):
• the charge pump is disabled;
The charge pump is internally monitored to ensure safe
operation of the charge pump circuit and the high−side
driver outputs (see § Protection and Diagnosis − Charge
Pump Monitoring). Due to the single stage configuration the
charge pump provides the following output characteristics
(see Figure 5, Figure 6, § SPI Diagnosis Set and § Electrical
Characteristics: Charge Pump):
• all gate drive currents are disabled;
• gate pull−down structures are enabled;
• HBx diagnostic test currents are available (see
§ OFF−state Monitoring of Half−bridge Drivers).
The device is placed into a full power state when
CR1.DRV_EN = 1.
Multiple GND pins are used in order to avoid loss of GND
due to a single−point failure, to improve ESD capability, and
to improve the VDS overload protection performance of the
device.
• V(CP, VS) < CP
FAIL
SR0.CPF → 1
the GHx and GLx outputs are shut down to prevent
damage to the external power MOSFETs;
• VS < VS
PWM
SR0.CPL → 1
Charge Pump
the CP output voltage follows the VS voltage (the
regulation saturates) with a maximum drop voltage per
A regulated charge pump circuit in single−stage /
complementary−phase configuration is implemented. The
charge pump is sized to drive up 2 high−side drivers in PWM
the equation V(CP, VS) = VS − CP
;
DROP
≤
(
.
• CP
< V(CP, VS) < CP
operation f
25 kHz)
FAIL
LOW
PWM
SR0.CPL → 1
• VS ≤ VS ≤ VS
The topology utilizes 2 external pump capacitors and an
external buffer capacitor (see Figure 2) to supply:
• the high−side gate driver outputs (GHx);
• an optional external reverse protection power
MOSFET;
PWM
OVSDR
the charge pump delivers a regulated output voltage
V(CP, VS) = CP and PWM operation of the GHx
REG
outputs is allowed;
• an optional external security switch power MOSFET.
www.onsemi.com
14
NCV7547
In the case of VS overvoltage, the charge pump
• VS
< VS < VS(CP
the charge pump including the CPSW output is
functional, but the GHx outputs are shut down;
)
OVSDF
OV
automatically resumes normal operation when the VS
.
voltage returns to below CP − CP
In the case of
it should be
OV
OV_HYS
VS < VS
or V(CP, VS) < CP
PWM
LOW
• VS > VS(CP
)
OV
considered for the microcontroller to adopt a PWM duty
ratio management schema in order to minimize charge pump
loading while ensuring smooth motor operation.
the charge pump is disabled and the charge pump buffer
capacitor is discharged to VS in order to protect the
device from destruction.
V(CP, VS)
CP In Regulation
CPREG
CPLOW
(MIN)
CP Low OR VS < VS
SR0.D[7] → 1
PWM
CPFAIL
(MIN)
CP Fail
GHx → L
GLx → L
SR0.D[6] → 1
V(VS)
VSPWM
(MAX)
VSOVSD
(MIN)
CPDROP
Figure 5. Charge Pump Characteristics
V
Load Dump Rise Time
(per ISO7637 Pulse 5b)
V(VSMAX
)
)
V(CPOV
CPREG
V(CP)
V(VS)
CPREG
t
CP Oscillator Stopped
Buffer Cap Discharged to VS
Figure 6. Charge Pump Overvoltage Behavior
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15
NCV7547
SPI Interface
Watchdog Timer) in order to facilitate module boot loader
programming. The timeout setting is controlled by the
CR1.WD_CFG bit:
A full−duplex synchronous serial data transfer interface
(SPI) is used to control the device and provide diagnosis
during normal operation. Daisy chain capability of the
interface is implemented in order to minimize circuit
expenditure and communication efforts. The SPI protocol
utilizes 16−bit data words (B15 = MSB). The idle state of
SCLK is low and the SI data must be stable before the falling
edge of SCLK (“legacy mode 1”: CPOL=0, CPHA=1).
The interface consists of 4 I/O lines with 5V CMOS logic
levels and termination resistors (see Figure 7, Figure 2):
• when CR1.WD_CFG=0 (default setting) the WD
timeout is t
= 25 ms;
WD
• when CR1.WD_CFG=1 the WD timeout is t
=
WD
500 ms.
The first WD bit value sent after VCC POR or wake−up
must be WD = 0 in the first frame, then WD = 1 in the next.
A correct communication is reported when bit SR0.SPIF
= 0 and the device is in NORMAL MODE (NM) when bit
SRx.NM = 1. The device enters FAILSAFE MODE
immediately in the event of an SPI communication error(see
§ Operating Modes).
• the active−low CSB enables the SPI interface;
• the SCLK pin clocks the internal shift registers of the
device;
• the SI pin receives data of the input shift registers MSB
first;
Serial Data and SPI Register Structures
• the SO pin sends data of the output shift registers MSB
The input and output message formats of the implemented
SPI protocol are as shown in the following tables. In the
descriptions in the following sections, it is implied that the
frame length is correct and that the WD bit has been properly
toggled when sending and receiving SPI messages. Please
also note that the SPI hardware protocol is a “frame−behind”
response type, i.e. the requested data is delivered in the next
frame.
first.
The device offers the following SPI communication error
checks in order to protect the application from unintended
motor activation:
• protocol length error (modulo 16);
• no edges on SCLK during a CSB period;
• an undefined SPI command (not used bits must be set
to logic 0);
• watchdog (WD) toggle (the internal watchdog bit
(CRx.WD) must be toggled with each SPI message);
• WD timeout (the WD bit must be toggled before the
internal watchdog timeout is reached).
SPI Control Set
The first 4 bits (D15 ... D12) serve as address bits, while
12 bits (D11 ... D0) are used as data bits. The D11 bit is the
WD toggle bit: A SPI fail is detected if the bit is not toggled
within the WD timeout. The D10 bit may be used as an
extended address in some messages.
All Control Register (CRx) bits are initialized to logic 0
after a reset. The predefined value is off / inactive unless
otherwise noted. The SPI control set (input data map) and
input data structure prototype are shown in the following
tables.
An SI pin stuck−at condition during a CSB period is
detected by a WD toggle error. A VCC under−voltage
condition is directly blocking the complete SPI functionality
via the VCC
signal.
PORF
The length of the watchdog timeout is SPI programmable
(see § SPI Control Set and § Electrical Characteristics:
TOGGLE
CSB
SAMPLE
4 − 13
1
2
3
14
15
16
SCLK
SI
X
B15
MSB
B15
B14
B14
B13
B13
B12 − B3
B12 − B3
B2
B2
B1
B1
B0
LSB
B0
Z
SO
X
Z
Note: SPI Legacy Mode 1; X=Don’t Care, Z=Tri−State
Figure 7. SPI Communication Frame Format
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Table 2. SPI INPUT DATA FORMAT
Command Input Message Format
MSB
LSB
B0
D0
B15
A3
B14
A2
B13
A1
B12
A0
B11
WD
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
WATCH DOG
11−bit INPUT DATA
4−bit REGISTER ADDRESS
Table 3. INPUT DATA STRUCTURE PROTOTYPE
Input Data Prototype
CRx
WD
?
D10
?
D9
?
D8
?
D7
?
D6
?
D5
?
D4
?
D3
?
D2
D1
?
D0
?
?
Table 4. SPI INPUT REGISTER DEFINITIONS
Defined Command Input Registers (CRx)
D15
A3
0
D14
A2
0
D13
D12
A0
0
D11
D10
Register Name
Status Output Mode & HBx Enable
HBx Mode
Alias
CR0
A1
0
WD
D10
D10
D10
0
CR1
0
0
0
1
HBx PWM Control
HBx PWM Mode A
HBx PWM Mode B
HBx Calibration Control
HB1 Configuration A
HB1 Configuration B
HB2 Configuration A
HB2 Configuration B
HB3 Configuration A
HB3 Configuration B
HB4 Configuration A
HB4 Configuration B
HB5 Configuration A
HB5 Configuration B
HB6 Configuration A
HB6 Configuration B
HB7 Configuration A
HB7 Configuration B
HBx Diagnosis
CR2
0
0
1
0
CR3A
CR3B
CR4
0
0
1
1
0
1
0
0
1
1
0
0
0
1
D10
0
CR5A
CR5B
CR6A
CR6B
CR7A
CR7B
CR8A
CR8B
CR9A
CR9B
CR10A
CR10B
CR11A
CR11B
CR12
CR13
CR14
CR15
1
0
0
0
1
1
1
1
0
1
1
0
1
WD
0
1
1
0
0
0
0
0
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
Not Used
0
HBx PWM De−glitch
Test Mode
0
D10
NOTE: Half−bridge gate drive settings must only be changed when HBx is in tri−state (HB_ENx = 0);
Gate drive pre−charge time settings must only be changed in single increments (i.e. 00 to 01, 01 to 10 etc.).
Table 5. CR0: STATUS OUTPUT MODE & HBx ENABLE REGISTER
CR0
WD
WD
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SRA_MODE
SRA[2:0]
HB_EN7 … HB_EN1
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Table 6. CR0 INSTRUCTION DEFINITIONS
Mnemonic
Value
Comment
SRA_MODE
The Status Register Address selected via CR0.SRA [2:0] will be used for a single read command. The address
always points to SR0 after the read (default state).
0
The Status Register Address selected via SRA [2:0] will be used for the next and all further read commands
until a new address is selected.
1
SRA[2:0]
000
001
010
011
100
101
110
111
0
SR0 data is returned in the next frame (default state).
SR1 data is returned in the next frame.
SR2 data is returned in the next frame.
SR3 data is returned in the next frame.
SR4 data is returned in the next frame.
SR5 data is returned in the next frame.
SR6 data is returned in the next frame.
SR7 data is returned in the next frame.
HBx output disabled (default state).
HBx output enabled.
HB_ENx
1
Table 7. CR1: HBx MODE CONTROL REGISTER
CR1
WD
WD
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DRV_EN
CP_SW
WD_CFG
HB_CFG7
HB_MODE7 … HB_MODE1
Table 8. CR1 INSTRUCTION DEFINITIONS
Mnemonic
Value
Comment
0
1
0
1
0
1
0
1
0
1
Charge pump and gate drive currents are disabled (default state).
Charge pump and gate drive currents are enabled.
Charge pump switched output is OFF: CPSW = Hi−Z (default state).
Charge pump switched output is ON: CPSW = V(CP−VS).
Watch dog timeout = 25 ms (default state).
DRV_EN
CP_SW
WD_CFG
HB_CFG7
HB_MODEx
Watch dog timeout = 500 ms.
Half−bridge configuration (default state).
Split configuration (see Figure 13 and Figure 16).
Low−side pre−driver active (default state).
High−side pre−driver active.
Table 9. CR2: HBx PWM CONTROL REGISTER
CR2
WD
WD
D10
0
D9
0
D8
0
D7
0
D6
D5
D4
D3
D2
D1
D0
HB_PWM7 … HB_PWM1
Table 10. CR2 INSTRUCTION DEFINITIONS
Mnemonic
Value
Comment
0
1
Output is in 100% ON mode (default).
Output is in PWM mode.
HB_PWMx
Table 11. CR3: HBx PWM MODE CONTROL REGISTER
WD
WD
WD
WD
D10
0
D9
D8
D7
D6
D5
D4
D3
D2
D2
D1
PWM1[1:0]
D1 D0
PWM6[1:0]
D0
CR3A
CR3B
PWM5[1:0]
PWM4[1:0]
PWM3[1:0]
PWM2[1:0]
D10
1
D9
0
D8
0
D7
0
D6
0
D5
D4
0
D3
0
PWM7[1:0]
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Table 12. CR3 INSTRUCTION DEFINITIONS
Mnemonic
Value
00
Comment
Output PWM source is input PWM1 (default).
Output PWM source is input PWM2.
Output PWM source is input PWM3.
Output PWM source is input PWM4.
PWMx[1:0]
01
10
11
Table 13. CR4: HBx CALIBRATION CONTROL REGISTER
WD
WD
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CR4
CAL_DLY[3:0]
CAL_PC[3:0]
CAL_SEL[2:0]
Table 14. CR4 INSTRUCTION DEFINITIONS
Mnemonic
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Comment
CAL_DLY[3:0]
Delay time: end of rising|falling slope 0.35 ms (default).
Delay time: end of rising|falling slope 0.55 ms.
Delay time: end of rising|falling slope 0.75 ms.
Delay time: end of rising|falling slope 0.95 ms.
Delay time: end of rising|falling slope 1.15 ms.
Delay time: end of rising|falling slope 1.35 ms.
Delay time: end of rising|falling slope 1.55 ms.
Delay time: end of rising|falling slope 1.75 ms.
Delay time: end of rising|falling slope 1.95 ms.
Delay time: end of rising|falling slope 2.15 ms.
Delay time: end of rising|falling slope 2.35 ms.
Delay time: end of rising|falling slope 2.55 ms.
Delay time: end of rising|falling slope 2.75 ms.
Delay time: end of rising|falling slope 2.95 ms.
Delay time: end of rising|falling slope 3.15 ms.
Delay time: end of rising|falling slope 3.35 ms.
Pre−charge time: start of rising|falling slope 50 ns (default).
Pre−charge time: start of rising|falling slope 150 ns.
Pre−charge time: start of rising|falling slope 250 ns.
Pre−charge time: start of rising|falling slope 350 ns.
Pre−charge time: start of rising|falling slope 450 ns.
Pre−charge time: start of rising|falling slope 550 ns.
Pre−charge time: start of rising|falling slope 650 ns.
Pre−charge time: start of rising|falling slope 750 ns.
Pre−charge time: start of rising|falling slope 850 ns.
Pre−charge time: start of rising|falling slope 950 ns.
Pre−charge time: start of rising|falling slope 1050 ns.
Pre−charge time: start of rising|falling slope 1150 ns.
Pre−charge time: start of rising|falling slope 1250 ns.
Pre−charge time: start of rising|falling slope 1350 ns.
Pre−charge time: start of rising|falling slope 1450 ns.
Pre−charge time: start of rising|falling slope 1550 ns.
CAL_PC[3:0]
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Table 14. CR4 INSTRUCTION DEFINITIONS
Mnemonic
Value
000
001
010
011
100
101
110
111
Comment
CAL_SEL[2:0]
Calibration unit disabled (default).
Select output HB1.
Select output HB2.
Select output HB3.
Select output HB4.
Select output HB5.
Select output HB6.
Select output SH7.
Table 15. CR5A − CR11A: HBx CONFIGURATION A REGISTER
CR5A – CR11A
WD
WD
D10
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BLANKx[1:0]
I_PCFx[2:0]
I_PCRx[2:0]
T_PCx[1:0]
Table 16. CR5A − CR11A INSTRUCTION DEFINITIONS
Mnemonic
Value
00
Comment
Select cross−conduction blanking time 1 ms (default).
BLANKx[1:0]
01
Select cross−conduction blanking time 2 ms.
10
Select cross−conduction blanking time 3 ms.
11
Select cross−conduction blanking time 4 ms.
I_PCFx[2:0]
I_PCRx[2:0]
T_PCx[1:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
00
Select falling slope pre−charge current 28.88mA (default).
Select falling slope pre−charge current 35.63 mA.
Select falling slope pre−charge current 42.00 mA.
Select falling slope pre−charge current 48.38 mA.
Select falling slope pre−charge current 55.13mA.
Select falling slope pre−charge current 61.50 mA.
Select falling slope pre−charge current 67.88 mA.
Select falling slope pre−charge current 74.63 mA.
Select rising slope pre−charge current 1.50 mA (default).
Select rising slope pre−charge current 5.25 mA.
Select rising slope pre−charge current 8.63 mA.
Select rising slope pre−charge current 12.38 mA.
Select rising slope pre−charge current 16.50 mA.
Select rising slope pre−charge current 20.25 mA.
Select rising slope pre−charge current 24.00 mA.
Select rising slope pre−charge current 28.13 mA.
Select rising/falling slope pre−charge time 100 ns (default).
Select rising/falling slope pre−charge time 200 ns.
Select rising/falling slope pre−charge time 300 ns.
Select rising/falling slope pre−charge time 400 ns.
01
10
11
Table 17. CR5B − CR11B: HBx CONFIGURATION B REGISTER
CR5B – CR11B
WD
WD
D10
1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VDSx[2:0]
T_DLY[3:0]
SR_CTRL[2:0]
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Table 18. CR5B − CR11B INSTRUCTION DEFINITIONS
Mnemonic
Value
000
Comment
VDSx[2:0]
Select VDS sense threshold 300 mV (default).
Select VDS sense threshold 400 mV.
Select VDS sense threshold 500 mV.
Select VDS sense threshold 600 mV.
Select VDS sense threshold 700 mV.
Select VDS sense threshold 800 mV.
Select VDS sense threshold 900 mV.
Select VDS sense threshold 1000 mV.
001
010
011
100
101
110
111
T_DLY[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
000
Select VDS overload detect delay 1.05 ms (default).
Select VDS overload detect delay 1.65 ms.
Select VDS overload detect delay 2.25 ms.
Select VDS overload detect delay 2.85 ms.
Select VDS overload detect delay 3.45 ms.
Select VDS overload detect delay 4.05 ms.
Select VDS overload detect delay 4.65 ms.
Select VDS overload detect delay 5.25 ms.
Select VDS overload detect delay 5.85 ms.
Select VDS overload detect delay 6.45 ms.
Select VDS overload detect delay 7.05 ms.
Select VDS overload detect delay 7.65 ms.
Select VDS overload detect delay 8.25 ms.
Select VDS overload detect delay 8.85 ms.
Select VDS overload detect delay 9.45 ms.
Select VDS overload detect delay 10.05 ms.
Select rising/falling slope slew phase current 1.5 mA (default).
Select rising/falling slope slew phase current 2.25 mA.
Select rising/falling slope slew phase current 3.38 mA.
Select rising/falling slope slew phase current 5.25 mA.
Select rising/falling slope slew phase current 7.88 mA.
Select rising/falling slope slew phase current 11.63 mA.
Select rising/falling slope slew phase current 17.25 mA.
Select rising/falling slope slew phase current 25.50 mA.
SR_CTRL[2:0]
001
010
011
100
101
110
111
Table 19. CR12: HBx DIAGNOSIS CONTROL REGISTER
CR12
WD
WD
D10
0
D9
0
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
TST_LS7 TST_LS5 TST_LS3 TST_LS1 TST_HS7 TST_HS5 TST_HS3 TST_HS1
Table 20. CR12 INSTRUCTION DEFINITIONS
Mnemonic
Value
Comment
TST_LSx
0
1
0
1
Disable low−side test current (default).
Enable low−side test current.
TST_HSx
Disable high−side test current (default).
Enable high−side test current.
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Table 21. CR14: HBx PWM DE−GLITCH
CR14
WD
WD
D10
0
D9
0
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
0
DGL7
DGL6
DGL5
DGL4
DGL3
DGL2
DGL1
Table 22. CR14 INSTRUCTION DEFINITIONS
Mnemonic
Value
Comment
0
1
Type 1 de−glitch: t
Type 2 de−glitch: t
= t
+ t
+ t
DLYx
(default).
PWM_DGL
BLANKx
PRCx
DGLx
= t
PRCx
+ t
DLYx
PWM_DGL
Table 23. CR15: TEST MODE REGISTER
CR15
WD
WD
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Factory Use Only
SPI Diagnosis Set
The first 3 bits D[15:13] serve as address bits, while the
13 bits D[12:0] are used as data bits. Output data for “not
used” register adresses is D[11:0] = 0. The address of the
Status Register (SRx) accessed for status information to be
retrieved via a subsequent SPI frame is selected by the
control register bits CR0.SRA_MODE and CR0.SRA[2:0]
(see Table 5, Table 6).
Two different reading modes are provided depending on
the SRA_MODE bit:
• when CR0.SRA_MODE = 0, the SRx address selected
via bits CR0.SRA[2:0] will be used for a single status
read command and the SR address returns to SR0
(device status register, default state) after reading;
All status diagnosis bits are initialized to logic 0 after a reset
event and in normal operation except:
• the NORMAL MODE (NM) bit indicates NORMAL MODE
when SRx.NM = 1;
• the Register Clear Flag (RCF) bit is set (SR0.RCF = 1)
after a mode change to NORMAL MODE
(see § Operating Modes).
The RCF bit indicates that all input and output registers
were initialized; the bit is cleared after SR0 is read.
All status diagnosis bits are latched with the exception of
the SR5.D[3:0] bits (see § Output Status Monitoring). To
de−latch a diagnosis:
• the referring failure has to be removed;
• when CR0.SRA_MODE = 1, the SRx address selected
via bits CR0.SRA[2:0] will be used for the next and all
further status read commands until a new address or
mode is selected.
• the referring failure bit has to be read by SPI diagnosis.
Refer to § Protection and Diagnosis to restart the outputs
after a fault condition. The SPI diagnosis set (output data
map) and output data structure prototype are shown in the
following tables.
The default reading mode and address after VCC POR or
wake−up is CR0.SRA_MODE = 0, CR0.SRA[2:0] = 00.
Table 24. SPI OUTPUT DATA FORMAT
Status Output Message Format
MSB
B15
A2
LSB
B14
A1
B13
A0
B12
NM
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D5
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
3−bit REGISTER
NORMAL
MODE
12−bit OUTPUT DATA
ADDRESS
Table 25. OUTPUT DATA STRUCTURE PROTOTYPE
Output Data Prototype
NM
NM
D11
?
D10
?
D9
?
D8
?
D7
?
D6
?
D5
?
D4
?
D3
?
D2
?
D1
D0
?
SRx
?
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Table 26. SPI OUTPUT REGISTER DEFINITIONS
Defined Status Output Registers (SRx)
D15
A2
0
D14
A1
0
D13
A0
0
D12
Register Name
Device Status
Alias
SR0
SR1
SR2
SR3
SR4
NM
HB 1…6 Status Monitor
HB 7 Status & VDS Monitors
HB 1…6 VDS Monitor
HBx Calibration Result
0
0
1
0
1
0
0
1
1
NM
1
0
0
SH7, DL7 & HB 1…6 Output Status
Not Used
SR5
SR6
SR7
1
0
1
1
1
0
Device ID/Test Mode
1
1
1
Table 27. SR0: DEVICE STATUS REGISTER
NM
NM
D11
TM
D10
D9
D8
D7
D6
D5
D4
OVF
D3
0
D2
0
D1
D0
0
SR0
RCF
FSM
SPIF
CPL
CPF
UVF
HB_QSB
Table 28. SR0 RESPONSE DEFINITIONS
Mnemonic
Value
Comment
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
Test mode inactive (default).
Test mode active.
TM
Registers not cleared (command input and status output registers).
Registers cleared (after mode change to “NORMAL”).
FSM input pin = 0 (FSM not asserted).
FSM input pin = 1 (FSM asserted).
SPI message correct.
RCF
FSM
SPIF
CPL
CPF
UVF
OVF
SPI message failure.
Charge pump in regulation
V(CP, VS) < CP
−OR− VS < VSPWM (Charge Pump Low).
LOW
Half bridge high−side pre−driver activation allowed.
Half bridge high−side pre−driver activation not allowed (Charge Pump Fail).
VS supply in normal range.
VS supply below normal range.
VS supply in normal range.
VS supply above normal range.
D3
D2
Not used.
Not used.
Quick Status Bit: VDS normal – no overload detected.
Quick Status Bit: VDS failure – overload detected (VDS_Hx or VDS_Lx).
Not used.
HB_QSB
D0
Table 29. SR1: HBx STATUS MONITOR REGISTER
NM
NM
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SR1
SWH6
SWL6
SWH5
SWL5
SWH4
SWL4
SWH3
SWL3
SWH2
SWL2
SWH1
SWL1
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Table 30. SR1 RESPONSE DEFINITIONS
Mnemonic
Value
Comment
0
1
0
1
GHx output is “low” (default).
GHx output is “high”.
SWHx
GLx output is “low” (default).
GLx output is “high”.
SWLx
Table 31. SR2: HB 7 STATUS & VDS MONITOR REGISTER
SR2
NM
NM
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
VDS_H7
VDS_L7
SWH7
SWL7
Table 32. SR2 RESPONSE DEFINITIONS
Mnemonic
Value
Comment
0
1
0
1
0
1
0
1
SH7 high−side power switch normal – no overload detected (default).
SH7 high−side power switch failure – overload detected.
DL7 low−side power switch normal – no overload detected (default).
DL7 low−side power switch failure –overload detected.
GH7 output is “low” (default).
VDS_H7
VDS_L7
SWH7
SWL7
GH7 output is “high”.
GL7 output is “low” (default).
GL7 output is “high”.
Table 33. SR3: HBx VDS MONITOR REGISTER
SR3
NM
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NM VDS_H6 VDS_L6 VDS_H5 VDS_L5 VDS_H4 VDS_L4 VDS_H3 VDS_L3 VDS_H2 VDS_L2 VDS_H1 VDS_L1
Table 34. SR3 RESPONSE DEFINITIONS
Mnemonic
Value
Comment
HBx high−side power switch normal – no overload detected (default).
HBx high−side power switch failure – overload detected.
HBx low−side power switch normal – overload detected (default).
HBx low−side power switch failure – overload detected.
0
1
0
1
VDS_Hx
VDS_Lx
Table 35. SR4: HBx CALIBRATION RESULT REGISTER
SR4
NM
NM
D11
0
D10
0
D9
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
CAL_READY CAL_DLY_R[1:0]
CAL_PC_R[1:0]
CAL_DLY F[1:0]
CAL_PC _F[1:0]
Table 36. SR4 RESPONSE DEFINITIONS
Mnemonic
Value
0
Comment
Calibration result not ready or has been read via SPI (default).
CAL_READY
1
Calibration is successfully performed with a valid result (the bit is reset after SPI read command).
Rising slope result: VHBx < 15% (default).
Rising slope result: 15% < VHBx < 85%.
00
01
10
11
00
01
10
11
CAL_DLY_R[1:0]
CAL_PC_R[1:0]
Rising slope result: 85% < VHBx < 95%.
Rising slope result: VHBx >95%.
Rising slope result: VHBx < 5% (default).
Rising slope result: 5% < VHBx < 15%.
Rising slope result: 15% < VHBx < 85%.
Rising slope result: VHBx > 85%.
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Table 36. SR4 RESPONSE DEFINITIONS
00
01
10
11
00
01
10
11
Falling slope result: VHBx > 85% (default).
Falling slope result: 85% > VHBx > 15%.
Falling slope result: 15% > VHBx > 5%.
Falling slope result: VHBx < 5%.
CAL_DLY_F[1:0]
Falling slope result: VHBx > 95% (default).
Falling slope result: 95% > VHBx > 85%.
Falling slope result: 85% > VHBx > 15%.
Falling slope result: VHBx < 15%.
CAL_PC _F[1:0]
Table 37. SR5: HBx OUTPUT STATUS REGISTER
SR5
NM
NM
D11
0
D10
0
D9
0
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
SH_OUT7 DL_OUT7
HB_OUT6 … HB_OUT1
Table 38. SR5 RESPONSE DEFINITIONS
Mnemonic
Value
Comment
SH_OUT7
0
1
0
1
0
1
Output < VHB
Output > VHB
Output < VHB
Output > VHB
Output < VHB
Output > VHB
(default).
(default).
(default).
THR
THR.
THR
THR.
THR
THR.
DL_OUT7
HB_OUTx7
Table 39. SR7: TEST MODE STATUS REGISTER − SR0.TM = 1: TEST MODE FORMAT
SR7
NM
NM
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D0
Factory Use Only
Table 40. SR7: DEVICE ID/TEST MODE STATUS REGISTER − SR0.TM = 0: DEVICE ID FORMAT
SR7
NM
NM
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DEV_ID[11:9]
DEV_ID[8:6]
DEV_ID[5:3]
DEV_ID[2:0]
Table 41. SR7 RESPONSE DEFINITIONS: DEVICE ID FORMAT
Mnemonic
ID Type
Value
000
Comment
NCV7547
001
NCV7544
DEV_ID[11:9]
Device Name
010
NCV7546
011−111
000
etc.
Generation 0
Generation 1 etc.
Generation 0 (NCV7547)
First Silicon (REV_n.m)
DEV_ID[8:6]
DEV_ID[5:3]
DEV_ID[2:0]
Generation
Silicon Revision
Mask Revision
001−110
111
000
001
Second Silicon (REV_n+1.m)
etc.
010−111
000
Initial Mask Revision (REV_n.m)
001
First Mask Revision (REV_n.m+1)
etc.
010−111
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NCV7547
Control of Half−bridge Drivers
When not in test mode (SR0.TM = 0), a status request via
CR0.D[10:7] returns SR7.D[11:0] = DEV_ID[11:0] as
defined in Table 41. The default content of SR7 after VCC
POR or wake−up is SR7.D[11:0] = 0.
The DEV_ID[5:0] revision value may be changed based on
whether the entire die (silicon) or intermediate layer (mask)
is affected. The revisions can be e.g. classified accordingly:
The operation of the drivers is controlled by SPI
configuration individually for each driver. All half−bridges can
be operated in 100% “ON” mode as well as in PWM mode.
The control schema for HB1 … HB7 in half−bridge
configuration and for HB7 in split configuration is shown in
Table 44 (see also § SPI Control Set).
The CR0.HB_ENx bits are used to enable the operation of
the selected half−bridges and to re−start the drivers after a
fault condition:
• silicon revision: defined area changed (isolation pocket or
other boundary, bond pad etc. changed/moved) or digital
core changed (isolation pocket changed or unchanged);
• mask revision: interconnect changed (metal and/or
polysilicon/contact/via).
• when CR0.HB_ENx=0, the GHx and GLx outputs are
disabled (i.e. VGS ≈ 0 V);
• when CR0.HB_ENx=1, the GHx and GLx outputs are
enabled.
The mask revision value is set to DEV_ID[2:0] = 000
whenever the die revision is incremented. Table 42 shows
how the value encoding scheme is used to indicate the device
revision level.
The CR1.HB_CFG7 bit is used to enable the split
configuration of half−bridge HB7:
• when CR1.HB_CFG7=0, HB7 is in operating in
half−bridge configuration;
Table 42. DEVICE REVISION LEVEL ENCODING
• when CR1.HB_CFG7=1, HB7 is in operating in split
Silicon Revision
DEV_ID[5:3] LEVEL
Mask Revision
DEV_ID[2:0] LEVEL
configuration.
NOTE: When operating HB7 in split configuration, both
the high−side and low−side switches are in
ON−state simultaneously. Therefore the
CR1.HB_CFG7 bit should only be set to ‘1’
when the application hardware is configured
correctly. In case of erratic hardware
000
001
010
011
100
101
110
111
A
B
C
D
E
F
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
configuration, VDS overload monitoring
protects the external power switches.
G
H
The CR1.HB_MODEx bits are used to control the polarity
of the selected half−bridge:
• when CR1.HB_MODEx=0, the low−side driver (PDL)
Half−bridge Gate Drivers
is in an ON state (i.e. GLx = VGS ≈ V
, see
PDLX
The half−bridge drivers are used to control the gates of
external logic−level NMOS power switches. Drivers HB1
… HB6 are dedicated to e.g. motor control – the switches are
normally connected in half−bridge configuration. HB7 is
dedicated to e.g. heater control – the switches are normally
connected independently in a split configuration but may be
optionally connected in a half−bridge configuration (see
Figure 2). The device is initialized at power−up into a reduced
power state (CR1.DRV_EN = 0, see Table 7, Table 8):
§ Electrical Characteristics: Half−Bridge Pre−Driver
Outputs);
• when CR1.HB_MODEx=1, the high−side driver (PDH)
is in an ON state (i.e. GHx = VGS ≈ V , see
PDHX
§ Electrical Characteristics: Half−Bridge Pre−Driver
Outputs).
The CR2.HB_PWMx bits are used to enable PWM mode
control of the selected half−bridge:
• when CR2.HB_PWMx=0, an output is in 100% ON
state according to its CR1.HB_MODEx bit;
• when CR2.HB_PWMx=1, an output is in PWM with
state according to its CR1.HB_MODEx bit.
• the charge pump is disabled;
• all gate drive currents are disabled.
• HBx diagnostic test currents are available (see
§ Monitoring of Half−bridge Drivers in OFF−state).
The device is placed into a full power state when
CR1.DRV_EN = 1. The half−bridges are held in
high−impedance state (external NMOS are off) via gate
pull−down structures which are activated during power−up,
while in reduced power state, or when in sleep mode.
The application of a PWM mode selected via the
CR2.HB_PWMx bits to the corresponding output is
performed asynchronous to the PWMx input (i.e. a change
is applied after the rising edge of the CSB signal). Each
half−bridge can be controlled in PWM mode by one of the
PWMx inputs as selected via the CR3.PWMx[1:0] bits
according to Table 43 (see also Table 11, Table 12):
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NCV7547
The application of a selected PWMx input signal routing
Table 43. CR3A/CR3B: PWM SOURCE SELECTION
to the corresponding output is performed asynchronous to
the PWMx input (i.e. a change is applied after the rising edge
of the CSB signal).
The selected output is controlled via the selected
positive−logic PWMx input (see Figure 8):
PWMx1
PWMx0
PWM Source Selection
0
0
1
1
0
1
0
1
Output PWM source is input PWM1
Output PWM source is input PWM2
Output PWM source is input PWM3
Output PWM source is input PWM4
• when input PWMx=0, the driver defined by its
HB_MODEx bit is turned OFF (i.e. VGS ≈ 0 V) and its
complementary gate driver is turned ON (i.e. VGS ≈
V
PDHX
or VGS ≈ V
);
PDLX
Table 44. HBx DRIVER CONTROL
CR0
CR1
CR1
CR2
External MOS Power
HB_ENx
HB_CFG7*
HB_MODEx
HB_PWMx
Switches Operation Mode
Output
Comment
0
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
X
0
1
0
1
X
0
1
X
0
0
1
1
0
1
1
HBx “OFF”
Disable (HBx = Hi−Z)
Low−side “ON”
HB1...HB7
Half−bridge
Configuration
100% “ON”
High−side “ON”
Low−side PWM
PWM Mode
100% “ON”
High−side PWM
Low−side & high−side “ON”
Low−side “ON”, high−side PWM
High−side “ON”, low−side PWM
HB7
Split
Configuration
PWM Mode
*HB_CFG7 = X for HB1...HB6 operations.
Switching Behavior of Half−bridge Drivers
• when input PWMx=1, the driver defined by its
HB_MODEx bit is turned ON (i.e. VGS ≈ V
The external high−side NMOS switches are controlled
with gate pre−charge and slew phases, while the external
low−side switches are controlled via simple drive stages
supplying a nominal 4x multiple of the selected high−side
driver slew current (see Figure 9 and § Electrical
Characteristics: Pre−driver Slope Control). The timing for
the gate drivers is provided by the digital logic, where the
key parameters can be programmed via SPI in order to adapt
different MOSFET types and application switching speeds.
Each individual half−bridge can be programmed via three
configuration registers, e.g. CR5A and CR5B for HB1, and
CR14 (see § SPI Control Set, Table 15 − Table 17 and
Table 21, summarized in Table 45):
or
PDHX
V
) and its complementary gate driver is turned
PDLX
OFF (i.e. VGS ≈ 0 V).
When multiple PWMx inputs are needed to be active, the
scheduled PWM signals should be offset in time to avoid
degradation of the VDS overload detection due to crosstalk
(see § Overload Protection). The minimum offset should be
based on the t
times appropriate for the respective
PWM_DGL
channels (see § Switching Behavior of Half−bridge Drivers,
Figure 10 and Figure 11).
NOTE: The PWM source selection logic does not
prevent more than one half−bridge output to be
controlled by the same PWMx input.
Table 45. HALF−BRIDGE CONFIGURATION REGISTERS
WD
WD
D10
0
D9
D8
D7
D6
D5
D5
D4
D3
D2
D2
D2
D1
D0
CR5A – CR11A
CR5B – CR11B
CR14
BLANKx[1:0]
I_PCFx[2:0]
I_PCRx[2:0]
T_PCx[1:0]
WD
WD
D10
1
D9
D8
D7
D6
D4
D3
D1
D0
VDSx[2:0]
T_DLY[3:0]
SR_CTRL[2:0]
WD
WD
D10
0
D9
0
D8
0
D7
0
D6
D5
D4
DGL5
D3
D1
D0
DGL7
DGL6
DGL4
DGL3
DGL2
DGL1
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NCV7547
GHx
GLx
0
time
PWMx
HB_PWMx
Low-side
High-side
High-side PWM
Low-side PWM
ON
ON
HB_MODEx
HB_ENx
0
time
Note 1. GLx and GHx are for the same HBx output control (e.g. HB1: GL1, GH1).
Note 2. GLx and GHx time offset from PWMx via adaptive PWM input de-glitch not shown.
Figure 8. Gate Drive Operation in PWM Mode
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NCV7547
For each individual half−bridge:
• cross−conduction blanking time is selected via the
BLANKx[1:0] bits;
• pre−charge current is selected via the I_PCRx[2:0]
bits for the rising slope and via the I_PCFx[2:0]
bits for the falling slope;
Please refer to § Electrical Characteristics for defined
blanking (t ), pre−charge (t ,
PRCX_R
,
I
BLANKX
PRCX
I
), slew (I
PRCX_F
), delay (t
) and VDS threshold
SRX
DLYX
(VDS
) parametric values.
THRX
NOTE: A proper initial switching parameter set (e.g.
VDS , t , I , I ) for a
I
THRX PRCX PRCX_R SRX, PRCX_F
• pre−charge time for both slopes is selected via the
chosen MOSFET has to be evaluated for a
desired switching speed (see also § Overload
Protection).
T_PCx[1:0] bits;
• slew current for both slopes is selected via the
SR_CTRLx[2:0] bits – this parameter controls the
external NMOS switches’ rise/fall times to adopt proper
EMC performance and minimize switching losses;
• VDS overload detection delay is selected via the
T_DLYx[3:0] bits – this parameter controls when the
VDS overload detection is performed (see § Overload
Protection);
• VDS overload detection threshold is selected via the
VDSx[2:0] bits – this parameter controls the VDS
monitoring comparator threshold (see Table 17,
Table 18);
• adaptive PWM input de−glitch construction when in
half−bridge configuration is selected by DGLx[6:0] bits
(see Figure 10, Figure 11, Table 21 and Table 22).
When operated in PWM mode, the PWMx input signals
are each provided with a symmetrical de−glitch within a
)
half− bridge’s control logic. The de−glitch time (t
PWM_DGL
,
,
is adapted to the SPI settings t
t
t
and
BLANKX PRCX DLYX
DGLx as selected for each channel (see § Electrical
Characteristics: Half−Bridge Pre−Driver Outputs &
Pre−driver Slope Control).
The adapted t
avoids mistreatment of the
PWM_DGL
half−bridge drivers by ensuring that a complete turn−on or
turn−off sequence is executed (erratic pulse widths are
thereby avoided) and assures correct operation of the VDS
overload protection (see § Overload Protection).
PWMx_DGL
1
< DEGLITCHED INTERNAL SIGNAL >
time
0
tBLANK
tBLANK
tBLANK
I(GHx)
tPRCx
tPRCx
tTIMEOUT
−I
PRCX_R
−I
SRX
−I
GHx_SS
0
time
+ISRX
+IPRCX_F
I(GLx)
−I
LSX
0
time
+ILSX
Figure 9. Gate Drive Current Evolution
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29
NCV7547
t
PWM_DGL + tPRCX ) tDLYX
In order to not overload the charge pump circuit in case of
(eq. 2)
loss of VS or in case of a disconnected security switch, the
When operating HB7 in PWM mode and in split
configuration, the adapted time is type 2 (CR14.DGL7 = X).
steady state output current of the high−side gate drivers is
(
limited to I
after t
see I(GHx) in Figure 9
GHX_SS
TIMEOUT
NOTE: To avoid synchronization issues, the de−glitch
type must be selected before beginning PWM of
a load.
Once a switching parameter set for EMC optimization and
stable VDS overload detection has been chosen, the
allowable duty ratio (D) is bounded by the selected adaptive
de−glitch type and PWM frequency such that:
and § Electrical Characteristics: Half−Bridge Pre−Driver
Outputs).
NOTE: Driver turn−ON/OFF via SPI (i.e.
CR1.HB_MODEx bits) includes both the
pre−charge and slew phases, but adapted
de−glitch strategy is not applied.
When operating HB1…HB7 in PWM mode and in
half−bridge configuration, type 1 de−glitch is selected when
CR14.DGLx = 0 (see Figure 10) and the adapted time is
given by:
ǒ
Ǔ
fPWM tPWM v D v 1 * fPWM tPWM
(eq. 3)
DGL
DGL
When operating HB1…HB7 in PWM mode and in
half−bridge configuration, the timing of the gate drivers is
according to Figure 12.
t
PWM_DGL + tBLANKX ) tPRCX ) tDLYX
(eq. 1)
Type 2 de−glitch is selected when CR14.DGLx = 1 (see
Figure 11) and the adapted time is given by:
PWMx
1
0
time
tPRCx
tDLYx
tPRCx
tDLYx
tBLANKX
tBLANKX
tPWM_DGL
tPWM_DGL
PWMx_DGL
1
0
< DEGLITCHED INTERNAL SIGNAL >
time
Type 1 PWM De−glitch
PWM_DGL = tBLANKX + tPRCX + tDLYX
t
Figure 10. Type 1 PWMx Input De−glitch − CR14.DGLx = 0
PWMx
1
0
time
time
tPRCx
tDLYx
tPRCx
tDLYx
tPWM_DGL
tPWM_DGL
PWMx_DGL
1
0
< DEGLITCHED INTERNAL SIGNAL >
Type 2 PWM De−glitch
t
PWM_DGL = tPRCX + tDLYX
Figure 11. Type 2 PWMx Input De−glitch − CR14.DGLx = 1
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30
NCV7547
PWMx_DGL
1
0
< DEGLITCHED INTERNAL SIGNAL >
time
tBLANK
tPRCx
tBLANK
tPRCx
V(GHx)
VPDHX
VGSP
V(HBx)
V(GLx)
VPDLX
time
PGND
V(HBx)
time
tDLYx
tBLANK
tDLYx
VS
0.9 VS
0.5 VS
VHBTHR
0.1 VS
GND
time
High−side
VDS Overload
Detection
Low−side
VDS Overload
Detection
Figure 12. HBx Output Switching in Half−Bridge Configuration
Slope Control Calibration Unit
When operating HB7 in PWM mode and in split
configuration, both the high−side and low−side drivers can
be in the ON−state simultaneously. Cross−conduction does
A slope control calibration unit is implemented in order to
allow adjustments to a selected MOSFET’s initial switching
parameter set and to verify proper setting of the high−side
gate drivers (GHx). The calibration assists optimizing EMC
performance and alignment of the GHx switching slopes
with the VDS overload detection delay time and threshold
to assure stable behavior of the protection strategy (see
§ Overload Protection).
not occur however, therefore t
is not needed and the
BLANK
timing of the gate is according to Figure 13 (e.g.
HB_CFG7=1, HB_PWM7=1, HB_MODE7=0 is shown).
In either configuration, in the pre−charge phase (V
<
GHX
V
GSP
) the GHx output delivers the selected rise (I
)
PRCX_R
or fall (I
) current for the selected time (t
), and in
PRCX_F
PRCx
A calibration detection unit, consisting of 4 multiplexed
high−speed comparators, samples the voltage at the desired
the slew phase (V
delivers the selected current (I
≤ V
≤ V
SRX
) the GHx output
) for up to the gate drive
GSP
GHX
PDHX
HBx input at a selected calibration sample time (see
timeout time (t
). After t
, the GHx output
). The GLx output
TIMEOUT
TIMEOUT
,
t
t
in § Electrical Characteristics: Slope
delivers the timeout current (I
CAL_PCx CAL_DLYx
GHx_SS
Control Calibration Unit). A complete calibration cycle
consists of sampling both the rising and falling switching
slopes, and the encoded calibration result is stored in the
device’s calibration register (SR4).
always delivers a multiple (I ) of the selected slew current
(see Figure 9 and § Electrical Characteristics: Half− Bridge
LSX
Pre−Driver Outputs, Pre−driver Slope Control)
.
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NCV7547
PWMx_DGL
1
0
< DEGLITCHED INTERNAL SIGNAL >
time
tBLANK
tPRCx
tBLANK
tPRCx
V(GH7)
VPDHX
VGSP
time
V(SH7)
V(GL7)
VPDLX
PGND
V(SH7)
time
tDLYx
tBLANK
tDLYx
VS
0.9 VS
0.5 VS
VHBTHR
0.1 VS
GND
time
High−side
VDS Overload
Detection
Low−side
VDS Overload
Detection
Figure 13. HB7 Output Switching in Split Configuration
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Calibration is enabled when the calibration register (CR4)
and falling edges are completed (see Figure 13). The
detection results are stored in the calibration result register
SR4 (summary Table 46 − see also Table 33):
is written (summary Table 46 − see also Table 13):
• the desired HBx input is selected by the
CR4.CAL_SEL[2:0] bits where the resulting binary
code refers directly to the selected half−bridge
(e.g. 100 = HB4);
The CAL_READY bit indicates that when:
• SR4.CAL_READY = 0, calibration has not been
executed OR the calibration result has been read;
• SR4.CAL_READY = 1, successful detection was
performed for both slopes AND a valid comparator
output state is delivered.
• the detection pre−charge and delay sample times
(t
and t
) for calibration of the desired
CAL_PCx
CAL_DLYx
input are selected individually by the
CR4.CAL_PC[3:0] bits and by the
CR4.CAL_DLY[3:0] bits for both the rising and falling
slopes.
As long as the CAL_READY bit is not set (≠ 1), the
calibration of a particular slope for the selected channel may
be repeated. Calibration may be terminated by sending
CR4.CAL_SEL[2:0] = 000.
The calibration result is encoded in the SR4.
CAL_PC_R[1:0] bits and the SR4.CAL_DLY_R[1:0] bits
for the rising slope and in the SR4. CAL_PC_F[1:0] bits and
the SR4.CAL_DLY_F[1:0] bits for the falling slope
according to Table 47.
The calibration unit is turned off when
CR4.CAL_SEL[2:0] = 000 (POR default) is selected (see
also Table 14).
Detection is started with the next edge of a routed PWMx
input signal (see § Control of Half−bridge Drivers) on the
selected channel and detection is finished when both rising
Table 46. HBx CALIBRATION CONTROL AND RESULT REGISTERS
WD
WD
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CR4
CAL_DLY[3:0]
CAL_PC[3:0]
CAL_SEL[2:0]
NM
NM
D11
0
D10
D9
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
SR4
0
CAL_READY CAL_DLY_R[1:0]
CAL_PC_R[1:0]
CAL_DLY F[1:0]
CAL_PC _F[1:0]
Table 47. CALIBRATION RESULT RELATIVE TO HBx SAMPLE TIME
Relative HBx Level Detected
at Selected Sample Times
Mnemonic
Value
Comment
Start of Rising Slope
00
01
10
11
VHBx < 5%
5% < VHBx < 15%
15% < VHBx < 85%
VHBx > 85%
Pre−charge too low.
Pre−charge within target.
Pre−charge too high.
CAL_PC_R[1:0]
Pre−charge far too high.
End of Rising Slope
CAL_DLY_R[1:0]
00
01
10
11
VHBx < 15%
15% < VHBx < 85%
85% < VHBx < 95 %
VHBx >95%
Transition far too slow.
Transition slightly too slow.
Gate drive setting correct.
Transition too fast.
Start of Falling Slope
CAL_PC _F[1:0]
00
01
10
11
VHBx > 95%
95% > VHBx > 85%
85% > VHBx > 15%
VHBx < 15%
Pre−charge too low.
Pre−charge within target.
Pre−charge too high.
Pre−charge far too high.
End of Falling Slope
CAL_DLY_F[1:0]
00
01
10
11
VHBx > 85%
85% > VHBx > 15%
15% > VHBx > 5%
VHBx < 5%
Transition far too slow.
Transition slightly too slow.
Gate drive setting correct.
Transition too fast.
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The temporal position (see Figure 13) of the target
transition detection point (e.g. 10%, 90%) with respect to
or t (or in normal operation, t ) of
• the I
slew phase current setting.
SRX
Calibration may be performed at the application level
during module end−of−line (EOL) test where the (adjusted)
settings may be stored in a microcontroller’s EEPROM. In
order to maintain stable function and proper EMC
performance with temperature drift and output load
variations, the calibration can be verified/updated on a
sample basis during normal application operation.
t
CAL_PCx
CAL_DLYx
DLYX
the channel selected for calibration is dependent upon:
• the PWMx_DGL resulting from the channel’s operating
configuration (see § Switching Behavior of Half−bridge
Drivers, Figure 10 and Figure 11);
• the t
cross−conduction blank time setting as
BLANKX
applicable;
• the t , I
and I
pre−charge phase time
PRCX PRCX_R
and current settings;
PRCX_F
PWMx_DGL
< DEGLITCHED INTERNAL SIGNAL >
PWMx_DGL
BLANK
tBLANKx
tBLANKx tBLANKx
tPRCx
tPRCx
PRE−CHARGE
tDLYx
tDLYx
(Low−side Overload)
SLEW
(High−side Overload)
time
V(HBx)
VCALR_U
90%
VCALR_L
95%
85%
RISING
SLOPE
FALLING
SLOPE
VCALF_U
15%
10%
VCALF_L
5%
time
CALx
tCAL_PCx
tCAL_PCx
CAL PRE−CHARGE
CAL SLEW
tCAL_DLYx
tCAL_DLYx
CAL_PC_R[1:0]
CAL_DLY_R[1:0]
CAL_PC_F[1:0]
CAL_DLY_F[1:0]
“01”
“10”
“01”
“10”
“1”
CAL_READY
time
Figure 14. HBx Slope Control Calibration
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OVERLOAD PROTECTION
Overload Protection
• the SR0.HB_QSB Quick Status Bits and the
appropriate VDS_Hx or VDS_Lx bit is latched in the
corresponding VDS monitor status register (SR2:
HB1...HB6 and SR3: HB7 − see Table 31 thru
Table 34).
A VDS monitoring technique is used to protect the
external MOS power switches in case of overload resulting
from short circuit conditions applied before or during the
turn−on process of the power switches (“short circuit 1”
condition), and short circuit conditions applied after the
turn−on process of the power switches (“short circuit 2”
condition).
The thresholds of the VDS monitoring comparators
(CMP1 and CMP2 in Figure 15 and Figure 16) are SPI
programmable for each individual half−bridge via the
VDSx[2:0] bits in the HBx configuration “B” registers. An
When a switch is in the ON−state and its drain−source
voltage exceeds the programmed VDS threshold (“short
circuit 2” condition, t > t
):
DLYx
• the corresponding half−bridge’s GHx and GLx drivers
are latched off immediately after the fixed de−glitch
time t
;
DGL_STAT
• the SR0.HB_QSB Quick Status Bits and the
appropriate VDS_Hx or VDS_Lx bit is latched in the
corresponding VDS monitor status register.
overload detection delay time parameter (t
) – which
DLYx
controls when the VDS overload detection is performed – is
also SPI programmable via the T_DLY[3:0] bits in the HBx
configuration “B” registers (see Table 17, Table 18 and
§Electrical Characteristics: Half−Bridge Diagnostics).
When a switch is in the turn−on process and its
drain−source voltage already exceeds the programmed VDS
threshold (“short circuit 1” condition):
Please refer to §Output Fault (Local) Protection to restart
the half−bridge drivers after a shutdown event.
NOTE: Additional protection via use of current sensing
in the low−side path of the power MOSFETs
(see Figure 2) may be necessary in order to
• the corresponding half−bridge’s GHx and GLx drivers
avoid destruction due to soft short condition.
are latched off immediately after the selected delay
time t
plus a fixed de−glitch time t
;
DLY
DGL_STAT
HB1...HB6 Diagnostic & Overload Protection
(Half−bridge Configuration)
CR1.D[5:0]
HB_MODEx
VDSTHR_S
VS
tDLY
+
tDGL_STAT
CMP1
SECURITY
SWITCH
−
STATIC VDS
VBAT_P
GHx
(reset dominant)
R
Q
PDH
LATCH
Q
S
VDS_HX
HBx
LOAD
SR3.D[11:0]
VDS_LX
S
Q
Q
GLx
PDL
LATCH
R
(reset dominant)
STATIC VDS
3−5
mW
+
PGND
CMP2
tDGL _STAT
tDLY
−
VDSTHR_S
SR5.D[5:0]
HB_OUTx
+
CMP3
VHBTHR
−
TRANSPARENT VS /2
= INDIRECT PATH
Figure 15. HB10HB6 Diagnostic and Overload Protection
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35
NCV7547
HB7 Diagnostic & Overload Protection
(Split Configuration )
CR1.D[6]
HB_MODE7
TRANSPARENT VS /2
VHBTHR
−
SH_OUT7
SR5.D[7]
CMP4
+
VDSTHR_S
VS
tDLY
tDGL_STAT
+
CMP1
SECURITY
SWITCH
−
STATIC VDS
VBAT_P
GHx
(reset dominant)
R
Q
PDH
LATCH
Q
S
VDS_H7
SH7
DL7
SR2.D[3:2]
VDS_L7
LOAD
S
Q
Q
GLx
PDL
LATCH
R
(reset dominant)
STATIC VDS
3−5
mW
+
PGND
CMP2
tDGL _STAT
tDLY
−
VDSTHR_S
SR5.D[6]
DL_OUT7
+
CMP3
VHBTHR
−
TRANSPARENT VS /2
= INDIRECT PATH
Figure 16. HB7 Diagnostic and Overload Protection
Gate Protection Features
OFF−state Monitoring of Half−bridge Drivers
The half−bridge gate drivers provide integrated gate
protection features for the external power MOSFETs:
In order to support functional safety and to avoid
unintended motor activation, the status of each of the
half−bridge gate drivers can be monitored by SPI diagnosis
(see § Gate Driver Status Monitoring). The switch nodes
(i.e. HBx) status can be monitored by SPI communication
via the half−bridge output status register (SR5.D[7:0] − see
Table 35, Table 36). The system response depends on the
load configuration; the test procedure has to be provided by
the supervising microcontroller.
• a passive pull−down resistor R
keeps the MOSFET
GSX
in OFF−state, when no control of the device is available
(see § Package Pin Description and § Electrical
Characteristics: Half−Bridge Pre−Driver Outputs);
• a clamping structure limits the gate−source voltage to
+V
or to −V
in order to protect the
GSX_CLP
GSX_CLN
power MOSFETs from destruction via e.g. gate oxide
failure (see § Electrical Characteristics: Half−Bridge
Pre−Driver Outputs).
Several test current sources (I
– see § Electrical
TST
Characteristics:
Half−Bridge
Diagnostics)
and
comparators are implemented in order to provide OFF−state
diagnosis of the power MOSFET half−bridges.
The resistors and clamping structures are available in all
operating modes, including SLEEP MODE and in case of loss
of supply voltage.
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36
NCV7547
The diagnostic consists of (see Figure 14 and Figure 15):
• a high−side and a low−side test current source at each
odd−numbered HBx feedback input;
• a comparator (CMP5) at each HBx feedback input.
activated individually by the TST_HSx and TST_LSx bits
in the HB diagnosis register (CR12.D[5:0] − see Table 19,
Table 20). Active pull−down current sources are disabled in
all GHx when any test current is activated via CR12. Passive
pull−down structures are always present.
Provided the device is in NORMAL MODE (see §Operating
Modes) and no global failure (see § Device Fault (Global)
Protection) has been detected, the test current sources can be
NOTE: Both TST_HSx and TST_LSx test currents can
be turned on simultaneously.
… HB
HB1
6 OFF−State Diagnostic
HB7 OFF−State Diagnostic
VS
VS
ITST
ITST
R
HB1, HB3,
CR12.TST_HS7
HB5
CR12.TST_HSx
SH7
+
SR5.SH_OUT7
SR5.DL_OUT7
CMP4
SR5.D[3:0]
HB_OUTx
HB1 ... HB6
+
−
CMP5
VHBTHR
−
DL7
ITST
+
ITST
R
CMP3
VHBTHR
HB1, HB3,
HB5
−
CR12.TST_LSx
CR12.TST_LS7
PGND
PGND
AGND
= INDIRECT PATH
Figure 17. Half−bridge OFF−state Diagnostic
Operating Modes
SR0.RCF bit inside the device status register is set (see
Table 27, Table 28).
The device enters FAILSAFE MODE when the device is
active and either a SPI failure condition is detected or the
external fail input (FSM) is activated i.e. FAILSAFE =
(RSTB = 1) AND [(SPIF=1) –OR– (FSM=1)].
The operating modes of the device are shown in the
diagram of Figure 16. The logic input pin pull up / pull down
resistors and the integrated gate protection pull−down
resistors and clamping structures (see § Gate Protection
Features) are available in all operating modes.
The SLEEP MODE is the default mode after applying VCC
In FAILSAFE MODE:
• the half−bridge gate drive outputs (GHx, GLx) are
disabled immediately;
• the HBx test currents (see § OFF−state Monitoring of
Half−bridge Drivers) are disabled immediately;
• the CPSW output is deactivated (the external MOS
half−bridge switches may be locked additionally by an
optional external security switch which can be under
control of a separate supervisory microcontroller (see
“WD_EN” in Figure 2) in order to support functional
safety even in case of logic issues/single point failures);
(VCC < VCC ) and while VCC > VCC
PORF
(power−on
PORR
reset) prior to wake−up of the device. During SLEEP MODE:
• the device is inactive and all outputs are disabled.
The device enters NORMAL MODE after applying the
wake−up signal (i.e. RSTB 0 → 1). During NORMAL MODE:
• the device is active (RSTB = 1);
• the entire device functionality is available;
• the SPI can be used to provide control and diagnosis of
the device.
When the device enters NORMAL MODE the internal
registers and settings are cleared to default values and the
• the charge pump is disabled;
• SPI control is not possible.
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37
NCV7547
VCC < VCCPOR
VCC > 0
SLEEP
MODE
VCC < VCC POR
−OR−
VCC < VCCPOR
−OR−
RSTB = 0
RSTB = 0
VCC>VCC POR
−AND−
RSTB=1
FAILSAFE
MODE
NORMAL
MODE
FSM = 0
−AND−
SPIF = 0
SRx.NM = 0
SRx.NM = 1
FSM = 1 −OR− SPIF = 1
Figure 18. Operating Modes State Diagram
Although SPI control of the outputs is not possible in
FAILSAFE MODE, the status registers are not cleared during
the transition from NORMAL MODE to FAILSAFE MODE. The
device status therefore is accessible in FAILSAFE MODE as
long as the SPI interface is available (i.e. as long as VCC is
present). The SPI can thus be used in FAILSAFE MODE to
provide limited diagnosis of the device (CR0.SRA_MODE,
CR0.SRA[2;0]) and to re−enter NORMAL MODE.
Re−entering NORMAL MODE after FAILSAFE MODE is
achieved by toggling the WD bit while FSM = 0. After this
mode change the internal registers and settings are cleared
and the SR0.RCF bit inside the device status register is set
(see Table 27, Table 28).
PROTECTION AND DIAGNOSIS
NOTE: An external aluminum electrolytic capacitor at
the VS terminal is necessary to handle the
turn−off energy of the motors in emergency
condition.
again and the restart will not be successful. The restart will
be only successful after the error condition is removed. It is
recommended to use OFF state diagnosis (see § OFF−state
Monitoring of Half−bridge Drivers) to check the HBx node
for any failure condition before restarting the output.
Output Fault (Local) Protection
The external power MOSFET switches are protected
against overload condition (see § Overload Protection) in
NORMAL MODE by VDS monitoring. In case of a VDS
overload failure, the corresponding pre−driver outputs are
latched off (GHx = L AND GLx = L) after a de−glitch time
and the status is reported in the VDS monitor register SR3
(see Table 32).
Device Fault (Global) Protection
The device is protected against all relevant failure
conditions inside the automotive application. In case of a
fault condition, the affected outputs are latched off
immediately after a de−glitch time and the status is reported
the device status register (SR0 − see Table 27, Table 28).
To restart the device:
To restart a faulted half−bridge:
• the diagnosis has to be de−latched by reading the
corresponding failure flag;
• the output has to be restarted via the corresponding bits
in the CR0.HB_ENx register (see § SPI Control Set).
• the diagnosis has to be de−latched by reading the
corresponding failure flag (see § SPI Diagnosis Set);
• the functionality has to be restarted by use of the
corresponding control bit (see § SPI Control Set).
Charge Pump Monitoring
As long as a failure flag is not de−latched via SPI status
read, a faulted output cannot be turned back on. If the failure
condition is still present at a restart, the error flag will be set
The high−side pre−driver outputs are protected by charge
pump monitoring (see § Charge Pump, Figure 5 and
Figure 6):
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38
NCV7547
• when the battery supply voltage VS is below the
minimum supply voltage for a regulated charge pump
voltage OR V(CP,VS) drops below the minimum
• GH pull−down current is reduced to 1 mA
X
typ.(register contents are not changed − the current will
revert to its prior value after VS over−voltage is
resolved);
output voltage CP
this status is reported by the
LOW
SR0.CPL bit in the device status register immediately
after a de−glitch time t (see Table 27,
• the HBx test currents (see § OFF−state Monitoring of
Half−bridge Drivers) are disabled immediately.
CPL_DGL
Table 28). During this condition it should be considered
for the microcontroller to adopt a PWM duty ratio
management schema in order to minimize charge pump
loading while ensuring smooth motor operation.
The VS over−voltage condition is reported by the
SR0.OVF bit in the device status register (see Table 27,
Table 28). When the battery supply voltage is in
over−voltage condition VS > VS
the SR0.CPF bit is
OVSDR
• when the charge pump output voltage V(CP, VS) drops
masked. Please refer to § Device Fault (Global) Protection
to restart the outputs after a shutdown event.
A VCC overvoltage condition can occur during
breakdown of the external voltage regulator. Please refer to
§ Failure of External Voltage Regulator for details.
below the charge pump fail threshold CP , the half
FAIL
bridge high−side and low−side gate drivers are latched
off immediately after a de−glitch time t and the
CPF_DGL
status is reported by the SR0.CPF bit in the device
status register (see Table 27, Table 28).
• when the battery supply voltage VS is in the nominal
Under Voltage Condition
operation range VS
< VS < VS
the full
PWM
OVSDR
In case of VS under voltage condition:
• all outputs (GHx, GLx) are disabled immediately after
PWM operation of the GHx and GLx outputs is
allowed;
the de−glitch time t
and the condition is reported
UVDGL
• when the battery supply voltage is in over−voltage
by the SR0.UVF bit in the device status register (see
Table 27, Table 28);
condition VS > VS , the SR0.CPF bit is masked;
OVSDR
• when the battery supply voltage is in over−voltage
• the charge pump circuit and the switched charge pump
output (CPSW) are still functional in order to keep the
optional reverse battery and security switches active.
condition VS < VS < CP the charge pump
OVSDF
OV
− including the CPSW output − is functional but the
GHx outputs are shut down;
Please refer to § Device Fault (Global) Protection to
restart the outputs after a shutdown event.
In case of VCC under voltage condition (power−on reset
• when the battery supply voltage exceeds the maximum
supply voltage for the charge pump VS > CP the
OV
charge pump is disabled and the charge pump buffer
capacitor is discharged to VS in order to protect the
device from destruction.
condition, VCC < VCC
):
POR
• the device enters SLEEP MODE immediately without
de−glitch time;
• logic input pull−up/down resistors, GHx & GLx output
pull−down resistors, and VCC under voltage lockout
assure safe operating states for all outputs.
Please refer to § Device Fault (Global) Protection to
restart the outputs after a shutdown event.
Over−voltage Condition
During VS over−voltage, the behavior of the gate drivers
(GHx and GLx) depends on the programmed operation
mode:
To restart the device after this condition a wake−up
sequence is necessary (see § Operating Modes).
• the high side gate drivers (GHx) are latched off
Logic I/O Plausibility Check
The logic I/O pins are protected against mistreatment by
input de−glitch circuits. The de−glitch circuits are
implemented digitally, refer to § Electrical Characteristics:
Digital I/O for values.
immediately after de−glitch time t
(see
OVDGL
§ Electrical Characteristics: VS Supply) in order to
protect the application from over load condition; while
the low−side gate driver outputs (GLx) are operable in
order to provide controlled braking (e.g. for lift gate
motors);
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39
NCV7547
FUNCTIONAL SAFETY SUPPORT STRATEGY
The device uses a closed−loop verification strategy in
microcontroller by means of the SPI communication (see
Figure 14 and § SPI Diagnosis Set):
order to avoid mistreatment of the outputs and to support
functional safety. The verification strategy is implemented
based on the features in the following sections.
The output voltage levels of the half−bridge switches are
monitored by the transparent VS/2 comparators. The
comparator states are not latched and the current node states
are indicated by the HB_OUTx bits in the SR5 half−bridge
output status register. The controller can use the motor status
information for correlation of the operating mode, OFF state
diagnosis, or for controlled brake activation.
SPI Communication Monitoring
The SPI is protected against communication errors by use
of the WD toggle bit and protocol check features (see § SPI
Interface). In case of SPI communication error the device
enters FAILSAFE MODE immediately (see § Operating
Modes). A correct communication is reported in the NM bit
(see § SPI Diagnosis Set).
External Fail Mode Activation
The FAILSAFE MODE can be also activated by an external
signal (e.g. watchdog circuitry) via the FSM input. In case
of a malfunction of the microcontroller, an external
watchdog can cause the device to enter FAILSAFE MODE (see
§ Operating Modes).
Gate Driver Status Monitoring
The correct activation of the half−bridge drivers can be
monitored by the microcontroller by means of SPI
communication (see § SPI Diagnosis Set). The switching
status of the output drivers is indicated by the SWLx and
SWHx bits in the half− bridge status monitor register SR1.
The bit value corresponds to the logic status of the driver. In
PWM mode, both SWHx = 1 and SWLx = 1.
Failure of External Voltage Regulator
In case of breakdown of the external voltage regulator, the
device and the application’s VCC node may be protected
against overload by use of an optional external voltage
In case of a discrepancy between control data and status
information from the device, the microcontroller has to
drive the device into FAILSAFE MODE in order to avoid
mistreatment of the motor drives, then transition the device
to NORMAL MODE for reprogramming.
limiter circuit which must limit the voltage to VCC
Figure 2 and § MAXIMUM RATINGS).
The SPI port’s SO pin is protected against reverse biasing
by use of a back−to−back switch. The reverse voltage for this
(see
MAX
condition is limited to V_SO
(see § MAXIMUM
MAX
RATINGS).
Output Status Monitoring
The status of the MOS switches and the motor connection
lines can be monitored during NORMAL MODE by the
FLEXMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
40
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFNW48 7x7, 0.5P
CASE 484AJ
ISSUE C
DATE 20 NOV 2019
1
48
SCALE 2:1
EXPOSED
COPPER
GENERIC
MARKING DIAGRAM*
A
= Assembly Location
1
WL = Wafer Lot
YY = Year
WW = Work Week
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
G
= Pb−Free Package
(Note: Microdot may be in either location) not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON83011G
QFNW48 7x7, 0.5P
PAGE 1 OF 1
ON Semiconductor and
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