NCV7685DQR2G [ONSEMI]
12 沟道，60 mA LED 线性电流驱动器，可控制 I2C，用于汽车应用;
| 型号： | NCV7685DQR2G |
| 厂家： | 
ONSEMI |
| 描述： | 12 沟道，60 mA LED 线性电流驱动器，可控制 I2C，用于汽车应用 驱动 驱动器 |
| 文件： | 总19页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12 Channels 60 mA LED
Linear Current Driver I2C
Controllable for Automotive
Applications
NCV7685
www.onsemi.com
The NCV7685 consists of twelve linear programmable constant
current sources with common reference. The part is designed for use in
the regulation and control of LED for automotive applications. The
NCV7685 allows 128 different duty cycle levels adjustable using
pulse width modulation (PWM) independently for each output
2
channel programmable via I C serial interface. PWM frequency can
be chosen in four different configurations up to 1200 Hz. The device
can be used with micro−controller applications using the I C bus or in
stand−alone applications where a choice could be done in between 2
different static configuration settings. The IC also provides 3.3 V
voltage reference to the application for loads up to 1 mA.
2
SSOP24−NB EP
CASE 940AQ
MARKING DIAGRAM
LED brightness level is easily programmed using an external
resistor. Each channel has an internal circuitry to detect open−load
conditions with an optional auto−recovery mode. If one driver is in
open−load condition, all other channels could be turned off according
to the programmable bit setting.
NCV7685
AWLYYWW
G
The device is available in small body size SSOP24−EP package.
NCV7685 = Specific Device Code
Features
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
• 12 Common Current Programmable Sources up to 60 mA
• Independent PWM Duty Cycle Control for each Channel via PC
2
• Common PWM Duty Cycle Control via I C
• On−Chip 150, 300, 600 and 1200 Hz PWM
• Open LED String Diagnostics
(Note: Microdot may be in either location)
• Low Dropout Operation for Pre−Regulator Applications
• Single Resistor for Current Set Point
• Voltage Reference 3.3 V/1 mA
ORDERING INFORMATION
Device
Package
Shipping†
2
• 8 Bits I C Interface with CRC8 Error Detection
NCV7685DQR2G SSOP24−EP
(Pb−Free)
2500/
Tape & Reel
• OTP Bank for Stand−Alone Operation (2 Configurations)
• Output Enable Pin
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Detection and Protection Against Open Load and Under−Voltage
• Over Temperature Detection and Protection
• Low Emission with Spread Spectrum Oscillator
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• SSOP24−EP Packaging
Applications
• Dashboard Applications
• Rear Combination Lamps (RCL)
• Daytime Running Lights (DRL)
• Fog Lights
• Center High Mounted Stop Lamps (CHMSL) Arrays
• Turn Signal and Other Externally Modulated Applications
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
October, 2020 − Rev. 2
NCV7685/D
NCV7685
VS
OUT1
OUT12
Life Support
3V3
REG
Vint.
REG
Vint.
REG
VCC
ctrl
ctrl
Iset
Iset
Iset
Iset
Vint.
GNDP
VDD
OEN
I2C
DIAG
Registers
Diagnostic control
SCL
SDA
DIAGEN
PWM Registers
CONF
OTP
NCV7685
EXPOSED PAD
Figure 1. Block Diagram
GND
VDD
SCL
SDA
GND
GNDP
Figure 2. ESD Schematic
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2
NCV7685
OUT1
OUT2
OUT3
VDD
SCL
SDA
OEN
DIAG
GNDP
DIAGEN
VS
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
V
CC
CONF
ISET
GND
Figure 3. Pinout Diagram
Vsupply
MRA4003T3G
LDO
or
DC/DC
VSTRING
COUT1
(optional)
1nF
COUT12
(optional)
1nF
C1
100 nF
e.g. sensor
C2
VS
OUT1
OUT12
Optional connection if MCU
control of OEN input is required.
1nF
R1
2.2K
VCC
Iset
t
3.3V/5V
LDO
VDD
VCC
R4
10K
4.7K
R5
CVDD
R7
4.7K 10K
R6
100nF
R2
ctrl
Iset
OEN
Open Drain
GPIO structure
10K
DIAG
SCL
SDA
CONF
I2C {
DIAGEN
R3
CDIAG
(optional)
1nF
2.2K
COEN
10nF
Micro−
NCV7685
controller
EXPOSED
PAD
GND
GNDP
This GND−track is exclusively
for COEN connection. (to avoid
common impedance coupling from
other GND−currents)
Figure 4. Application Diagram with Micro−controller (I2C Mode)
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3
NCV7685
Vsupply
MRA4003T3G
LDO
VSTRING
or
DC/DC
COUT1
(optional)
1nF
COUT12
(optional)
1nF
C1
100nF
e.g. sensor
C2
OUT1
OUT12
VS
1nF
R1
2.2K
VCC
Iset
VDD
Vsupply
R4
10K
ctrl
Iset
R7
10 K
R2
OEN
10K
DIAG
DIAGEN
SCL
SDA
CONF
VS
R3
2.2K
COEN
10 nF
NCV7685
EXPOSED
PAD
GND
GNDP
CDIAG
(optional)
1 nF
This GND−track is exclusively for
COEN connection. (to avoid
common impedance coupling from
other GND−currents)
Figure 5. Application Diagram without Micro−controller (Stand Alone Mode)
Table 1. PIN FUNCTION DESCRIPTION
Pin #
1
Label
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
GND
Description
Channel 1 Current Output to LED
2
Channel 2 Current Output to LED
Channel 3 Current Output to LED
Channel 4 Current Output to LED
Channel 5 Current Output to LED
Channel 6 Current Output to LED
Channel 7 Current Output to LED
Channel 8 Current Output to LED
Channel 9 Current Output to LED
Channel 10 Current Output to LED
Channel 11 Current Output to LED
Channel 12 Current Output to LED
Signal Ground
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ISET
Current Setting/EoL Enable Pin
Stand Alone Mode Selection Bank
CONF
VCC
3.3 V Voltage Reference Output (Needs External Decoupling Capacitor)
Supply Voltage Input
VS
DIAGEN
GNDP
DIAG
Diagnostic Voltage Sensing Node for V Via Resistor Divider
STRING
Power Ground for output drivers
Open−drain diagnostic input/output.
Reporting Open Circuit and thermal shutdown.
Normal Operation = HIGH
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NCV7685
Table 1. PIN FUNCTION DESCRIPTION (continued)
Pin #
Label
Description
21
22
OEN
SDA
SCL
VDD
epad
Output Enable Input
2
I C Serial Data
2
23
I C Serial Clock
24
Digital Supply Voltage Input
epad
True Ground
Do NOT Connect to PCB Traces other than GND
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Unit
V
_VS
Power supply voltage:
MAX
Continuous supply voltage
−0.3
28
40
V
V
Transient Voltage (t < 500 ms, “load dump”)
Input pin voltage (DIAGEN, DIAG, CONF, OEN)
Continuous Output Pin voltage
Transient Voltage (t < 500 ms, “load dump”) or during PWM
period = OFF
−0.3
V
MAX
_INx
−0.3
40
V
V
MAX
_OUTx
−0.3
−0.3
28
40
V
V
V
_VCC
_VDD
Stabilized supply voltage
−0.3
−0.3
−0.3
−0.3
−
3.6
5.5
5.5
3.6
750
150
30
V
V
MAX
V
MAX
Digital input supply voltage
DC voltage at pins (VDD, SCL, SDA)
DC voltage at pin ISET
V
_IO
V
MAX
V
MAX
_ISET
V
I
_GNDP
Maximum Ground Current
mA
°C
°C
MAX
T
Junction Temperature, T
−40
10
JMAX
J
T
OTP Zap Ambient Temperature
A_zap
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are
considered as outside normal operating range. Protection functions are not designed for continuous repetitive operation.
Table 3. ATTRIBUTES
Parameter
Value
Unit
ESD Capability (Note 2)
ESD Voltage, HBM (Human Body Model); (100 pF, 1500 W)
− All pins
2
4
kV
kV
− Output pins OUTx to GND
ESD according to CDM (Charge Device Model)
− All pins
500
750
V
V
− Comer pins
ESD according to MM (Machine Mode)
− All pins
150
MSL2
V
Moisture sensitivity (SSOP24−EP) (Note 3)
Storage Temperature
−55 to 150
°C
Package Thermal Resistance (SSOP24−EP) (Note 4)
− Junction to Ambient, R
45.8
8.8
10.1
°C/W
°C/W
°C/W
q
JA
− Junction to Board, R
q
JB
− Junction to Case (Top), R
q
JC
2. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model
ESD MM according to AEC−Q100
3. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D,
and Application Note AND8003/D.
4. Values represent thermal resistances under natural convection are obtained in a simulation on a JEDEC−standard, 2S2P; High Effective
Thermal Conductivity Test Board as specified in JESD51−7, in an environment described in JESD51−2a.
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5
NCV7685
Table 4. ELECTRICAL CHARACTERISTICS
(5 V < VS < 18 V, 3.15 V < VDD < 5.5 V, R1 = 1.82 kΩ, −40°C ≤ T ≤ 150°C, unless otherwise specified)
J
Characteristic
GENERAL
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply Voltage
VS_EXT
Functional extended range (limited temper-
ature)
5
−
28
V
VS_OP
VSUV
Parametric operation
VS rising
5
−
4.1
−
18
4.4
18
V
V
V
Supply Under−Voltage
3.8
13
Supply range during
OTP zapping
VS_OTPzap
2.5 V ≤ ISET ≤ 3.3 V;
VS current peak capability ≥ 70 mA
Supply Under−Voltage
hysteresis
VSUVhys
−
200
−
mV
Supply Current (Vs)
Is(error mode)
all OUTx OFF except channel in open load
SCL = SDA = 0
−
−
Iout_VCC = 0 mA
Iout_VCC = 1 mA
1.2
2.2
1.5
2.5
mA
mA
Is(active)
Active Mode
−
7
10
mA
VS = 16 V, Vcc unloaded
OUTx = 1 V, R1 = 2 kW
2
Digital supply current
IDD
I C mode, VS = 12 V
−
−
2
0.24
−
2
2.9
−
mA
V
VDD Under Voltage
detection
VDDUV_R
VDDUV_F
VDD rising
VDD falling
−
V
CURRENT SOURCE OUTPUTS
Output current
IOUThot
IOUTcold
ImatchCold
Imatch
OUTx = 1 V, Tj = 150°C
OUTx = 0.5 V, Tj = −40°C
Tj = −40°C (Note 5)
Tj = 25°C (Note 5)
Tj = 150°C (Note 5)
10% to 90%
50
50
−7
−6
−5
−
55
55
0
60
60
7
mA
mA
%
Current Matching from
channel to channel
0
6
%
ImatchHot
ISRx
0
5
%
Current Slew Rate
30
50
−
mA/ms
Open Circuit Detection
Threshold
OLDT
IOUTx > 20mA
30
70
% of output
current
Open load recovery in
auto−recovery mode
OLR
5
10
15
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Matching formulas:
2IOUTx(min)
IOUTx(min) ) IOUTx(max)
2IOUTx(max)
IOUTx(min) ) IOUTx(max)
ƪ
* 1ƫ 100 and ƪ
* 1ƫ
100
Table 5. ELECTRICAL CHARACTERISTICS
(5 V < VS < 18 V, 3.15 V < V < 5.5 V, R1 = 1.82 kΩ, −40°C ≤ T ≤ 150°C, unless otherwise specified)
DD
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VOLTAGE REFERENCE
V_VCC
Iout_VCC
Cload_VCC
Output Voltage Tolerance
Output Current
I_VCC ≤ 1 mA
ESR < 200 mW
3.20
−
3.30
−
3.45
−1
V
mA
nF
Load Capacitor
0.9
1.0
2.5
INPUTS: OEN, CONF
VinL
VinH
Input Low Level
0.7
−
1.0
1.25
250
200
−
V
V
Input High Level
1.66
400
280
Vin_hyst
Rin_pd
Input Hysteresis
100
120
mV
kW
Input Pull−down Resistor
INPUTS: SCL, SDA
VinL
Input Low Level
−
−
0.3×VDD
V
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NCV7685
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(5 V < VS < 18 V, 3.15 V < V < 5.5 V, R1 = 1.82 kΩ, −40°C ≤ T ≤ 150°C, unless otherwise specified)
DD
J
Symbol
INPUTS: SCL, SDA
VinH
Parameter
Test Conditions
Min
Typ
Max
Unit
Input High Level
Input Hysteresis
Output Current
0.7×VDD
0.05×VDD
3
−
−
−
−
−
−
V
V
Vin_hyst
Iout_SDA
V (SDA) = 0.4 V
mA
DIAGEN PIN
VDiagenTH
Rdiagen_pd
DIAG PIN
VoutL
VS Diagnostic Enable Threshold
1.9
2.0
2.1
V
Input Pull−down Resistor
120
200
280
kW
Output Low Level
Diagnostic Activated,
Idiag = 1 mA
−
0.2
0.4
V
DiagRes
tp_DIAG
Diagnostic Reset Voltage
1.65
1.80
10
1.95
20
V
Filter Time to Set the DIAG Fail Pin in
Failure Mode
Idiag = 1 mA
VDIAG = 5 V
−
ms
DIAG_leak
ISET INPUT PIN
VISET
DIAG Output Leakage
−
−
10
mA
Global Current Setting
IOUT ISET Factor
0.94
−
1.0
100
−
1.06
−
V
−
K
tsetupISET
Setup−up Time to 90% of the ISET
Regulated Value
VS > 5 V
−
50
ms
INTERNAL PWM CONTROL UNIT (OUT1− OUT12)
Symbol
PWM1
PWM2
PWM3
PWM4
Parameter
Test Conditions
Min
132
Typ
150
Max
168
Unit
Hz
2
2
PWM1 Frequency, I C Mode
Configuration Via I C
2
2
PWM2 Frequency, I C Mode
Configuration Via I C
264
300
336
Hz
2
2
PWM3 Frequency, I C Mode
Configuration Via I C
528
600
672
Hz
2
2
PWM4 Frequency, I C Mode
Configuration Via I C
1056
1200
1344
Hz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 6. THERMAL WARNING AND THERMAL SHUTDOWN PROTECTION
Symbol
Tjwar_on
TSD
Parameter
Min
−
Typ
TSD−30
−
Max
−
Unit
°C
Thermal Warning Threshold (Junction Temperature)
Thermal Shutdown Threshold (Junction Temperature)
160
180
°C
T Increasing
J
Tjsd_hys
Thermal Shutdown Hysteresis
10
−
15
°C
General
Output Current Programming (ISET/IOUTx)
The NCV7685 is a twelve channel LED driver. Each
output can drive currents up to 60 mA/channel and are
programmable via an external resistor. The target
applications for the device are in automotive rear lighting
systems and dashboard applications. The device can be used
The maximum current can be defined with the Iset input
pin. The equations below can be used to calculate this
maximum output current:
Iset + 1 VńR1
(eq. 1)
IOUTx + K Iset
(eq. 2)
2
with micro−controller applications using the I C bus or in
Example:
R1 = 2 kΩ
stand−alone applications. In both cases it is mandatory to
supply the LED channels by an external ballast transistor, or
by an LDO or a DC/DC to have low voltage drop on the
outputs which will lead to a decrease in power dissipation in
the device. In order to have very low electromagnetic
emission, this device has an embedded spread spectrum
oscillator.
using eq. 1 → Iset = 500 μA
and using eq. 2 → IOUTx = 50 mA
To avoid potential disturbances when all drivers are
activated at the same time, a typical activation delay of
400 ns between groups of 2 consecutive outputs is
implemented (see Figure 6).
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NCV7685
PWM period counter
PWM signal
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
driver 1
driver 2
driver 3
driver 4
driver 5
driver 6
driver 7
driver 8
driver 9
driver 10
driver 11
driver 12
Figure 6.
Power Supply and Voltage Reference (VS, VCC, VDD
)
ISET resistor is connected to the I
pin, the access to the
SET
VS is the analog power supply input of the device. VS
supply is monitored with respect to the crossing of VSUV
level (typ. 4.1 V). When VS rises above VSUV, the device
starts the power−up state. When VS is above the VS_OP
minimum level (typ. 5 V), the device can work properly.
VCC is a voltage reference providing 3.3 V derived from
the VS main supply. It is able to deliver up to 1 mA and is
primarily intended to supply 3.3 V loads. If VCC output
reference is not used, then the VCC capacitor can be omitted.
VDD is the digital power supply input of the device.
OTP registers is not possible. Zapping is only possible with
VS above 13 V. The outputs are disabled as soon as 2.5 V is
applied to the ISET pin. After the ID_LOCK_OTP I2C
message is properly received, no further OTP zapping is
possible.
Output Enable (OEN)
When the OEN input voltage is high, all output channels
are programmed according to the I2C or SAM
configuration. When OEN voltage is below 0.7 V, all
outputs are disabled in the SAM or I2C mode regardless on
the registers setting. If the OEN pin is left floating, the
internal pull down resistor will cause switching off all
channels. The OEN pin has to have max slope of 5 mV for
first 10 ms until VCC is activated. The recommended
examples are shown in Figure 4 and Figure 5. The Figure 11
shows the example of the driving multiple NCV7685 drivers
from one MCU.
5V
VS
Activation of the VDD can be
before or after VS supply
VDD
Configuration (CONF)
*)VCC is internally
derived from VS
When the CONF input voltage will be below 0.7 V the
configuration 1 will be selected (One Time Programmable
OTP 1 register called SAM_CONF_1) and when the CONF
input voltage will be above 1.66 V the configuration 2 will
be selected (OTP 2 register called SAM_CONF_2). There
is ability to change the configuration in error mode (either
VCC
OEN
μs
tsetupISET is up to 50
OEN pin has to have max slope of
5 mV/10 μs until VCC is activated.
Slope on the OEN pin has to be slower
than slope on the VS or slope on VDD
(depends on what comes first)
2
with CONF in SAM or through I C in I2C mode).
I2C Bus (SCL, SDA)
2
The I C bus consists of two wires, Serial Data (SDA) and
Figure 7. Power−up Sequence for OEN pin
Serial Clock (SCL), carrying information between the
devices connected on the bus. Each device connected to the
bus is recognized by a unique address and operates as either
a transmitter or receiver, depending on the function of the
device. The NCV7685 can both receive and transmit data
with CRC8 error detection algorithm. The NCV7685 is a
slave device.
SDA is a bi−directional line connected to a positive supply
voltage via an external pull−up resistor. When the bus is free
both lines are HIGH. The output stages of the devices
connected to the bus must have an open drain to perform the
Ground Connections (GND: Pin 13 and GNDP Pin 19)
The device ground connection is split to two pins called
GND and GNDP. Both pins have to be connected on the
application PCB.
Chip Select for OTP Programing (Using ISET
)
2
The device can be programmed using the I C bus in End
of Line cases. When the voltage on the ISET pin is pulled
higher than 2.5 V, the device can be set in OTP control mode
2
via the I C bus. During normal mode where only an external
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NCV7685
2
wired−AND function. Data on the I C bus can be transferred
up to 400 kb/s.
Diagnostic Enabling (DIAGEN)
The device is capable to detect for each independent
channel an open load condition. Versus the number of LEDs
and the Vstring voltage supply, a wrong open load condition
can be detected if the fault detection is activated when there
is not enough voltage across the LEDs. This threshold can
be programmable thanks to an external divider connected to
the DIAGEN pin. When the divided voltage is below a
typical value of 2 V, the LED diagnostic is disabled. When
the divided voltage is above the typical value of 2 V, the LED
diagnostic is enabled.
Diagnostic Feedback (DIAG)
The DIAG is an open drain output pin who can alert a
microcontroller as soon as one of the outputs is in error mode
(DIAG Low = open load or thermal shut−down or I
SET
Figure 9. Power−up Sequence for DIAG pin. VDD is
shorted). Forcing the DIAG pin below 1.8 V will force a
fault condition if the DIAGEN input pin is above a typical
value of 2 V. If the DIAGEN input pin is below the typical
value of 2 V then forcing the DIAG input pin will not have
any effect.
Due to certain sensitivity on the DIAG pin during the
startup, it is recommended to have the pull−up resistor
connected to the VCC supply. In case if the application
deviate from the proposal mentioned in the Figure 4 or
Figure 5, the power−up sequence has to follow the timing
diagrams in the Figure 8 or Figure 9.
supplied first, VS comes up later or equal.
Parallel Outputs
The maximum rating per output is 60 mA. In order to
increase system level LED string current, parallel
combinations of any number of outputs is allowed.
Combining all 12 outputs will allow for a maximum system
level string current design of 720 mA.
Required Time Delay for OTP Zapping
As soon as the ID_LOCK_OTP message is received, the
I C acknowledge is immediately sent out to the MCU.
2
However, the internal circuitries still requires 500 ms time
delay to complete the OTP zapping of one OTP bit.
Therefore, no I C confirmation is send. The number of OTP
5 V
2
VS
bits that are zapped corresponds with each change from the
default values. It is needed 16.5 ms in total to successfully
finish the zapping sequence of all 32 customer bits + one
internal bit. The verification of the OTP banks can be done
DIAG
2
by readout of the ID_READ_OTP I C message after
zapping delay.
*) VCC is internally
derived from VS
VCC
VDD
t
is up to 50 ms t ≥ 0 ms
setupISET
Figure 8. Power−up Sequence for DIAG pin. VS is
supplied first, VDD comes up later.
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9
NCV7685
V
BAT
V
SUPPLY
C1
MRA4003T3G
LDO
or
DC/DC
V
V
C
STRING
STRING
V
SUPPLY
C1
OUT1
C
OUT1
(optional)
100nF
C
C
OUT12
(optional)
(optional)
1nF
OUT12
(optional)
100nF
1nF
VCC_U1
C2
1nF
1nF
C2
R1
R1
1nF
R7
1nF
2.2K
VS
OUT1
OUT12
Iset
2.2K
OUT1
OUT12
Iset
VS
VCC
VCC
5K
3.3V/5V
LDO
VCC_U1
_
R4
100K
To VDD supply
R
C
100nF
VDD
VDD
VDD
R
59K
OEN
OEN
C
VDD
R6
4.7K
NCV7685
Open Drain
R5
R2
R2
NCV7685
GPIO structure
59K
100nF
OEN
SCL
SDA
10K
4.7K
10K
OEN
SCL
SDA
DIAG
DIAGEN
DIAG
DIAGEN
2
{
I C
To MCU
C
DIAG
33nF
CONF
CONF
EP
R3
C
OEN
R3
C
100nF
OEN
GND GNDP
EP GND GNDP
2.2K
Micro−
controller
2.2K
100nF
U1
U2
This GND−track is exclusively
C
DIAG
(optional)
This GND−track is exclusively for
for COEN connection. (to avoid
COEN connection. (to avoid
common impedance coupling from
other GND−currents)
1nF
common impedance coupling from
other GND−currents)
DIAG
Figure 10. Example of using Multiple NCV7685 Drivers Controlled from One MCU
www.onsemi.com
10
NCV7685
DIGITAL PART AND I2C REGISTERS
2
The I C bus consists of two wires, serial data (SDA) and
serial clock (SCL), carrying information between the
devices connected on the bus. Each device connected to the
bus is recognized by a unique address. The NCV7685 can
both receive and transmit data with CRC8 error detection
algorithm. The NCV7685 is a slave device only. Generation
2
of the signals on the I C bus is always the responsibility of
the master device.
They are multiple kinds of message structure possible
versus ID code received.
Table 7. IDENTIFIER ADDRESSING (ID) MESSAGE
Name
ID
00
01
02
03
Access type
Name of Register Addressed
ID_I2C_CONF
ID_PWM
W
W
W
W
I2C_CONF
PWM_DUTY
ID_PWM_CONF
ID_PWM_ALL
PWM_CONF, PWM_DUTY_EN
PWM_D1, PWM_D2, PWM_D3, PWM_D4, PWM_D5, PWM_D6,
PWM_D7, PWM_D8, PWM_D9, PWM_D10, PWM_D11, PWM_D12
ID_WRITEALL
ID_STATUS
04
08
09
0A
20
21
28
W
R
I2C_CONF, PWM_CONF, PWM_DUTY_EN
I2C_STATUS
ID_FAULT
R
FAULT_STATUS
ID_READALL
ID_SET_OTP
ID_LOCK_OTP
ID_READ_OTP
R
I2C_CH_STATUS, I2C_STATUS, FAULT_STATUS
SAM_CONF_1, SAM_CONF_2, ADD_SAM_SET
SAM_CONF_1, SAM_CONF_2, ADD_SAM_SET
ID_VERS_1, ID_VERS_2, SAM_CONF_1, SAM_CONF_2, ADD_SAM_SET
W
W
R
There are 3 kinds of registers, Hard Coding, OTP and
volatile registers.
Volatile Registers:
I2C_CONF
I2C_STATUS
Hard Coding Registers:
ID_VERS_1
ID_VERS_2
I2C_CH_STATUS
FAULT_STATUS
PWM_DUTY
PWM_D1 − PWM_D12
PWM_DUTY_EN
PWM_CONF
OTP Registers:
ADD_SAM_SET
SAM_CONF_1
SAM_CONF_2
Format of the I2C frames
S
0
A
A
ID
A
Data
A
CRC
A
P
NCV7685 address
NCV7685 address
N bytes +
acknowledge
‘0’ = Write
S = Start condition
P = Stop condition
A = Acknowledge
From master to NCV7685
From NCV7685 to master
A* = Not acknowledge
Figure 11. Format of I2C Write Access Frames
NCV7685
address
NCV7685
address
NCV7685
address
S
0
A
A
ID
A
CRC A* Sr
1
A
Data
A
CRC A* P
N bytes +
acknowledge
‘0’ = Write
‘1’ = Read
S = Start condition
From master to NCV7685
From NCV7685 to master
Sr = Repeated start condition
P = Stop condition
A = Acknowledge
A* = Not acknowledge
Figure 12. Format of I2C Read Access Frames
Remark: CRC byte is not transmitted when CRC
protection is turned off (ERREN = 0)
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11
NCV7685
Figure 14. Format of I2C OTP Frames
Figure 13. Format of I2C Frames
www.onsemi.com
12
NCV7685
There is a safety mechanism implemented by repeating
the address. Since the I C address is 7 bits long, first bit of
the second address byte starts with a “0” in the repeated byte
(see tables below).
2
Table 8.
st
1
byte
7
7
6
6
5
5
4
3
3
2
2
1
1
0
2
I C device Address
R/W Bit
nd
2
byte
4
0
0
2
I C device Address
CRC ERROR DETECTION ALGORITHM
2
The CRC protection is turned off by default. It can be
enabled by activation of the OTP ERREN bit (ERREN = 1).
Example of the CRC used in the I C message with
2
I2C_CONF byte = 0xCFFF and with I C address 0x60
2
The every I C byte including both addresses with R/W flag
(0xC0) is 0x2E.
are calculated using CRC8 algorithms. The CRC
8
5
3
2
polynomial is following: x + x + x + x + x + 1.
HARD CODING REGISTERS
Table 9. HARD CODING REGISTERS
Bit
D7
R
0
D6
R
1
D5
R
0
D4
R
0
D3
R
0
D2
R
0
D1
R
1
D0
R
1
ID_VERS_1
Access type
Bit name
ID1[7:0]
ID2[7:0]
Reset value
ID_VERS_2
Access type
Bit name
R
R
R
R
0
R
0
R
1
R
0
R
0
Reset value
0
0
0
1. ID1[7:0] = 43h (ON Semiconductor device identifier)
ID2[7:0] = 04h (The actual version)
OTP REGISTERS
Table 10. ADD_SAM_SET
Bit
D7
R/W
AUTOR
0
D6
R/W
D5
R/W
ERREN
0
D4
D3
D2
R/W
D1
D0
Access type
Bit name
R/W
R/W
R/W
R/W
DETONLY
1
ADD[4:0]
0
Reset value
0
0
0
0
ADD[4:0] are the programmable BUS address registers
(in I2C mode ADD[6:5] = 11).
DETONLY: When DETONLY=1, open load diagnostic is
performed. When a fault is detected, the DIAG pin is set
without taking any action on the current regulation. When
fault is recovered, DIAG is reset. If the DIAG pin is
triggered externally, no action is taken.
When AUTOR = DETONLY = 0, no diagnostic performed
When AUTOR = DETONLY = 1, no change
(same as previously setting).
AUTOR: When AUTOR=1 (and DIAGEN is high), open
load diagnosis is performed. When a fault is detected, the
DIAG pin is set and LED driver imposes a low current on the
faulty branch alone, switching off the others. When fault is
recovered, LED driver returns to normal operation after
resetting the DIAG pin. If the DIAG pin is triggered
externally, LED driver outputs are switched off and the low
power mode is entered.
ERREN: When ERREN = 1, CRC error detection
2
algorithm is activated for I C communication.
www.onsemi.com
13
NCV7685
Table 11. SAM_CONF
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SAM_CONF_1
Access type
Bit name
R
−
0
R
−
0
R
−
0
R
−
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
SAM1conf[11:0]
Reset value
SAM_CONF_2
Access type
Bit name
0
0
0
0
0
0
0
0
0
0
0
0
R
−
0
R
−
0
R
−
0
R
−
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
SAM2conf[11:0]
Reset value
1
1
1
1
1
1
1
1
1
1
1
1
1. SAM1conf[x] = 0 means channel is OFF and SAM1conf[x] = 1 means channel is ON
SAM2conf[x] = 0 means channel is OFF and SAM2conf[x] = 1 means channel is ON
VOLATILE REGISTERS
Table 12. I2C_CONF
Bit
D15
D14
D13
D12
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type
Bit name
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
I2CFLAG I2CautoR I2CdOnly PWMEN
I2Cconf[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I2CFLAG: the I2CFLAG should be reset whenever
standalone mode is entered. When I2CFLAG=1 and when
VDD is high, the I2C mode is activated, in all other
conditions the device is in Stand Alone Mode.
I2CdOnly: When I2CdOnly =1, open load diagnostic is
performed. When a fault is detected, the DIAG pin is set
without taking any action on the current regulation. When
fault is recovered, DIAG is reset. If the DIAG pin is
triggered externally, no action is taken.
When I2CautoR = I2CdOnly = 0, no diagnostic
performed.
When I2CautoR = I2CdOnly = 1, no change (same as
previously setting).
PWMEN: When PWMEN = 1, PWM is activated, when
PWMEN = 0 the content of the complete register
PWM_DUTY_EN is not reset and PWM is disabled.
I2Cconf[x] = 0 means channel is OFF and I2Cconf[x] = 1
means channel is ON.
I2CautoR: When I2CautoR=1 (and DIAGEN is high),
open load diagnosis is performed. When a fault is detected,
the DIAG pin is set and LED driver imposes a low current
on the faulty branch alone, switching off the others. When
fault is recovered, LED driver returns to normal operation
after resetting the DIAG pin. If the DIAG pin is triggered
externally, LED driver outputs are switched off and the low
power mode is entered. Whenever the device is configured
in autorecovery (AUTOR in standalone mode or I2CautoR
in I2C mode), it is not allowed to put PWMDUTY = 0 or
PWMDx = 0 to a channel which has detected an open load.
Table 13. I2C_STATUS
Bit
D7
D6
R
D5
R
D4
D3
R
D2
R
D1
D0
R
Access type
Bit name
R
SC_Iset
0
R
diagRange
0
R
DIAGERR
0
I2Cerr
0
UV
0
TW
0
TSD
0
OL
0
Reset value
SC_Iset: SC_Iset = 1 means there is short−circuit on the
external resistor on I pin and drivers are switched OFF
and DIAG pin is set. SC_Iset=0 no short−circuit.
I2Cerr: I2Cerr=1 means an error has been detected during
the I2C communication, I2Cerr=0 means no error during
I2C communication has been detected.
diagRange: when diagRange = 1 the divided voltage is
above the typical value of 2 V (LED diagnostic is enabled),
diagRange = 0 means the divided voltage is below the
typical value of 2 V (LED diagnostic is disabled).
TW: when TW=1 the device is in the thermal warning
range (typ 140°C), this flag is just a warning no action is
foreseen on the output drivers. TW=0 means the device is
below the thermal warning range.
SET
UV: the device is in under voltage condition (VS is below
VSUV threshold, all channels OFF).
www.onsemi.com
14
NCV7685
TSD: when TSD = 1 the device is in the Thermal shutdown
OL: OL = 1 means at least one channel is in Open Load
range, TSD = 0 means the device is below the thermal
shutdown range.
condition, OL = 0 no Open Load.
DIAGERR: DIAGERR = 1 means an error is detected by
DIAG pin forced externally.
Table 14.
SC_Iset
set when a short−circuit on the external resistor on I
pin, latched if permanent after 10 ms.
SET
Reset in case of short−circuit disappear permanently for at least 10ms.
I2Cerr
set if an error has been detected during the I2C communication.
Reset on register reading.
UV
set when device is in under voltage condition (VS is below VSUV, all channels OFF).
diagRange
set when divided voltage is above the VDiagenTH threshold.
Reset when the divided voltage is below the VDiagenTH threshold.
TW
TSD
set when junction temperature is above the Tjwar_on threshold.
Reset on register reading AND temperature is below the (Tjwar_on − Tjsd_hys) threshold
set when junction temperature is above the TSD threshold.
Reset on register reading AND temperature is below the TSD − Tjsd_hys) threshold
DIAGERR
OL
set by DIAG pin forced low externally, latched if permanent after 10 ms.
Reset in case DIAG pin is not forced permanently for at least 10 ms.
set in Open Load condition and DIAGEN is high, latched if permanent after 10 ms.
Reset if Open Load disappear permanently for at least 10 ms.
Fault information is maintained on falling DIAGEN threshold exceeded
Table 15. I2C_CH_STATUS
Bit
D15
D14
D13
D12
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
Bit name
R
I2CFLAG
0
R
I2CautoR
0
R
I2CdOnly
0
R
PWMEN
0
R
R
R
R
R
R
R
R
R
R
R
R
I2C_CH_STATUS[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
I2CFLAG: same as I2C_CONF register
I2CautoR: same as I2C_CONF register
I2CdOnly: same as I2C_CONF register
PWMEN: same as I2C_CONF register
Remark: When NCV7685 is configured in I2C mode and
output channel OUTx is configured to operate in PWM
mode, I2C_CH_STATUS[x] shall contain value ‘1’.
I2C_CH_STATUS[11:0]: same as I2C_CONF[11:0] bits
in I2C mode or same as SAM_CONF_1[11:0],
SAM_CONF_2[11:0] bits in Standalone mode.
Table 16. FAULT_STATUS
Bit
D15
R
D14
R
D13
R
D12
R
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
Bit name
R
R
R
R
R
R
R
R
R
R
R
R
−
−
−
−
FAULT[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FAULT[11:0]: when FAULT[x] = 1 the OUTx channel is
in fault mode (Open Load latched when the duration is
longer than 10 ms), when FAULT[x] = 0 the OUTx channel
is working properly. The register is reset on each read
operation.
www.onsemi.com
15
NCV7685
Table 17. PWM_DUTY
Bit
D7
−
D6
D5
D4
D3
D2
D1
D0
Access type
Bit Name
W
W
W
W
W
W
W
−
PWMDUTY[6:0]
0
Reset Value
0
0
0
0
0
0
0
PWMDUTY[6:0]: logarithmic (or linear) common
dimming for all channels via embedded PWM generator
(128 steps). Following formula applies when logarithmic
When PWMDUTY = 0 all channels are switched off.
Whenever the device is configured in autorecovery
(AUTOR in standalone mode or I2CautoR in I2C mode), it
is not allowed to put PWMDUTY = 0 or PWMDx = 0 to a
channel which has detected an open load.
(N−i)
dimming is selected: Duty_Cycle_Percent = 100 × α
where α = 0.9471 and N = 127 rounded with an accuracy
2
of 400 ns.
Transmitting PWM_DUTY via I C will cause setting the
When PWMDUTY = 127 all channels ar fully switched
on.
value to all channels.
Table 18. PWM_Dx
Bit
D7
−
D6
D5
D4
D3
D2
D1
D0
Access type
Bit Name
W
W
W
W
W
W
W
−
PWMDx[6:0]
0
Reset Value
0
0
0
0
0
0
0
PWMDx[6:0]: logarithmic (or linear) independent PWM
dimming for each OUTx channel via embedded PWM
generator (128 steps). Following formula applies when
Whenever the device is configured in autorecovery
(AUTOR in standalone mode or I2CautoR in I2C mode), it
is not allowed to put PWMDUTY = 0 or PWMDx = 0 to a
channel which has detected an open load.
logarithmic dimming is selected: Duty_Cycle_Percent =
(N−i)
100 × α
where α = 0.9471 and N = 127 rounded with
To set independent PWM Duty Cycle value to each
channel simultaneously, all twelve PWM_Dx bytes has to be
an accuracy of 400 ns.
2
When PWMDx = 127 the OUTx channel is fully switched
transferred via I C bus in ID_PWM_ALL message. If
on.
PWM_DUTY register is updated, all PWM_Dx bytes will
be overwritten by the same value from PWM_DUTY
register.
When PWMDx = 0 the OUTx channel is switched off.
Table 19. PWM_DUTY_EN
Bit
D15
−
D14
−
D13
−
D12
−
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access type
Bit name
W
W
W
W
W
W
W
W
W
W
W
W
−
−
−
−
PWMDUTYen[11:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWMDUTYen[11 :0] : when PWMDUTYen[x] = 1,
PWM dimming is enabled for OUTx channel, when
PWMGAINen[x] = 0 means PWM dimming is disabled for
OUTx channel. When the PWM dimming is disabled, the
output channel is programmed according to the I2Cconf[x]
settings.
Table 20. PWM_CONF
Bit
D7
W
−
D6
W
−
D5
W
−
D4
W
−
D3
W
−
D2
D1
W
D0
W
Access type
Bit Name
W
PWMLIN
0
PWMF2
0
PWMF1
0
Reset Value
0
0
0
0
0
PWMLIN bit shall select between between logarithmic
(PWMLIN=0) and linear (PWMLIN=1) translation of
PWMDUTY bits to duty cycle of internal PWM signal.
PWMF2 and PWMF1 bits set typical PWM frequency
settings according to the Table 21.
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16
NCV7685
Table 21. TYPICAL PWM FREQUENCY SETTINGS
PWMF2
PWMF1
typ. PWM frequency [Hz]
0
0
1
1
0
1
0
1
150
300
600
1200
Figure 15. Output Duty Cycle vs. Register Setting
Figure 16. Output Duty Cycle vs. Register Setting
− Detail
2
ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
www.onsemi.com
17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SSOP−24 NB EP
CASE 940AQ
ISSUE O
SCALE 1:1
DATE 18 AUG 2017
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
0.20 C A-B
NOTE 4
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
BE 0.10 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE
FOOT. DIMENSION b APPLIES TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.10 TO 0.25
FROM THE LEAD TIP.
NOTE 6
D
L1
A
24
13
2X
H
L2
0.20 C
GAUGE
PLANE
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 PER SIDE. DIMENSION D IS
DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE. DIMENSION E1 IS DETERMINED AT DA-
TUM PLANE H.
E1
E
L
A1
NOTE 5
PIN 1
SEATING
PLANE
DETAIL A
C
NOTE 7
REFERENCE
1
12
0.20 C
e
2X 12 TIPS
24X b
B
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
NOTE 6
M
0.12
C A-B D
7. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
8. CONTOURS OF THE THERMAL PAD ARE UN-
CONTROLLED WITHIN THE REGION DEFINED
BY DIMENSIONS D2 AND E2.
TOP VIEW
DETAIL A
A
h
A2
h
0.10 C
0.10 C
M
MILLIMETERS
DIM MIN
MAX
1.75
0.10
1.65
0.30
0.20
c
A
A1
A2
b
---
0.00
1.10
0.19
0.09
A1
SEATING
PLANE
END VIEW
24X
C
SIDE VIEW
c
M
0.15
C A-B D
D
8.64 BSC
NOTE 8
D2
E
2.50
2.70
D2
6.00 BSC
3.90 BSC
1.80 2.00
0.65 BSC
0.25 0.50
0.40 0.85
1.00 REF
0.25 BSC
E1
E2
e
M
0.15
C A-B
D
h
L
E2
L1
L2
M
NOTE 8
0
8
_
_
GENERIC
MARKING DIAGRAM*
BOTTOM VIEW
RECOMMENDED
XXXXXXXXXG
AWLYYWW
SOLDERING FOOTPRINT*
3.00
XXXX = Specific Device Code
24X
1.15
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
2.20
6.40
1
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
24X
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON73645G
SSOP−24 NB EP
PAGE 1 OF 1
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