NCV7708EDWR2G [ONSEMI]
双六路驱动器;
| 型号： | NCV7708EDWR2G |
| 厂家： | 
ONSEMI |
| 描述： | 双六路驱动器 电动机控制 驱动 光电二极管 驱动器 |
| 文件： | 总17页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV7708E
Double Hex Driver
The NCV7708E is a fully protected Hex−Half Bridge−Driver
designed specifically for automotive and industrial motion control
applications. The six low and high side drivers are freely configurable
and can be controlled separately. This allows for high side, low side,
and H−Bridge control. H−Bridge control provides forward, reverse,
brake, and high impedance states. The drivers are controlled via a
standard SPI interface.
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SOIC−28
DW SUFFIX
CASE 751F
Features
• Ultra Low Quiescent Current Sleep Mode
• Six Independent High−Side and Six independent Low−Side Drivers
• Integrated Freewheeling Protection (LS and HS)
• Internal Upper and Lower Clamp Diodes
• Configurable as H−Bridge Drivers
MARKING DIAGRAM
• 0.5 A Continuous (1 A peak) Current
• R
= 0.8 W (typ)
NCV7708E
DS(on)
AWLYYWWG
• 5 MHz SPI Control
• SPI Valid Frame Detection
• Compliance with 5 V and 3.3 V Systems
• Overvoltage Lockout
• Undervoltage Lockout
• Fault Reporting
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
= Pb−Free Package
G
• Current Limit
• Overtemperature Protection
PIN CONNECTIONS
• Internally Fused Lead in SOIC−28
Packaged for Better Thermal Performance
• These are Pb−Free Devices*
1
OUTL5
OUTH6
OUTL6
SI
OUTH5
OUTH4
OUTL4
VS2
SCLK
CSB
Typical Applications
• Automotive
GND
GND
GND
GND
GND
GND
GND
• Industrial
GND
V
VS1
CC
• DC Motor Management
OUTL3
OUTH3
OUTH2
OUTL2
SO
EN
OUTL1
OUTH1
ORDERING INFORMATION
†
Device
Package
Shipping
NCV7708EDWR2G SOIC−28W
(Pb−Free)
1000/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
June, 2014 − Rev. 1
NCV7708E/D
NCV7708E
VS1
DRIVE 1
VS
CP
VS
High−Side
Driver
EN
Charge
Pump
ENABLE
BIAS
OUTH1
OUTL1
Waveshaping
Control
Logic
V
CC
Fault
Detect
Low−Side
Driver
POR
Waveshaping
SPI
Control
SO
SI
Under−load
Overcurrent
Thermal
16 Bit
Logic
and
SPI
Warning/Shutdown
Latch
SCLK
CSB
VS
CP
OUTH2
OUTL2
DRIVE 2
VS
CP
OUTH3
OUTL3
DRIVE 3
VS1
Undervoltage
Lockout
VS
CP
OUTH4
OUTL4
VS2
DRIVE 4
DRIVE 5
DRIVE 6
VS
CP
OUTH5
OUTL5
VS1
VS2
Overvoltage
Lockout
VS
CP
OUTH6
OUTL6
GND
VS2
Figure 1. Block Diagram
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2
NCV7708E
PIN DESCRIPTION
Pin No.
Symbol
Description
1
2
OUTL5
OUTH5
OUTH4
OUTL4
VS2
Output Low Side 5. Open drain output driver with internal reverse diode.
Output High Side 5. Open source output driver with internal reverse diode. Drain connected to VS2.
3
Output High Side 4. Open source output driver with internal reverse diode. Drain connected to VS2.
4
Output Low Side 4. Open drain output driver with internal reverse diode.
5
Voltage Power Supply input for the High−Side Output Drivers 4, 5, and 6.
6
GND
Ground
Ground
Ground
Ground
7
GND
8
GND
9
GND
10
VS1
Voltage Power Supply input for the High−Side Output Drivers 1, 2, and 3, All six low side pre−drivers,
and all six charge pumps.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OUTL3
OUTH3
OUTH2
OUTL2
OUTH1
OUTL1
EN
Output Low Side 3. Open drain output driver with internal reverse diode.
Output High Side 3. Open source output driver with internal reverse diode. Drain connected to VS1.
Output High Side 2. Open source output driver with internal reverse diode. Drain connected to VS1.
Output Low Side 2. Open drain output driver with internal reverse diode.
Output High Side 1. Open source output driver with internal reverse diode. Drain connected to VS1.
Output Low Side 1. Open drain output driver with internal reverse diode.
Enable. Input high wakes the IC up from a sleep mode.
Serial Output. 16 bit serial communications output.
SO
V
CC
Power supply input for Logic.
GND
GND
GND
GND
CSB
Ground
Ground
Ground
Ground
Chip Select Bar. Active low serial port operation.
SCLK
SI
Serial Clock. Clock input for use with SPI communication.
Serial Input. 16 bit serial communications input.
OUTL6
OUTH6
Output Low Side 6. Open drain output driver with internal reverse diode.
Output High Side 6. Open source output driver with internal reverse diode. Drain connected to VS2.
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3
NCV7708E
MAXIMUM RATINGS
Rating
Value
Unit
Power Supply Voltage (VS1, VS2)
(DC)
V
−0.3 to 40
−1.0
(AC), t < 500 ms, Ivsx > −2 A
Output Pin OUTHx
(DC)
V
V
−0.3 to 40
−8.0
(AC – inductive clamping)
Output Pin OUTLx
(DC)
−0.3 to 34
−1.0
(AC), t < 500 ms, IOUTLx > −2 A
(AC Inductive Clamping)
48
Pin Voltage (Logic Input pins, SI, SCLK, CSB, SO, EN, V
)
−0.3 to 7.0
V
A
CC
Output Current (OUTL1, OUTL2, OUTL3, OUTL4, OUTL5, OUTL6, OUTH1, OUTH2, OUTH3, OUTH4,
OUTH5, OUTH6)
(DC) Vds = 12 V
−1.5 to 1.5
−0.7 to 0.7
−0.25 to 0.25
−2.0 to 2.0
−0.9 to 0.9
−0.3 to 0.3
(DC) Vds = 20 V
(DC) Vds = 40 V
(AC) Vds = 12 V, (50 ms pulse, 1 s period)
(AC) Vds = 20 V, (50 ms pulse, 1 s period)
(AC) Vds = 40 V, (50 ms pulse, 1 s period)
Electrostatic Discharge, Human Body Model, VS1, VS2, OUTx
Electrostatic Discharge, Human Body Model, all other pins
Electrostatic Discharge, Machine Model
4.0
2.0
kV
kV
V
200
Electrostatic Discharge, Charged Device Model
Operating Junction Temperature
1.0
kV
°C
°C
−
−40 to 150
−55 to 150
MSL 3
260
Storage Temperature Range
Moisture Sensitivity Level
Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C (Note 1)
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. For additional information, please see or download the ON Semiconductor Soldering and Mounting Techniques Reference Manual,
SOLDERRM/D.
RECOMMENDED OPERATING CONDITIONS
Value
Min
3.0
5.1
−
Max
5.5
28
Rating
Unit
V
Digital Supply Input Voltage (V
)
CC
Battery Supply Input Voltage (V )
V
S
DC Output Current (D , S )
0.5
125
A
x
x
Junction Temperature (T )
−40
°C
J
THERMAL CONDITIONS
Test Conditions, Typical Value
Board Details (Note 2)
Board Details (Note 3)
Thermal Parameters
Junction−to−Lead (psi−JL8, Y ) or Pins 6−9, 20−23
Unit
°C/W
°C/W
10
73
11
56
JL8
Junction−to−Ambient (R , q
)
q
JA JA
2
2. 1−oz copper, 240 mm copper area, 0.062″ thick FR4. This is the minimum pad board size.
2
3. 1−oz copper, 986 mm copper area, 0.062″ thick FR4.
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4
NCV7708E
ELECTRICAL CHARACTERISTICS
(−40°C < T < 150°C, 5.5 V < VSx < 40 V, 3 V < V < 5.25 V, EN = V , unless otherwise specified)
J
CC
CC
Characteristic
Test Conditions
Min
Typ
Max
Unit
GENERAL
Supply Current (VS1 + VS2)
Sleep Mode (Note 4)
VS1 = VS2 = 13.2 V, V = CSB = 5 V,
CC
−
1.0
5.0
mA
EN = SI = SCLK = 0 V (−40°C to 85°C)
Supply Current (VS1)
Active Mode
EN = V , 5.5 V < VSx < 35 V
CC
−
−
2.0
1.0
4.0
2.5
mA
No Load
Supply Current (V ) − Sleep Mode (Note 4)
CSB = V , EN = SI = SCLK = 0 V
mA
CC
CC
(−40°C to 85°C)
Supply Current (V ) − Active Mode
EN = CSB = V , SI = SCLK = 0 V
−
−
1.5
0.5
3.0
1.0
mA
mA
CC
CC
Supply Current (VS2)
Active Mode
EN = V , 5.5 V < VSx < 35 V
CC
No Load
V
Power−On−Reset Threshold
2.60
4.2
2.80
4.6
−
3.00
5.1
400
40.0
5.5
170
−
V
V
CC
VSx Undervoltage Detection Threshold
VSx Undervoltage Detection Hysteresis
VSx Overvoltage Detection Threshold
VSx Overvoltage Detection Hysteresis
Thermal Warning (Note 5)
VSx decreasing
VSx increasing
100
35.0
1.5
mV
V
37.5
3.5
145
30
V
120
−
°C
°C
°C
−
Thermal Warning Hysteresis (Note 5)
Thermal Shutdown (Note 5)
155
1.05
175
1.20
195
−
Ratio of Thermal Shutdown to Thermal Warning (Note 5)
OUTPUTS
Output High R
(source)
I
= −500 mA
W
DSon
out
8 V < Vs < 40 V
−
−
−
−
−
0.8
−
1.8
1.0
2.2
−
8 V < Vs < 40 V, T = 25°C
5.5 V < Vs ≤ 8 V
5.5 V < Vs ≤ 8 V, T = 25°C
1.3
Output Low R
(sink)
I
= 500 mA
W
DSon
out
8 V < Vs < 40 V
−
−
−
−
−
0.8
−
1.8
1.0
2.2
−
8 V < Vs < 40 V, T = 25°C
5.5 V < Vs ≤ 8 V
5.5 V < Vs ≤ 8 V, T = 25°C
1.3
Source Leakage Current
Sink Leakage Current
OUTH(1−6) = 0 V, VSx = 40 V, V = 5 V
−5.0
−1.0
−
−
−
−
mA
mA
CC
OUTH(1−6) = 0 V, Vsx = 13.2 V, V = 5V
CC
OUTL(1−6) = 34 V, V = 5 V, T = 125°C
−
−
−
−
5.0
1.0
CC
OUTL(1−6) = 34 V, V = 5 V, T = 25°C
CC
Overcurrent Shutdown Threshold (OUTHx)
Current Limit (OUTHx)
V
CC
V
CC
V
CC
V
CC
= 5 V, Vsx = 13.2 V
= 5 V, Vsx = 13.2 V
= 5 V, Vsx = 13.2 V
= 5 V, Vsx = 13.2 V
−1.9
−5.0
1.0
−1.45
−3.0
1.45
−1.0
−2.0
1.9
A
A
Overcurrent Shutdown Threshold (OUTLx)
A
Overcurrent Shutdown Delay Time − Source
Overcurrent Shutdown Delay Time − Sink
10
10
25
25
50
50
ms
4. For temperatures above 85°C, refer to graphs for VSx and V Sleep Current vs. Temperature on page 13.
CC
5. Thermal characteristics are not subject to production test.
6. Refer to “Typical High−Side Negative Clamp Voltage” graph on page 13.
7. Not production tested.
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5
NCV7708E
ELECTRICAL CHARACTERISTICS
(−40°C < T < 150°C, 5.5 V < VSx < 40 V, 3 V < V < 5.25 V, EN = V , unless otherwise specified)
J
CC
CC
Characteristic
Test Conditions
Min
Typ
Max
Unit
OUTPUTS
Current Limit (OUTLx)
V
V
V
V
= 5 V, Vsx = 13.2 V
2.0
3.0
−15
200
−
3.0
8.0
−6.0
350
0.9
−
5.0
15
A
mA
mA
ms
V
CC
CC
CC
CC
Under Load Detection Threshold (OUTLx)
Under Load Detection Threshold (OUTHx)
Under Load Detection Delay Time
Power Transistor Body Diode Forward Voltage
High−Side Clamping Voltage (Note 6)
Low−Side Clamping Voltage
= 5 V, Vsx = 13.2 V
= 5 V, Vsx = 13.2 V
= 5 V, Vsx = 13.2 V
−2.0
600
1.3
−0.7
48
I = 500 mA
F
I(OUTHx) = −50 mA
I(OUTLx) = 50 mA
−
V
34
−
−
V
Low−Side Clamping Energy
I(OUTLx) = 0.6 A, T = 25°C, DC = 0.5%
−
15
mJ
A
Logic Inputs (EN, SI, SCLK, CSB)
Input Threshold − High
Input Threshold − Low
−
−
−
70
−
%V
CC
30
Input Hysteresis
100
300
600
mV
Input Pulldown Current (EN, SI, SCLK)
Sleep Mode (SI, SCLK)
EN = SI = SCLK = V
5.0
10
10
50
50
mA
CC
EN = 0, SI = SCLK = V
100
CC
Input Pullup Current (CSB)
Sleep Mode
CSB = 0 V, EN = V
−50
−10
−50
−5.0
−10
mA
CC
EN = 0 V, V = 5 V
−100
CC
Input Capacitance (Note 7)
Logic Output (SO)
Output High
−
10
15
pF
I
I
= 1 mA
V
CC
– 1.0
V – 0.7
CC
−
V
V
out
Output Low
= −1.6 mA
−
−10
−
0.2
−
0.4
10
15
out
Tri−state Leakage
CSB = V , 0 V < SO < V
mA
pF
CC
CC
Tri−state Input Capacitance (Note 7)
Timing Specifications
High Side Turn On Time
High Side Turn Off Time
Low Side Turn On Time
Low Side Turn Off Time
High Side Rise Time
High Side Fall Time
Low Side Rise Time
Low Side Fall Time
CSB = V , 0 V < V < 5.25 V
10
CC
CC
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
= 25 W
= 25 W
= 25 W
= 25 W
= 25 W
= 25 W
= 25 W
= 25 W
−
−
7.5
3.0
6.5
2.0
4.0
2.0
1.0
1.0
−
13
6.0
13
5.0
8.0
3.0
2.0
3.0
−
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
load
load
load
load
load
load
load
load
−
−
−
−
−
−
Non−Overlap Time
High Side Turn Off To Low Side Turn On
Low Side Turn Off To High Side Turn On
1.5
1.5
Non−Overlap Time
−
−
4. For temperatures above 85°C, refer to graphs for VSx and V Sleep Current vs. Temperature on page 13.
CC
5. Thermal characteristics are not subject to production test.
6. Refer to “Typical High−Side Negative Clamp Voltage” graph on page 13.
7. Not production tested.
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6
NCV7708E
ELECTRICAL CHARACTERISTICS
(−40°C < T < 150°C, 5.5 V < VSx < 40 V, EN = V = 5 V, unless otherwise specified)
J
CC
Timing
Chart #
Characteristic
Conditions
Min
Typ
Max
Unit
Serial Peripheral Interface (V = 5 V)
CC
SCLK Frequency
−
−
5.0
MHz
ns
SCLK Clock Period
V
V
= 5 V
200
500
−
−
−
−
CC
= 3.3 V
CC
Maximum Input Capacitance (Note 8)
SCLK High Time
SI, SCLK
−
1
2
−
−
−
−
12
−
pF
ns
ns
ns
85
85
SCLK Low Time
−
SCLK Setup Time
3
4
85
85
−
−
−
−
SI Setup Time
SI Hold Time
11
12
50
50
−
−
−
−
ns
ns
ns
CSB Setup Time
5
6
100
100
−
−
−
−
CSB High Time (Note 9)
SO enable after CSB falling edge
SO disable after CSB rising edge
SO Rise Time
7
8
200
−
−
−
−
ns
ns
ns
ns
ns
ns
50
50
25
25
50
9
−
−
C
C
= 40 pF
= 40 pF
−
−
10
10
20
load
load
SO Fall Time
−
−
SO Valid Time
SCLK High to SO 50%
10
−
8. Not tested in production
9. This is the minimum time the user must wait between SPI commands.
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7
NCV7708E
4
7
CSB
6
5
SCLK
3
1
2
CSB
SO
8
9
SI
12
SCLK
11
10
SO
Figure 2. SPI Timing Diagram
SPI Communication
Standard 16−bit communication has been implemented
for the communication of this IC to turn drivers on and off,
and to report faults. (Reference the SPI Communication
Frame Format Diagram). The LSB (Least Significant Bit) is
clocked in first.
Communication is implemented as follows:
1. CSB goes low to allow serial data transfer.
2. A 16 bit word is clocked (SCLK) into the SI
(serial input) pin. The SI input signal is latched on
the falling edge of SCLK.
3. CSB goes high to transfer the clocked in
information to the data registers.
(Note: SO is tristate when CSB is high.)
4. The SI data will be accepted when a valid SPI
frame is detected. A valid SPI frame consists of
the above conditions and a complete set of
multiples of 16 bit words.
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8
NCV7708E
CSB
SI
SRR OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3 OUTL4 OUTH4 OUTL5 OUTH5 OUTL6 OUTH6 OCD
ULD
ULD
OVLO
SCLK
TW
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3 OUTL4 OUTH4 OUTL5 OUTH5 OUTL6 OUTH6 OLD
PSF
SO
Figure 3. SPI Communication Frame Format
The table below defines the programming bits and
diagnostic bits. Fault information is sequentially clocked out
the SO pin of the NCV7708E as programming information
is clocked into the SI pin of the device. Daisy chain
communication between SPI compatible IC’s is possible by
connection of the serial output pin (SO) to the input of the
sequential IC (SI).
Input Data
Output Data
Bit
Bit
Number
Number
Bit Description
Bit Status
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Off
Bit Description
Bit Status
0 = No Fault
1 = Fault
0 = No Fault
1 = Fault
0 = No Fault
1 = Fault
0 = Off
15
Over Voltage Lock Out
Control (OVLO)
15
Power Supply Fail Signal
(OVLO or UVLO = PSF)
14
13
12
11
10
9
Under Load Detection Shut
Down Control (ULD)
14
13
12
11
10
9
Under Load Detect Signal
(ULD)
Over Current Detection Shut
Down Control (OCD)
Over Load Detect Signal
(OLD)
OUTH6
OUTH6*
1 = On
1 = On
OUTL6
0 = Off
OUTL6*
0 = Off
1 = On
1 = On
OUTH5
0 = Off
OUTH5*
0 = Off
1 = On
1 = On
OUTL5
0 = Off
OUTL5*
0 = Off
1 = On
1 = On
8
OUTH4
0 = Off
8
OUTH4*
0 = Off
1 = On
1 = On
7
OUTL4
0 = Off
7
OUTL4*
0 = Off
1 = On
1 = On
6
OUTH3
0 = Off
6
OUTH3*
0 = Off
1 = On
1 = On
5
OUTL3
0 = Off
5
OUTL3*
0 = Off
1 = On
1 = On
4
OUTH2
0 = Off
4
OUTH2*
0 = Off
1 = On
1 = On
3
OUTL2
0 = Off
3
OUTL2*
0 = Off
1 = On
1 = On
2
OUTH1
0 = Off
2
OUTH1*
0 = Off
1 = On
1 = On
1
OUTL1
0 = Off
1
OUTL1*
0 = Off
1 = On
1 = On
0
Status Register Reset (SRR)
0 = No Reset
1 = Reset
0
Thermal Warning (TW)
0 = Not in TW
1 = In TW
*Output Bits [1:12] represent the state of the designated outputs.
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9
NCV7708E
DETAILED OPERATING DESCRIPTION
General
initialized in the off (high impedance) condition, and will
remain off regardless of the status of V . This allows
The NCV7708E Double Hex Driver provides drive
CC
capability for 3 independent H−Bridge configurations, or 6
High Side configurations with 6 Low Side configurations, or
any combination of arrangements. Each output drive is
characterized for a 500 mA load and has a typical 1.0 A surge
capability (at 12 V). Strict adherence to integrated circuit die
temperature is necessary. Maximum die temperature is
150°C. This may limit the number of drivers enabled at one
time. Output drive control and fault reporting is handled via
the SPI (Serial Peripheral Interface) port.
An Enable function (EN) provides a low quiescent sleep
current mode when the device is not being utilized. No data
is stored when the device is in sleep mode. A pull down
current source is provided on the EN input to ensure the
device is off if the input signal is lost. Pull down current
sources are also provided on the SI and SCLK inputs. A pull
up current source is provided for the CSB input for the same
reason. A loss of signal pulls the CSB input high to stop any
spurious signals into the SPI port.
power up sequencing of V , VS1, and VS2 up to the user.
The voltage on VS1 and VS2 should be operated at the same
potential.
A built−in hysteresis on the under voltage threshold is
included to prevent an unknown region on the power pins.
After a device has powered up and the output drivers are
allowed to turn on, the output drivers will not turn off until
the voltage on the supply pins is reduced from the initial
under voltage threshold, or if shut down by either a SPI
command or a fault condition.
CC
Internal power−up circuitry on the logic supply pin
supports a smooth turn on transition. V power up resets
CC
the internal logic such that all output drivers will be off as
power is applied. Exceeding the under voltage lockout
threshold on V allows information to be input through the
CC
SPI port for turn on control. Logic information remains
intact over the entire VS1 and VS2 voltage range.
Current Limitation
Power Up/Down Control
Input bit 13 (OCD) controls the action of driver shutoff
during current limit. With a 0 for bit 13, there is no driver
shutoff, and the drivers current limit at 3 A. With a 1 for input
bit 13, the output drivers shut off when the shutdown
threshold current is passed. Devices can be turned back on
via the SPI port. Note: high currents could cause a high rise
in die temperature. Devices will not turn on if the die
temperature exceeds the thermal shutdown temperature.
An under voltage lockout circuit prevents the output
drivers from turning on unintentionally. This control is
provided by monitoring the voltages on the VS1, VS2, and
V
CC
pins. Each analog power pin (VS1 or VS2) powers their
respective output drivers (VS1 powers OUTH1, OUTH2,
OUTH3, all 6 charge pumps and all 6 low−side pre−drivers,
VS2 powers OUTH4, OUTH5, and OUTH6). All drivers are
Over Current Detection Shut Down
OCD Input
Bit 13
OUTx OCD
Condition
Output Data Bit 13 Over
Load Detect (OLD) Status
Current Limit
of all Drivers
OUTx Status
Unchanged
0
0
1
1
0
1
0
1
0
3 A
3 A
3 A
3 A
1 (Need SRR to reset)
0
Unchanged
Unchanged
1 (Need SRR to reset)
OUTx Latches Off (Need SRR to reset)
Under Load Detection
The under−load detection is accomplished by monitoring
the current from each output driver. A minimum load current
(this is the maximum open circuit detection threshold) is
required when the drivers are turned on. If the under−load
circuit detection threshold has been crossed for more than
the under−load delay time, the bit indicator (output bit #14)
for open circuit will be set to a 1. In addition, the offending
driver will be turned off only if input bit 14 (ULD) is set to
1 (true).
Under Load Detection Shut Down
ULD Input
Bit 14
OUTx ULD
Condition
Output Data Bit 14 Under
Load Detect (ULD) Status
OUTx Status
Unchanged
0
0
1
1
0
1
0
1
0
1 (Need SRR to reset)
0
Unchanged
Unchanged
1 (Need SRR to reset)
OUTx Latches Off (Need SRR to reset)
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10
NCV7708E
Over Voltage Shutdown
Over voltage shutdown circuitry monitors the voltage on
the VS1 and VS2 pins. When the Over−voltage Threshold
voltage level has been breached on both or either one of the
VSx supply inputs, output bit 15 will be set and, if input bit
15 (OVLO) is set to 1, all outputs will turn off. Turn on/off
status is maintained in the logic circuitry. When proper input
voltage levels are re−established, the programmed outputs
will turn back on. Over−voltage shutdown can be disabled
by using the SPI input bit 15 (OVLO = 0).
Over Voltage Lock Out (OVLO) Shut Down
OVLO In-
put Bit 15
VSx OVLO
Condition
Output Data Bit 15 Power
Supply Fail (PSF) Status
OUTx Status
0
0
1
1
0
1
0
1
0
Unchanged
Unchanged
1 (Need SRR to reset)
0
Unchanged
1 (Need SRR to reset)
All Outputs Off (Remain off until VSx is out of OVLO)
Thermal Shutdown
Six independent thermal shutdown circuits are featured
(one common sensor for each HS and LS transistor pair).
Each sensor has two levels, one to give a Thermal Warning
(TW) and a higher one, Over Temperature, which will shut
the drivers off. When the part reaches the temperature point
of Thermal Warning, the output data bit 0 (TW) will be set
to a 1, and the outputs will remain on. With one or more
sensors detecting the over temperature level, all channels
will be turned off simultaneously. All outputs will return to
normal operation when the part thermally recovers
(Thermal toggling), because the over temperature shutdown
does not change the actual channel selection. The output
data bit 0, Thermal Warning, will latch and remain set, even
after cooling, and is reset by using a software command to
input bit 0 (SRR). Since thermal warning precedes a thermal
shutdown, software polling of this bit will allow for load
control and possible prevention of thermal shutdown
conditions.
Thermal warning information can be retrieved
immediately without performing a complete SPI access
cycle. Figure 4 below displays how this is accomplished.
Bringing the CSB pin from a 1 to a 0 condition immediately
displays the information on the output data bit 0, thermal
warning, even in the absence of a SCLK signal. As the
temperature of the NCV7708E changes from a condition
from below the thermal warning threshold to above the
thermal warning threshold, the state of the SO pin changes
and this level is available immediately when the CSB goes
to 0. A 0 on SO indicates there is no thermal warning, while
a 1 indicates the IC is above the thermal warning threshold.
This warning bit is reset by using the input data bit 0, SRR.
CSB
CSB
SCLK
SCLK
TWH
Tristate Level
SO
SO
Tristate Level
NTW
Thermal Warning High
No Thermal Warning
Figure 4. Access to Temperature warning information shows the thermal information is available immediately
with activation of the CSB signal without having to toggle the SCLK line.
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11
NCV7708E
Applications Drawing
The applications drawing below displays the range with
which this part can drive a multitude of loads.
1. H−Bridge Driver configuration
2. Low Side Driver
3. High Side Driver
+
VSx
VSx
3
2
OUTHx
OUTLx
OUTHx
OUTLx
1
GND
GND
M
VSx
OUTHx
OUTLx
GND
Figure 5. Application Drawing
Any combination of motors and high side drivers can be designed in. This allows for flexibility in many systems.
H−Bridge Driver Configuration
Overvoltage Clamping − Driving Inductive Loads
To avoid excessive voltages when driving inductive loads
in a single−side−mode (LS or HS switch, no freewheeling
path), the NCV7708E provides internal clamping diodes.
Thus any load type can be driven without the requirement of
external freewheeling diodes. Due to high power dissipation
during clamping, the maximum energy capability of the
driver transistor has to be considered.
The NCV7708E has the flexibility of controlling each
driver independently. When the device is set up in an
H−Bridge configuration, the software design has to take care
of avoiding simultaneous activation of connected HS and LS
transistors. Resulting high shoot through currents could
cause irreversible damage to the device.
Thermal Model
Various copper areas used
for heat spreading
Lead #1
Package Construction
With and Without Mold Compound
1
Molded as / Symmetry
4
Active Area (red)
Lead #8 (one of 8 thermal leads)
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12
NCV7708E
TYPICAL OPERATING CHARACTERISTICS
−1.2
−1.0
−0.8
−0.6
−0.4
4.0
3.0
2.0
1.0
0
−0.2
0
0
−1.0
−2.0
−3.0
−4.0
−50
0
50
100
150
HIGH SIDE PIN VOLTAGE (V)
T , TEMPERATURE (°C)
J
Figure 6. Typical High−side Negative Clamp
Voltage vs. Reverse Current, Room Temperature
Figure 7. VCC Sleep Supply Current vs.
Temperature
110
100
90
7.0
6.0
5.0
80
4.0
3.0
2.0
70
1 oz
2 oz
60
50
40
1.0
0
0
100 200 300 400 500 600 700 800 900 1000
−50
0
50
100
150
2
COPPER AREA (mm )
T , TEMPERATURE (°C)
J
Figure 8. qJA vs. Copper Spreader Area
Figure 9. VS1 + VS2 Sleep Current vs.
Temperature
100
10
2
Cu_Area = 239 mm 1 oz
2
Cu_Area = 986 mm 1 oz 1 S
1.0
0.1
0.01
0.000001 0.00001
0.0001
0.001
0.01
TIME (sec)
0.1
1.0
10
100
1000
Figure 10. SOIC 28−Lead Single Pulse Heating Curve
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13
NCV7708E
100
D = 0.50
D = 0.20
D = 0.10
D = 0.05
10
D = 0.01
1.0
0.1
2
Cu_Area = 986 mm 1 oz 1 S
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
PULSE DURATION (sec)
Figure 11. SOIC 28−Lead Thermal Duty Cycle Curves on 1, Spreader Test Board
SOIC 28−lead Thermal RC Network Models
2
2
2
2
239 mm
986 mm
239 mm
986 mm
Cu
Area
Cauer Network
Foster Network
C’s
2.68E−05
1.02E−04
2.82E−04
9.58E−04
2.72E−03
2.02E−03
2.93E−02
0.116
C’s
Units
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
W−s/C
Tau
Tau
Units
sec
sec
sec
sec
sec
sec
sec
sec
sec
sec
2.68E−05
1.02E−04
2.84E−04
9.73E−04
2.63E−03
1.95E−03
3.12E−02
0.091
1.00E−06
1.00E−05
1.00E−04
5.00E−04
1.00E−03
1.00E−02
8.00E−02
4.00E−01
2.00E+00
6.00E+01
R’s
1.00E−06
1.00E−05
1.00E−04
5.00E−04
1.00E−03
1.00E−02
8.00E−02
4.00E−01
2.00E+00
5.50E+01
R’s
0.16
0.21
1
1
R’s
R’s
0.048
0.048
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
2.84E−02
6.14E−02
1.94E−01
0.100
2.84E−02
6.14E−02
1.94E−01
0.100
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
0.115
0.115
0.352
0.349
0.777
0.776
0.599
0.630
0.500
0.480
1.677
1.667
1.839
1.933
2.968
3.151
2.207
1.836
6.424
5.527
1.249
2.291
6.940
6.689
8.225
8.000
53.503
36.970
59.000
41.000
Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items
in the Foster network are computed by the square root of time constant R(t) = 28.4 * sqrt(time(sec)). The constant is derived
based on the active area of the device with silicon and epoxy at the interface of the heat generation.
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14
NCV7708E
The Cauer networks generally have physical significance
circuit simulating tools, whereas Foster networks may be
more easily implemented using mathematical tools (for
instance, in a spreadsheet program), according to the
following formula:
and may be divided between nodes to separate thermal
behavior due to one portion of the network from another.
The Foster networks, though when sorted by time constant
(as above) bear a rough correlation with the Cauer networks,
are really only convenient mathematical models. Both
Foster and Cauer networks can be easily implemented using
n
*tńtau
i
ǒ
Ǔ
R(t) + ȍR 1 * e
i
i+1
R
R
R
R
n
Junction
1
2
3
C
C
C
C
n
1
2
3
Time constants are not simple RC products. Amplitudes
of mathematical solution are not the resistance values.
Ambient
(thermal ground)
Figure 12. Grounded Capacitor Thermal Network (“Cauer” Ladder)
R
R
R
R
n
1
2
3
Junction
C
C
C
C
n
1
2
3
Ambient
(thermal ground)
Each rung is exactly characterized by its RC−product
time constant; amplitudes are the resistances.
Figure 13. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)
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15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−28 WB
CASE 751F
ISSUE J
DATE 23 SEP 2015
SCALE 1:1
−X−
D
28
15
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBER
PR5OTRUSION SHALL NOT BE 0.13 TOTATL IN
EXCESS OF B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
H
E
M
M
Y
0.25
−Y−
1
14
PIN 1 IDENT
MILLIMETERS
DIM MIN
MAX
2.65
0.29
0.49
0.32
18.05
7.60
A
A1
B
2.35
0.13
0.35
0.23
17.80
7.40
A
L
C
0.10
D
E
−T−
SEATING
PLANE
G
A1
G
H
1.27 BSC
C
10.05
0.41
0
10.55
0.90
8
B
L
M
M
M
S
S
Y
_
_
0.025
T X
SOLDERING FOOTPRINT
GENERIC
MARKING DIAGRAM*
8X
11.00
28
1
28X
1.30
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
AWLYYWWG
1
28
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
28X
0.52
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1.27
PITCH
14
15
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42345B
SOIC−28 WIDE BODY
PAGE 1 OF 1
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