NCV7723DQBR2G [ONSEMI]
6 Channel Half-Bridge Driver;
| 型号： | NCV7723DQBR2G |
| 厂家： | 
ONSEMI |
| 描述： | 6 Channel Half-Bridge Driver 电动机控制 栅 驱动 光电二极管 |
| 文件： | 总25页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Hex Half-Bridge Driver
NCV7723B
MARKING
DIAGRAM
The NCV7723B is a six channel half−bridge driver with protection
features designed specifically for automotive and industrial motion
control applications. The product has independent controls and
diagnostics, and the drivers can be operated in forward, reverse, brake,
and high impedance states. The device is controlled via a 16 bit SPI
interface and is daisy chain compatible. Outputs 1 and 2 can be
controlled through an external PWM signal.
NCV7723B
AWLYWWG
SSOP24 NB EP
CASE 940AK
NCV7723B = Specific Device Code
A
= Assembly Location
= Wafer Lot
WL
Y
= Year
Features
WW
G
= Work Week
= Pb−Free Package
• Low Quiescent Current Sleep Mode
• High−Side and Low−Side Drivers
Connected in Half−Bridge Configurations
• Integrated Freewheeling Protection (LS and HS)
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of
this data sheet.
• 500 mA Typical, 1.1 A Peak Current
• R
= 0.8 W (Typ)
DS(on)
• OUT1 and OUT2 External PWM Control
• 5 MHz SPI Communication
• 16 Bit Frame Error Detection
• Daisy Chain Compatible with Multiple of 8 bit Devices
• Compliance with 3.3 V and 5 V Systems
• Undervoltage and Overvoltage Lockout
• Per Channel Fault Reporting
• Overcurrent Protection
• Overtemperature Protection
• Underload Detection (HS and LS)
• Exposed Pad Package
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This is a Pb−Free Device
Typical Applications
• Automotive
• Industrial
• DC Motor Management for HVAC Application
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
October, 2021 − Rev. 2
NCV7723B/D
NCV7723B
High−side
Driver
NCV7723B
OUT1
Low−side
Driver
VS1
VS2
10 mF 0.1 mF
13.2 V
HS
OUT2
OUT3
LS
VCC
Voltage
Regulator
Power On
Reset
HS
0.1 mF
LS
HS
EN
OUT4
OUT5
Watchdog
Control
Logic
LS
HS
Protection:
LS
Under Load
Over Temperature
Under−voltage
Over−voltage
High−side
Driver
PWM1
PWM2
OUT6
Over Current
Low−side
Driver
SO
SI
uC
16−Bit
Serial
Data
Interface
SCLK
CSB
GND
Figure 1. Typical Application
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2
NCV7723B
VS1
DRIVE1
VS
VS
EN
ENABLE
BIAS
High Side
Charge
Pump
Driver
VS1
Wave Shaping
OUT1
VCC
Fault
Reporting
Control
Logic
Wave Shaping
VS
POR
Low Side
Driver
SO
SI
HS+LS Under Load
Overcurrent
SCLK
CSB
SPI and 16 Bit Logic Control
Thermal Warning &
Shutdown
PWM1
PWM2
VS1
VS2
VS2
VS1
VS2
OUT2
OUT3
OUT4
OUT5
OUT6
DRIVE 2
DRIVE 3
DRIVE 4
DRIVE 5
DRIVE 6
VS1,
VS2
Overvoltage
Lockout
Undervoltage
Lockout
GND
GND GND
GND
VS2
Figure 2. Block Diagram
1
24
23
22
21
20
19
18
17
16
15
14
13
GND
OUT1
OUT5
NC
GND
2
OUT2
NC
3
4
VS1
5
SI
SCLK
CSB
6
VCC
SO
EPAD
7
PWM2
PWM1
VS2
8
EN
9
NC
10
11
12
OUT6
OUT4
GND
NC
OUT3
GND
Figure 3. Pinout – SSOP24 NB EP
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3
NCV7723B
PIN FUNCTION DESCRIPTION The pin−out for the Half−Bridge Driver in SSOP24 NB EP package is shown in the table below.
Pin#
SSOP24
Symbol
GND
OUT1
OUT5
NC
Description
Ground. Must be connected to other GND pins externally.
1
2
Half−bridge output 1
3
Half−bridge output 5
4
No Connection. This pin should be isolated from any traces or via on the PCB board.
16 bit serial communication input. 3.3 V / 5 V (TTL) Compatible − internally pulled down.
Power supply input for Logic.
5
SI
6
VCC
SO
7
16 bit serial communication output. 3.3 V / 5 V Compliant
Enable − active high; wakes the device from sleep mode. 3.3 V / 5 V (TTL) Compatible − internally pulled down.
No Connection. This pin should be isolated from any traces or via on the PCB board.
Half−bridge output 6
EN
8
9
NC
10
11
12
13
14
15
16
17
OUT6
OUT4
GND
GND
OUT3
NC
Half−bridge output 4
Ground. Must be connected to other GND pins externally.
Ground. Must be connected to other GND pins externally.
Half−bridge output 3
No Connection. This pin should be isolated from any traces or via on the PCB board.
Power Supply input for outputs 3, 4, and 6. This pin must be connected to VS1 externally.
VS2
PWM1
External PWM input for output 1. 3.3 V / 5 V (TTL) Compatible − internally pulled down. Connect to ground or
leave floating if unused.
18
19
PWM2
CSB
External PWM input for output 2. 3.3 V / 5 V (TTL) Compatible − internally pulled down. Connect to ground or
leave floating if unused.
Chip select bar − active low; enables serial communication operation. 3.3 V / 5 V (TTL) Compatible − internally
pulled up.
20
21
22
23
24
SCLK
VS1
Serial communication clock input. 3.3 V / 5 V (TTL) Compatible − internally pulled down.
Power Supply input for outputs 1, 2, and 5. This pin must be connected to VS2 externally.
No Connection. This pin should be isolated from any traces or via on the PCB board.
Half−bridge output 2
NC
OUT2
GND
Ground. Must be connected to other GND pins externally.
EPAD Exposed Pad Connect to GND or leave unconnected.
MAXIMUM RATINGS (Voltages are with respect to GND)
Rating
Symbol
Value
Unit
VSx Pin Voltage
(VS1, VS2)
V
(DC)
VsxdcMax
VSxac
−0.3 to 45
−1.0
(AC), t < 500 ms, Ivsx > −2 A
Pin Voltage
(Vcc, SI, SCLK, CSB, SO, EN, PWM1, PWM2)
VioMax
−0.3 to 5.5
V
V
OUTx Pin Voltage
(DC)
(AC)
VoutxDc
VoutxAc
−0.3 to 45
−0.3 to 45
−1.0
(AC), t < 500 ms, IOUTx > −1.1 A
(AC), t < 500 ms, IOUTx < 1 A
1.0
OUTx Pin Current (OUT1, ..., OUT6)
IoutxImax
−2.0 to 2.0
−40 to 150
−55 to 150
260
A
Junction Temperature Range
T
J
°C
°C
°C
Storage Temperature Range
Tstr
Peak Reflow Soldering Temperature: Pb−free 60 to 150 seconds at 217°C
(Note 1)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. See or download onsemi’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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4
NCV7723B
ATTRIBUTES
Characteristic
Symbol
Value
Unit
Short Circuit Reliability Characterization
AECQ10x
Grade A
ESD Capability
Human Body Model per AEC−Q100−002
VSx, OUTx
All Other Pins
Vesd4k
Vesd2k
Vesd750
≥
≥
≥
4.0 kV
2.0 kV
750 V
Charged Device Model per AEC−Q100−011
Moisture Sensitivity Level
MSL
MSL2
Package Thermal Resistance – Still−air
Junction–to–Ambient
(Note 2)
(Note 2)
R
32.1
21.8
°C/W
°C/W
q
JA
Junction–to–Board
R
Y
JBOARD
2
2. Based on JESD51−7, 1.6 mm thick FR4, 2S2P PCB with 600 mm 2 oz. copper and 18 thermal vias to 80x80 mm 1 oz. internal spreader
planes. Simulated with each channel dissipating 0.2 W.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCCOp
VSxOp
IxOp
Min
3.15
5.5
−
Max
5.25
32
Unit
V
Digital Supply Input Voltage
Battery Supply Input Voltage (VS1 = VS2)
DC Output Current
V
0.5
A
Junction Temperature
TjOp
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T ≤ 150°C, 5.5 V ≤ VSx ≤ 40 V, 3.15 V ≤ V ≤ 5.25 V, EN = V , unless otherwise specified.)
J
CC
CC
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES
Supply Current (VS1 + VS2)
Sleep Mode
IqVSx85
IvsOp
VS1 = VS2 = 13.2 V, V = 0 V
CC
−40°C to 85°C
−
−
1.0
0.5
1.0
2.5
1.0
2.5
mA
mA
mA
Supply Current (VS1 + VS2)
Active Mode
EN = V , 5.5V < VSx < 32 V
CC
No Load,All Outputs Off
Supply Current (Vcc)
Sleep Mode
CSB = V , EN = SI = SCLK = 0 V
CC
IqV
−40°C to 85°C
−
CC
EN = CSB = V , SI = SCLK = 0 V
CC
Active Mode
IV Op
CC
No Load, All Outputs Off
−
−
1.5
2.0
3.0
5.0
mA
Total Sleep Mode Current
I(VS1) + I(VS2) + I(VCC)
IqTot
Sleep Mode, −40°C to 85°C
VS1 = VS2 = 13.2 V, No Load
mA
VCC Power−on Reset Threshold
V
por
V
increasing
−
2.70
2.90
V
V
CC
CC
VSx Undervoltage Detection Threshold
VSxuv
VSx decreasing
VSx increasing
3.5
3.7
4.1
4.3
4.5
4.7
VSx Undervoltage Detection Hysteresis
VSx Overvoltage Detection Threshold
VSxuHys
VsXov
100
−
450
mV
V
VSx increasing
VSx decreasing
32
29.5
36
33.5
40
37.5
VSx Overvoltage Detection Hysteresis
VSxoHys
−
2.5
−
V
DRIVER OUTPUT CHARACTERISTICS
Output High R
(source)
RDSonHS Iout = −500 mA, Vs = 13.2 V
= 3.15 V
−
−
0.8
0.8
1.8
1.8
W
W
DS(on)
V
CC
Output Low R
(sink)
RDSonLS
Iout = 500 mA, Vs = 13.2 V
DS(on)
V
= 3.15 V
CC
Source Leakage Current
V
= 5 V, OUT (1−6) = 0 V, EN = 0/5 V
CC
IsrcLkg13.2 VSx = 13.2 V
−1.0
−2.0
−
−
−
−
mA
mA
IsrcLkg28
VSx = 28 V
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NCV7723B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T ≤ 150°C, 5.5 V ≤ VSx ≤ 40 V, 3.15 V ≤ V ≤ 5.25 V, EN = V , unless otherwise specified.) (continued)
J
CC
CC
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
DRIVER OUTPUT CHARACTERISTICS
Sink Leakage Current
V
= 5 V, EN = 0/5 V
CC
OUT (1−6) = VSx = 13.2 V
OUT (1−6) = VSx = 28 V
−
−
−
−
1.0
2.0
IsnkLkg13.2
IsnkLkg28
mA
mA
Overcurrent Shutdown Threshold (Source)
Overcurrent Shutdown Threshold (Sink)
Over Current Delay Timer
IsdSrc
IsdSnk
TdOc
V
V
= 5 V, VSx = 13.2 V
= 5 V, VSx = 13.2 V
−2.0
1.1
10
−1.5
1.5
−1.1
2.0
50
A
A
CC
CC
25
ms
mA
mA
ms
V
Underload Detection Threshold (Low Side)
Underload Detection Threshold (High Side)
Underload Detection Delay Time
IuldLS
−
2.5
7.5
−
V
CC
V
CC
V
CC
= 5 V, VSx = 13.2 V
= 5 V, VSx = 13.2 V
= 5 V, VSx = 13.2 V
−7.5
200
−
−2.5
350
0.9
IuldHS
TdUld
600
1.3
Body Diode Forward Voltage
IbdFwd
If = 500 mA
DRIVER OUTPUT SWITCHING CHARACTERISTICS
High Side Turn On Time
High Side Turn Off Time
Low Side Turn On Time
Low Side Turn Off Time
High Side Rise Time
High Side Fall Time
ThsOn
ThsOff
TlsOn
TlsOff
ThsTr
ThsTf
TlsTr
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
Vs = 13.2 V, R
= 70 W
= 70 W
= 70 W
= 70 W
= 70 W
= 70 W
= 70 W
= 70 W
= 70 W
−
−
120
20
120
35
30
30
30
30
−
165
45
165
75
50
50
50
50
−
ms
ms
ms
ms
ms
ms
ms
ms
ms
load
load
load
load
load
load
load
load
load
−
−
10
10
10
10
5
Low Side Rise Time
Low Side Fall Time
TlsTf
High Side Off to Low Side On
Non−Overlap Time
ThsOffLsOn Vs = 13.2 V, R
Low Side Off to High Side On
Non−Overlap Time
TlsOffHsOn Vs = 13.2 V, R
= 70 W
5
−
−
ms
load
PWM High to High Side On Time
PWM Low to High Side Off Time
PWM High to Low Side On Time
PWM Low to Low Side Off Time
THERMAL RESPONSE
ThsOnPWM Vs = 13.2 V, R
ThsOffPWM Vs = 13.2 V, R
TlsOnPWM Vs = 13.2 V, R
TlsOffPWM Vs = 13.2 V, R
= 70 W
= 70 W
= 70 W
= 70 W
−
−
−
−
120
20
165
45
ms
ms
ms
ms
load
load
load
load
120
35
165
75
Thermal Warning
Twr
TwHy
Tsd
(Note 3)
(Note 3)
(Note 3)
(Note 3)
120
−
140
20
170
−
°C
°C
°C
°C
Thermal Warning Hysteresis
Thermal Shutdown
150
−
175
20
200
−
Thermal Shutdown Hysteresis
TsdHy
LOGIC INPUTS − EN, SI, SCLK, CSB, PWM1, PWM2
Input Threshold
High
Low
VthInH
VthInL
2.0
−
−
−
−
0.6
V
V
Input Hysteresis − SI, SCLK, CSB, PWM1,
PWM2
VthInHys
50
150
300
mV
Input Hysteresis − EN
VthENHys
Rpdx
150
50
400
125
800
200
mV
Pull−down Resistance − EN, SI, SCLK,
PWM1, PWM2
EN = SI = SCLK = V
kW
CC
Pull−up Resistance − CSB
RpuCSB
Cinx
CSB = 0 V
(Note 3)
50
125
250
15
kW
Input Capacitance
−
−
pF
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NCV7723B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T ≤ 150°C, 5.5 V ≤ VSx ≤ 40 V, 3.15 V ≤ V ≤ 5.25 V, EN = V , unless otherwise specified.) (continued)
J
CC
CC
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
LOGIC OUTPUT − SO
Output High
VsoH
ISOURCE = −1 mA
V
–
−
−
V
CC
0.6
Output Low
VsoL
ISINK = 1.6 mA
CSB = 5 V
−
−5
−
−
−
−
0.4
5
V
Tri−state Leakage
ItriStLkg
ItriStCout
mA
pF
Tri−state Output Capacitance
SERIAL PERIPHERAL INTERFACE
SCLK Frequency
CSB = V , 0 V < V < 5.25 V (Note 3)
15
CC
CC
Fclk
−
−
−
5.0
MHz
ns
SCLK Clock Period
TpClk
V
CC
V
CC
= 5 V
= 3.3 V
200
500
−
−
−
−
−
1
SCLK High Time
SCLK Low Time
SCLK Setup Time
SI Setup Time
TclkH
TclkL
85
85
85
−
−
−
−
−
−
−
−
ns
ns
ns
ns
2
TclkSup
TsiSup
3, 4
11
50
50
SI Hold Time
TsiH
TcsbSup
TcsbH
12
5, 6
7
−
−
−
−
−
−
−
ns
ns
ms
ns
ns
CSB Setup Time
100
5.0
−
CSB High Time
(Note 4)
−
SO enable after CSB falling edge
SO disable after CSB rising edge
TenSo
TdisSo
8
200
200
9
−
−
−
SO Rise/Fall Time
SO Valid Time
TsoR/F
TsoV
Cload = 40 pF (Note 3)
−
10
50
25
ns
ns
Cload = 40 pF (Note 3)
SCLK ↑ to SO 50%
10
100
EN Low Valid Time
TenL
V
= 5 V; EN H → L 50% to
−
−
−
ms
10
CC
OUTx turning off 50%
EN High to SPI Valid
TenHspiV
Tsrr
−
−
−
−
100
ms
ms
−
SRR Delay Between Consecutive Frames
(Note 5)
−
150
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Not production tested.
4. This is the minimum time the user must wait between SPI commands.
5. This is the minimum time the user must wait between consecutive SRR requests.
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NCV7723B
CHARACTERISTIC TIMING DIAGRAMS
TlsTr
90%
TlsOff
10%
LS Turn OFF
TlsOffHsOn
90%
10%
HS Turn ON
ThsTr
90%
ThsOn
CSB
LS Turn On
TlsTf
90%
TlsOn
10%
HS Turn Off
ThsOffLsOn
90%
10%
ThsTf
90%
ThsOff
CSB
Figure 4. Detailed Driver Timing
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NCV7723B
TlsTf
LS Turn On
90%
TlsOnPWM
10%
90%
10%
HS Turn ON
ThsTr
90%
ThsOnPWM
PWMx
TlsTr
90%
TlsOffPWM
LS Turn Off
HS Turn Off
10%
90%
10%
ThsTf
PWMx
ThsOffPWM
90%
Figure 5. Detailed Driver Timing (OUT1 / OUT2 PWM)
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NCV7723B
4
7
CSB
5
SCLK
6
3
1
2
CSB
SO
9
8
SI
SCLK
SO
12
11
10
Figure 6. Detailed SPI Timing
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NCV7723B
TYPICAL PERFORMANCE GRAPHS
3.5
3.0
2.5
2.0
1.5
1.0
1.40
VSx = 13.2 V
1.38
VSx = 13.2 V
150°C
25°C
1.36
1.34
1.32
1.30
1.28
1.26
1.24
V
= 5.25 V
= 5 V
CC
V
CC
−40°C
V
= 3.15 V
50
0.5
0
CC
1.22
1.20
−50
0
100
150
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
VCC VOLTAGE (V)
Figure 7. IqTot vs. Temperature
Figure 8. I(VCC) Active Mode vs. V(VCC)
1.8
1.6
1.4
1.2
1.0
1.0
VSx = 13.2 V
I = 0.5 A
f
0.95
0.9
HSx
LSx
HSx
0.85
LSx
0.8
0.8
0.6
0.75
−50
0
50
100
150
−50
0
50
TEMPERATURE (°C)
100
150
TEMPERATURE (°C)
Figure 9. RDS(on) vs. Temperature
Figure 10. Body Diode vs. Temperature
0.2
0.18
0.16
0.14
0.12
0.1
1.7
1.6
VSx = 13.2 V
= 5 V
V
CC
LSx
1.5
1.4
1.3
1.2
0.08
0.06
0.04
VSx = 13.2 V
= 5.0 V
HSx
I
snk
V
CC
0.02
0
I
src
−50
0
50
TEMPERATURE (°C)
100
150
−50
0
50
100
150
TEMPERATURE (°C)
Figure 11. Overcurrent vs. Temperature
Figure 12. Leakage vs. Temperature
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NCV7723B
DETAILED OPERATING DESCRIPTION
SPI Communication
General Overview
The NCV7723B is comprised of twelve NMOS power
drivers. The drivers are arranged as six half−bridge output
channels, allowing for three independent full−bridge
configured loads. Output control and status reporting is
handled via the SPI (Serial Peripheral Interface)
communications port. OUT1 and OUT2 can be controlled
with an external PWM signal.
16−bit full duplex SPI communication has been
implemented for device configuration, driver control, and
reading the status data. In addition to the 16−bit status data,
a pseudo−bit (PRE_15) can also be retrieved from the SO
output.
The device must be enabled (EN = H) for SPI
communication. The SPI inputs are TTL compatible and the
Each output is characterized for a typical 0.5 A DC load
and has a maximum 2.0 A surge capability (at VSx =
13.2 V). Maximum allowable junction temperature is
150°C and may constrain the maximum load current and/or
limit the number of drivers active at once.
An active−high enable function (EN) allows global
control of the outputs and provides a low quiescent current
sleep mode when the device is not being utilized. An internal
pull−down resistor is provided on the input to ensure the
device enters sleep mode if the input signal is lost.
SO output high level is defined by the applied V . The
CC
active−low CSB input has a pull−up resistor and the
remaining inputs have pull−down resistors to bias them to
known states when SPI communication is inactive.
The latched thermal shutdown (TSD) status bit PRE_15
is available on SO until the first rising SCLK edge after CSB
goes low. The following conditions must be met for a valid
TSD read to be captured:
1. SCLK and SI are low before the CSB cycle;
2. CSB transitions from high to low;
After EN transitions from low to high, the V POR cycle
3. CSB setup time (TcsbSup: Figure 6, #5) is
satisfied.
Figure 13 shows the SPI communication frame format,
and Tables 1 and 2 define the command input and diagnostic
status output bits.
CC
will proceed and bring the device into normal operation. The
device configuration registers can then be programmed via
SPI. Bringing EN low clears all registers (no configuration
or status data is stored), disables the drivers, and enters sleep
mode.
CSB
SRR
HBSEL
ULDSC
B[12:7] → HBEN[6:1]
B[12:7] → HBST[6:4]
B[6:1] → HBCNF[6:1]
B[6:1] → HBST[3:1]
OVLO
SI
SCLK
SO
15
OCS
14
PSF
13
0
TSD
ULD
TW
PRE_15
PSEUDO−BIT
Figure 13. SPI Communication Frame Format
Communication is implemented as follows and is also
illustrated in Figures 13 and 15:
5. Current SO data is simultaneously shifted out on
every rising edge of SCLK, starting with the MSB
(OCS).
6. CSB goes high to end the frame and SO becomes
tri−state.
7. The last 16 bits clocked into SI are transferred to
the device’s data register if no frame error is
detected, otherwise the entire frame is ignored and
the previous input data is preserved.
1. SI and SCLK are set low before the CSB cycle.
2. CSB goes low to begin a serial data frame;
pseudo−bit PRE_15 is immediately available at
SO.
3. SI data is shifted in on every rising edge of SCLK,
starting with the most significant bit (MSB), SRR.
4. SI data is recognized on every falling edge of the
SCLK.
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12
NCV7723B
Table 1. SPI COMMAND INPUT DEFINITIONS
Channels 6 – 1
Function
Bit#
15
14
13
12
11
10
9
Name
SRR
Status*
1 = Reset
Reserved
1 = Enabled
Scope
Global Status Reset
−
Status Register Reset**
Half Bridge Selection
Underload Shutdown Control
Enable Half−Bridge 6
Enable Half−Bridge 5
Enable Half−Bridge 4
Enable Half−Bridge 3
Enable Half−Bridge 2
Enable Half−Bridge 1
Configure Half−Bridge 6
Configure Half−Bridge 5
Configure Half−Bridge 4
Configure Half−Bridge 3
Configure Half−Bridge 2
Configure Half−Bridge 1
VSx Overvoltage Lockout
HBSEL***
ULDSC
HBEN6
HBEN5
HBEN4
HBEN3
HBEN2
HBEN1
HBCNF6
HBCNF5
HBCNF4
HBCNF3
HBCNF2
HBCNF1
OVLO
Per Half−Bridge Operation
0 = Hi−Z
1 = Enabled
Per Half−Bridge
8
7
6
5
4
0 = LS On, HS Off
1 = LS Off, HS On
Per Half−Bridge
3
2
1
0
1 = Enabled
Global Lockout
*All command input bits are set to 0 at V power−on reset.
CC
**Latched faults are cleared and outputs can be re−programmed if no fault exists after SRR asserted.
***HBSEL enables channel group selection for family devices with more than 6 channels. In the NCV7723B it is recommended to set the HBSEL
bit to 0.
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13
NCV7723B
Table 2. SPI STATUS OUTPUT DEFINITIONS
Channels 6 – 1
Bit#
PRE_15
15
Name
TSD
Function
Status*
1 = Fault
1 = Fault
Scope
Latched Thermal Shutdown
Global Notification; Per Half−Bridge Operation
Global Notification; Per Half−Bridge Operation
OCS
Latched Overcurrent Shutdown
VS1 and/or VS2
14
PSF
ULD
1 = Fault
1 = Fault
Global Notification; Global Operation
Undervoltage or Overvoltage
13
12
11
10
9
Underload Detect
Global Notification; Per Half−Bridge Operation
HBST6[1:0]
HBST5[1:0]
HBST4[1:0]
HBST3[1:0]
HBST2[1:0]
Half Bridge 6 Output Status
Half Bridge 5 Output Status
Half Bridge 4 Output Status
Half Bridge 3 Output Status
Half Bridge 2 Output Status
8
0x00b – Output
Disabled
0x01b − OCS
0x10b − ULD
0x11b − Output
Enabled
7
Per Half−Bridge
6
5
4
3
2
HBST1[1:0]
TW
Half Bridge 1 Output Status
Thermal Warning
1
0
1 = Fault
Global Notification; Per Half−Bridge Operation
*All status output bits are set to 0 at Vcc power−on reset (POR).
HBSTx[1:0] bits are priority encoded to provide the status information of each of the half−bridge outputs. Figure 14 shows the priority encoding
state diagram for the HBSTx[1:0] bits.
PSF, TSD
HBENx = ‘0’
Power On Reset
Output Enabled
“11”
Under
Load
HBENx = ‘1’
PWMx = ‘1’
PSF Recovery*
TSD Recovery**
Output Disabled
“00”
ULD
“10”
Over
Current
(default)
PSF
TSD
Over
Current
OCS
“01”
PSF
TSD
SRR = ‘1’
Power On Reset
*PSF Recovery: VSx rising above the undervoltage threshold or falling below the overvoltage threshold (OVLO = 1)
**TSD Recovery: Sending SRR after junction temperature has fallen below the thermal shutdown threshold
Figure 14. SO HBSTx [1:0] Priority Encoding State Diagram
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14
NCV7723B
Priority Encoding
CSB and SCLK are parallel connected to every device in
the chain while SO and SI are series connected between each
device. The master’s MOSI is connected to the SI of the first
device and the first device’s SO is connected to the next
device’s SI. The SO of the final device in the chain is
connected to the master’s MISO.
The hardware configuration for the NCV7723B daisy
chained with an 8−bit SPI device is shown in Figure 15.
A 24−bit frame made of 16−bit word ‘A’ and 8−bit word ‘B’
is sent from the master. Command word B is sent first
followed by word A. The master simultaneously receives
status word B first followed by word A. The progression of
data from the MCU through the sequential devices is
illustrated in Figure 15.
Compliance with the illustrated frame format is required
for proper daisy chain operation. Situations should be
avoided where an incorrect multiple of 8 bits is sent to the
devices, but the frame length does not cause a frame error in
the devices. For example, the word order could be
inadvertently interleaved or reversed. Invalid data is
accepted by the NCV7723B in such scenarios and possibly
by other devices in the chain, depending on their frame error
implementation. Data is received as a command by the
device at the beginning of the chain, but the device at the end
of the chain may receive status data from the preceding
device as a command.
If an under load event precedes an over current event on
the same half−bridge, the device will report HBSTx = ‘10’
and then HBSTx = ‘01’ as shown in Figure 14. An over
current event preceding an under load event will report
HBSTx = ‘01’ since there is no direct path from the OCS
state to the ULD state. Thus an over current shutdown fault
must be cleared before an underload fault is reported on the
same half−bridge.
Frame Error Detection
The NCV7723B employs frame error detection to help
ensure input data integrity. SCLK is compared to an n x 8 bit
counter and a valid frame (CSB H−L−H cycle) has integer
multiples of 8 SCLK cycles. For the first 16 bits shifted into
SI, SCLK is compared to a modulo16 counter (n = 2), and
SCLK is compared to a modulo 8 counter (n = 1, 2, ...m)
thereafter. This variable modulus allows for daisy chain
operation with devices using different word lengths.
The last 16 bits clocked into SI are transferred to the
NCV7723B’s data register if no frame error is detected,
otherwise the entire frame is ignored and the previous input
data is preserved.
Daisy Chain Operation
Daisy chain operation is possible with multiple 16−bit and
8−bit devices that have a compatible SPI protocol. The clock
phase and clock polarity with respect to the data for all the
devices in the chain must be the same as the NCV7723B.
CMD [x, n] = Command Word to Device ‘x’, Length ‘n’
STA [x, n] = Status Word from Device ‘x’, Length ‘n’
NCV7723B
16−bit Device
8−bit Device
MCU
CSB
CSB
CSB
SCLK
MOSI
SCLK
SCLK
SI
MISO
SI
SO
SO
STA [B, 8]
+
STA [A, 16]
CMD [B, 8]
+
CMD [A, 16]
STA [A, 16]
+
CMD [B, 8]
Device A
Master
Device B
Figure 15. Daisy Chain Configuration
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15
NCV7723B
24bit Frame
Word B − 8 bits
Word A − 16 bits
CSB
7
6
1
0
15
8
7
0
SCLK
SI
MSB
MSB
LSB
MSB
MSB
LSB
LSB
SI data is recognized on the falling SCLK. edge
LSB
SO
TSD
SO data is shifted out on the rising SCLK edge.
Modulo 16 counter begins on the first rising SCLK edge after CSB goes low.
Modulo 16 counter ends − 16 bit word length valid.
Modulo 8 counter begins on the next rising SCLK edge.
Modulo 8 counter ends − 8 bit word length valid. valid n*8 bit frame.
Figure 16. Daisy Chain – 24 bit Frame Format
TSD Bit in Daisy Chain Operation
Since the TSD status of any device propagates
automatically through the entire chain, it is not possible to
determine which device (or devices) has a fault (TSD = 1).
The usual status data from each device will need to be
examined to determine where a fault (or faults) may exist.
The SO frame is designed to allow TSD status retrieval in
a daisy chain configuration using NCV7723B or other
devices with identical SPI functionality. The TSD status bit
is OR’d with SI and then multiplexed with the device’s usual
status data (Figure 17).
CSB is held high and SI and SCLK are held low by the
master before the start of the SPI frame. TSD status is
immediately available as bit PRE_15 at SO (SO = TSD)
when CSB goes low to begin the frame. The usual status data
(SO = STA) becomes available after the first rising SCLK
edge.
The TSD status automatically propagates through the
chain from the SO output of the previous device to the SI
input of the next. This is shown in Figures 18 and 19, first
without a TSD fault in either device (Figure 18), and then
subsequently with a latched TSD fault (TSD = 1) in device
“A” propagating through to device “B” (Figure 19).
SI
M
U
X
TSD
SO
SO
SI
SPI
SEL
Figure 17. TSD SPI Link
NCV7723B
NCV7726B
MCU
or NCV7723B
1 → 0
CSB
CSB
CSB
0
0
SCLK
MOSI
SCLK
SI
SCLK
Z → 0
Z → 0
MISO
SO
SI
SO
Device A
No TSD
Master
Device B
No TSD
Figure 18. Daisy Chain Without TSD Fault
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16
NCV7723B
NCV7723B
NCV7726B
MCU
or NCV7723B
1 → 0
CSB
CSB
CSB
0
SCLK
MOSI
SCLK
SI
SCLK
SI
0
Z → 1
Z → 1
MISO
SO
SO
Device A
Master
Device B
No TSD
Latched TSD
Figure 19. Daisy Chain With TSD Fault
Power Up/Down Control
applying a logic level signal to pin 17 (PWM1). OUT2 can
be turned on/off using the HBEN2 bit or applying a logic
level signal to pin 18 (PWM2). Simplified logic functions
are shown below in Figure 20.
The V supply input powers the device’s logic core. A
CC
V
CC
power−on reset (POR) function provides controlled
power−up/down. V POR initializes the command input
CC
and status output registers to their default states (0x00), and
ensures that the bridge output and SO drivers maintain Hi−Z
as power is applied. SPI communication and normal device
PWM Example: Turn on OUT1 High Side
To use OUT1 High Side with external PWM control,
perform the following steps:
operation can proceed once V rises above the POR
CC
1. Send command 0b0000000000000010 (0x0002)
♦ Configures OUT1 to High Side (HBCNF1)
♦ Disables OUT1 SPI Enable (HBEN1)
threshold and EN remains high.
The VS1 and VS2 supply inputs power their respective
output drivers (refer to Figure 2 and the PIN FUNCTION
DESCRIPTION). The VSx inputs are monitored to ensure
that the supply stays within the recommended operating
range. If the VSx supply moves into either of the VS
undervoltage or overvoltage regions, the output drivers are
switched to Hi−Z but command and status data is preserved.
Output drivers will remain on if OVLO = 0 during an
overvoltage condition.
2. Apply logic level PWM signal to PWM1
To use OUT1 Low Side with external PWM, set the
HBCNF1 bit to 0 during step 1.
HBCNFx
VS
HSx
LSx
Driver Control
OUTx
HBENx
PWMx
The NCV7723B has the flexibility to control each
half−bridge driver channel via SPI. Actual driver output
state is determined by the command input and the current
fault status bits.
High−side (HSx) and low−side (LSx) drivers of the same
channel cannot be active at the same time, and non−overlap
delays are imposed when switching between HSx and LSx
drivers in the same channel, preventing current
shoot−through.
After the device has powered up and the drivers are
allowed to turn on, the drivers remain on until commanded
off via SPI or until a fault condition occurs.
GND
PWMx
HBENx HBCNFx
HSx
OFF
OFF
ON
LSx
OUTx
0
x
x
1
1
0
1
1
x
x
x
0
1
0
1
OFF
ON
Z
Low
High
Low
High
OFF
ON
OFF
ON
PWM Control
OFF
Outputs 1 and 2 can be controlled in two ways: through
normal SPI control (see Table 1) or from an external PWM
signal. OUT1 can be turned on/off using the HBEN1 bit or
Figure 20. PWM Control Logic
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17
NCV7723B
DIAGNOSTICS, PROTECTIONS, STATUS REPORTING AND RESET
Overview
resolved. Table 4 shows output states during faults and
output recovery modes, and Table 5 shows the status
memory and memory clear modes.
The NCV7723B employs diagnostics designed to prevent
destructive overstress during a fault condition. Diagnostics
are classified as either supervisory or protection functions
(Table 3). Supervisory functions provide status information
about device conditions. Protection functions provide status
information and activate fault management behaviors.
Diagnostics resulting in output shutdown and latched status
may depend on a qualifier and may require user intervention
for output recovery and status memory clear. Diagnostics
resulting in output lockout and non−latched status (VSOV
or VSUV) may recover and clear automatically. Output
configurations can be changed during output lockout.
Outputs assume the new configurations or resume the
previous configurations when an auto−recover fault is
Table 3. DIAGNOSTIC CLASSES AND FUNCTIONS
Name
TSD
Class
Function
Protection
Protection
Protection
Thermal Shutdown
Overcurrent Shutdown
OCS
PSF
Under/overvoltage Lockout
(OVLO = 1)
ULD
HBSTx[1:0]
TW
Protection
Supervisory
Supervisory
Underload Shutdown
Half−Bridge X Output Status
Thermal Warning
Table 4. OUTPUT STATE VS. FAULT AND OUTPUT RECOVERY
Fault
TSD
Qualifier
OUTx State
→ Z
OUTx Recovery
OUTx Recovery Scope
−
Send SRR
All Outputs
All Outputs
All Outputs
−
OCS
−
→ Z
Send SRR
PSF – VSOV
OVLO = 1
OVLO = 0
−
→ Z → Y | Y
Auto*
n
n+1
Unaffected
−
PSF – VSUV
ULD
→ Z → Y | Y
Auto*
All Outputs
All Outputs
−
n
n+1
ULDSC = 1
ULDSC = 0
−
→ Z
Send SRR
Unaffected
Unaffected
−
−
TW
−
*OUTx returns to its previous state (Yn) or new state (Yn+1) if fault is removed.
Table 5. STATUS MEMORY VS. FAULT AND MEMORY CLEAR
Fault
TSD
Qualifier
Status Memory
Latched
Memory Clear
Send SRR
Send SRR
Auto*
Memory Clear Scope
−
−
Global
Global
Global
Global
OCS
Latched
PSF – VSOV
PSF – VSUV
OVLO = X
Non−Latched
Non−Latched
Auto*
−
ULD
TW
ULDSC = X
Latched
Send SRR
Auto*
Global
Global
−
Non−Latched
*Status memory returns to its no−fault state if fault is removed.
Status Information Retrieval
Status Register Reset − SRR
Current status information is retrieved during each SPI
frame. To preserve device configuration and output states,
the previous SI data pattern must be sent during the status
retrieval frame.
Sending SRR = 1 clears status memory and re−activates
faulted outputs for all channels. The previous SI data pattern
must be sent with SRR to preserve device configuration and
output states.
Status information is prevented from being updated
during a SPI frame but new status becomes available after
CSB goes high at the end of the frame provided the frame did
not contain an SRR request. Status information includes
both global and per channel fault notification. To determine
the channel(s) affected after detecting a global fault,
examine driver output status and input configuration.
At the rising edge of CSB, the SRR function is activated
and an internal timer (Tsrr) is started. Tsrr is the minimum
time the user must wait between consecutive SRR requests.
If a fault is still present when SRR is sent, protection will be
re−engaged and shutdown will recur. The status registers can
also be reset by toggling the EN pin or by VCC power−on
reset.
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18
NCV7723B
Diagnostics Details
detection transitions. Undervoltage timing is shown in
Figure 21.
The following sections describe individual diagnostics
and behaviors. In each description and illustration, a SPI
frame is assumed to always be valid and the SI data pattern
sent for HBCNFx and HBENx is the same as the previous
frame. Actual results can depend on asynchronous fault
events and SPI clock frequency and frame rate.
Undervoltage at either VSx input turns off all outputs and
sets the power supply fail (PSF) status bit. The outputs return
to their previously programmed state and the PSF status bit
is cleared when VSx rises above the hysteresis voltage level.
SPI communication is available and programmed output
enable and configuration states are maintained if proper
VCC is present during VSx undervoltage. Output enable and
configuration states can also be programmed during VSx
undervoltage if proper VCC is present, and state changes
will take effect as VSx rises above the undervoltage
threshold level.
Undervoltage Lockout
Global Notification, Global Operation
Undervoltage detection and lockout control is provided
by monitoring the VS1, VS2 and VCC supply inputs.
Undervoltage hysteresis is provided to ensure clean
OUTx
LS
OUTx
LS
OUTx
LS
OUTx
LS
OUTx
HS
OUTx
HS
OUTx
HS
SI
SO
No
Fault
No
Fault
No
Fault
X
PSF
PSF
Z
?
0x00
0x00
No
Fault
No
Fault
Status
No Fault
?
Output
State
ALL
Z
ALL
Z
OUTx GND
OUTx VS
?
OUTx GND
VSx
Vcc
VSUV
VccUV
t
Figure 21. Undervoltage Timing
Overvoltage Lockout
Global Notification, Global Operation
Output enable and configuration states can also be
programmed during an overvoltage lockout event but will
not change state until VSx falls below the overvoltage
threshold level.
Overvoltage detection and lockout control is provided by
monitoring the VS1 and VS2 supply inputs. Hysteresis is
provided to ensure clean detection transitions. Overvoltage
timing is shown in Figure 22. Overvoltage at either VSx
input turns off all outputs if the overvoltage lockout input bit
is set (OVLO = 1) and sets the power supply fail (PSF) status
bit (see Tables 4 and 5). The outputs return to their
previously programmed state and the PSF status bit is
cleared when VSx falls below the hysteresis voltage level.
NOTE: to reduce stress, it is recommended to operate the
device with OVLO bit asserted to ensure that the
drivers turn off during a load dump scenario. If
OVLO = 0 during an overvoltage condition,
outputs will remain on and the PSF status bit will
be set.
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19
NCV7723B
OUTx ON
OVLO = 0
OUTx
ON
OUTx
ON
OUTx ON
OVLO = 1
OUTx
ON
OUTx
OFF
SI
SO
No
Fault
No
Fault
No
Fault
X
?
PSF
PSF
PSF
PSF
No
Fault
No
Fault
No
Fault
No
Fault
Status
Output
State
OUTx
ON
OUTx
ON
ALL
Z
OUTx Z
?
VSOV
VSOV
VSx
t
Figure 22. Overvoltage Timing
Overcurrent Shutdown
global overcurrent (OCS) status bit is set. The channel’s
corresponding HBSTx[1:0] bits are also set to “01” to
indicate an OCS fault. Note that OCS fault reporting has
priority over other faults as shown in Figure 14. The global
OCS bit and individual channel bits are cleared and channels
are re−activated by sending SRR = 1.
Global and per Channel Notification
Per Half−Bridge Operation
Overcurrent detection and shutdown control is provided
by monitoring each HS and LS driver. Overcurrent timing is
shown in Figure 23. Overcurrent in either driver starts a
channel’s overcurrent delay timer (TdOc). If overcurrent
exists after the delay, both drivers are latched off and the
A persistent overcurrent cause should be resolved prior to
re−activation to avoid repetitive stress on the drivers.
OUTx ON
SRR = 0
OUTx
ON
OUTx
ON
OUTx ON
SRR = 1
OUTx
ON
OUTx
ON
SI
SO
No
Fault
No
Fault
No
Fault
OCS
OCS
OCS
OCS
No
Fault
No
Fault
Status
OCS
Output
State
OUTx
ON
OUTx
ON
OUTx Z
OUTx Z
TdOc
TdOc
Output
Current
IsdSxx
t
Figure 23. Overcurrent Timing
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20
NCV7723B
Underload Shutdown
(ULD) status bit is set along with the corresponding per
channel status bits HBSTx[1:0] set to “10”. Drivers will
remain on if the ULDSC input bit is 0 (see Table 4 and 5).
The global ULD bit and per channel HBSTx bits are cleared
and channels are re−activated by sending SRR = 1.
Global and per Channel Notification
Global Shutdown Control, Per Half−Bridge Operation
Underload detection and shutdown control is provided by
monitoring each half bridge driver. Underload timing is
shown in Figure 24. Underload at any driver starts the global
underload delay timer. If underload occurs in another
channel after the global timer has been started, the delay for
any subsequent underload will be the remainder of the timer.
If underload exists after the global delay timer and if the
underload shutdown (ULDSC) command bit is set, both
HSand LS drivers are latched off and the global underload
NOTE: underload may result from a fault (e.g. open−load)
condition or normal circuit behavior (e.g. L/R
tau). In motor applications it is often desirable to
actively brake the motor by turning on both HS or
LS drivers in two half−bridge channels which may
result in an underload condition as current decays.
LSx
ON
LSx ON
LSx
ON
LSx ON
SRR = 1
LSx ON
LSx ON
SRR = 1
SI
SO
ULDSC = 0
ULDSC = 1
No
Fault
No
Fault
No
Fault
ULD
ULD
ULD
ULD
No
Fault
Status
No Fault
No Fault
ULD
Output
State
OUTx
Z
OUTx
ON
OUTx GND
TdUld
IuldLS
OUTx GND
TdUld
TdUld
Output
Current
t
Figure 24. Underload Timing
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21
NCV7723B
Thermal Warning and Thermal Shutdown
Global Notification, Per Half−Bridge Operation
The TW status bit is set when a half−bridge’s sensor
Thermal warning (TW) and thermal shutdown (TSD)
detection and control are provided for each half−bridge by
monitoring the driver pair’s thermal sensor. Thermal
hysteresis is provided for each of the warning and shutdown
functions to ensure clean detection transitions. Software
polling of the TW bit allows for avoidance of thermal
shutdown since TW notification precedes TSD notification.
Thermal warning and shutdown timing is shown in
Figure 25.
temperature exceeds the warning level (T > Twr), and the
bit is automatically cleared when sensor temperature falls
J
below the warning hysteresis level (T < TwHy). A channel’s
J
output state is unaffected by TW.
When sensor temperature exceeds the shutdown level
(T > Tsd), the channel’s HS and LS drivers are latched off,
J
the TW bit is/remains set, and the TSD (PRE_15) bit is set.
The TSD bit is cleared and all affected channels are
re−activated (T < TsdHy) by sending SRR = 1.
J
OUTx
ON
OUTx
ON
OUTx
ON
OUTx
ON
OUTx ON
SRR = 1
OUTx ON
SRR = 1
SI
SO
TSD
TW
No
Fault
No
Fault
TW
TW
TW
TW
TW
TW
No
Fault
No
Fault
TSD
TW
Status
TW
Output
State
OUTx
ON
OUTx Z
OUTx ON
TJ
TSD
TsdHy
TWR
TwHy
t
Figure 25. Thermal Warning and Shutdown Timing
The latched thermal shutdown (TSD) information is
available on SO after CSB transitions from high to low and
before the first rising SCLK edge. The following procedures
must be met for a true TSD reading:
undetermined SPI behavior or/and an incorrect
TSD reading.
2. CSB transitioning from high to low.
3. CSB setup time (TcsbSup) is satisfied and the data
is captured before the first SCLK rising edge.
1. SCLK and SI are low before the CSB cycle.
Violating these conditions will results in an
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22
NCV7723B
THERMAL PERFORMANCE ESTIMATES
Figure 26. Transient R(t) vs. Pulse Time for 2 oz Spreader
ORDERING INFORMATION
Device
†
Package
Shipping
NCV7723DQBR2G
SSOP24 NB EP
2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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23
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SSOP24 NB EP
CASE 940AK
ISSUE O
SCALE 1:1
DATE 24 APR 2012
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
0.20 C A-B
NOTE 4
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
BE 0.10 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE
FOOT. DIMENSION b APPLIES TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.10 TO 0.25
FROM THE LEAD TIP.
NOTE 6
D
L1
A
24
13
2X
H
L2
0.20 C
GAUGE
PLANE
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 PER SIDE. DIMENSION D IS
DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE. DIMENSION E1 IS DETERMINED AT DA-
TUM PLANE H.
E1
E
L
A1
NOTE 5
PIN 1
SEATING
PLANE
DETAIL A
C
NOTE 7
REFERENCE
1
12
0.20 C
e
2X 12 TIPS
24X b
B
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
NOTE 6
M
0.12
C A-B D
7. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
8. CONTOURS OF THE THERMAL PAD ARE UN-
CONTROLLED WITHIN THE REGION DEFINED
BY DIMENSIONS D2 AND E2.
TOP VIEW
DETAIL A
A
A2
h
h
0.10 C
0.10 C
M
MILLIMETERS
DIM MIN
MAX
1.70
0.10
1.65
0.30
0.20
c
A
A1
A2
b
---
0.00
1.10
0.19
0.09
A1
SEATING
PLANE
END VIEW
24X
C
SIDE VIEW
c
M
0.15
C A-B D
D
8.64 BSC
NOTE 8
D2
E
5.28
5.58
D2
6.00 BSC
3.90 BSC
2.44 2.64
0.65 BSC
0.25 0.50
0.40 0.85
1.00 REF
0.25 BSC
E1
E2
e
M
0.15
C A-B
D
h
L
E2
L1
L2
M
NOTE 8
0
8
_
_
GENERIC
MARKING DIAGRAM*
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT
XXXXXXXXXG
AWLYYWW
5.63
XXXX = Specific Device Code
24X
1.15
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
2.84
6.40
(Note: Microdot may be in either location)
1
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
24X
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON79998E
SSOP24 NB EP
PAGE 1 OF 1
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相关型号：
NCV77320DB0R2G
Inductive Position Sensor interface; analog, SPI and SENT output; ISO26262 ASIL B (D); Automotive; Industrial
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