NCV7755DQR2G [ONSEMI]
Octal High-Side Driver that can be controlled via SPI or direct drive inputs. ;
| 型号： | NCV7755DQR2G |
| 厂家： | 
ONSEMI |
| 描述： | Octal High-Side Driver that can be controlled via SPI or direct drive inputs. |
| 文件： | 总46页 (文件大小：477K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Octal High-Side Driver
NCV7755
SSOP24 NB EP
CASE 940AK
The NCV7755 is an automotive grade integrated driver with eight
high−side switches. The device provides drive capability up to
700 mA per channel and is protected for overload and overtemperature
conditions. All the channels have integrated output clamps for
switching inductive loads, multiple start pulses for bulbs, and can be
mapped to two internal PWM generators for LED loads. The output
control and diagnostic reporting is via SPI. Additionally, INx pins can
be mapped to any of the outputs for direct control.
MARKING DIAGRAM
NCV7755G
AWLYYWW
G
A dedicated limp−home mode enables operational control of two
high−side drivers via logic input pins.
The NCV7755 is available in a SSOP−24 exposed pad package for
optimal thermal performance.
NCV7755 = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
• 8 High−Side Channels
WL
YY
WW
G
♦ For Relays (Flyback Clamps)
♦ Bulbs (Multiple Pulse in−rush Scheme)
♦ LEDs (Internal PWM Generator)
♦ 2.3 A Peak Current (Max)
(Note: Microdot may be in either location)
♦ R
0.9 W (Typ), 1.8 W (Max)
DS(on)
ORDERING INFORMATION
♦ Paralleling of Two Output Pair is Allowed
• SPI Control (16 Bit)
Device
Package
Shipping
♦ Frame Error Detection (16 Bits + 8*n Bits)
♦ Daisy Chain Capable
NCV7755DQR2G
SSOP24−EP
(Pb−Free)
2500
Units/Rail
• Two Input Pins with Mapping for PWM Operation
• Low Quiescent Current in Sleep Mode
• Limp Home Mode with Auto−retry
• Supports Cranking Voltage of 3 V Minimum on VS
• 3.3 V & 5 V Compatible Digital Input Supply Range
Applications
• Automotive Body Control Unit
• Automotive Engine Control Unit
• Relay Drive
• Bulb Drive
• LED Drive
• Fault Reporting
♦ Openload (OFF or ON)
♦ Overload
♦ Overtemperature
♦ Power Supply Fail (VS, VDD Undervoltage)
♦ Output Short to GND and Battery
• Reverse Polarity Protection
• Loss of Ground Protection
• Power−on Reset (VDD)
• SSOP−24 with an Exposed Pad
• NCV Prefix for Automotive
♦ Site and Change Control
♦ AEC−Q100 Qualified
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
January, 2022 − Rev. 0
NCV7755/D
NCV7755
Vbat
14V
Cvs
68 nF
Rvdd
100 ohm
Vbat2
Vbat1
VDD
3.3V or 5V
Cvdd
C2bat1
C2bat2
100 nF
C1bat2 C1bat1
100 nF
100 nF 10 mF
10 mF
IN0
LimpHome
VDD
VS
VS1
IN1
LimpHome
Rin0**
4.7k
Lload
IN0
OUT0
OUT2
OUT4
Cout0***
10 nF
Rin1**
4.7k
Lload
IN1
Cout2***
10 nF
Rlh
10 ohm
Ridl*
4.7k
Lload
IDLE
Cout4***
10 nF
Lload
LimpHome
Active
OUT6
Cout6***
10 nF
VS2
Rcsb*
500 ohm
Lload
CSB
OUT1
OUT3
OUT5
OUT7
Cout1***
10 nF
Lload
Rsclk*
500 ohm
SCLK
Cout3***
10 nF
Lload
Rsi*
500 ohm
SI
Cout5***
10 nF
Lload
Rso*
500 ohm
SO
Cout7***
10 nF
GND
*
Required for Reverse Polarity protection.
** Required for Reverse Polarity and Loss of Ground protection.
*** Required for EMC.
Figure 1. Application Diagram
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2
NCV7755
VS2
VS1
4
4
VS
Channels 1,3,5,7
SPI
IN1 (LHI)
OUT3
OUTx programmable
Fault
IN0/IN1 (non−LHI)
4
VS
Channels 0,2,4,6
BIAS and
POR
VDD
Reverse
Battery
Sense
Charge Pump
VS
−
+
SPI
IN0 (LHI)
OUT2
OUTx
programmable
IN0/IN1 (non−LHI)
Control
Logic
OUT0
OUT1
OUT2
SI
SPI Input Logic Block
& Control
SCLK
CSB
OUT3
OUT4
Bulb Inrush Select
Open Load (OFF or ON)
PWM generator Select
Fault
4
Overload
OUT5
OUT6
OUT7
Limp Home Selection
[IN0] OUT2
Overtemperature
Output Short
SO
IN0
IN1
[IN1] OUT3
Enable Auto−retry
High−side Driver
NON−Limp Home INx selection
[IN0] programmable
[IN1] programmable
IDLE
Fault
Limp Home
Reporting
Register
VS
Undervoltage
Lockout
VDD
GND
Figure 2. Block Diagram
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3
NCV7755
PACKAGE PIN DESCRIPTION
SSOP−24
EPAD
Symbol
CSB
SCLK
SI
Description
1
SPI Chip Select “Bar” (120 kW pull−up resistor to VDD)
SPI Clock (120 kW pull−down resistor)
2
3
SPI Serial Data Input (120 kW pull−down resistor)
4
SO
SPI Serial Data Output. Tri−state when CSB is high
5
GND
OUT0
NC
Ground
6
High−side driver output. Requires an external pull−down component for operation
No connection. Internally not bonded
7
8
OUT2
VS1
High−side driver output. Requires an external pull−down component for operation
Power supply input for High−side drivers channels 0, 2, 4, and 6
High−side driver output. Requires an external pull−down component for operation
High−side driver output. Requires an external pull−down component for operation
No connection. Internally not bonded
9
10
11
12
13
14
15
16
17
18
19
20
21
OUT4
OUT6
NC
NC
No connection. Internally not bonded
OUT7
OUT5
VS2
High−side driver output. Requires an external pull−down component for operation
High−side driver output. Requires an external pull−down component for operation
Power supply input for High−side drivers channels 1, 3, 5, and 7
High−side driver output. Requires an external pull−down component for operation
No connection. Internally not bonded
OUT3
NC
OUT1
VS
High−side driver output. Requires an external pull−down component for operation
Power supply input for output power switches gate control
IDLE
High activates low Iq Idle mode (120 kW pull−down resistor)
Low with IN0 = IN1 = low puts device in sleep mode. Low puts all SPI registers in reset
Low with INx = high puts device in limp home mode
22
23
IN1*
IN0*
Input pin 1. Controls channel 3 (default) and in Limp Home Mode (with IDLE = low).
Outputs can be mapped to this pin.
(120 kW pull−down resistor)
Input pin 0. Controls channel 2 (default) and in Limp Home Mode (with IDLE = low).
Outputs can be mapped to this pin.
(120 kW pull−down resistor)
24
VDD
Digital power supply input for SPI and support interface to VS
EPAD
Exposed Pad
Connect to GND for best thermal performance or leave unconnected.
Internally, the EPAD is isolated from the GND signal
*Ground if not used for best EMI performance.
Alternatively keep open and internal pull−down will hold the input low through a 120 kW pull down resistor.
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4
NCV7755
MAXIMUM RATINGS
Rating
Symbol
Min
Max
Unit
Battery supply input voltage (VS)
DC
VsMax
VsacMax
−0.3
−
36
42
V
V
Positive Transient input supply voltage (Note 1)
Battery supply input voltage (VS1, VS2)
DC input supply voltage with short circuit
Positive Transient input supply voltage (Note 1)
VsdcscMax
VsxacMax
0
−
36
42
V
V
Logic Supply Input Voltage (VDD)
DC
VddMax
VoutMax
−0.3
−25
5.5
V
V
Output Voltage (OUTx)
VSx+0.3
Output Current (OUTx)
Specified is the maximum overload detection threshold.
IoutMax
−
2.3
A
Digital I/O pin voltage
(IDLE, IN0, IN1, CSB, SCLK, SI,)
(SO)
VioMax
ViosoMax
−0.3
−0.3
5.5
VDD+0.3V
V
V
Digital I/O input current
(IDLE, IN0, IN1, CSB, SCLK, SI, SO)
IioMax
−10.0
2.0
mA
Clamping Energy
Maximum (single pulse)
(Tj = 25°C, Iout = 440 mA)
(Tj = 150°C, Iout = 400 mA)
Repetitive (multiple pulse)
VclpDc25Max
VclpDc150Max
VclpAcMax
−
−
−
50
25
Note 2
mJ
mJ
mJ
Operating Junction Temperature Range
Storage Temperature Range
Tj
−40
−65
150
150
°C
°C
Tstr
ESD Capability (AEC−Q100−002, AEC−Q100−011)
Human body model (100 pF, 1.5 kW) (VSx, OUTx pins)
Human body model (100 pF, 1.5 kW) (all other pins)
Charged Device Model (corner pins)
Vesd4k
Vesd2k
Vesd750
Vesd500
−4000
−2000
−750
4000
2000
750
V
V
V
V
−500
500
Charged Device Model (all other pins)
AECQ10x−12
AECQ10x
Grade A
−
Short Circuit Reliability Characterization
1. Ton = 400 ms; ton/toff = 10%, 100 pulse limit.
2. 2 M pulses (triangular), VS = 15 V, 63 W, 390 mH, T = 25°C.
A
0.65 mm Pitch
CSB
SCLK
SI
VDD
IN0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
IN1
SO
IDLE
VS
GND
OUT0
NC
OUT1
NC
OUT2
VS1
OUT3
VS2
OUT5
OUT7
NC
9
OUT4
OUT6
NC
10
11
12
Figure 3. Pin−out
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NCV7755
PACKAGE
Moisture Sensitivity Level
MSL
Treflow
R
2
−−
Lead Temperature Soldering: SMD style only, Reflow (Note 3)
Lead – Free Part 60 – 150 sec above 217°C,
40 sec max at peak
265 peak
°C
Package Thermal Resistance and Characterization Parameter
SSOP−24 EPAD
Junction−to−Ambient (Note 4)
Junction−to−pin (exposed pad)
35.1
24.3
°C/W
°C/W
q
JA
Y
JB
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. For additional information, see or download onsemi’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D and
Application Note AND8083/D.
4. Per JEDEC JESD51−7 at natural convection on FR4 2s2p board (76.2 mm x 114.3 mm x 1.5 mm) with 2 inner copper layers.
RECOMMENDED OPERATING CONDITIONS
Value
Min
3.00
7.0*
−−−
−40
Max
5.5
Rating
Digital Supply Input Voltage (VDD)
Battery Supply Input Voltage (VS, VS1, VS2)
Symbol
VDDRec
VSRec
Unit
V
18**
330
150
V
DC Output Current (OUTx), (T = 85°C, all channels)
IoutRec
mA
°C
A
Junction Temperature
T
J
*Extended operation down to 3 V with possible parameter shift. **Extended operation up to 28 V with possible parameter shift.
ELECTRICAL CHARACTERISTICS (−40°C < T < 150°C, 3.0 V < VDD < 5.5 V, 7 V < VS = VS1 = VS2 < 18 V,
J
IDLE = high unless otherwise specified)
Characteristic
VS CURRENTS
Conditions
Symbol
Min
Typ
Max
Unit
Operating Current (VS)
Active Mode
Set to Active Mode via SPI
HWCR.ACT (bit 7) = 1
IDLE = CSB = VDD
SCLK=0V
No Open Circuit Diag Current
7 V < VS < 18 V, IN0 = IN1 = 0
VS < VDD−1 V, IN0 = IN1 = 0
7 V < VS < 18 V, IN0 = IN1 = VDD
VS < VDD−1 V, IN0 = IN1 = VDD
Channels Off
Channels On
VSactOFF1
VSactOFF2
VSactON1
VSactON2
−
−
−
−
−
−
−
7.7
5.0
8.7
5.0
mA
mA
mA
mA
2.3
Operating Current (VS)
Idle Mode
IDLE = CSB = VDD
IN0 = IN1 = SCLK = 0 V
All Channels Off
7 V < VS < 18 V
VS < VDD−1 V
VSidl1
VSidl2
−
−
−
−
2.2
0.3
mA
mA
Operating Current (VS)
Sleep Mode
CSB = VDD
IDLE = IN0 = IN1 = 0 V
T = 85ºC
VSslp85
VSslp150
−
−
0.1
0.1
3
20
mA
mA
J
T = 150ºC
J
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NCV7755
ELECTRICAL CHARACTERISTICS (continued)(−40°C < T < 150°C, 3.0 V < VDD < 5.5 V, 7 V < VS = VS1 = VS2 < 18 V,
J
IDLE = high unless otherwise specified)
Characteristic
VDD CURRENTS
Conditions
Symbol
Min
Typ
Max
Unit
Operating Current (VDD)
Active Mode
Set to Active Mode via SPI
HWCR.ACT (bit 7) = 1
IDLE = CSB = VDD
SCLK = 0 V
No Open Circuit DIAG current
7 V < VS < 18 V, IN0 = IN1 = 0
VS < VDD−1 V, IN0 = IN1 = 0
7 V < VS <18 V, IN0 = IN1 = VDD
VS < VDD−1 V, IN0 = IN1 = VDD
Channels Off
Channels On
VDDactOFF1
VDDactOFF2
VDDactON1
VDDactON2
−
−
−
−
−
−
−
−
0.3
2.7
0.3
3.5
mA
mA
mA
mA
Operating Current (VDD)
Idle Mode
IDLE = CSB = VDD,
IN0 = IN1 = SCLK = 0 V
All Channels Off
7 V < VS < 18 V
VS < VDD−1 V
VDDidl1
VDDidl2
−
−
−
−
0.3
2.2
mA
mA
Operating Current (VDD)
Sleep Mode
CSB = VDD
IDLE = IN0 = IN1 = 0 V
T = 85ºC
VDDslp85
VDDslp150
−
−
0.1
−
2.5
10
mA
mA
J
T = 150ºC
J
TOTAL CURRENTS
Total Sleep Current
(VS + VDD)
CSB=VDD
IDLE=IN0=IN1=0V
Tj=85ºC
Slp85
Slp150
−
−
−
−
5
30
mA
mA
Tj=150ºC
Total Idle Mode
Current Consumption
(VS + VDD)
IDLE=CSB=VDD
IN0=IN1=SCLK=0V
All Channels Off
VSVDDidl
−
−
2.5
mA
Total Active Mode
Current Consumption
(VS + VDD)
Set to Active Mode via SPI
HWCR.ACT (bit 7) = 1
IDLE = CSB = VDD, SCLK = 0 V
All outputs off
All outputs on
Channels Off
Channels On
VSVDDactOFF
VSVDDactON
−
−
−
−
8
9
mA
mA
VS OPERATING RANGE
VS
VS falling
OUTx = ON
RL = 50 W
VSUVLO
VSUVLOhys
VSmin
1.5
−
2.7
1
3.0
−
V
V
V
Undervoltage Shutdown
VS
Undervoltage Shutdown
Hysteresis
VS
VS rising
−
−
4.0
Minimum Operating Voltage
OUTx = ON
RL = 50 W
VDD OPERATING RANGE
VDD
Lower Operating Voltage
VDDLOP
3.0
−
4.5
V
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NCV7755
ELECTRICAL CHARACTERISTICS (continued)(−40°C < T < 150°C, 3.0 V < VDD < 5.5 V, 7 V < VS = VS1 = VS2 < 18 V,
J
IDLE = high unless otherwise specified)
Characteristic
Conditions
Symbol
Min
Typ
Max
Unit
VDD OPERATING RANGE
VDD
VDD falling
VDDUVLO
1.0
2.7
3.0
V
Undervoltage Shutdown
SI = SCLK = CSB = 0 V
SO from low to high impedance
THERMAL PERFORMANCE
Thermal Shutdown
Note 11
Note 11
TSD
150
10
175
25
200
°C
°C
Thermal Hysteresis
TSDhys
−
OUTPUT DRIVER
Output Transistor RDSon
IOUT = 220 mA
T = 25ºC
Rdson25
−
−
0.9
1.6
−
W
W
J
Rdson150
1.8
T = 150ºC
J
Reverse Polarity ON Resistance
VSx = −16 V
IOUT = 220 mA
Tj = 25ºC
Revpol25
Revpol150
−
−
0.9
1.6
−
−
W
W
Tj = 150ºC
Overload Detection Current
st
1
2
threshold (OVL0)
threshold (OVL1)
ILovl0
ILovl1
1.30
0.70
1.80
1.05
2.30
1.30
A
A
nd
Overload Shutdown
Delay Time
Active Mode
tOVLO
4
7
11
ms
including Bulb Inrush Mode
Individual channel operation
BIM.OUTn = HWCR.PAR = 0
B
Output Leakage
VS = VDD = 0 V
VOUT = 0 V
VDS = 28 V
Tj = 85ºC
Leak85
Leak150
−
−
0.01
0.1
0.5
5.0
mA
mA
Tj = 150ºC
Output Current
RL = 50 W
−2.0
−
−
mA
During Loss of Ground
VS = VS1 = VS2
LOG
Drop
Dropout Voltage
RL = 50 W
VS = VS1 = VS2 = 4 V
−
−
1
V
Output Drain/Source Clamp
Output Source/GND Clamp
IL = 20 mA
42
46
−
54
−16
V
VS = VS1 = VS2 = 36 V
clampDS
clampSG
IL = 20 mA
VS = VS1 = VS2 = 7 V
−25
V
MODE DELAY TIMES
IDLE pin going high (50%)
To TER+INST register = 8680
Sleep to Idle Delay
Slp2idl
Slp2lh
−
−
200
300
400
600
ms
ms
H
INx going high
To VDS = 10%VS
Sleep to Limp Home Delay
Idle to Sleep Delay
IDLE pin going low (50%)
To Standard Diagnostics
Idl2slp
−
100
200
ms
clearing = 0000
H
INx going high to MODE = 10
From CSB going high
B
Idl2actINx
Idl2actCSB
−
−
100
100
200
200
ms
ms
Idle to Active Delay
To MODE = 10
B
INx going low
To Standard Diagnostics
clearing = 0000
Limp Home to Sleep Delay
Limp Home to Active Delay
Lh2slp
Lh2act
−
−
200
50
400
100
ms
ms
H
IDLE going high
To MODE=10
B
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NCV7755
ELECTRICAL CHARACTERISTICS (continued)(−40°C < T < 150°C, 3.0 V < VDD < 5.5 V, 7 V < VS = VS1 = VS2 < 18 V,
J
IDLE = high unless otherwise specified)
Characteristic
Conditions
Symbol
Min
Typ
Max
Unit
MODE DELAY TIMES
INx going low to MODE = 11
From CSB going high
Act2idlINx
100
100
200
200
ms
ms
B
Active to Idle Delay
−
To MODE = 11
Act2idlCSB
B
IDLE going low
To TER + INST
register=
Active to Limp Home Delay
Act2lh
−
−
50
50
100
100
ms
ms
8683 (IN0 = VDD, IN1 = VDD)or
H
8682 (IN0 = GND, IN1 = VDD)or
H
8681 (IN0 = VDD, IN1 = GND)
H
IDLE going low
To Standard Diagnostics
clearing = 0000
Active to Sleep Delay
Act2slp
H
Rload = 10K to GND
OUTPUT TIMING SPECIFICATION
Turn On Delay
VS = VS1 = VS2 = 13.5 V, RL = 50 W
Active Mode
INx to 10% VOUT
CSB rising edge to 10% VOUT
tONactINx10
tONactCSB10
1
1
4
4
8
8
ms
ms
Limp Home Mode
Turn Off Delay
INx to 10% VOUT
tONlh10
1
4
8
ms
VS = VS1 = VS2 = 13.5 V, RL = 50 W
Active Mode
INx to 90% VOUT
CSB rising edge to 90% VOUT
tOFFactINx90
tOFFactCSB90
1
1
6
6
12
12
ms
ms
Limp Home Mode
INx to 90% VOUT
tOFFlh90
1
6
12
ms
Turn On / Turn Off Matching
Active Mode
tMatchACT
tMatchLH
−10
−10
0
0
10
10
ms
ms
VS = VS1 = VS2 = 13.5 V,
RL = 50 W
Limp Home Mode
Rise Time
Active Mode
Limp Home Mode
VS = VS1 = VS2 = 13.5 V, RL = 50 W
30% to 70% VS
tRiseAct
tRiselh
2.4
2.4
5.25
5.25
7.7
7.7
ms
ms
Fall Time
Active Mode
Limp Home Mode
VS = VS1 = VS2 = 13.5 V, RL = 50 W
70% to 30% VS
tFallAct
tFalllh
2.8
2.8
5.25
5.25
7.7
7.7
ms
ms
LIMP HOME TIMING
Limp Home Auto−Retry Times
Limp Home Mode 0
tRSTlh0
tRSTlh1
tRSTlh2
tRSTlh3
7
10
20
40
80
13
26
52
ms
ms
ms
ms
Limp Home Mode 1
Limp Home Mode 2
Limp Home Mode 3
14
28
56
104
BULB INRUSH TIMING
Restart Time
Bulb Inrush Mode
tRSTbim
tOVLIN
tBIM
−
110
−
−
40
260
−
ms
ms
Overload Current Switch Threshold
Delay Time
185
40
Reset Time
Bulb Inrush Mode
ms
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NCV7755
ELECTRICAL CHARACTERISTICS (continued)(−40°C < T < 150°C, 3.0 V < VDD < 5.5 V, 7 V < VS = VS1 = VS2 < 18 V,
J
IDLE = high unless otherwise specified)
Characteristic
PWM GENERATOR
Conditions
Symbol
Min
Typ
Max
Unit
Internal Frequency
HWCR_PWM.ADJ = 1000
fINT
80
102
125
15
kHz
%
B
Internal Frequency Variation
between
fVAR
−15
−
Generator 0 and Generator 1
Internal Frequency Synchronization
Time (Note 5)
HWCR_PWM.ADJ = 1000
tSYNC
−
5
10
ms
B
OPEN LOAD OUTPUT STATUS MONITOR
Output Status Monitor
Comparator Settling Time
OpenT
OpenV
−
−
20
ms
Output Status Monitor
Threshold Voltage
3.0
3.3
3.6
V
Output Status Monitor
Diagnostic Source Current
OpenI
25
30
50
100
300
mA
kW
Open Load equivalent resistance
OpenR
−
OPEN LOAD AT ON
Open Load ON
Wait for Diagnostic
(Note 6)
tDIAGwait
6
15
58
35
76
ms
ms
Open Load ON
Waiting Time
tMUXopnON
40
before mux activation (Note 7)
Open Load ON
Settling Time (Note 8)
tSETopnON
tSWTopnON
IopnON
−
−
1
20
10
6
40
20
10
ms
ms
Open Load ON
Channel Switching Time(Note 9)
Open Load ON
Threshold Current
mA
5. Basis in timing requirements for
i) Reset Overload Current Thresholds.
ii) Auto−retry timing reset in limp home mode.
iii) Open Load at ON multiplex operation (but not direct channel diagnostic).
6. Time required to wait before programming for Open Load ON Diagnostic Control.
7. Delay from PWM generator going high to fault recognized in DIAG_OLON.OUT.
8. Delay from Open Load ON Diagnostic Control (with system fault) bit set to fault recognized in DIAG_OLON.OUT.
9. Delay time between Open Load at ON event and to fault recognized in DIAG_OLON.OUT.
DIGITAL INTERFACE CHARACTERISTICS
Characteristic
Conditions
Symbol
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Digital Input Threshold
VthIn
VhysIn
Rpdx
0.8
50
50
1.4
175
120
2.0
300
190
V
(IDLE, IN0, IN1, CSB, SCLK, SI)
Digital Input Hysteresis
(IDLE, IN0, IN1, CSB, SCLK, SI)
mV
kW
Input Pull−down Resistance
(IDLE, IN0, IN1, SI, SCLK)
IDLE = IN0 = IN1 = SI = SCLK =
VDD
Input Pull−up Resistance (CSB)
CSB = 0 V
RpdCSBx
50
120
190
100
kW
mA
CSB Leakage to VDD
CSB = 5 V, VDD = 0 V
IlkgCSBV
−
−
DD
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10
NCV7755
DIGITAL INTERFACE CHARACTERISTICS (continued)
Characteristic
OUTPUT CHARACTERISTICS
SO – Output High
Conditions
Symbol
Min
Typ
Max
Unit
I(out) = 1.5 mA
I(out) = −2.0 mA
VsoH
VDD−
0.4
−
VDD
V
SO – Output Low
VsoL
−
−
−
0.4
1
V
SO Tri−state Leakage
SPI TIMING (VDD = 4.5 V and VS > 7 V)
SCLK Frequency
CSB = VDD, 0 V < SO < VDD
IlkzSOtstate
−1
mA
Fclk
TpClk
−
200
85
−
−
−
−
−
5
−
−
−
−
MHz
ns
SCLK Clock Period
SCLK High Time
TCLKH
TCLKL
TCLKSU1
ns
SCLK Low Time
85
ns
SCLK Setup Time
To CSB going low
Falling SCLK to falling CSB
Falling SCLK to rising CSB
85
ns
SCLK Setup Time
To CSB going high
TCLKSU2
85
−
−
ns
SI Setup Time
SI Hold Time
TISU
50
50
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ms
ns
TIHT
CSB Setup Time
CSB Setup Time
CSB High Time
TCSBSU1
TCSBSU2
TCSBHT
TSOCSBF
100
100
5.0
−
−
−
(Note 10)
−
SO enable
after CSB falling edge
200
SO disable
After CSB rising edge
TSOCSBR
−
−
200
ns
SO Rise Time
SO Fall Time
SO Valid Time
Cload = 40 pF (Note 11)
Cload = 40 pF (Note 11)
TSOrise
TSOfall
TSOV
−
−
−
10
10
50
25
25
ns
ns
ns
Cload 40 pF (Note 11)
SCLK rising 80% to SO 50%
100
10.This is the minimum time the user must wait between SPI commands.
11. Not production tested.
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11
NCV7755
CSB
CSB
Tfall
Trise
OUTx
OUTx
tONactCSB10
tOFFactCSB90
Figure 4. Serial Turn On
Figure 5. Serial Turn Off
INx
INx
High−Side
OUTx
tOFFactINx90
tOFFlh90
tONactINx10
tONlh10
Figure 6. INx Control Turn On
Figure 7. INx Control Turn Off
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12
NCV7755
Figure 8. Serial Peripheral Interface Detailed Timing
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13
NCV7755
TYPICAL PERFORMANCE GRAPHS
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
1.850
1.800
1.750
1.700
1.650
1.600
1.550
1.500
VSx = 18 V
VDD = 5.5 V
−50
0
50
100
150
−50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Open Load On Threshold vs. Temperature
Figure 10. Total Idle Current vs. Temperature
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.800
OVL0
0.750
0.700
0.650
0.600
0.550
0.500
VSx = 18 V
VDD = 5.5 V
OVL1
0.9
0.8
−50 −30 −10 10 30 50 70 90 110 130 150
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Total Sleep Current vs. Temperature
Figure 12. Overload Threshold vs. Temperature
1.8
1.6
1.4
1.2
1
6.25
6.2
VSx = 18 V
6.15
6.1
V
DD
= 5.5 V
VSx = 7.0 V
6.05
6
5.95
5.9
5.85
5.8
0.8
0.6
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
Figure 13. RDS(on) vs. Temperature
Figure 14. Total Active Mode Current
vs. Temperature
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14
NCV7755
DETAILED OPERATING DESCRIPTION
General Overview
internally limited by the maximum overload detection
threshold of 2.3 A (each channel)
• VDD – Digital Supply Input – Internal logic supply
input. Runs from 3.3 V input or 5 V input. The
maximum current drain is 3.5 mA over temperature
The NCV7755 is comprised of eight DMOS high−side
power drivers. There are two connection pins (VS1, VS2)
for the drain of each output driver with 4 common drivers per
pin. Communication to the device is through a 16−bit SPI
port for output control, programming, and fault reporting.
The device also features a limp home mode with an IDLE
control pin for limp home entry and two input control pins
(IN0 & IN1) for output engagement.
It’s important to note the maximum combined current
drain of both VS and VDD is specified at 9 mA with the
channels on.
Output loads can be varied from inductive loads, bulb
loads, or LED loads. Special features for each load type
include output clamps, in−rush design considerations, and
two on−chip PWM generators.
The NCV7755 allows independent mapping of the INx
pins to the outputs and independent mapping of the two
PWM generators to the outputs.
Sleep mode current for VS is 3 mA at 85°C and the
maximum combination of VS+VDD is 5 mA at 85°C.
The exposed pad connection should be connected to
ground with as large a pc board metal connection as possible
for best thermal performance and EMC considerations.
However this is not a ground connection for IC ground
currents.
The device is capable of running down to VS = 3 V for
automotive cranking events.
Load Dump – During a peak transient event such as
automotive load dump the outputs maintain their operation
up to the maximum rating for Positive Transient input
supply voltage of 42 V as programmed via SPI or the input
control pins IN0 and IN1.
Cranking Conditions – Automotive cranking conditions
can cause the battery (aka VS) to dip to low levels. In order
to maintain circuit operation down to the lowest possible
levels the battery connection is OR’d with the logic supply
voltage (VDD). Diodes D1 and D2 provide the OR’d
condition into the voltage regulator. The reduction or
removal of current into D1 from VS will cause the current
into D2 from VDD to increase to keep the voltage regulator
alive. Additional current can also come from SO.
Power Supply
There are four power supply input requirements. The
descriptions of their internal connections are listed below.
• VS − Analog Supply Input – Battery input for all
internal analog circuitry. The maximum current drain is
8.7 mA over temperature
• VS1 – Output Driver Drain connection for OUT0,
OUT2, OUT4, OUT6. The maximum current is
internally limited by the maximum overload detection
threshold of 2.3 A (each channel)
• VS2 − Output Driver Drain connection for OUT1,
OUT3, OUT5, OUT7. The maximum current is
VS1
Charge
Pump
Q1
D1
VS
Gate
Drive
OUT, 0, 2, 4, 6
Voltage
Regulator
Charge
Pump
VS2
D2
VDD
SO
Q2
Power Supply Connections
Gate
Drive
VDD
Undervoltage
Monitor
OUT, 1, 3, 5, 7
SPI
Output Drivers
B1
VS
Undervoltage
Monitor
CSB
Figure 15. Power Supply
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15
NCV7755
Power−Up/Power−Down Control
Sufficient voltage on VS allows for output turn−on.
During cranking conditions as VS dips, the diode OR’d
circuit described in the previous section allows for the IC to
maintain current into the logic solely from VDD. All
channels which are on keep their state during cranking
unless commanded to turn off. Channel turn−on may not be
possible during cranking.
VDD Low Operation Voltage – VDD is monitored and its
status is reported in the Diagnostic Register as bit 13
(LOPVDD). The default value is set to a “1” during power
up and is continuously monitored for the electrical
parameter VDD Lower Operating Voltage (between 3.0 V
and 4.5 V). Because of this threshold, operation for VDD
with a 3.3 V supply will continuously report a “1” in this
register. The LOPVDD bit can only be reset by reading the
Standard Diagnostic Register.
VDD and VS each has their own Power−On reset
monitors which serve to hold off proper operation until
sufficient voltage is present to control the output device. The
device powers up with sufficient voltage on either or both
VDD or VS, and INx or IDLE pin are high. The Standard
Diagnostic Register initially reports both VS Undervoltage
(Monitor) and VDD Lower Operating Range (Monitor).
SPI communication is present with sufficient voltage on
VDD. An undervoltage on VDD resets all the registers to
their default values and no SPI communication is available,
although memory of Overload / Overtemperature conditions
is maintained in ERR of the Standard Diagnostics Register
and can be retrieved when VDD is present. If VS is present
with VDD undervoltage, Limp Home mode control is
possible.
DIAGNOSTIC REGISTER (Default listing after Power−up or Reset)
Field
UVRVS
LOPVDD
MODE
TER
State
Description
There was an undervoltage condition on VS
VDD was previously below 4.5 V
Idle Mode (2 bits)
1
1
11
1
Previous transmission failed
No open load ON detected
No open load OFF detected
No Failure detected
OLON
OLOFF
ERR
0
0
0
INST REGISTER (This is the 1st Register Read back after a Logic Reset)
Field
State
Description
Previous transmission failed.
Input pins are set low
INST
TER = 1
INx = 0
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16
NCV7755
DEFAULT LISTING AFTER LOGIC RESET
Field
Description
OUT
BIM
Output is off
Output latches off with overload
IN0 is mapped to OUT2
MAPIN0
MAPIN1
INST
IN1 is mapped to OUT3
Previous transmission failed.
Input pins are set low
DIAG_IOL
DIAG_OSM
DIAG_OLON
DIAG_OLONEN
HWCR
Diagnostic current is not enabled
Voutx is less than the Output Monitor Threshold
Normal operation
Open Load ON not active
Normal operation, no reset command, no parallel combinations
Normal operation, no latch clear
HWCR_OCL
HWCR_PWM
PWM generator 1 not active.
PWM generator 0 not active
PWM_CR0
PWM_CR1
PWM_OUT
PWM_MAP
Generator 0 Base Frequency Internal clock divided by 1024
Generator 1 Base Frequency Internal clock divided by 1024
The selected output is not driven by a PWM generator
The selected output is connected to PWM Generator 0
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17
NCV7755
Table 1. DEVICE CAPABILITY AS A FUNCTION OF VS AND VDD
VDD < VDDUVLO (Note 15)
VDD = VDDLOP (Note 16)
VDD > VDDLOP (Note 17)
VS < 3.0 V (Note 12)
Channels −
Channels −
Channels −
Cannot be controlled
Cannot be controlled
Cannot be controlled
SPI registers − Reset
SPI registers − Available
SPI registers − Available
SPI communication −
Not available
SPI communication − Possible
(fsclk = 1 MHz)
SPI communication − Possible
(fsclk = 5 MHz)
Limp Home Mode −
Limp Home Mode −
Limp Home Mode −
Not available
Available (channels are off)
Available (channels are off)
3.0 V < VS < VSmin (Note 13)
Channels −
Channels −
Channels −
Cannot be controlled by SPI
Can be controlled by SPI
Can be controlled by SPI
(Rdson deviations possible).
(Rdson deviations possible).
SPI registers − Reset
SPI registers − Available
SPI registers − Available
SPI communication −
Not available
SPI communication − Possible
(fsclk = 1 MHz)
SPI communication − Possible
(fsclk = 5 MHz)
Limp Home Mode − Available
Limp Home Mode − Available
Limp Home Mode − Available
(Rdson deviations possible)
(Rdson deviations possible)
(Rdson deviations possible)
VS > VSmin (Note 14)
Channels −
Channels −
Channels −
Cannot be controlled by SPI
Can be controlled by SPI
Can be controlled by SPI
(Rdson deviations possible).
(Rdson deviations possible).
SPI registers − Reset
SPI registers − Available
SPI registers − Available
SPI communication −
SPI communication − Possible
SPI communication − Possible
Not available
(fsclk = 5 MHz)
(fsclk = 5 MHz)
Limp Home Mode − Available
Limp Home Mode − Available
Limp Home Mode − Available
(Rdson deviations possible
with VS < 7 V)
(Rdson deviations possible
with VS < 7 V)
(Rdson deviations possible
with VS < 7 V)
12.(Undervoltage Shutdown max specification VUVLO = 3 V)
13.VSmin = (Minimum Operating Voltage)
14.VSmin = (Minimum Operating Voltage)
15.VDDUVLO = VDD Undervoltage Shutdown
16.VDDLOP = VDD Lower Operating Voltage
17.VDDLOP = VDD Lower Operating Voltage
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18
NCV7755
Modes of Operation
2. Idle Mode
There are 4 modes of operation. Each is presented in the
state diagram below.
3. Active Mode
4. Limp Home Mode
1. Sleep Mode
VS > 4V
Or
INx = 0
and
&
VDD > 3V
IDLE = 0
Power-up
IDLE = “1”
INx = “0”
Sleep Mode
INx = “1”
IDLE = “0”
OUT0-OUT7 Off
& IDLE = “0”
INx = “0”
INx = “0”
Limp Home
Mode
& VDD < VDD (UV)
Idle Mode
& IDLE = “0”
INx = “0”
& HWCR.ACT = “0”
& OUT.OUTn = “0”
IDLE = “1”
& HWCR_PWM.PWMn = “0”
Active
Mode
INx = “1”
or HWCR.ACT = “1”
INx = “1”
or OUT.OUTn = “1”
& IDLE = “0”
or HWCR_PWM.PWMn = “1”
Figure 16. Modes of Operation
TABLE 2. DEVICE FUNCTION VERSUS VS AND VDD VOLTAGES
VS
VS no
VS no
VS Undervoltage
VDD<VDDUVLO
Undervoltage
Undervoltage
Undervoltage
VDD > VDDUVLO
VDD<VDDUVLO
VDD > VDDUVLO
Operation Mode
Sleep
Function
Channels
Channels not available
no SPI communication
SPI Register Reset
SPI Communication
SPI Registers
Channels
Idle
x
x
x
x
SPI Communication
SPI Registers
Channels
x
reset
Active
(INx pins only)
SPI Communication
SPI Registers
Channels
x
reset
Limp Home
(INx pins only)
x
(INx pins only)
(read only)
SPI Communication
SPI Registers
(read only)
(read only)
reset
(read only)
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19
NCV7755
Power−up
active with a proper logic supply voltage (VDD). Overload
/ Overtemperature bits are not cleared when entering Idle
mode from active mode for safety reasons.
The power−up condition for the NCV7755 is an OR’d
condition between the VS battery input and the VDD logic
input. Either of the supplies exceeding their minimum
operative voltage (4.0 V max for VS) or (3.0 V for VDD)
will initiate the internal power−on sequence. In addition to
these low voltage attributes, the device will maintain its state
with battery voltages down to VS = 3 V such as during
cranking. For SPI communication, the digital power supply
must also be maintained at > 3 V.
Active Mode
The normal operational mode for the device is Active
Mode. The high−side drivers can be activated, loads can be
driven, device output status can be retrieved, and device
attributes can be programmed. The device enters active
mode with any of the following commands.
• IDLE is high and IN0 or IN1 is set to a one
Sleep Mode
• IDLE is high and the Hardware Configuration Register
The NCV7755 enters sleep mode when pins IDLE and
IN0 and IN1 are all low. All outputs are off and all SPI
registers are reset. Operating current is at a minimum (3 mA
max at 85°C).
(HWCR.ACT) is set to a 1 via a SPI command
B
• IDLE is high and the Power Output Control Register
(OUT.OUTn) is set to a 1 for one or more of the
B
outputs via a SPI command
Idle Mode
• IDLE is high and a PWM Configuration Register
(HWCR.PWM.PWMn) is set active via a SPI command
The device enters Idle Mode when the IDLE pin is brought
high with IN0 and IN1 low. All channels are off and Open
Load Diagnostic Current is off. The internal regulator
powers on and SPI registers and communication become
Any transition into Active Mode institutes
a
communication link between IN0, IN1 and OUT2, OUT3.
DIGITAL MODE CHART
MODE
Sleep
IDLE
IN0
0
IN1
0
0
1
1
0
IDLE
0
0
Active*
Limp Home
1
1
and/or
and/or
1
1
*Additionally, Active Mode can be entered via SPI control.
Hardware Configuration Register − HWCR.ACT = 1
Power Output Control Register − OUT.OUT = 1
PWM Configuration Register − HWCR_PWM.PWMn = 1
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20
NCV7755
Limp Home Mode
The NCV7755 incorporates an auto−retry function for
highly capacitive loads in Limp Home Mode. In normal
operation (Active Mode), the device can compensate for
capacitive loads (in case of Overload, Short Circuit or
Overtemperature) with the external microprocessor drive
control time, but when in Limp Home Mode this is not
possible. Attempted tries to turn on an output with a constant
input high control when exposed to Overload (Ilovl0), Short
Circuit or Overtemperature will occur with the following
characteristics.
• 10 ms (8 retries)
• 20 ms (8 retries)
• 40 ms (8 retries)
• 80 ms (continuously)
Only Channel 2 and 3 are controlled (via IN0 and IN1)
during Limp Home Mode. Limp Home mode requires only
VS and VSx for driver turn−on. VDD is not required. The
device enters Limp Home Mode when the IDLE pin is low
and IN0 and/or IN1 are high. When IN0 is high, channel 2
turns on. When IN1 is high, channel 3 turns on. These two
input control pins and corresponding channels are also
active after a power up condition.
SPI communication is active (with VDD>VDDUVLO) in
read−only mode only and reports Overload and
Overtemperature faults, and will also continue to monitor
for Output Status Monitor conditions (on all channels), but
Open Load Diagnostic Current is inactive (on all channels).
When entering Limp Home Mode, the Undervoltage
Monitor (UVRVS) and Lower Operating Range Monitor
It is important to note the 8 counts do not include the initial
turn−on attempt of the device.
A reset to the initial 8 retries at 10 ms can be realized with
a low on the input of 2 times the Internal Frequency
Synchronization Time (typically 2 x 5 ms).
(LOPVDD) bits are set to 1 while the Open Load ON
(OLON) State and Open Load OFF (OLOFF) State are set
B
to 0 . The Transmission Error bit (TER) is set to “1” for the
B
first SPI command which is sent back with the INST register
returned with the first SPI command, and will act normally
afterwards.
tOVLO
7 ms
INx
1
8
1
8
1
8
IOUTx
20 ms
tRSTlh1
(Mode 1)
40 ms
tRSTlh2
(Mode 2)
10 ms
tRSTlh0
(Mode 0)
80 ms
tRSTlh3
*Ilovl0 − This is the higher current threshold used in Active Mode.
Figure 17.
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21
NCV7755
Output Control
The 8 outputs can be controlled via 4 ways which are listed
below.
are set to OUT2 (IN0) and OUT3 (IN1) after
power−up.
3. Limp Home Mode – A low on IDLE will allow
control of OUT2 (IN0) and OUT3 (IN1).
4. PWM Control − A SPI command can connect any
of the outputs to either of 2 PWM generators
whose properties for frequency and duty cycle are
programmable.
1. Output Control via SPI. Commands to turn a
device on are input through the SPI interface.
2. Output Control via IN0 and/or IN1. To activate
this, a SPI command must be sent to map the
control to either IN0 (MAPIN0) or IN1
(MAPIN1). By default, mapping of IN0 and IN1
VSx
IN0
MAPIN0
Activate
OUT2
control
Output
Select
IN1
MAPIN1
OUTx
Activate
IDLE
OUT3
control
0
7
Output
Control
SI
SO
SPI
CSB
}
PWM
generator 0
SCLK
Output
Frequencies
400Hz
200Hz
100Hz
PWM
generator 1
Figure 18. Output Control
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22
NCV7755
OUTPUTS
The 8 outputs of the NCV7755 are designed to work with
multiple types of loads and with the capability of paralleling
two paired channels.
minimum of −25 V. Paired output drivers are permissible
with the use of the paired channel synchronization handling
of overload and overtemperature conditions.
Resistive Loads
Resistive loads are primarily concerned with output
current, switching delays, and slew rates. The NCV7755 has
Bulbs
The NCV7755 is designed to drive 2 W lamps or 5 W
lamps (using two channels in parallel) with its Bulb Inrush
feature. Incandescent bulb in−rush characteristics are
exhibited as a high current event due to the bulb filament
initial low resistance. As the bulb heats up the resistance
increases. Initial high currents could trigger an overload
condition latching off the output. Setting a bit in the Bulb
Inrush Mode register (BIM) allows the device to latch off
(and report ERRn during that time [tRSTbim]) and
automatically restart after the Bulb Inrush Mode Restart
Time of 40 ms (max). Overtemperature conditions can also
trigger a latch off event and auto−restart. The auto−restart
helps to increase the bulb resistance putting the overload
threshold out of range. Bulb Inrush Mode continues until the
bulb is illuminated (not in overload) or the Bulb Inrush
Mode reset time is reached (typically 40 ms). Dual Overload
Detection Current thresholds continue to be valid in Bulb
Inrush Mode.
st
two overload thresholds. The 1 overload threshold is 1.3 A
(min) and has an overload current switch threshold delay
time (tOVLIN) of 110 ms (min) triggered by OUT.OUTn.
Once this delay time has been exceeded, the overload
threshold reduces to 0.7 A (min). Turn−on delay time is 8 us
(max) and turn−off delay time is 12 ms (max). Rise and fall
times are both 2.8Ăms (min).
A turn off time longer than 2 x Internal Frequency
Synchronization Time will reset the overload threshold back
to the 1st level.
Relays
Relay loads are supported using an internal inductive
clamp on the output driver to protect the driver. The negative
transients seen when turning off an inductive load are
internally limited on the output drivers with a clamp voltage
INn
OUT.OUTn
t
ILn
ILovl0
1.8A [typ]
ILovl1
1.05 A [typ]
tOVLO
tOVLO
7 ms [typ]
7 ms [typ]
t
tRSTbim
tOVLIN
tRSTbim
40us [max]
185 ms [typ]
BIM Continues for tBIM (40ms) [typ] provided OUT.OUTn=1 or bulb is illuminated.
Figure 19. Bulb In−rush Mode
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23
NCV7755
Output Clamping
Internal protection is provided for the output drivers for
the maximum drain to source voltage and the absolute
maximum voltage from the output to negative voltages
which occurs on OUTx when inductive loads are turned off.
Protection for Q1 drain to source is provided by D1, D2,
and Rgs.
Protection for negative clamp voltages is provided by
Rgs, D3, and D4.
VSx
VSx
D1
D1
VS
VS
High
Current
Path
High
Current
Path
D2
D2
Q1
Q1
D5
D5
Rgs
Rgs
OUTx
OUTx
D3
D4
D3
D4
Zener
Breakdown
Path
Zener
Breakdown
Path
Load
Load
(refi clampSG)
(refi clampDS)
GND
GND
NCV7755
NCV7755
Figure 20. Output Clamp (Normal Operation)
Figure 21. Output Clamp (at High Voltage)
Outputs in Parallel
The NCV7755 was designed for operation with the
capability to parallel some of the outputs for increased
current handling for an individual load. This is not
recommended for most other integrated circuits due to the
asynchronous turn−off of paralleled outputs causing undo
stress to the last channel on. The channels in the list below
are allowed to run in parallel by programming the Hardware
Configuration Register (HWCR.PAR) which can deactivate
both channels synchronously during an overload or
overtemperature event.
Please note during Limp Home Mode only Channel 2 and
Channel 3 are active. Because a parallel combination of
channels 2 and 3 is not allowed, there is no provision for
parallel outputs during Limp Home Mode.
Parallel Combination
HWCR.PAR
Bit address
Channel Number
Channel Number
0
1
4
5
2
3
6
7
0
1
2
3
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24
NCV7755
Fault Detection
lower IC temperature levels during any shorted events while
still providing proper operation.
Overload
This multi−level threshold strategy is implemented
whenever the driver is active on. When operating in
Bulb−Inrush mode (BIM), the auto−restart feature will also
be active.
Overload detection conditions are latched off and require
a SPI command to reactivate the effected output.
Two overload current thresholds (ILovl0 & ILovl1)
triggered by a turn−on command support the designer in
driving highly capacitive loads. A higher initial current
threshold (ILovl0) ignores potential in−rush events caused
nd
by high capacitance. The 2 level supports maintenance of
INn
OUT.OUTn
t
ILovl
ILovl0
ILovl1
tovln
t
Figure 22.
Thermal Shutdown − Individual thermal sensors are
provided for each channel. A breach of the thermal
shutdown threshold will latch the channel off and set the
diagnostic bit ERRn for the channel. Clearing the error bit
is done by setting the corresponding HWCR_OCL.OUTn
bit to “1”. HWCR_OCL.OUTn is cleared after the error bit
is cleared and the channel will accept commands to turn on.
During Bulb Inrush Mode, the output is “latched” off
when the thermal threshold is breached, and will
auto−restart once the thermal sensor no longer detects a
fault.
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25
NCV7755
FAULT REPORTING
ERRn, Overload & Overtemperature
cleared after the error bit is cleared and the channel will
accept commands to turn on.
Short to Ground
–
Overload conditions or
Overtemperature conditions latch off the affected channel
and the diagnostic bit ERRn is set. Reactivation must be via
the SPI commands in normal operation using
HWCR_OCL.OUTn. The logic inputs will not reset the
latch. Limp Home Mode however utilizes an output restart
time.
After a breach of the ILovl0 or Ilovl1 level the channel is
latched off and an error diagnostic bit is set (ERRn).
Clearing the error bit is done by setting the corresponding
HWCR_OCL.OUTn bit to “1”. HWCR_OCL.OUTn is
Short to Battery – An output shorted to battery will be
detected with the Open Load output off circuitry. When the
device is off, the expectation is for the load to hold the output
pin low. If a short to battery exists, the pin will be pulled high
and an open circuit will be reported.
………………………………………………………………………………………………….
• OverLoad – Reference the Fault Detection section
• Open Load – Reference the Fault Detection section
• Thermal Shutdown – Reference the Fault Detection
section
VS
VSx
Charge Pump
OpenI
VBAT
50 mA
Open Load
current
source
control
Output Turn−
on Control
Channel x
+
OUTx
GND
−
Roc
Output Status
(DIAG_OSM)
Comparator1
OpenV = Open Load Detection Threshold Voltage
OpenV
3.3V
OpenI = Open Load Detection Source Current
Lload
Figure 23. Open Load at OFF
Open Load at OFF
Open Load
Open Load diagnostics are active for an open load in the
on state or open load in the off state.
On State – Open load at on is detected if the output current
is less than 6 mA (typ) and 10 mA over the temperature
range.
Off State – Utilizes an internal current source for detection
and is reported as a state condition in the Output Status
Monitor. The output with a load present in the off state
should be low. If the OpenI current source pulls OUTX high
when enabled by DIAG_IOL.OUTn, an open circuit
condition is reported.
Open load detection is often a system requirement for
reporting a malfunction to the host controller. Board level
deviations such as dendrites between traces can effect this
measurement. A dendrite between the output pin and ground
will reference a voltage into the Output Status Voltage
Threshold Monitor from the Output Status Monitor
diagnostic Source Current during an open load off
diagnostic event (with an open load) from the dendrite
impedance.
An impedance range is established with the extremes of
the threshold voltage (OpenV) and the current source
(OpenI) to eliminate false opens or failure to report an open.
3.0 V
100 mA
3.6 V
25 mA
OpenV
OpenI
Open Load Impedance +
Impedance min +
+ 30 kW Impedance max +
+ 144 kW
Open Loads will be detected between the 30 kW and
144 kW range.
Acceptable loads will be < 30 kW.
Acceptable impedances between printed circuit board
traces will be > 144 kW.
In normal operation, when OpenI is active, the current is
low and should not be high enough to trip an open circuit
flag. OUTx should be held close to ground via Roc + Lload.
If Roc + Lload are missing, OpenI will pull OUTx above the
OpenV threshold and signal an open load.
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26
NCV7755
Open Load at ON
each channel diagnostic. Value 1111 (default) is set back in
B
Open Load at ON is controlled by the
DIAG_OLONEN.MUX bits in the DIAG_OLONEN
register. The default setting after reset is not active.
DIAG_OLON.OUTn is set and mirrored into the Standard
Diagnostic (bit OLON) if the output current is less than the
Open Load ON Threshold Current. This is synonymous to
an under load condition.
DIAG_OLONEN.MUX can be commanded on for a
direct channel diagnostic or a diagnostic loop. Direct
Channel diagnostic uses direct drive and is defined as control
via SPI (Power output control register or control is mapped
to IN0 (MAPIN0.outn) or IN1 (MAPIN1.outn). Diagnostic
loop is programmed via SPI to the DIAG_OLONEN register
DIAG_OLONEN after the last channel is evaluated.
Direct Channel Diagnostic
For Direct Channel Diagnostic, the device requires:
1. Time for the Internal Frequency Sync
(10 ms [max]) (t
)
SYNC
2. Time for the output to turn on (tDIAGwait)
(35 ms [max]). (t
)
DIAGwait
Open Load Monitor is now active.
3. Programming time for Open Load ON Diagnostic
Control (DIAG_OLONEN.mux).
(Time not specified here as this involves external
control times)
4. Once step #3 is performed some Settling Time
(tSETopnON) is required for the Open Load at ON
Monitor (DIAG_OLON.OUT) to be available
(DIAG_OLONEN.MUX = 1010 ).
B
When operating in a direct channel mode, a detected open
load will set the corresponding DIAG_OLON.OUTn bit and
reset all the other bits in the DIAG_OLON register. Bits are
updated upon register reading.
(40 ms [max] (t
)
SETopnON
Once available, an Open Load at ON corresponding to a
channel in the Open Load at ON Diagnostic Control Register
(DIAG_OLONEN.MUX) will be reported upon request.
Only one channel is available at a time. All other channels
will report “0”.
For operation in a diagnostic loop, DIAG_OLEN.MUX
should be programmed with the value 1010 . All channels
B
are checked for Open Load at ON when operating in this
mode. DIAG_OLON.OUTn is updated upon completion of
Program Time for Open Load
ON Diagnostic Control
→
≠ 1111
1111
Iout
DIAG_OLONEN.MUX
1
0/1
DIAG.OLON.OUTn
DIAG.OLON.OUTn
40 ms [max]
45 ms [max]
+ t
(t
)
SETopnON
(t
SYNC
)
DIAGwait
Figure 24. Direct Channel Time for Monitor Active
Figure 25. Open Load ON Diagnostic Control
Settling Time
When operated with the output previously commanded
on, the time delay from fault occurrence to report in the
register is the Open Load ON Channel Switching Time
(20 ms [max]) (t
).
SWTopnON
Iout
1
0
0
0
DIAG.OLON.OUTn
20 ms [max]
(t
)
SWTopnON
Figure 26. Direct Channel Event Delay Time
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27
NCV7755
Diagnostic Loop
A diagnostic loop systematically tests all channels for
off channels set to “0” after diagnostic.
st
Open Load at ON when 1010 is programmed into the Open
The timing for completion of the 1 diagnostic is
B
Load at ON diagnostic control (DIAG.OLONEN.MUX).
1. Direct Channels are tested first.
different than the rest. This includes the internal
synchronization time (t ) and the Settling
SYNC
Channels are checked in numerical sequence with
Time (t ) (50 ms [max])
SETopnON
1010
1010
DIAG_OLONEN.MUX
DIAG.OLON.OUTn
DIAG_OLONEN.MUX
1
1
0
0
0
DIAG.OLON.OUTn
30 ms [max]
50 ms [max]
(t
+ t
)
SYNC
SWTopnON
(t
+ t
SETopnON
)
SYNC
st
Y−axis – End of 1 channel completion
Figure 27. First Direct Channel Diagnostic
Completion Timing
Figure 28. Subsequent Channel Loop Delay Times
st
st
Subsequent delay times after the 1 diagnostic are
The timing for completion of the 1 diagnostic is
triggered by the internal synchronization time (t
) plus
triggered by the channel activation ON state from the PWM
Generator. Timing includes Settling Time for the trigger
SYNC
the Channel Switching Time (t
) (30 ms [max]).
SWTopnON
This sequence is repeated until all channel are evaluated.
event (t ) (40 ms [max]) plus any possible OFF state
SETopnON
programmed by the user in the PWM generator (tPWM) as
a low duty cycle event.
Once the PWM generator goes high there is a time delay
2. Channels configured for PWM operation are tested
second with PWM Generator 0 tested first
followed by PWM Generator 1
for Waiting Time before mux activation (t
[max]) plus Channel Switching Time (t
[max]).
) (76 ms
) (20 ms
MUXopnON
SWTopnON
1010
1010
DIAG_OLONEN.MUX
DIAG_OLONEN.MUX
1
1
0
PWM Generator
PWM Generator
1
1
0
0
0
DIAG.OLON.OUTn
DIAG.OLON.OUTn
tPWM
96 ms [max]
(t + t
20 ms [max]
(t
)
)
MUXopnON
SWTopnON
SWTopnON
Y−axis – End of 1st channel diagnostic.
diagnostic takes place provided the PWM generator is in the high state.
Y−axis – End of Direct Channel diagnostic
tPWM = a low state in the PWM generator
programmed by the user as a duty cycle
Figure 29. First MUX Channel diagnostic
Completion Timing
Figure 30. Subsequent Channel Delay Times
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28
NCV7755
Channel Switching Delays (t
) (20 ms [max]) are
minimum on time for a reliable diagnosis. Operation at low
duty cycle in PWM mode may not meet this requirement.
The user must insure the minimum on time is met for an
accurate Open Load at ON reading.
SWTopnON
linked to all the subsequent channel diagnostic for Open
Load at ON. The PWM Generator must be in its high state
for diagnostic.
A channel in its off state must wait as per the first channel
diagnostic which includes the delay for Waiting Time before
If subsequent channels do not have the PWM generator
high, the 1 mux Channel diagnostic Completion Timing
st
applies.
mux activation (t
) (76 ms [max]) plus Channel
MUXopnON
Switching Time (t
) (20 ms [max]). This is the
SWTopnON
Table 3. OLON BIT IN THE STANDARD DIAGNOSTICS REGISTER
DIAG_OLON.MUX
OLON Bit Description
0000 ³ 0111
Displays the Open Load at ON status for requested channel.
“OR” combination of all bits in the DIAG_OLON register while loop is running.
Show the latest diagnostic results
B
B
1010
B
1111
B
Reserved – Should not be used.
OLON Bit will set to “0”.
1000 , 1001 , 1011 , 1100 , 1101 , 1100
B
B
B
B
B
B
FAULT HANDLING CHART
Driver Condition
after Parameters within
Specified Limits
Driver Condition
during Fault
Fault
Reporting
Fault
Output Register Clearing Requirements
Overload
Channel
Latch Off
OUTn is off
ERRn is set
SPI clearing with
HWCR_OCL.OUTn. Set to “1”.
After cleared, the output will immediately turn
on if OUT.OUTn = 1
Overload
(BIM Mode)
Autorestart
for 40 ms
Normal Operation
ERRn is
reported
periodically in
Bulb In−Rush
restart time
No register reporting if bulb starts
within 40 ms.
Else wise reference “Overload” Fault
Open Load
Off State
Per setting
Per setting
Normal Operation
OLOFF is set
DIAG_OSM is
set
Load re−connected.
or transition
to the ON state.
Open Load
On State
Normal Operation
OUTn is off.
OLON is set
ERRn is set
Load re−connected.
Thermal
Shutdown
Channel
Latch Off
SPI clearing with
HWCR_OCL.OUTn. Set to “1”.
After cleared, the output will immediately turn
on if OUT.OUTn = 1.
VS
With VDD =
Undervoltage
outputs are off
All Outputs off
UVRVS is set
UVRVS is set
Reading the Standard Diagnostic Register
Undervoltage
With VDD >
Undervoltage
outputs are per
setting
Outputs per setting
Reading the Standard Diagnostic Register
VDD Low Oper-
ating Voltage
Per setting
Per setting
LOPVDD is
set
Reading the Standard Diagnostic Register
Transmission
Error
Previous state
Per command
TER is set
CSB low until 1st low−to−high transition on
SCLK
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29
NCV7755
Reverse Protection
Thermal Shutdown with VS Powered
In reverse polarity (OUTx > VSx), each channel will be
on at nearly the forward Rdson for both VS operational
(Figure 31 when commanded on) and at ground (Figure 32)
or will conduct through the body diode (Figure 31 when
commanded off).
A thermal shutdown event will be sensed whenever VS is
powered and set the appropriate ERRn bit during inverse
current. The IC will control (turn off) the output transistor
during thermal shutdown as the gate drive is active with VS
powered. The system effect will be the output transistor will
conduct at nearly the forward Rdson (when commanded on)
or the output will conduct through the body diode between
OUTx and VSx (when commanded off) prior to a thermal
shutdown event. When a thermal event is sensed, the output
transistor will be commanded off and the output will conduct
through the body diode of the output transistor.
VS Powered
Parametric deviations, but no functional deviations of
unaffected channels are possible during the reverse polarity
event with VS Powered.
The reverse polarity channel stays in the ON (output =
Rdson) or OFF (output = body diode) state as programmed
before reverse polarity with VS powered (Figure 31). ON /
OFF state (Rdson or body diode) is still programmable while
in reverse polarity. Current in the output channels is limited
by only the external loads. Limiting for VDD and logic pins
(IDLE, IN0, IN1, CSB, SCLK, SI, SO) require their own
external protection (external series resistors) typically
100 ohms for VDD, 500 ohms for the SPI pins (CSB, SCLK,
SI, SO), 4.7 kohms for IN0 & IN1, and (4.7 kohms +
10 ohms) for IDLE in the application.
Overcurrent with VS Powered
Overcurrent is not active during inverse current with VS
powered.
VS at Ground
In reverse polarity with VS also at ground, (Figure 32) the
device will automatically sense the condition and turn on
with Rdson comparable to the forward Rdson characteristic.
No on/off control is present. There is no other IC
functionality with VS at ground including thermal shutdown
or overload.
REVERSE PROTECTION TABLE
Protection
Mechanism
(thermal shutdown)
Protection
Mechanism
(overload detection)
ON / OFF Control*
(Rdson or body diode)
Output Transistor
State
Thermal Shutdown
Detection ERR bit
VS
Powered
yes
As commanded
(Rdson or body diode)
yes
yes
no
Ground
no
Rdson
no
no
no
* with sufficient VS voltage
Overcurrent with VS at Ground
Overcurrent is not active during inverse current with VS at Ground.
VS
VSx
VS
VSx
Reverse
Battery
Sense
Reverse
Battery
Sense
−
−
+
+
Output
Select
Output
Select
OUTx
OUTx
Zload
GND
Zload
GND
Thermal Shutdown
Detection
ERR bit setting
Figure 31. Reverse Polarity Control
Figure 32. Reverse Polarity Turn−On
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30
NCV7755
Loss of Ground
be monitored to display the logic level of the input pins (also
in limp home mode) provided VDD is present. IN0 and IN1
can be controlled with or without VDD present making this
ideal for Limp Home applications.
All channels are guaranteed off during a loss of ground
event to insure unwanted activation of external loads with a
missing ground connection to the module. Output Current is
tested to be less than 2 mA during a loss of ground event.
PWM Control
Logic Inputs
In addition to the two input pins (IN0 and IN1) which
provide the capability for PWM control, the NCV7755 also
includes two internal independent PWM generators which
can be assigned to one or more channels.
The duty cycle and frequency of the internal PWM
generators can be adjusted with the PWM Configuration
Register (HWCR.PWM, PWM.CR0, and PWM.CR1). The
base frequency can be adjusted (−35%, +35%) from the Base
Frequency of 102 kHz. The Duty Cycle is adjusted with the
PWM Generator 0/1 Configuration Register (with 0.39%
resolution) and has 4 options, 100% duty cycle, Base
IN0 and IN1 provide logic input control for the outputs for
both normal mode and Limp Home Mode. Control is
maintained with or without the digital supply input voltage.
The NCV7755 mapping function allows for input control for
any single output or any multiple outputs. A single output
can be controlled by both IN0 and IN1 as an OR’d condition.
Mapping
There are two mapping functions allowed in the
NCV7755. The first is for mapping of IN0 and IN1 to any
assigned outputs. The second is for mapping the two PWM
generators to any assigned outputs.
Frequency/256 (corresponding
Frequency/512 (corresponding
f
f
=
=
400 Hz), Base
200 Hz), Base
Frequency/1024 (corresponding f = 100 Hz).
The PWM generator will complete a cycle if commanded
to change via the SPI.
Mapping of IN0 and IN1
IN0 and IN1 are designed to control two outputs (by
default) when in Limp Home Mode (or after POR). IN0
controls channel 2 and IN1 controls channel 3 as an OR’d
function between the INx controls, the OUT register and the
PWM Generator. The mapping function of the NCV7755
allows connection to other outputs as well as to assign
multiple outputs to the same input pin in active mode. The
two mapping registers (MAPIN0 & MAPIN1) allow the
flexibility for this. The Status Monitor Register (INST) can
Mapping the PWM Generators
Channel mapping of the PWM generator is accomplished
via the PWM mapping registers (PWM_OUT and
PWM_MAP). PWM_OUT selects which outputs are to be
driven by the PWM generator. PWM_MAP selects which of
the two generators is connected to the outputs which are to
be driven by the PWM generator.
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31
NCV7755
Daisy Chain
Serial Connection
The NCV7755 is capable of being daisy chain connected
using the SPI connectivity. While the NCV7755 is a 16−bit
device, it can be coupled with other 8−bit SPI devices. It is
important to note compatible SPI devices must clock data in
on the negative edge of the clock. Reference the SPI
diagram.
Daisy chain setups are possible with the NCV7755. The
serial setup shown in Figure 33 highlights the NCV7755
along with any 16 bit device using a similar SPI protocol.
Particular attention should be focused on the fact that the
first 16 bits which are clocked out of the SO pin when the
CSB pin transitions from a high to a low will be as per the
SPI Protocol table. Additional programming bits should be
clocked in which follow this. The timing diagram shows a
typical transfer of data from the microprocessor to the SPI
connected IC’s.
CSB SCLK
CSB SCLK
IC3
CSB SCLK
IC2
CSB SCLK
IC1
IC4
NCV7755
Any IC using
16 Bit SPI
protocol
Any IC using
16 Bit SPI
protocol
Any IC using
16 Bit SPI
protocol
SO
SO
SO
SO
SI
SI
SI
SI
Figure 33. Serial Daisy Chain
CSB
SCLK
SI
1st CMD
2nd CMD
3rd CMD
4th CMD
Figure 34. Serial Daisy Chain Timing Diagram
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32
NCV7755
Table 4. SERIAL DAISY CHAIN DATA PATTERN
CLK = 16 bits
CLK = 32 bits
CLK = 48 bits
CLK = 64 bits
st
nd
rd
th
IC4
1
CMD
2
1
CMD
CMD
3
CMD
CMD
CMD
4
3
CMD
CMD
CMD
CMD
st
nd
rd
IC3
IC2
IC4 DIAG
IC3 DIAG
IC2 DIAG
IC1 DIAG
2
st
nd
IC4 DIAG
IC3 DIAG
IC2 DIAG
1
2
st
IC1
IC4 DIAG
IC3 DIAG
1
microprocessor
IC4 DIAG
8−bit Devices
Table 4 refers to the transition of data over time of the
Serial Daisy Chain setup of Figure 33 as word bits are shifted
through the system. 64 bits are needed for complete
transport of data in the example system. Each column of the
table displays the status after transmittal of each word (in 16
bit increments) and the location of each word packet along
the way.
The NCV7755 is also compatible with 8 bit devices due
to the features of the frame detection circuitry. The internal
bit counter of the NCV7755 starts counting clock pulses
when CSB goes low. The 1st valid word consists of 16 bits
and each subsequent word must be comprised of just 8−bits
(reference the Frame Detection Section).
CSB SCLK
IC1
CSB SCLK
The NCV7755 is
IC2
also compatible
with 8−bit devices
NCV7755
Any IC using
8 Bit SPI
protocol
SO
SO
SI
SI
NOTE: Compatibility Note the SCLK timing requirements of the NCV7755. Data is sampled from SI on the falling edge of SCLK.
Data is shifted out of SO on the rising edge of SCLK. Devices with similar characteristics are required for operation in a daisy
chain setup.
Figure 35. Serial Daisy Chain with 8−bit Devices
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33
NCV7755
Input Parallel Connection of ICs in a Daisy Chain
Configuration
device in the serial string must first pass through all the
previous devices. The parallel control setup eliminates that
requirement, but at the cost of additional control pins from
the microprocessor for each individual CSB (chip select bar)
pin for each controllable device. Serial data is only
recognized by the device that is activated through its
respective CSB pin. The Figure below shows the waveforms
for typical operation when addressing IC1.
A more efficient way (time focused) to control multiple
SPI compatible devices is to connect them in a parallel
fashion and allow each device to be controlled in a multiplex
mode. The Figure below shows a typical connection
between the microprocessor or microcontroller and multiple
SPI compatible devices. In
a serial daisy chain
configuration, the programming information for the last
NCV7755
CSB1
CSB2
IC1
SI
SI
SCLK
SCLK
CSB
SO
OUT0
OUT7
SO
CSB
chip1
NCV7755
IC2
SI
CSB
SCLK
CSB
SO
chip2
CSB3
SCLK
SI
OUT0
OUT7
CSB
chip3
NCV7755
SI
SCLK
CSB
SO
OUT0
OUT7
Figure 36.
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34
NCV7755
SPI Communication
The SPI protocol works in conjunction with the 4 SPI pins,
CSB, SCLK, SI, & SO.
pin) data is shifted in first. The Register Structure is
composed of address and data bits with read/write
designators
• CSB – Chip Select Bar
• SO – Serial output pin. The Diagnostics Register is
clocked out of SO at the same time SI is input into the
SI pin. The exception here is when operating in a daisy
chain configuration when the 16−bit word clocked out
the intended data for the next serial device
A high to low transition signals the IC that data is about
to be clocked into the IC. Data is then clocked in via the
SCLK and SI pins. Data completion is signaled by a
low to high transition on the CSB pin
• SCLK – Serial clock input pin. Data bits from SI are
shifted into the IC on the falling edge of SCLK. Data
bits are shifted out of SO at the same time data bits are
shifted into the IC. SCLK must be low when CSB
makes a transition
SPI Diagnostics
All 16 bit words from the SPI Diagnostics are read only
bits. The SPI Diagnostics are returned following a received
command.
• SI – Serial input pin. Data is shifted into the IC via the
SI pin with the SCLK pin. The MSB (most significant
CSB
MSB
LSB
B0
B14
B14
B13
B13
B12
B11
B10
B9
B8
B7
B7
B6
B6
B5
B5
B4
B3
B3
B2
B1
B1
SI
B15
B15
SCLK
SO
B12
B11
B10
B9
B8
B4
B2
TER
B0
Figure 37. Serial Peripheral Interface
The timing diagram highlighted above shows the SPI
interface communication.
1. There was a transmission error in the previous
frame
TER information retrieval is as simple as bringing CSB
high−to−low. No clock signals are required although SI must
be low when reading TER.
a. The response is the Standard diagnostic with
the TER
2. Coming out of VDD POR.
a. The response is the INST register with the
TER (8680h)
NOTES:
1. The MSB (most significant bit) is the first
transmitted bit
2. Data is sampled from SI on the falling edge of
3. There is a syntax error.
a. The response to “11” MSB is the Standard
diagnostic
b. The response to “00” MSB is the Standard
diagnostic
c. The response to “reserved” or “not used”
registers is the Standard diagnostic.
SCLK
3. Data is shifted out from SO on the rising edge of
SCLK
4. SCLK should be in a low state when CSB makes a
transition
5. SI should be in a low state during TER retrieval
time
reference the
Register Structure for 2 bit designators
write commands = “10” MSB
read commands = “01” MSB
SPI Operation
SPI operation works by sending the previous response
frame back when a new frame has been clocked in unless
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35
NCV7755
SPI PROTOCOL
SI
SO
Communication
Frame A
Frame B
Frame C
Previous response
Response to Frame A
Response to Frame B
Register Content Sent back to
the microprocessor
Write Register A
Previous response
Read Register A
New command
Standard Diagnostic
Register A content
Response after a transmission error
Frame A
Previous response
(error in transmission)
New command
Standard Diagnostic +TER
Response with VDD < POR
Response after VDD POR
Frame A
Frame B
SO = hi impedance
INST Register +TER
(8680h)
Frame C
Response to Frame B
Response after Command Syntax or
addressing Error
Frame A
(error)
Previous Response
Standard Diagnostic
New command
SPI Register Reset
SCLK edge in the INST register, and the Standard
Diagnostics Register.
In addition to unqualified bit counts setting TER = 1, the
bit will also be set by
The following will reset the SPI registers.
Device transitions to Sleep Mode.
This includes both of the conditions:
a. INx and IDLE are all = “0”
1. Coming out of UVLO for VDD
2. Transitioning from Limp Home Mode to Active
Mode
b. Both VDD and VS are in undervoltage
NOTE: Execution of a reset command (HWCR.RST =
“1”) will clear (turn off) the outputs, but the
3. Transitioning from Sleep Mode to Idle Mode
The TER bit is cleared by sending any valid SPI
command.
ERR bits will not be cleared for safety reasons.
Frame Detection Transmission Error (TER)
The TER bit is multiplexed with the SPI SO data and OR’d
with the SI input to allow for reporting in a serial daisy chain
configuration. A TER error bit as a “1” automatically
propagates through the serial daisy chain circuitry from the
SO output of one device to the SI input of the next.
The NCV7755 detects the number of bits transmitted after
CSB goes low for verification of word integrity. Bit counts
not a multiple of 8 (16 bit minimum) are reported as a fault
on the TER bit. The transmission error information (TER)
is available on SO after CSB goes low until the first rising
www.onsemi.com
36
NCV7755
Frame detection mode ends with CSB
rising edge.
Frame detection starts
after the CSB falling edge
and the SCLK rising edge.
CSB
SCLK
B15
B14
B13
B12
4
B11
B10
B9
B8
B7
9
B6
B5
B4
B3
B2
B1
B0
SI
Internal Counter
1
2
3
5
6
7
8
10
11
12
13
14
15
16
Valid 16 bits shown
Figure 38. Frame Detection
TER False Reporting
demonstrates what could happen if SI is a one during TER
status retrieval. In this situation a “1” on SI propagates to SO
regardless of the state of TER. Hence a transmission error
(TER) could be reported when it is not true.
SI should be in a low state during TER status retrieval
(from CSB going low to the 1strising edge of the clock pulse)
reporting the previous transmission status. Figure 39
SI
TER
SO
S
SI
SPI
TER SPI Link
SI
SO
SI
SO
“0”
“0”
“0”
TER
“0”
TER
“0”
Device #1
NCV7755
NCV7755
TER (no error)
SI
SO
SI
SO
“1”
“0”
“1”
TER
“1”
TER
“0”
Device #1
NCV7755
NCV7755
TER Error Propagation
SI
“1”
“1”
1
“1”
SO
2
“1”
“don’t care”
During TER
TER
During TER status
retrieval, location 1 is
active in the output of
the Mux.
Location 2 is not active
in the output of the
status retrieval
SPI SO’
Mux Select
SI ’
S
register
TER False Reporting
st
NOTE: TER is valid from CSB going low until the 1 low−to−high transition of SCLK to allow for propagation of the SI signal.
For proper TER status retrieval, SI should be in a low state.
Figure 39.
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NCV7755
REGISTERS
STANDARD DIAGNOSTICS REGISTER (LISTING SUMMARY)
Description
VS Undervoltage Monitor
VDD Lower Operating Range Monitor
Operative Mode Monitor
UVRVS
LOPVDD
MODE
TER
Reports undervoltage condition for VS.
Reports VDD between 3 V and 4.5 V.
Displays Active, Idle, and Limp modes
Transmission Error
Reports error from modulo 8/16 counter
Reports open load when requested in On mode
Reports open load when requested in Off mode
Reports Overload or Overtemperature conditions
Open Load ON State Diagnostics
Open Load OFF State Diagnostics
Overload / Overtemperature Diagnostics
OLON
OLOFF
ERRn
REGISTERS (LISTING SUMMARY)
Register Name
Bits
Function
Output control On or Off
Power output control register
Bulb Inrush Mode
OUT.OUTn
BIM.OUTn
MAPIN0.OUTn
MAPIN1.OUTn
INST
Sets latchoff or auto restart mode
Mapping of IN0 to OUTx
Mapping IN0
Mapping IN1
Mapping of IN1 to OUTx
Input Status Monitor
Reports transmission bit errors
Reports INx input pin status
Open Load Diagnostic Current Control
Output Status Monitor
DIAG_IOL.OUTn
DIAG_OSM.OUTn
Enables diagnostic current
Reports open circuit conditions in OFF state.
This reporting is synonymous with short to battery (shorted
output FET) conditions
Also reports output status in the ON state
Reports open circuit conditions in ON state
Sets open load On monitoring
Open Load On Monitor
DIAG_OLON.OUTn
Open Load On Diagnostic Control
Hardware Configuration Register
DIAG_OLONEN.MUX
HWCR.ACT
HWCR.RST
HWCR.PAR
Active Mode transitions
SPI register reset
Sets parallel channel operation
Output Clear Latch
HWCR_OCL.OUTn
Clears the error latch for the selected output
PWM Configuration Register
HWCR_PWM.ADJ
HWCR_PWM.PWM1
HWCR_PWM.PWM0
Base PWM frequency adjust
PWM Generator 1 activation
PWM Generator 0 activation
PWM Generator Configuration 0
PWM Generator Configuration 1
PWM_CR0.FREQ
PWM_CR0.DC
PWM_CR1.FREQ
PWM_CR1.DC
PWM_OUTn
Sets internal divide by clock of PWM generator for Generator 0
Sets PWM Generator 0 duty cycle
Sets internal divide by clock of PWM generator for Generator 1
Sets PWM Generator 1 duty cycle
PWM Generator Output Control
PWM Generator Output Mapping
Selects active the PWM generator for OUTx
Selects one of the two PWM generators
PWM_MAP.OUTn
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38
NCV7755
SPI COMMAND SUMMARY
Requested Operation
Read Standard Diagnostics
Write 8−bit register
Frame Sent (SI Pin)
0xxxxxxxxxxxxx01
Frame Out (from SO Pin) with the Next Command
0ddddddddddddddd
B
B
10aaaabbcccccccc
0ddddddddddddddd
B
B
Read 8−bit register
01aaaabbxxxxxx10
10aaaabbcccccccc
B
B
B
Write 10−bit register
10aaaacccccccccc
0ddddddddddddddd
B
B
Read 10−bit register
01aaaaxxxxxxxx10
10aaaacccccccccc
B
x = don’t care
a = ADDR0 field
b = ADDR1 field
c = register content
d = diagnostic bit
HEX SPI COMMAND QUICK LIST
Register
OUT
Read Command
Write Command
Content Written
4002
4102
4402
4502
4602
4802
4902
80XX
81XX
84XX
85XX
XX = xxxxxxxx
H
H
H
H
H
H
H
H
H
H
H
H
B
B
B
B
BIM
XX = xxxxxxxx
H
MAPIN0
XX = xxxxxxxx
H
MAPIN1
XX = xxxxxxxx
H
INST
(read only)
88XX
−
DIAG_IOL
DIAG_OSM
DIAG_OLON
DIAG_OLONEN
HWCR
XX = xxxxxxxx
H
H
B
B
(read only)
XX = xxxxxxxx
H
4A02
4B02
8AXX
−
H
H
H
H
8BXX
XX = xxxxxxxx
H
B
B
B
B
4C02
4D02
8CXX
8DXX
XX = xxxxxxxx
H
H
H
H
H
H
H
H
HWCR_OCL
HWCR_PWM
PWM_CR0
XX = xxxxxxxx
H
4E02
8EXX
XX = xxxxxxxx
H
5002
90XX
91XX
92XX
93XX
0XX = 00xxxxxxxx
H
H
H
H
H
B
B
B
B
1XX = 01xxxxxxxx
H
2XX = 10xxxxxxxx
H
3XX = 11xxxxxxxx
H
PWM_CR1
5402
94XX
95XX
96XX
97XX
0XX = 00xxxxxxxx
H
H
H
H
H
H
B
B
B
B
1XX = 01xxxxxxxx
H
2XX = 10xxxxxxxx
H
3XX = 11xxxxxxxx
H
PWM_OUT
PWM_MAP
6402
6502
A4XX
A5XX
XX = xxxxxxxx
H
H
H
B
B
XX = xxxxxxxx
H
H
H
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NCV7755
SPI STANDARD DIAGNOSTICS
A Read Standard diagnostics command provides a
All 16 bit words from the SPI Diagnostics are read only
bits. The SPI Diagnostics are returned with the next
command after a Read Standard Diagnostics Command
response with a snapshot of the status of all the monitored
faults on the IC. Further fault details (channel fault number
etc…) can be reviewed in the subsequent register structure
banks.
0xxxxxxxxxxxxx01 where x = don’t care.
B
Table 5. SPI DIAGNOSTIC TABLE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
UVRVS
LOPVDD
MODE
TER
OLON
OLOFF
ERR
Default after power up or reset is the INST register
including TER = 1 The TER bit will afterward display the
B.
proper transmission state.
Table 6. DETAILED DIAGNOSTICS REGISTER DESCRIPTION
Field
Bits
Description
UVRVS
14
VS Undervoltage Monitor
0
B
1
B
No undervoltage condition on VS
(default) There was an undervoltage VS condition
since the last Standard Diagnostics request
LOPVDD
MODE
13
VDD Lower Operating Range Monitor
0
B
1
B
VDD is above 4.5 V
(default) VDD was below 4.5 V since the last Standard Diagnostics request (Note 19)
12,11
Operative Mode Monitor
00 (reserved)
B
01 Limp Home Mode
B
10 Active Mode
B
11 (default) Idle Mode
B
TER
10
Transmission Error
0
1
Previous transmission was successful. (modulo 16 + n*8 where n = 0,1,2…)
(default after reset) Previous transmission failed
B
B
The first frame after a reset is the INST register with TER = 1
B
The second frame (when the Standard Diagnostics Register is requested) is the Standard
Diagnostics register with TER = 0 provided the previous transmission was good
B
OLON
OLOFF
ERR
9
8
Open Load On State Diagnostics
0
B
1
B
(default) No Open Load ON detected
Open Load On detected
Open Load Off State Diagnostics
0
B
1
B
(default) No Open Load Off detected
Open Load Off detected
0−7
Overload / Overtemperature Diagnostics
0
B
1
B
(default) No failure detected
Overload or Overtemperature was detected
REGISTER STRUCTURE (all registers except PWM_CR0/1)(8 bit DATA register)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R= 0
W=1
R=1
W=0
ADDR0
ADDR1
DATA
18.Read and Write designators require two bits (14 and 15)(r = read, w = write).
19.This bit will be continuously set when operating with a standard 3.3 V supply on VDD.
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40
NCV7755
REGISTER STRUCTURE (PWM_CR0/1 registers)(10 bit DATA register)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R=0
R=1
ADDR0
DATA
W=1
W=0
20.Read and Write designators require two bits (14 and 15)(r = read, w = write).
Table 7. DETAILED REGISTER STRUCTURE
Register Name
ADDR0
ADDR1
Type
Purpose
Power Output Control Register bits (OUT.OUT.n)
OUT
0000
0000
0001
00
B
01
B
00
B
r/w
B
B
B
0
1
(default) Output is Off
Output is On
B
B
DATA = Channel number 7 to 0 (7:0)
BIM
r/w
r/w
Bulb Inrush Mode bits (BIM.OUTn)
0
1
(default) Output latches off with overload
Output restarts with overload
B
B
DATA = Channel number 7 to 0 (7:0)
MAPIN0
Input Mapping (IN0) bits (MAPIN0.OUTn)
0
1
(default) No connection to input pin
Output is connected to the input pin
B
B
DATA = Channel number 7 to 0 (7:0)
Note – Channel 2 has the corresponding bit set to “1” by default
MAPIN1
INST
0001
0001
01
10
r/w
Input Mapping (IN1) bits (MAPIN1.OUTn)
B
B
0
1
(default) No connection to input pin
Output is connected to the input pin
B
B
DATA = Channel number 7 to 0 (7:0)
Note – Channel 3 has the corresponding bit set to “1” by default
r
Input Status Monitor
B
B
TER bit bit (TER) (7)
0
1
Previous transmission was successful
(default) Previous transmission failed
B
B
Inx Bit bits (INST.RES) (6:2) – reserved, bits (INST.INn) (1:0)
0
B
1
B
(default) The input pin is set low
The input pin is set high
DIAG_IOL
0010
0010
00
01
r/w
Open Load Diagnostic Current Control
bits (DIAG_IOL.OUTn)
B
B
0
1
(default) Diagnostic current is not enabled
Diagnostic current is enabled
B
B
DATA = Channel number 7 to 0 (7:0)
DIAG_OSM
r
Output Status Monitor bits (DIAG_OSM.OUTn)
B
B
0
(default) Voutx is less than the Output Status Monitor Threshold
Voltage 3.3 V (typ)
Voutx is more than the Output Status Monitor Threshold Voltage 3.3 V
B
1
B
(typ)
DATA = Channel number 7 to 0 (7:0)
DIAG_OLON
0010
10
B
r
Open Load On Monitor bits (DIAG_OLON.OUTn)
B
0
1
(default) Normal operation or diagnostic performed with channel off
Open load On detected
B
B
DATA = Channel number 7 to 0 (7:0)
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41
NCV7755
Table 7. DETAILED REGISTER STRUCTURE
Register Name
ADDR0
0010
ADDR1
11
Type
Purpose
DIAG_OLONEN
r/w
Open Load On Diagnostic Control
bits (7:4) – reserved,
B
B
bits 1000 , 1001 , 1011 , 1100 , 1101 , 1100 − reserved
B
B
B
B
B
B
bits (DIAG_OLONEN.MUX) (3:0)
0000
0001
0010
Open Load ON active channel 0
Open Load ON active channel 1
Open Load ON active channel 2
Open Load ON active channel 3
Open Load ON active channel 4
Open Load ON active channel 5
Open Load ON active channel 6
Open Load ON active channel 7
B
B
B
B
0011
0100
0101
B
B
B
B
0110
0111
1010
Open Load ON Diagnostic Loop Start
(default) Open Load ON not active
B
1111
B
HWCR
0011
00
B
r/w
Hardware Configuration Register bits (5:4) − reserved
B
Active Mode bits (HWCR.ACT) (7)
0
(default) Normal operation
or device leaves Active Mode
Device enters Active Mode
B
1
B
SPI Register Reset bits (HWCR.RST) (6)
0
1
(default) Normal operation
Reset command executed
B
B
ERRn bits are not cleared by a reset command for safety reasons
Channels Operating in Parallel bits (HWCR.PAR) (3:0)
0
1
(default) Normal operation
B
Two neighboring channels have overload and overtemperature
B
synchronized. See section “Outputs in Parallel” for output combinations
HWCR_OCL
HWCR_PWM
0011
0011
01
10
w
Output Latch (ERRn) Clear bits (HWCR_OCL.OUTn)
B
B
0
1
(default) Normal operation
Clear the error latch for the selected output
B
B
The HWCR_OCL.OUTn bit is set back to “0” internally after de−latching the
channel
DATA = 7 to 0 (7:0)
r/w
PWM Configuration Register (HWCR_PWM.RES) (3:2) (reserved)
B
B
PWM Adjustment bits (HWCR_PWM.ADJ) (7:4)
HWCR_PWM.ADJ Bit
Absolute delta for fINT
Relative delta between steps
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1001B
1010B
1011B
1100B
1101B
1110B
1111B
(reserved)
Base Frequency
Base Frequency
Base Frequency
Base Frequency
Base Frequency
Base Frequency
Base Frequency
Base Frequency
Base Frequency
Base Frequency
Base Frequency
Base Frequency
Base Frequency
Base Frequency
Base Frequency
−35.0%
−35.0% (66.3 kHz[typ])
−30.0%
−25.0%
−20.0%
−15.0%
−10.0%
−5.0%
fINT (102 kHz [typ])(default)
+5.0%
+10.0%
+15.0%
+20.0%
+25.0%
+30.0%
+35.0%
+35.0 (137.7 kHz[typ])
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42
NCV7755
Table 7. DETAILED REGISTER STRUCTURE
Register Name
ADDR0
ADDR1
Type
Purpose
PWM1 Active bits (HWCR_PWM.PWM1) (1)
0
B
1
B
(default) PWM Generator 1 not active
PWM Generator 1 active
PWM0 Active (HWCR_PWM.PWM0) (0)
0
B
1
B
(default) PWM Generator 0 not active
PWM Generator 0 active
PWM_CR0
0100
−−−
r/w
PWM Generator 0 Configuration
B
CR0 Frequency (PWM_CR0.FREQ) (9:8)
00
01
10
Internal clock divided by 1024 (100 Hz) (default)
Internal clock divided by 512 (200 Hz)
Internal clock divided by 256 (400 Hz)
100% Duty Cycle.
B
B
B
B
11
CR0 generator on/off control (PWM_CRO.DC) (7:0)
00000000
PWM generator is off. (default)
B
11111111
PWM generator is On (99.61% DC).
B
PWM_CR1
0101
−−−
r/w
PWM Generator 1 Configuration
B
CR1 Frequency(PWM_CR1.FREQ) (9:8)
00
01
10
Internal clock divided by 1024 (100Hz) (default)
Internal clock divided by 512 (200 Hz)
Internal clock divided by 256 (400 Hz)
100% Duty Cycle
B
B
B
B
11
CR1 generator on/off control (PWM_CR1.DC) (7:0)
00000000
PWM generator is off. (default)
B
11111111
PWM generator is On (99.61% DC)
B
PWM_OUT
PWM_MAP
1001
1001
00
01
r/w
r/w
PWM Generator Output Control (PWM_OUT.OUTn)
(default) The selected ouput is not driven by one of the two PWM gen-
erators
The selected output is connected to a PWM generator
B
B
0
B
1
B
DATA = Channel number 0 to 7
PWM Generator Output Mapping (PWM_MAP.OUTn)
B
B
0
1
(default) The selected output is connected to PWM Generator 0
The selected output is connected to PWM Generator 1
B
B
DATA = Channel number 0 to 7
Works in conjunction with PWM_OUT
www.onsemi.com
43
NCV7755
THERMAL PERFORMANCE ESTIMATES
100
Duty Cycle = 0.5
10
1
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.1
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (s)
Figure 40. Transient R(t) vs. Pulse Time (JESD51−7, 600 mm2)
www.onsemi.com
44
NCV7755
PACKAGE DIMENSIONS
SSOP24 NB EP
CASE 940AK
ISSUE O
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
0.20 C A-B
NOTE 4
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
BE 0.10 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE
FOOT. DIMENSION b APPLIES TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.10 TO 0.25
FROM THE LEAD TIP.
NOTE 6
D
L1
A
24
13
2X
H
L2
0.20 C
GAUGE
PLANE
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 PER SIDE. DIMENSION D IS
DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE. DIMENSION E1 IS DETERMINED AT DA-
TUM PLANE H.
E1
E
L
A1
NOTE 5
PIN 1
SEATING
PLANE
DETAIL A
C
NOTE 7
REFERENCE
1
12
0.20 C
e
2X 12 TIPS
24X b
B
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
NOTE 6
M
0.12
C A-B D
7. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
8. CONTOURS OF THE THERMAL PAD ARE UN-
CONTROLLED WITHIN THE REGION DEFINED
BY DIMENSIONS D2 AND E2.
TOP VIEW
DETAIL A
A
A2
h
h
0.10 C
0.10 C
M
MILLIMETERS
DIM MIN
MAX
1.70
0.10
1.65
0.30
0.20
c
A
A1
A2
b
---
0.00
1.10
0.19
0.09
A1
SEATING
PLANE
END VIEW
24X
C
SIDE VIEW
c
M
0.15
C A-B D
D
8.64 BSC
NOTE 8
D2
E
5.28
5.58
D2
6.00 BSC
3.90 BSC
2.44 2.64
0.65 BSC
0.25 0.50
0.40 0.85
1.00 REF
0.25 BSC
E1
E2
e
M
0.15
C A-B
D
h
L
E2
L1
L2
M
NOTE 8
0
8
_
_
RECOMMENDED
SOLDERING FOOTPRINT
BOTTOM VIEW
5.63
24X
1.15
2.84
6.40
1
24X
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
www.onsemi.com
45
NCV7755
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
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For additional information, please contact your local Sales Representative
onsemi Website: www.onsemi.com
◊
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