NCV78723MW0R2G_技术文档

High Efficiency Buck Dual

LED Driver with Integrated

Current Sensing for

Automotive Front Lighting

NCV78723

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The NCV78723 is a single-chip and high efficient Buck Dual LED

Driver designed for automotive front lighting applications like high

beam, low beam, DRL (daytime running light), turn indicator, fog

light, static cornering, etc. The NCV78723 is in particular designed for

high current LEDs and provides a complete solution to drive 2 LED

strings of up-to 60 V. It includes 2 independent current regulators for

the LED strings and required diagnostic features for automotive front

lighting with a minimum of external components – the chip doesn’t

need any external sense resistor for the buck current regulation.

The available output current and voltages can be customized per

individual LED string. When more than 2 LED channels are required

on 1 module, then 2, 3 or more devices NCV78723 can be combined;

also with NCV78713 device – the derivative of the NCV78723

incorporating Buck Single LED Driver. Thanks to the SPI

programmability, one single hardware configuration can support

various application platforms.

24

1

QFN24

CASE 485CS

QFNW24

CASE 484AF

MARKING DIAGRAM

1

ON

N78723−0

AWLYYWWG

G

Features

• Single Chip

ON

• Buck Topology

N78723−2

FAWLYYWWG

G

• 2 LED Strings up-to 60 V

• High Current Capability up to 1.6 A DC per Output

• High Overall Efficiency

• Minimum of External Components

• Integrated High Accuracy Current Sensing

• Integrated Switched Mode Buck Current Regulator

• Average Current Regulation through the LEDs

• High Operating Frequencies to Reduce Inductor Sizes

• Low EMC Emission for LED Switching and Dimming

• SPI Interface for Dynamic Control of System Parameters

• Fail Safe Operating (FSO) Mode, Stand-Alone Mode

N78723−0 = Specific Device Code

N78723−2 = Specific Device Code

F

A

WL

YY

WW

G

= Fab Indicator

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

ORDERING INFORMATION

See detailed ordering and shipping information on page 31 of

this data sheet.

Compliant

Typical Applications

• High Beam

• Low Beam

• DRL

• Position or Park Light

• Turn Indicator

• Fog

• Static Cornering

1

Publication Order Number:

January, 2020 − Rev. 4

NCV78723/D

NCV78723

TYPICAL APPLICATION SCHEMATIC

VBOOST

C_M3V

VBOOSTM3V VBOOST

LED-String 1

VINBCK1

C_BCK_1

LBCKSW1

L_BCK_1

D_1

LBCKSW1

R_LED_1

VLED1

ON Semiconductor

External

C_LED_1

VDD Supply

LED Driver

2-Channel Buck

LED-String 2

NCV78723

VDD

V

of MCU

CC

VINBCK2

C_DD

C_BCK_2

LBCKSW2

L_BCK_2

R_SDO

LBCKSW2

VLED2

D_2

R_LED_2

RSTB

LEDCTRL1

LEDCTRL2

SCLK

C_LED_2

mC

SDI

SDO

CSB

Figure 1. Typical Application Schematic

Function

Table 1. EXTERNAL COMPONENTS

Component

Typical Value

Unit

mH

nF

L_BCK_x

C_BCK_x

C_M3V

C_DD

Buck Regulator Coil (see Buck Regulator Chapter for Details)

Buck Regulator Output Capacitor (see Buck Regulator Chapter for Details)

Capacitor for M3V Regulator

47

220

(see Table 6 − VBOOSTM3V)

nF

V

DD

Decoupling Capacitor

470

nF

C_LED_x

R_LED_x

R_SDO

D_x

Optional VLEDx Pin Filter Capacitor (Note 2)

VLEDx Pin Serial Resistor (Notes 2 and 3)

SPI Pull-Up Resistor

1

nF

Min. 1

kW

1

Buck Regulator Free-Wheeling Diode

e.g. MBRS2H100T3G

1. Pin TEST has to be connected to ground. TEST1 and TEST2 pins can be connected to ground or left floating.

2. C_LED_x is optional. If used, time constant of the C_LED_x and R_LED_x filter has to be lower than minimal LEDCTRLx ON time in PWM

dimming for proper VLED measurement.

3. R_LED_x is necessary to ensure Absolute Maximum Ratings of IVLEDx current (see Table 3).

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2

NCV78723

BLOCK DIAGRAM

Buck

VBOOST

VDD

VBOOSTM3V

Regulator

OTP

Vref

Bandgap

VBOOSTM3V

VINBCK1

Current

Sense CMP

POR

Bias

OSC

CTRL

Predriver

LBCKSW1

VINBCK2

LEDCTRL1

Current

Sense CMP

5 V Input

LEDCTRL2

RSTB

CTRL

SDI

SCLK

CSB

Predriver

5 V Input/

OD Output

LBCKSW2

SDO

TEST

VLED2

VLED1

LV IOs

TEST1

Temp

TEST2

ADC

MUX

VBOOST,

VDD,

VLEDx

Dividers

EXPOSED PAD

GND

Figure 2. Block Diagram

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3

NCV78723

ESD SCHEMATIC

SELF PROT PDMOS

TEST

TEST1

1

2

3

18

17

VDD

SDI

VBOOSTM3V

16

15

SCLK

CSB

4

VBOOST

TEST2

GND

5

6

14

13

SDO

RSTB

SELF PROT PDMOS

Figure 3. ESD Schematic

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4

NCV78723

PACKAGE AND PIN DESCRIPTION

24

23

22

21

20

19

18

17

VDD

SDI

1

2

TEST

TEST1

SCLK

CSB

16

15

3

4

VBOOSTM3V

VBOOST

NCV78723

5

6

TEST2

GND

SDO 14

13

RSTB

7

8

9

10

11

12

Figure 4. Pin Connections

Table 2. PIN DESCRIPTION

Pin No.

Pin Name

TEST

Description

Test Pin

I/O Type

LV In

1

2

TEST1

Test Pin

LV IN/OUT HV Tolerant

HV OUT (Supply)

HV Supply

LV IN/OUT HV Tolerant

Ground

3

VBOOSTM3V

VBOOST

TEST2

VBOOSTM3V Regulator Output Pin

Booster Input Voltage Pin

Test Pin

4

5

6

GND

Ground

7

VLED2

LED String 2 Forward Voltage Sense Input

Buck 2 Switch Output

HV IN

8

LBCKSW2

GND/NC

VINBCK2

LEDCTRL2

RSTB

HV OUT

9, 11, 20, 22

GND/NC Connection in Application

Buck 2 High Voltage Supply

LED String 2 Enable

NC

10

12

13

14

15

16

17

18

19

21

23

24

HV Supply

MV IN

External Reset Signal

MV IN

SDO

SPI Data Output

MV Open-Drain

MV IN

CSB

SPI Chip Select (Chip Select Bar)

SPI Clock

SCLK

MV IN

SDI

SPI Data Input

MV IN

VDD

3 V Logic Supply

LV Supply

MV IN

LEDCTRL1

VINBCK1

LBCKSW1

VLED1

LED String 1 Enable

Buck 1 High Voltage Supply

Buck 1 Switch Output

HV Supply

HV OUT

LED String 1 Forward Voltage Sense Input

HV IN

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5

NCV78723

Table 3. ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Minimum

Maximum

Unit

V

VBOOST Supply Voltage

V

−0.3

+68

BOOST

VINBCKx Supply Voltage (Note 4)

VBOOSTM3V Supply Voltage (Note 5)

VLED Sense Voltage

VINBCKx

VBOOSTM3V

VLEDx

Max of VBOOSTM3V − 0.3, −0.3

Min of V

+ 0.3, 68

V

BOOST

Max of V

− 3.6, −0.3

Min of V

+ 0.3, 68

V

BOOST

−0.3

V

BOOST

Logic Supply Voltage (Note 6)

Medium Voltage IO Pins (Note 7)

Test Pins (Note 8)

V

−0.3

−2.0

−30

3.6

V

DD

IOMV

TESTx

7.0

V

Min of V

+ 0.3, 68

V

BOOST

Buck Switch Low Side (Note 4)

VLED Sink/Source Current

Storage Temperature (Note 9)

The Exposed Pad (Note 10)

LBCKSWx

IVLEDx

VINBCKx + 0.3

30

V

mA

°C

V

T

STRG

−50

150

EXPAD

GND − 0.3

GND + 0.3

Electrostatic Discharge on Component

Level (Note 11)

Human Body Model

V

−2

−500

+2

+500

kV

V

ESD_HBM

ESD_CDM

Charge Device Model

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

4. V(VINBCKx − LBCKSWx) < 70 V, the driver in off state.

5. The VBOOSTM3V regulator in off state.

6. Absolute maximum rating for pins: VDD, TEST. Also valid for relative difference V

− VBOOSTM3V.

BOOST

7. Absolute maximum rating for pins: SCLK, CSB, SDI, SDO, LEDCTRL1, LEDCTRL2, RSTB. The mC interface pins (the IOMV pins) accept

5 V while the device is in the power-off mode (V = 0 V).

DD

8. Absolute maximum rating for pins: TEST1, TEST2.

9. For limited time up to 100 hours. Otherwise the max storage temperature is 85°C.

10.The exposed pad must be hard wired to GND pin in an application to ensure both electrical and thermal connection.

11. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC*Q100*002 (EIA/JESD22*A114)

ESD Charge Device Model tested per EIA/JESD22*C101

Latch-up Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78

Operating ranges define the limits for functional

operation and parametric characteristics of the device.

A mission profile (Note 12) is a substantial part of the

operation conditions; hence the Customer must contact

ON Semiconductor in order to mutually agree in writing on

the allowed missions profile(s) in the application.

Table 4. RECOMMENDED OPERATING RANGES

Characteristic

Symbol

Min

Typ

Max

Unit

Boost Supply Voltage

N78723−0 Device

N78723−2 Device

V

BOOST

+8

+6

+67

VINBCKx Supply Voltage (Note 13)

Low Voltage Supply

VINBCKx

V

− 0.1

V

+ 0.1

V

BOOST

V

DD

3.05

3.3

3.6

Buck Switch Output Current

I_LBCKSW

1.9

A

Functional Operating Junction Temperature

Range (Note 14)

T

−40

155

°C

JF

Parametric Operating Junction Temperature

Range (Note 15)

T

JP

150

°C

The Exposed Pad Connection (Note 16)

EXPOSED_PAD

GND − 0.1

GND

GND + 0.1

V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

12.A mission profile describes the application specific conditions such as, but not limited to, the cumulative operating conditions over life time,

the system power dissipation, the system’s environmental conditions, the thermal design of the customer’s system, the modes, in which the

device is operated by the customer, etc. No more than 100 cumulated hours in life time above T

13.Hard connection of VINBCKx to VBOOST on PCB.

.

TW

14.The circuit functionality is not guaranteed outside the functional operating junction temperature range. Also please note that the device is

verified on bench for operation up to 170°C but that the production test guarantees 155°C only.

15.The parametric characteristics of the circuit are not guaranteed outside the Parametric operating junction temperature range.

16.The exposed pad must be hard wired to GND pin in an application to ensure both electrical and thermal connection.

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6

NCV78723

Table 5. THERMAL RESISTANCE

Characteristic

Package

Symbol

Min

Typ

Max

Unit

Thermal Resistance Junction to Exposed Pad (Note 17)

QFN24 5x5

R

−

5

−

°C/W

thjp

17.Includes also typical solder thickness under the Exposed Pad (EP).

Table 6. ELECTRICAL CHARACTERISTICS

(All Min and Max parameters are guaranteed over full junction temperature (T ) range (−40°C; 150°C), unless otherwise specified)

JP

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

VDD: 3 V LOW VOLTAGE ANALOG AND DIGITAL SUPPLY

The VDD Current

Consumption

I_VDD

−

6

mA

V

POR Toggle Level on VDD

Rising

POR

2.7

3.05

2.8

3V_H

3V_L

POR Toggle Level on VDD

Falling

POR

2.45

V

POR Hysteresis

POR

0.01

13

0.2

0.75

15

V

3V_HYST

OTP UV Toggle Level on

VBOOST

OTP_UV

−

OTP UV Toggle Level

Hysteresis

OTP_UV_HYST

0.01

0.2

0.75

V

VBOOSTM3V: HIGH SIDE AUXILIARY SUPPLY

VBSTM3 Regulator Output

Voltage

V

Referenced to VBOOST

−3.6

−3.3

−3.0

V

BSTM3

DC Output Current

Consumption

M3V_IOUT

mA

N78723−0 Device

−

5

28

(Note 18)

22.5

N78723−2 Device

(Note 19)

Output Current Limitation

M3V_ILIM

−

200

2.2

mA

VBSTM3 External Decoupling

Cap.

C

Referenced to VBOOST

0.3

mF

VBSTM3V

VBSTM3 Ext. Decoupling

Cap. ESR

C

_ESR

−

200

5.5

mW

VBSTM3V

VBOOST POR Level on

N78723−2 Device (Note 20)

M3V_VBSTPOR

3.5

V

OSC10M: SYSTEM OSCILLATOR CLOCK

System Oscillator Frequency FOSC10M

, V , V , V , TEMP

LED2

8

10

8

12

MHz

ADC FOR MEASURING V

BOOST DD

LED1

ADC Resolution

ADC_RES

−

Bits

Nonlinearity

Integral (INL)

Differential (DNL)

Best Fitting Straight Line

Method

LSB

ADC_INL

ADC_DNL

−1.5

−2.0

−

+1.5

+2.0

Full Path Gain Error for

ADC_GAINER

−3.25

−

3.25

%

Measurements of V , V

,

DD

LEDx

V

BOOST

Offset at Output of ADC

Time for 1 SAR Conversion

ADC_OFFSET

ADC_CONV

ADCFS_VDD

−2

−

8

4

2

LSB

ms

Full Conversion of 8 Bits

6.67

3.87

10

ADC Full Scale for V

Measurement

4.13

V

DD

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

18.V

19.V

= 68 V, V

= 34 V, f

= 2 MHz, maximum total gate charge for both activated BUCK channels Q

= 14 nC.

GATE

BOOST

LED1,2

BUCK

GATE

= 1.61 MHz, maximum total gate charge for both activated BUCK channels Q

= 14 nC.

20.On N78723−2 device, the Buck switch is switched off when VBOOST drops below M3V_VBSTPOR level. When VBOOST returns back

above M3V_VBSTPOR level, normal operation is restored.

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NCV78723

Table 6. ELECTRICAL CHARACTERISTICS (continued)

(All Min and Max parameters are guaranteed over full junction temperature (T ) range (−40°C; 150°C), unless otherwise specified)

JP

Characteristic

Symbol

, V

Condition

Min

Typ

Max

Unit

ADC FOR MEASURING V

, V , V

, TEMP

LED2

BOOST DD

LED1

ADC Full Scale for V

Measurement

ADCFS_VLED00

ADCFS_VLED01

ADCFS_VLED10

ADCFS_VLED11

The V

Range Code is “00”

Range Code is “01”

Range Code is “10”

Range Code is “11”

67.725

48.375

38.700

29.025

70

50

40

30

72.275

51.625

41.300

30.975

V

LEDx

LED

ADC Full Scale for V

Measurement

ADCFS_VBST

67.725

70

72.275

V

BOOST

ADC Full Scale for Temp.

Measurement

N78723−0 Device

N78723−2 Device

ADCFS_TEMP

°C

193.5

190

200

206.5

210

TSD Threshold Level

ADC_TSD

ADC_TEMPHOT

ADC_TEMPCOLD

VLED_RES

ADC Measurement of Junction

Temperature

163

169

175

°C

kW

Temperature Measurement

Accuracy at Hot

t = 125°C

−8

−

8

Temperature Measurement

Accuracy at Cold

t = −40°C

−15

−

15

V

Input Impedance

N78723−0 Device

N78723−2 Device

LEDx

210

280

−

650

790

BUCK REGULATOR − SWITCH

On Resistance, Range 1

Rdson1

Rdson1_hot

Rdson2

At Room-Temperature,

I(VINBCKx) = 0.18 A,

−

5.2

7.2

2.6

3.6

1.3

1.8

0.65

0.9

W

V(BOOST − VINBCKx) ≤ 0.2 V

On Resistance at Hot,

Range 1

At Tj = 150 °C,

I(VINBCKx) = 0.18 A,

V(BOOST − VINBCKx) ≤ 0.2 V

On Resistance, Range 2

At Room-Temperature,

I(VINBCKx) = 0.375 A,

V(BOOST − VINBCKx) ≤ 0.2 V

On Resistance at Hot,

Range 2

Rdson2_hot

Rdson3

At Tj = 150 °C,

I(VINBCKx) = 0.375 A,

V(BOOST − VINBCKx) ≤ 0.2 V

On Resistance, Range 3

At Room-Temperature,

I(VINBCKx) = 0.75 A,

V(BOOST − VINBCKx) ≤ 0.2 V

On Resistance at Hot,

Range 3

Rdson3_hot

Rdson4

At Tj = 150 °C,

I(VINBCKx) = 0.75 A,

V(BOOST − VINBCKx) ≤ 0.2 V

On Resistance, Range 4

At Room-Temperature,

I(VINBCKx) = 1.5 A,

V(BOOST − VINBCKx) ≤ 0.2 V

On Resistance at Hot,

Range 4

Rdson4_hot

At Tj = 150 °C,

I(VINBCKx) = 1.5 A,

V(BOOST − VINBCKx) ≤ 0.2 V

Switching Slope – ON Phase

(Note 21)

T

−

3

−

V/ns

RISE

Switching Slope – OFF Phase

(Notes 21 and 22)

FALL

BUCK REGULATOR − CURRENT REGULATION

Current Sense Threshold

Level, Range 1, Min Value

ITHR1_000

[BUCKx_VTHR = 00000000]

End of the BUCK ON-Phase

23.905

28.125

32.344

mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

21.When DRV_SLOW_EN bit is 1 on N78723−2 device, the switching slopes are typically by 30% slower.

22.Falling switching slope depends on used current (range, current sense threshold level) and free-wheeling diode capacitance.

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NCV78723

Table 6. ELECTRICAL CHARACTERISTICS (continued)

(All Min and Max parameters are guaranteed over full junction temperature (T ) range (−40°C; 150°C), unless otherwise specified)

JP

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

BUCK REGULATOR − CURRENT REGULATION

Current Sense Threshold

Level, Range 1, Spec. Value

ITHR1_110

[BUCKx_VTHR = 01101110]

End of the BUCK ON-Phase.

Min. Value for Specified

Precision

−

112.5

−

mA

Current Sense Threshold

Level, Range 1, Max Value

ITHR1_255

ITHR2_000

ITHR2_110

[BUCKx_VTHR = 11111111]

End of the BUCK ON-Phase

−

47.813

−

224.15

56.25

225

−

64.688

−

mA

Current Sense Threshold

Level, Range 2, Min Value

[BUCKx_VTHR = 00000000]

End of the BUCK ON-Phase

Current Sense Threshold

Level, Range 2, Spec. Value

[BUCKx_VTHR = 01101110]

End of the BUCK ON-phase.

Min. Value for Specified

Precision

Current Sense Threshold

Level, Range 2, Max Value

ITHR2_255

ITHR3_000

ITHR3_110

[BUCKx_VTHR = 11111111]

End of the BUCK ON-Phase

−

95.625

−

448.3

112.5

450

−

129.375

−

mA

Current Sense Threshold

Level, Range 3, Min Value

[BUCKx_VTHR = 00000000]

End of the BUCK ON-Phase

Current Sense Threshold

Level, Range 3, Spec. Value

[BUCKx_VTHR = 01101110]

End of the BUCK ON-Phase.

Min. Value for Specified

Precision

Current Sense Threshold

Level, Range 3, Max Value

ITHR3_255

ITHR4_000

ITHR4_110

[BUCKx_VTHR = 11111111]

End of the BUCK ON-phase

−

191.25

−

896.6

225

−

258.75

−

mA

Current Sense Threshold

Level, Range 4, Min Value

[BUCKx_VTHR = 00000000]

End of the BUCK ON-Phase

Current Sense Threshold

Level, Range 4, Spec. Value

[BUCKx_VTHR = 01101110]

End of the BUCK ON-Phase.

Min. Value for Specified

Precision

900

Current Sense Threshold

Level, Range 4, Max Value

ITHR4_255

dITHR1

[BUCKx_VTHR = 11111111]

End of the BUCK ON-Phase

−

1791.75

0.77

−

mA

%

Current Sense Threshold

Increase per Code, Range 1

8 Bit, Linear Increase

Current Sense Threshold

Increase per Code, Range 2

dITHR2

1.54

Current Sense Threshold

Increase per Code, Range 3

dITHR3

3.08

Current Sense Threshold

Increase per Code, Range 4

dITHR4

6.15

Current Threshold Accuracy

Only with Trimming Constant

for the Highest Range

(Note 23)

N78723−0

N78723−2

ITHR_ERR_DD

Specified for BUCKx_VTHR ≥

01101110, without the Delta of

the Trimming Code and without

Temp. Compensation

−8

−9

−

+8

+9

Current Threshold Accuracy

without Temperature

Compensation (Note 23)

N78723−0

ITHR_ERR_D

ITHR_ERR

Specified for BUCKx_VTHR ≥

01101110, with the Delta of the

Trimming Code and without

Temp. Compensation

%

−6

−7

−

+6

+7

N78723−2

Current Threshold Accuracy

(Note 23)

N78723−0

N78723−2

Specified for BUCKx_VTHR ≥

01101110, the Delta of the

Trimming Code and Temp.

Compensation

−3

−4

−

+3

+4

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

23.Measured as comparator DC threshold value, without comparator delay and switch falling slope.

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NCV78723

Table 6. ELECTRICAL CHARACTERISTICS (continued)

(All Min and Max parameters are guaranteed over full junction temperature (T ) range (−40°C; 150°C), unless otherwise specified)

JP

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

BUCK REGULATOR − CURRENT REGULATION

Offset of Peak Current

Comparator on N78723−2

Device

CMP_OFFSET

−10

−

+10

mV

Over-Current Detection Level,

Range 1

OCDR1

OCDR2

OCDR3

OCDR4

TC_00

Typ. 1.5 × ITHR1_255

Typ. 1.5 × ITHR2_255

Typ. 1.5 × ITHR3_255

Typ. 1.5 × ITHR4_255

[BUCKx_TOFF = 00000]

[BUCKx_TOFF = 11111]

286

573

1148

2295

−

388

776

1553

3105

−

mA

ms·V

%

Over-Current Detection Level,

Range 2

Over-Current Detection Level,

Range 3

−

Over-Current Detection Level,

Range 4

−

Time Constant for Longest Off

Time

50

5

Time Constant for Shortest Off

Time

TC_31

−

T

OFF

Time Relative Error

TOFF_ERR

TC = T

@ VLED > 2 V,

> 350 ns

× V

LED

−10

−

+10

OFF

T

OFF

T

OFF

Time Absolute Error

TOFF_ERR_ABS

TC = T

× V

−35

−

+35

ns

OFF

LED

@ VLED > 2 V,

≤ 350 ns

T

OFF

Time Constant Decrease per

Code

dTC

5 Bits, Exponential Decrease

−

7.16

1.8

−

%

V

Detection Level of V

Too Low

to be

VLED_LMT

TC_LOW

1.62

1.98

LED

T

Time for Low V

VLED < VLED_LMT

ms

OFF

LED

Voltages

N78723−0 Device

N78723−2 Device (Note 24)

78

72

105

120

140

The Zero-cross Detection

Threshold Level (Note 25)

TC_ZCD

−0.125

−

−0.005

V

The Zero-cross Detection

Filter Time

TC_ZCD_FT

20

−

350

ns

OpenLEDx Detection Time

TON_OPEN

TON_MIN

40

50

60

ms

Buck Minimum T Time

For

−

250

ns

ON

VINBCKx – LBCKSWx < 2.4 V,

No Failure at LBCKSWx Pin

Delay from BUCKx ISENS

Comparator Input Voltage

Balance to BUCKx Switch

Going OFF

ISENSCMP_DEL

ISENS Cmp. Over-Drive

ramp > 1 mV/10 ns

−

70

−

ns

5 V TOLERANT DIGITAL INPUTS (SCLK, CSB, SDI, LEDCTRL1, LEDCTRL2, RSTB)

High-Level Input Voltage

Low-Level Input Voltage

Pull Resistance (Note 26)

VINHI

2

−

V

VINLO

0.8

R

40

4.4

−

160

6.95

kW

ms

PULL

LED PWM Propagation Delay

(Note 27)

BUCKx_SW_DEL

Activation Time of the BUCKx

Switch from the LEDCTRLx Pin

5.5

Sampling Resolution

LEDCTRL_SR

RSTB_DEB

−

100

125

200

ns

RSTB Debouncer Time

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

24.Unless zero-cross detection stops the TOFF time on N78723−2 device.

25.The voltage at LBCKSWx pin when the comparator toggles, rising edge.

26.Pull down resistor (R ) for RSTB, LEDCTRLx, SDI and SCLK, pull up resistor (R ) for CSB to VDD.

PD

PU

27.Jitter is present due to the internal resynchronization.

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10

NCV78723

Table 6. ELECTRICAL CHARACTERISTICS (continued)

(All Min and Max parameters are guaranteed over full junction temperature (T ) range (−40°C; 150°C), unless otherwise specified)

JP

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

5 V TOLERANT OPEN-DRAIN DIGITAL OUTPUT (SDO)

Low-Voltage Output Voltage

VOUTLO

I

= −10 mA

−

0.4

V

OUT

(Current Flows into the Pin)

Equivalent Output Resistance

SDO Pin Leakage Current

SDO Pin Capacitance

RDSON

SDO_ILEAK

SDO_C

Low-Side Switch

−

10

−

40

2

W

mA

pF

ns

−

10

60

CLK to SDO Propagation

Delay

SDO_DL

Low-Side Switch Activation/

Deactivation Time; @ 1 kW to

5 V, 100 pF to GND, for Falling

Edge V(SDO) Goes below

0.5 V

−

3 V DIGITAL INPUTS (TEST, TEST1, TEST2)

High-Level Input Voltage

Low-Level Input Voltage

Pull Resistance

VIN3HI

VIN3LO

2.3

−

V

0.8

60

R

Pull-Down Resistance

−

kW

PD3

SPI INTERFACE

CSB Setup Time

t

0.5

0.25

0.5

−

ms

CSS

CSB Hold Time

t

CSH

SCLK Low Time

t

WL

SCLK High Time

t

0.5

WH

Data-In (DIN) Setup Time,

Valid Data before Rising Edge

of CLK

t

0.25

SU

Data-In (DIN) Hold Time, Hold

Data after Rising Edge of CLK

t

0.275

0.08

−

ms

H

Output (DOUT) Disable Time

(Note 28)

t

0.32

0.32 +

DIS

Output (DOUT) Valid

(Note 28)

t

→

V1

0

1

Output (DOUT) Valid

(Note 29)

−

→

V0

t

(RC)

Output (DOUT) Hold Time

CSB High Time

t

0.01

1

−

ms

HO

t

−

CS

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

28.SDO low-side switch activation time.

29.Time depends on the SDO load and pull-up resistor.

t

CS

Initial State of SCLK after CSB Falling Edge

is Don’t Care, It Can be Low or High

V

IH

CSB

V

IL

t

WL

CSS

WH

t

CSH

V

IH

SCLK

t

H

V

IL

SU

V

IH

DIN13

DIN15

DIN14

DIN1

DIN0

DIN

V

IL

t

DIS

HO

V

IH

HI−Z

DOUT15

DOUT14

DOUT13

DOUT1

DOUT0

DOUT

HI−Z

V

IL

Figure 5. SPI Communication Timing

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11

NCV78723

TYPICAL CHARACTERISTICS

2000

1800

1600

1400

1200

1000

Accuracy ( 3%/ 6%/ 8%) Guaranteed from VTHR Code 110 [dec]

1791.15 mA at VTHR = 255 in Range 4

+6.15 mA/step in Range 4

ITHR = 4

896.6 mA at VTHR = 255 in Range 3

+3.08 mA/step in Range 3

225 mA at VTHR = 0 in Range 4

112.5 mA at VTHR = 0 in Range 3

800

600

400

200

0

ITHR = 3

ITHR = 2

448.3 mA at VTHR = 255 in Range 2

+1.54 mA/step in Range 2

224.15 mA at VTHR = 255 in Range 1

56.25 mA at VTHR = 0 in Range 2

+0.77 mA/step in Range 1

160 192

ITHR = 1

128

0

32

64

96

224

256

110

28.125 mA at VTHR = 0 in Range 1

Buck VTHR Code (−)

Figure 6. Buck Peak Current vs. Ranges and VTHR Code

120

100

80

60

40

20

0

−60

−40

−20

0

20

40

60

80

100

120

140

160

Temperature (5C)

Figure 7. Typical Temperature Behavior of Buck Switch R_DSONRelative to the Value at 1505C

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12

NCV78723

TYPICAL CHARACTERISTICS

5.20

52.0

T

OFF

⋅ V

= 5 ms ⋅ V

5.15

5.10

5.05

5.00

4.95

4.90

LED

51.0

T

OFF

⋅ V

LED

= 50 ms ⋅ V

50.0

49.0

48.0

−40

0

40

80

120

−40

0

40

80

120

Temperature (5C)

Figure 8. Typical Temperature Dependency of T_OFFV V_LEDConstant

(Shortest T_OFFV V_LED= 5 ms V V and Longest T_OFFV V_LED= 50 ms V V)

140

120

100

80

−40°C

25°C

150°C

60

40

20

0

0.001

0.01

0.1

1

10

Slope (A/ms) (for Range 4*)

* In lower ranges, the same current slope (A/s) translates into a higher voltage slope (V/s) at the input of the comparator,

because of the higher R . Resulting equations for all ranges:

DSON

Range 4: Comp. Delay [ns] = (0.0365 · Temp [°C] − 10.41) · ln(Slope [A/ms, Range 4]) + 46

Range 3: Comp. Delay [ns] = (0.0365 · Temp [°C] − 10.41) · ln(Slope · 2 [A/ms, Range 4]) + 46

Range 2: Comp. Delay [ns] = (0.0365 · Temp [°C] − 10.41) · ln(Slope · 4 [A/ms, Range 4]) + 46

Range 1: Comp. Delay [ns] = (0.0365 · Temp [°C] − 10.41) · ln(Slope · 8 [A/ms, Range 4]) + 46

Figure 9. Typical Comparator Delay vs. Slope

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13

NCV78723

DETAILED OPERATING DESCRIPTION

Buck Current Regulation Principle

Each buck controls the individual inductor peak current

Supply Concept in General

Two voltages have to be supplied to the NCV78723 chip

– low voltage VDD logic supply and high voltage VBOOST

for providing energy to the buck regulators. More detailed

description follows.

(I

)

and incorporates

a

constant ripple

BUCKpeak

(DI

) control circuit to ensure also stable average

BUCKpkpk

current through the LED string, independently from the

string voltage. The buck average current is in fact described

by the formula:

VDD Supply

The VDD supply is the low voltage digital and analog

supply for the chip. NCV78723 does not contain internal

VDD regulator and this voltage is supposed to be provided

externally by a dedicated voltage regulator that fulfills

specified voltage and current needs or can be supplied from

the NCV78702/NCV78703 VDD pin.

The Power-On-Reset circuit (POR) monitors the VDD

voltage and RSTB pin to control the out-of-reset and reset

entering state. At power-up, the chip will exit from reset

state when VDD > POR3V_H and RSTB pin is in “log. 1”.

No SPI communication is possible in reset state.

DI_BUCK

pkpk

(eq. 1)

I_BUCK

+ I_BUCK

*

AVG

peak

2

This is graphically exemplified by Figure 10.

Buck Peak Current

Buck

Current

Buck Average Current

Buck Current Ripple

= T

/ L

BUCK

OFF_V_BUCK

T

OFF

time

VBOOST Supply

Figure 10. Buck Regulator Controlled

Average Current

The VBOOST supply voltage is the main high voltage

supply for the chip. The voltage is supposed to be provided

by booster chip such as NCV78702/NCV78703 or

NCV878763 in an application. VINBCKx pins have to be

connected by low impedance track to this supply to ensure

proper buck performance.

The VBOOST voltage is monitored by under-voltage

comparator to check sufficient zapping voltage at VBOOST

pin during OTP programming operation.

The parameter I

is programmable through the

BUCKpeak

device by means of the internal registers for range selection

BUCKx_ISENS_THR[1:0] and code BUCKx_VTHR[7:0].

The formula that defines the total ripple current over the

buck inductor is also hereby reported:

ǒ

Ǔ

T_OFF@ V_LED) V_DIODE

DI_BUCK

+

^

pkpk

L_BUCK

(eq. 2)

VBOOSTM3V Supply

T_OFF@ V_LED

T_OFF_V_LED_i_SPI

^

+

The VBOOSTM3V is the high side auxiliary supply for

the gate drive of the buck regulators’ integrated high-side

P-MOSFET switches. This supply receives energy directly

from the VBOOST pin.

L_BUCK

In the formula above, T

represents the buck switch off

OFF

time, V

is the LED voltage feedback sensed at the

LED

NCV78723 VLEDx pin and L

value. The parameter T _V

is the buck inductance

BUCK

_i is programmable by

LED SPI

Internal Clock Generation – OSC10M

OFF

SPI (BUCKx_TOFF[4:0] register), with values related to

Table 6 − Buck Regulator – Current Regulation. In order to

achieve a constant ripple current value, the device varies

An internal RC clock named OSC10M is used to run all

the digital functions in the chip. The clock is trimmed in the

factory prior to delivery. Its accuracy is guaranteed under

full operating conditions and is independent from external

component selection (refer to Table 6 − OSC10M: System

Oscillator Clock for details). All timings depend on

OSC10M accuracy.

the T

time inversely proportional to the V

sensed at

OFF

LED

the device pin, according to the selected factor

_V _i . As a consequence to the constant ripple

T

OFF

LED SPI

control and variable off time, the buck switching frequency

depends on the boost voltage and LED voltage in the

following way:

Buck Regulator

ǒ_V

Ǔ

_BOOST* V_LED

General

1

T_OFF

f_BUCK

+

@

+

The NCV78723 contains two high-current integrated

buck current regulators, which are the sources for the LED

strings. The bucks are powered from the external booster

regulator.

V_BOOST

(eq. 3)

ǒ_V

Ǔ

_BOOST* V_LED

V_LED

+

@

V_BOOST

T_OFF_V_LED_i_SPI

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14

NCV78723

The LED average current in time (DC) is equal to the buck

time average current. Therefore, to achieve a given LED

current target, it is sufficient to know the buck peak current

and the buck current ripple. A rule of thumb is to count a

minimum of 50% ripple reduction by means of the capacitor

C

and this is normally obtained with a low cost ceramic

BUCK

component ranging from 100 nF to 470 nF (such values are

typically used at connector sides anyway, so this is included

in a standard BOM). The following figure reports a typical

example waveform:

Figure 11. LED Current AC Components Filtered Out by Output Impedance (Oscilloscope Snapshot)

The use of C

is a cost effective way to improve EMC

L

, which would be certainly a far more expensive

BUCK

performances without the need to increase the value of

solution.

VBOOST

Supply

VBOOSTM3V

C

VBOOST

M3V

VBOOSTM3V

Reg.

POWER STAGE

Driver

VINBCKx

L

LED String

LBCKSWx

D

I

/OC

SENSE

C

VLEDx

Digital

Control

Constant

Ripple Control

Figure 12. Buck Regulator Circuit Diagram

Buck Offset Compensation

of the polarity change, the peak current is toggling between

two threshold values, one high value and one low, as shown

in the picture below. The related sub-harmonic frequency

(half the buck switching frequency) will appear in the

spectrum. This has to be taken into account from EMC point

of view. The use of the offset cancellation is very effective

in case of high precision levels for low currents.

The N78723−2 device features a peak current offset

compensation that can be disabled by the corresponding

BUCKx_OFF_CMP_DIS SPI bit. When this bit is “0”

(offset compensation is enabled), the offset changes polarity

each buck period, so that the average effect over time on the

peak current is minimized (ideally zero). As a consequence

Figure 13. Buck Offset Compensation Feature

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15

NCV78723

SW Compensation of the Buck Current Accuracy

In order to ensure buck current accuracy as specified in Table 6 − Buck Regulator – Current Regulation, set of constants

trimmed during manufacturing process is available. Microcontroller should use them in the following way:

To Reach 8% ( 9% for N78723−2) Accuracy ( 6% for Range 4) Over Whole Temperature Operating Range:

All ranges: BUCKx_ISENS_TRIM[6:0] = BUCKx_ISENS_RNG[6:0]

BUCKx_ISENS_RNG[6:0] is trimming constant for the highest current range (Range 4) at hot temperature.

BUCKx_ISENS_RNG[6:0] constant is loaded into BUCKx_ISENS_TRIM[6:0] register automatically after the reset of the

device.

To Reach 6% ( 7% for N78723−2) Accuracy Over Whole Temperature Operating Range:

BUCKx_ISENS_Dx[3:0] registers, meaning delta of the trimming constant with respect to the higher current range at hot

temperature, have to be used. Trimming constant for the particular range at hot temperature can be then calculated as:

Range 4: BUCKx_R4_trim_hot = BUCKx_ISENS_RNG[6:0],

Range 3: BUCKx_R3_trim_hot = BUCKx_ISENS_RNG[6:0] + BUCKx_ISENS_D3[3:0],

Range 2: BUCKx_R2_trim_hot = BUCKx_ISENS_RNG[6:0] + BUCKx_ISENS_D3[3:0] + BUCKx_ISENS_D2[3:0],

Range 1: BUCKx_R1_trim_hot = BUCKx_ISENS_RNG[6:0] + BUCKx_ISENS_D3[3:0] + BUCKx_ISENS_D2[3:0] +

BUCKx_ISENS_D1[3:0],

where:

delta of the trimming constant BUCKx_ISENS_Dx[3:0] is signed, coded as two’s complement. Range of this constant is

decadic <−8; 7>, binary <1000; 0111>.

Calculated trimming constant has to be then written into trimming SPI register:

BUCKx_ISENS_TRIM[6:0] = BUCKx_Ry_trim_hot

To Reach 3% ( 4% for N78723−2) Accuracy Over Whole Temperature Operating Range:

In addition to BUCKx_ISENS_Dx[3:0] registers, the BUCK_ISENS_TCx[3:0] registers, meaning temperature coefficients

for the appropriate ranges, have to be used.

When TC_VERSION = 0, trimming value for a certain temperature should be calculated as:

2

Range 4: BUCKx_R4_trim = BUCKx_R4_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L3

Q

2

Range 3: BUCKx_R3_trim = BUCKx_R3_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L2

Q

2

Range 2: BUCKx_R2_trim = BUCKx_R2_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L1

Q

2

Range 1: BUCKx_R1_trim = BUCKx_R1_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L0

Q

When TC_VERSION = 1, trimming value for a certain temperature should be calculated as:

2

Range 4: BUCK2_R4_trim = BUCK2_R4_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L3

Q

2

Range 3: BUCK2_R3_trim = BUCK2_R3_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L3

Q

2

Range 2: BUCK2_R2_trim = BUCK2_R2_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L2

Q

2

Range 1: BUCK2_R1_trim = BUCK2_R1_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L2

Q

2

Range 4: BUCK1_R4_trim = BUCK1_R4_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L1

Q

2

Range 3: BUCK1_R3_trim = BUCK1_R3_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L1

Q

2

Range 2: BUCK1_R2_trim = BUCK1_R2_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L0

Q

2

Range 1: BUCK1_R1_trim = BUCK1_R1_trim_hot + k · (Tj – Thot) + k · (Tj – Thot) ,

L0

Q

where:

buck temperature coefficient BUCK_ISENS_TCx[3:0] is signed, coded as two’s complement. Range of this constant is

decadic <−8; 7>, binary <1000; 0111>,

2

k

is linear coefficient for each current range calculated: k = (BUCK_ISENS_TCx[3:0] – k · (170°C) )/(−170°C)

Lx

Q

[code/°C] when TC_VERSION = 0

is linear coefficient for each current range calculated: k = (BUCK_ISENS_TCx[3:0] – k · (200°C) )/(−200°C)

2

k

Lx

Q

[code/°C] when TC_VERSION = 1

k is quadratic constant for all current ranges: k = 2.18 · 10 [code/(°C) ]

−4

2

Q

Tj is junction temperature in °C calculated from VTEMP[7:0] SPI register value according to the equation defined in chapter

ADC: Device Temperature ADC: V

TEMP

Thot temperature is constant equal to 125°C when TC_VERSION = 0

Thot temperature is constant equal to 155°C when TC_VERSION = 1.

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16

NCV78723

Calculated trimming constant has to be then written into trimming SPI register:

BUCKx_ISENS_TRIM[6:0] = BUCKx_Ry_trim

Note: The BUCKx_ISENS_TRIM[6:0] SPI register allows compensation of the peak current app. in range 40 % from

actual value according to the following equation:

IBUCKx = (ITHRx_000 + dITHRx · BUCKx_VTHR[7:0]) · (1 + 0.4 · ((BUCKx_ISENS_TRIM[6:0] − 63)/63)),

where:

ITHRx_000 is current for VTHR code 0 in ITHRx range (see Table 6 − Buck Regulator – Current Regulation),

dITHRx code step in range ITHRx (see Table 6 − Buck Regulator – Current Regulation).

Paralleling the Bucks for Higher Current Capability

Different buck channels can be paralleled at the module

output (after the buck inductors) for higher current

capability on a unique channel, summing up together the

individual DC currents.

logic status of the LEDCTRLx pins. The only difference is

the controlled phase shift of typical 5.5 ms (Table 6 − 5 V

Tolerant Digital Inputs) that allows synchronized

measurements of the VLEDx pins via the ADC (see

dedicated section for more details). As the phase shift is

applied both to rising edges and falling edges, with a very

limited jitter, the PWM duty cycle is not affected. Apart from

the phase shift and the system clock OSC10M, there is no

limitation to the PWM duty cycle values or resolutions at the

bucks, which is a copy of the reference provided at the

inputs.

Buck Overcurrent Protection

Being a current regulator, the NCV78723 buck is by

nature preventing overcurrent in all normal situations.

However, in order to protect the system from overcurrent

even in case of failures, protection mechanism is available.

This protection is based on internal sensing over the buck

switch: when the peak current rises above the maximum

limit (OCDRx level, see see Table 6 − Buck Regulator –

Current Regulation), an internal counter starts to increment

at each period, until the count written in

BUCKx_OC_OCCMP_THR[1:0] + 1 is attained. The count

is reset if the current drops below OCDRx level or the buck

channel is disabled and also at each dimming cycle. From the

moment the count is reached onwards, the buck is kept

continuously off, until the SPI error flag OCLEDx is read.

After reading the flag, the buck channel “x” is automatically

re-enabled and will try to regulate the current again.

ZOOM: Buck Inductor Switching Current

DIM_DUTY = DIM_T / DIM_T = DIM_T ⋅ F

ON

DIM_T

ON

DIM_T

Figure 14. Buck Current Digital or PWM Dimming

ADC

General

The built-in analog to digital converter (ADC) is an 8-bit

Dimming

successive approximation register (SAR). This embedded

peripheral can be used to provide the following

measurements to the external Micro Controller Unit

(MCU):

The NCV78723 supports both analog and digital

dimming (or so called PWM dimming). Analog dimming is

performed by controlling the LED amplitude current during

operation. This can be done by means of changing the peak

current level and/or the T _V

commands (see Buck Regulator section).

In this section, we only describe PWM dimming as this is

the preferred method to maintain the desired LED color

temperature for a given current rating. In PWM dimming,

the LED current waveform frequency is constant and the

duty cycle is set according to the required light intensity. In

order to avoid the beats effect, the dimming frequency

should be set at “high enough” values, typically above

300 Hz.

• VBOOST Voltage: Sampled at the VBOOST Pin

_i constants by SPI

LED SPI

OFF

• VDD Voltage: Sampled at the VDD Pin

• VLED1ON, VLED2ON Voltages

• VLED1 and VLED2 Voltages

• VTEMP Measurement (Chip Temperature)

The internal NCV78723 ADC state machine samples all

the above channels automatically, taking care for setting the

analog MUX and storing the converted values in memory.

The external MCU can read out all ADC measured values

via the SPI interface, in order to take application specific

decisions. Please note that none of the MCU SPI commands

interfere with the internal ADC state machine sample and

conversion operations: the MCU will always get the last

available data at the moment of the register read.

PWM dimming is controlled externally by means of

LEDCTRLx inputs.

Digital Dimming

The two independent control inputs LEDCTRLx handle

the dimming signals for the related channel “x”. In digital

dimming, the buck activation is transparently linked to the

The state machine sampling and conversion scheme is

represented in the figure below.

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17

NCV78723

default selection is given to channel “1”. Then an internal

flag keeps priority tracking, toggling at each time between

channels pre-selection. Therefore, up to two dimming

periods will be required to obtain a full measurement update

of the two channels. This is not considered however

a limitation, as typical periods for dimming signals are in the

order of 1 ms period, thus allowing very fast failure

detection.

V

Sample & Convert

DD

Update

LED_SEL_DUR

Count; When Counter

Ripples, Trigger

VLEDx Interrupt for

Once

V

BOOST

A flow chart referring to the ADC interrupts is also

displayed.

V

TEMP

Sample & Convert

V

Sample & Convert

BOOST

YES

NO

V

LEDx

Interrupts

Enabled?

Synchronization

Signal?

Figure 15. ADC Sample and Conversion Main

Sequence

YES

NO

V

Sample & Convert

LEDx

Referring to the figure above, the typical rate for a full

SAR plus digital conversion per channel is 8 ms (Table 6 −

ADC for Measuring VBOOST, VDD, VLED1, VLED2,

TEMP). For instance, each new VBOOST ADC converted

sample occurs at 16 ms typical rate, whereas for both the

VDD and VTEMP channel the sampling rate is typically

32 ms, that is to say a complete cycle of the depicted

sequence. This time is referred to as TADC_SEQ.

Toggle Channel “x” Selection

In Case of Interrupt on Second

Channel do Not Serve Immediately

and Complete the ADC Sequence

First

If the SPI setting LED_SEL_DUR[8:0] is not zero, then

interrupts for the VLEDx measurements are allowed at the

points marked with a rhombus, with a minimum cadence

corresponding to the number of the elapsed ADC sequences

(forced interrupt). In formulas:

Proceed to Next Step in the ADC Sequence

Figure 16. ADC VLEDx Interrupt Sequence

T_{VLEDx_INT_Forced}+ LED_SEL_DUR[8 : 0] @ T_{ADC_SEQ}

(eq. 4)

All NCV78723 ADC registers data integrity is protected

by ODD parity on the bit 8 (that is to say the 9th bit if

counting from the LSbit named “0”). Please refer to the SPI

map section for further details.

In general, prior to the forced interrupt status,

the VLEDx ADC interrupts are generated when a falling

ON

edge on the control line for the buck channel “x” is detected

by the device. In case of digital dimming, this interrupt start

signal corresponds to the LEDCTRLx falling edge together

with a controlled phase delay (Table 6 −5 V Tolerant Digital

Inputs). The purpose of the phase delay is to allow

completion the ongoing ADC conversion before starting the

one linked to the VLEDx interrupt: if at the moment of the

conversion LEDCTRLx pin is logic high, then the updated

registers are VLEDxON[7:0] and VLEDx[7:0]; otherwise,

if LEDCTRLx pin is logic low, the only register refreshed is

VLEDx[7:0]. This mechanism is handled automatically by

the NCV78723 logic without need of intervention from the

user, thus drastically reducing the MCU cycles and

embedded firmware and CPU cycles overhead that would be

otherwise required.

Logic Supply Voltage ADC: V_DD

The logic supply voltage is sampled at VDD pin. The

(8-bit) conversion ratio is 4/255 (V/dec) = 0.0157 (V/dec)

typical. The converted value can be found in the SPI register

VDD[7:0], protected with ODD parity bit.

Boost Voltage ADC: V_BOOST

This measurement refers to the boost voltage at the

VBOOST pin, with an 8 bit conversion ratio of 70/255

(V/dec) = 0.274 (V/dec) typical, result can be found inside

the SPI register VBOOST[7:0]. The value is protected by

ODD parity bit. This measurement can be used by the MCU

for diagnostics and booster control loop monitoring.

To avoid loss of data linked to the ADC main sequence,

one LED channel is served at a time also when interrupt

requests from both channels are received in a row and a full

sequence is required to go through to enable a new interrupt

VLEDx. In addition, possible conflicts are solved by using

a defined priority (channel pre-selection). Out of reset, the

Device Temperature ADC: V_TEMP

By means of the VTEMP measurement, the MCU can

monitor the device junction temperature (T ) over time.

The conversion formula is:

J

T_J+ (VTEMP[7 : 0] * 50.5)ń0.805

(eq. 5)

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NCV78723

VTEMP[7:0] is the value read out directly from the

(latched). Once occurred, the thermal shutdown condition

is exited when the temperature drops below the thermal

warning level, thus providing hysteresis for thermal

shutdown recovery process. Outputs are re-enabled

automatically if BUCKx_TSD_AUT_RCRV_EN = 1, or

they are re-enabled by rising edge on BUCKx_EN if

BUCKx_TSD_AUT_RCRV_EN = 0. The application

thermal design should be made as such to avoid the

thermal shutdown in the worst case conditions. The

thermal shutdown level is not user programmable and is

factory trimmed (see ADC_TSD in Table 6 − Buck

Regulator – Switch).

related 8bit-SPI register (please refer to the SPI map).

The value is also used internally by the device for the

thermal warning and thermal shutdown functions. More

details on these two can be found in the dedicated sections

in this document. The value is protected by ODD parity bit.

LED String Voltages ADC: V_LEDx, V_LEDxON

The voltage at the pins VLEDx (1, 2) is measured. There

are 4 ranges available, that can be selected by means of

ADC_VLEDx_RNG_SEL[1:0] register, to obtain higher

resolution for LED voltage measurement.

Conversion ratios in dependency on selected range are:

• SPI Error: in case of SPI communication errors the

SPIERR bit in status register 0x14 is set. The bit is

latched. For more details, please refer to section “SPI

protocol: Framing and Parity Error”.

• Open LEDx String: individual open LED diagnostic flags

indicate whether the “x” string is detected open. The

detection is based on a counter overflow of typical 50 ms

when the related channel is activated. Both OPENLED1

and OPENLED2 flags (latched) are contained in status

register 0x13. Please note that the open detection does not

disable the buck channel(s).

• Short LEDx String: a short circuit detection is available

independently for each LED channel per means of the flag

SHORTLEDx (latched, status register 0x13). The

detection is based on the voltage measured at the VLEDx

pins via a dedicated internal comparator: when the

voltage drops below the VLED_LMT minimum

threshold (typical 1.8 V, see Table 6 − Buck Regulator –

Current Regulation) the related flag is set. Together with

the detection, a fixed TOFF is used. On N78723−2 device,

TOFF time is terminated immediately when the inductor

current reaches zero. This improves the dimming

behavior via external short switches (pixel control).

0x0: 70/255 (V/dec) = 0.274 (V/dec);

0x1: 50/255 (V/dec) = 0.196 (V/dec);

0x2: 40/255 (V/dec) = 0.157 (V/dec);

0x3: 30/255 (V/dec) = 0.118 (V/dec).

This information, found in registers VLEDxON[7:0] and

VLEDx[7:0], can be used by the MCU to infer about the

LED string status, for example, individual shorted LEDs. As

for the other ADC registers, the values are protected by

ODD parity.

Please note that in the case of constant LEDCTRLx inputs

and no dimming (in other words dimming duty cycle equals

to 0% or 100%) the VLEDx interrupt is forced with a rate

equal to T

, given in the ADC general

VLEDx_INT_forced

section. This feature can be exploited by MCU embedded

algorithm diagnostics to read the LED channels voltage

even when in OFF state, before module outputs activation

(module startup pre-check).

Diagnostics

The NCV78723 features a wide range of embedded

diagnostic features. Their description follows. Please also

refer to the previous SPI section for more details.

Diagnostic Description

• Overcurrent on Channel x: this diagnostics protects the

LEDx and the buck channel x electronics from

overcurrent. As the overcurrent is detected, the OCLEDx

flag (latched, status register 0x13) is raised and the related

buck channel is disabled. More details about the detection

mechanisms and parameters are given in section “Buck

Overcurrent Protection”.

• Buckx Status: register BUCKx_STATUS shows the

actual status of Buckx output. When BUCKx_STATUS is

1, the corresponding output regulates current to the LED.

• LEDCTRLx Pin Status: SPI registers LED1VAL resp.

LED2VAL indicate the actual logic level of the

debounced LEDCTRLx pins. These signals follow the

output of 200 ns digital debouncers implemented on

LEDCTRLx pins.

• Buckx Running at Minimum TON Time: register

BUCKx_MIN_TON (latched) indicates that minimal

TON time is detected on the corresponding channel. It is

clear by read flag. This information can be used for

• Thermal

Warning:

this

mechanism

detects

a user-programmable junction temperature which is in

principle close, but lower, to the chip maximum allowed,

thus providing the information that some action (power

de-rating) is required to prevent overheating that would

cause Thermal Shutdown. A typical power de-rating

technique consists in reducing the output dimming duty

cycle in function of the temperature: the higher the

temperature above the thermal warning, the lower the

duty cycle. The thermal warning flag (TW) is given in

status register 0x14 and is latched. When VTEMP[7:0]

raises to or above THERMAL_WARNING_THR[7:0]

threshold, the TW flag is set. At power up the default

thermal warning threshold is typically 159°C (SPI code

179).

• Thermal Shutdown: this safety mechanism intends to

protect the device from damage caused by overheating,

by disabling the both buck channels. The diagnostic is

displayed per means of the TSD bit in status register 0x14

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19

NCV78723

detection of transition period during which the BUCKx

output current decreases due to the change of

BUCKx_VTHR code or BUCKx_ISENS_THR range.

BUCKx_TON_DUR[7:0] register keeps the last

measured TON time.

• HW Reset: the out of reset condition is reported through

the HWR bit (latched). This bit is set only at each Power

On Reset (POR) and indicates the device is ready to

operate.

• Buckx

TON

Time

Duration:

SPI

register

BUCKx_TON_DUR[7:0] reflects the last measured

Buckx TON time (1LSB = 200 ns) on the corresponding

channel. When Buckx runs with TON time < typ. 200 ns,

the BUCKx_TON_DUR[7:0] SPI register returns value

A short summary table of the main diagnostic bits related

to the LED outputs follows.

0x00.

When

Buckx

is

stopped,

the

Table 7. LED OUTPUT DIAGNOSTIC SUMMARY

Diagnose

Flag

Description

Detection Level

LED Output

Latched

TW

Thermal Warning

SPI Register Programmable

Not Disabled

(If No TSD, otherwise Disabled)

Yes

TSD

Thermal Shutdown

Factory Trimmed

Disabled

(Automatically Re-Enabled when

Temp Falls below TW and

Yes

BUCKx_TSD_AUT_RCVR_EN = 1)

SPIERR

SPI Error

(See SPI Section)

Buck on Time > TON_OPEN

VLEDx < VLED_LMT

Not Disabled

Yes

OPENLEDx

SHORTLEDx

LED String Open Circuit

LED String Short Circuit

Not Disabled

(Fixed Buck TOFF or Zero Cross

TOFF Applied when output is On)

OCLEDx

LED String Overcurrent

Ibuckx > OCDR{1..4}

Mode = RESET (0)

Disabled

Yes

Transition Priority

(0) − Highest

(1)

(2)

TSD = 1 (1)

OFF

LED is Off

(3) − Lowest

OCLED = 1 or

BUCKx_EN = 0 (2)

OCLED = 0 and

BUCKx_EN = 1 (2)

DIMMING

NORMAL Mode: LED is On if LEDCTRLx = 1

FSO/STANDALONE Mode: LED is On

BUCKx_TSD_AUT_RCVR_EN = 1

or Rising Edge on BUCKx_EN

Detected (3)

TSD = 1 (1)

RECOVERY

TSD

LED is Off

(BUCKx_TSD_AUT_RCVR_EN = 1

or Rising Edge on BUCKx_EN Detected)

and (OCLED = 1 or BUCKx_EN = 0) (2)

VTEMP < THERMAL_WARNING_THR(1)

Figure 17. LED Dimming State Diagram

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NCV78723

Functional Mode Description

Overview of all functional modes is in accordance to the state diagram on Figure 18. Individual states are described below.

Transition Condition (Priority Level)

Action Executed when Transition is

Performed

Transition Priority:

(0) − Highest

(1)

POR (0)

(2) − Lowest

RESET

SPI Disabled

Dimming Disabled

HWR:=1

RSTB = 0 (1)

RSTB = 1 (1)

INIT

SPI Disabled

Dimming Disabled

OTP Refresh Ongoing

RSTB = 0 and

(FSO_MD = 000 or

001 or 110 or 111)

(1)

RSTB = 0 (1)

150 ms Timeout Expired

(2)

SPI Pre-Load from OTPs when

FSO_MD = 001 or 100 or 101

or 110 or 111

(FSO_MD = 110 or 111) and

OTP_CUST_LOCK = 1

(2)

SPI Pre-Load from OTPs

FSO:=1

NORMAL

SPI Enabled

Dimming: LEDCTRLx

RSTB = 0 and

(FSO_MD = 010 or 011

or 100 or 101) and

OTP_CUST_LOCK = 1

(2)

FSO_MD = 000 or 001

(2)

STANDALONE

SPI Disabled when

FSO_MD = 110

Dimming: BUCKx_EN

SPI Pre-Load from OTPs

FSO:=1

RSTB = 1 or

(FSO_MD = 000 or 001)

(1)

FSO

SPI Enabled when

FSO_MD = 010 or 100

Dimming: BUCKx_EN

Figure 18. Functional Modes State Diagram

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NCV78723

Reset

BUCKx_ISENS_TRIM[6:0] register is preloaded from

Asynchronous reset is caused either by POR (POR always

corresponding BUCKx_ISENS_RNG[6:0] register.

In FSO (entered via falling edge on RSTB pin) and

Stand-Alone modes, BUCK1_EN & BUCK2_EN are

controlled from SPI register map (SPI registers are updated

from OTP’s after entrance into these modes).

BUCK1_EN and BUCK2_EN are supposed to be set ‘1’

for the BUCKx operation in the FSO/stand-alone mode.

When control registers are pre-loaded from OTP’s after

POR and FSO mode is not entered (valid for FSO_MD[2:0]

= 100 or 101), BUCK1_EN and BUCK2_EN are kept

inactive (‘0’) until the first valid SPI operation is finished to

avoid potential activation of buck regulators immediately

after POR (to prevent undefined state of LEDCTRLx pins in

case MCU leaves POR later than NCV78723).

In FSO and Stand-Alone modes, the logic level at

LEDCTRLx pins is ignored and digital PWM dimming

with LEDCTRLx pins is not available. The outputs can be

dimmed only by means of BUCKx_EN register.

A falling edge on RSTB pin may trigger either entrance

into FSO mode or reset in dependency on FSO_MD[2:0]

register value. Please refer to Table 8 and Figure 18 for more

details.

causes asynchronous reset − transition to reset state) or by

falling edge on RSTB pin (in normal/stand-alone mode,

when FSO_MD[2:0] = 000 or 001 or 110 or 111).

Init and Normal Mode

Normal mode is entered through Init state after internal

delay of 150 ms. In Init state, OTP refresh is performed. If

OTP bits for FSO_MD[2:0] register and OTP Lock Bit are

programmed, transition to FSO/SA mode is possible.

FSO/Stand-Alone Mode

FSO (Fail-Safe Operation)/Stand-Alone modes can be

used for two main purposes:

• Default power-up operation of the chip (Stand-Alone

functionality without external microcontroller or

preloading of the registers with default content for default

operation before microcontroller starts sending SPI

commands for chip settings)

• Fail-Safe functionality (chip functionality definition in

fail-safe mode when the external microcontroller

functionality is not guaranteed)

Once FSO mode is entered via falling edge on RSTB pin,

reset function of RSTB pin is blocked until FSO mode is

exited. FSO mode can be exited by the rising edge on RSTB

pin or by writing FSO_MD[2:0] = 000 or 001 (possible only

in FSO modes, where SPI control register update is allowed:

FSO_MD[2:0] = 011 or 101).

FSO/stand-alone function is controlled according to

Table 8. Entrance into FSO/Stand-alone mode is possible

only after customer OTP zapping when OTP Lock Bit is set.

After FSO mode activation, the FSO bit in status register is

set. FSO register is cleared by read register.

When FSO/Stand-Alone mode is activated, content of the

following SPI registers is preloaded from OTP memory:

In stand-alone mode (FSO_MD[2:0] = 110 or 111), RSTB

has always reset functionality.

BUCK1_VTHR[7:0],

BUCK1_ISENS_THR[1:0],

BUCK2_VTHR[7:0],

BUCK2_ISENS_THR[1:0],

BUCK1_TOFF[4:0],

BUCK2_TOFF[4:0],

BUCK1_EN,

BUCK2_EN,

FSO_MD[2:0],

During entrance into FSO mode, value of FSO_MD[2:0]

SPI register (preloaded from OTP at power-up only) is

latched into internal register and all FSO related functions

are then controlled according to it. Purpose is to avoid the

reset of the device when FSO mode is active and

FSO_MD[2:0] is changed to value corresponding to

stand-alone mode, where RSTB pin has reset functionality.

The internal register is cleared after POR or when FSO mode

is exited.

BUCK1_TSD_AUT_RCVR_EN,

BUCK2_TSD_AUT_RCVR_EN,

BUCKx_OC_OCCMP_THR[1:0]].

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NCV78723

RSTB in Normal or Stand-Alone Mode

PORB

(Internal)

RSTB

Normal Mode

(SPI Possible)

Reset

Mode

Reset Mode (No SPI)

Normal Mode

Power-Up

Possible OTP Pre-Load

RSTB iN FSO Mode

PORB

(Internal)

RSTB

Normal Mode

(SPI Possible)

FSO Mode

(SPI Possible/No SPI)

FSO

Mode

Normal Mode

Power-Up

OTP Pre-Load

Figure 19. RSTB Pin Functionality in Normal, Stand-Alone and FSO Modes

Table 8. FSO MODES

FSO_MD[2:0]

Description

000 = 0

FSO Mode Disabled, Registers are Loaded with Safe Value = 0x00h after POR, Default

b

• After the reset, control registers are loaded with 0x00h value.

• Entrance into FSO mode is not possible unless dedicated SPI write command to change FSO_MD[2:0] value is

sent

• RSTB pin has reset functionality

• LEDCTRLx pins are functional (buck enable/disable, digital PWM dimming available)

001 = 1

FSO Mode Disabled, Registers are Loaded with Data from OTP Memory after POR

b

• After the reset, control registers are loaded with data stored in OTP memory (device’s OTP memory has to be

programmed, OTP Lock Bit has to be set). It reduces number of SPI transfers needed to configure the device

after the reset.

• Entrance into FSO mode is not possible

• RSTB pin has reset functionality

• LEDCTRLx pins are functional (buck enable/disable, digital PWM dimming available)

010 = 2

FSO Entered after Falling Edge on RSTB Pin, Registers (except FSO_MD[2:0]) are Loaded with

Safe Value = 0x00h after POR

b

• After FSO mode activation, control registers are loaded with data stored in OTP memory.

• SPI register update (SPI write/read operation) in FSO mode is disabled (SPI write operation is blocked; clearing

of SPI registers is blocked; in case of invalid SPI frame, SPIERR flag is set).

• RSTB pin serves to enter/exit FSO mode.

• LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM

dimming not available).

011 = 3

FSO Entered after Falling Edge on RSTB Pin, Registers (except FSO_MD[2:0]) are Loaded with

Safe Value = 0x00h after POR

b

• After FSO mode activation, control registers are loaded with data stored in OTP memory.

• SPI register update (SPI write/read operation) in FSO mode is enabled

• FSO mode can be exited by writing FSO_MD[2:0] = 000 or 001

• RSTB pins serves to enter/exit FSO mode.

• LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM

dimming not available).

100 = 4

FSO Entered after Falling Edge on RSTB Pin, Registers are Loaded with Data from OTP Memory after POR

b

• After FSO mode activation, control registers are loaded with data stored in OTP memory.

• SPI register update (SPI write/read operation) in FSO mode is disabled (SPI write operation is blocked; clearing

of SPI registers is blocked; in case of invalid SPI frame, SPIERR flag is set).

• RSTB pin serves to enter/exit FSO mode.

• LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM

dimming not available).

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NCV78723

Table 8. FSO MODES (continued)

FSO_MD[2:0]

Description

101 = 5

FSO Entered after Falling Edge on RSTB Pin, Registers are Loaded with Data from OTP Memory after POR

b

• After FSO mode activation, control registers are loaded with data stored in OTP memory.

• SPI register update (SPI write/read operation) in FSO mode is enabled

• FSO mode can be exited by writing FSO_MD[2:0] = 000 or 001

• RSTB pin serves to enter/exit FSO mode.

• LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM

dimming not available).

110 = 6

SA (Stand-Alone)/FSO Entered after POR (RSTB Pin Rising Edge), Registers are Loaded with Data from

OTP Memory

b

• After FSO/SA mode activation, control registers are loaded with data from OTP memory

• SPI register update (SPI write/read operation) in SA/FSO mode is disabled (SPI write operation is blocked;

clearing of SPI registers is blocked; in case of invalid SPI frame, SPIERR flag is set).

• RSTB pin has reset functionality

• LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM

dimming not available).

111 = 7

SA (Stand-Alone)/FSO Entered after POR (RSTB Pin Rising Edge), Registers are Loaded with Data from

OTP Memory

b

• After SA/FSO mode activation, control registers are loaded with data from OTP memory

• SPI register update (SPI write/read operation) in SA/FSO mode is enabled

• FSO mode can be exited by writing FSO_MD[2:0] = 000 or 001

• RSTB pin has reset functionality

• LEDCTRLx pins are not functional (buck enable/disable only by means of BUCKx_EN SPI/OTP bits, digital PWM

dimming not available).

SPI Interface

General

A slave or chip select line (CSB) allows individual

The serial peripheral interface (SPI) is used to allow

an external microcontroller (MCU) to communicate

with the device. NCV78723 acts always as a slave and it

cannot initiate any transmission. The operation of the device

is configured and controlled by means of SPI registers,

which are observable for read and/or write from the master.

The NCV78723 SPI transfer size is 16 bits.

During an SPI transfer, the data is simultaneously

transmitted (shifted out serially) and received (shifted in

serially). A serial clock line (SCLK) synchronizes shifting

and sampling of the information on the two serial data lines:

SDO and SDI. The SDO signal is the output from the Slave

(NCV78723), and the SDI signal is the output from the

Master.

selection of a slave SPI device in a time multiplexed

multiple-slave system.

The CSB line is active low. If an NCV78723 is not

selected, SDO is in high impedance state and it does not

interfere with SPI bus activities. Since the NCV78723

always clocks data out on the falling edge and samples data

in on rising edge of clock, the MCU SPI port must be

configured to match this operation.

The implemented SPI allows connection to multiple

slaves by means of star connection (CSB per slave) or by

means of daisy chain.

An SPI star connection requires a bus = (3 + N) total lines,

where N is the number of Slaves used, the SPI frame length

is 16 bits per communication.

MOSI

MCU

(SPI Master)

NCV78723 Dev#1

(SPI Slave)

SDO1

MISO

(SPI Slave)

SCB1

SCB2

SDI2

MCU

(SPI Master)

NCV78723 Dev#2

(SPI Slave)

NCV78723 Dev#2

(SPI Slave)

SDO2

SDIN

SCBN

NCV78723 Dev#N

(SPI Slave)

NCV78723 Dev#N

(SPI Slave)

SDON

Figure 20. SPI Star vs. Daisy Chain Connection

SPI Daisy Chain Mode

SPI daisy chain connection bus width is always four lines

independently on the number of slaves. However, the SPI

transfer frame length will be a multiple of the base frame

length so N × 16 bits per communication: the data will be

interpreted and read in by the devices at the moment the CSB

rises.

A diagram showing the data transfer between devices in

daisy chain connection is given further: CMDx represents

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NCV78723

the 16-bit command frame on the data input line transmitted

Device in the same time replies to the master (on the

by the Master, shifting via the chips’ shift registers through

the daisy chain. The chips interpret the command once the

chip select line rises.

SDO):

• If the previous command was a write and no SPI error had

occurred, a copy of the command, address and data

written fields,

• If the previous command was a read, the response frame

summarizes the address used and an overall diagnostic

check (copy of the main detected errors, see Figures 22

and 23 for details),

Commands in the Shift Registers

are Executed on Rising Edge of CS

CS

16

Cycles

16

Cycles

16

Cycles

SCLK

CMD1

x

CMD2

CMD1

CMD3

CMD2

DIN

1

• In case of previous SPI error or after power-on-reset, only

DOUT

1

the MSB bit will be 1, followed by zeros.

DIN

2

If parity bit in the frame is wrong, device will not perform

command and <SPI> flag will be set.

1

DOUT

2

3

x

CMD1

x

DIN

3

DOUT

The frame protocol for the read operation:

Figure 21. SPI Daisy Chain Data Shift between

Slaves. The Symbol ‘x’ Represents the Previous

Content of the SPI Shift Register Buffer

Read; CMD = ‘0’

High

LED1

LED2

BUCKOC

=

OPENLED1 or SHORTLED1

OPENLED2 or SHORTLED2

= OCLED1 or OCLED2

Low

−> immediate value of STATUS BITS;

Dedicated SPI READ Command of the

STATUS Register has to be performed to

clear the value of read−by−clear STATUS

bits

The NCV78723 default power up communication mode

is “star”. In order to enable daisy chain mode, a multiple of

16 bits clock cycles must be sent to the devices, while the

SDI line is left to zero.

C

M

D

A

4

A

3

A

2

A

1

A

0

SDI

P

Low

S

P

I

E

R

B

U

C

K

O

C

L

E

D

2

L

E

D

1

Data from address A [4:0]

shall be returned

T

S

D

D D D D D D D D D D

T

W

SDO

9

8 7 6 5 4 3 2 1 0

NOTE: To come back to star mode the NOP register (address

0x0000) must be written with all ones, with the proper data

parity bit and parity framing bit: see SPI protocol for details

about parity and write operation.

HIGH−Z

SCLK

Low

SPI Transfer Format

P = not(CMD xor A4 xor A3 xor A2 xor A1 xor A0)

Two types of SPI commands (to SDI pin of NCV78723)

from the micro controller can be distinguished: “Write to

a control register” and “Read from register (control or

status)”.

Figure 23. SPI Read Frame

Referring to the previous picture, the read frame coming

from the master (into the SDI) is composed from the

following fields:

The frame protocol for the write operation:

• Bit[15] (MSB): CMD bit = 0 for read operation,

• Bits[14:10]: 5 bits READ ADDRESS field,

Write; CMD = ‘1’

Low

High

• Bit[10]: frame parity bit. It is ODD parity formed by the

negated XOR of all other bits in the frame,

• Bits [8:0]: 9 bits zeroes field.

C

M

D

A A A A

D D D D D D D D D D

SDI

P

3

2

1

0

9 8 7 6 5 4 3 2 1 0

Low

S

P

I

E

R

Previous SPI WRITE command

resp. “SPIERR + 0x000hex”

after POR or SPI Command

C

M

D

A A A A D D D D D D D D D D

Device in the same frame provides to the master (on the

SDO) data from the required address (in frame response),

thus achieving the lowest communication latency.

SDO

3

2

1

0

9

8

7

6

5

4

3

2

1

0

HIGH

PARITY/FRAMING Error

−Z

S

P

I

E

R

B

U

C

K

O

C

M

D

L

E

D

2

L

E

D

1

T

S

D

A A A A A

Previous SPI READ command

& NCV78723 status bits resp.

“SPIERR + 0x000hex” after

POR or SPI Command

T

W

P0 1

1

4

3 2 1 0

SPI Framing and Parity Error

SCLK

Low

PARITY/FRAMING Error

SPI communication framing error is detected by the

NCV78723 in the following situations:

P

= not(CMD xor A3 xor A2 xor A1 xor A0 xor D9 xor D8 xor D7 xor

D6 xor D5 xor D4 xor D3 xor D2 xor D1 xor D0)

• Not an integer multiple of 16 CLK pulses are received

during the active-low CSB signal;

• LSB bits (8..0) of a read command are not all zero;

• SPI parity errors, either on write or read operation.

Figure 22. SPI Write Frame

Referring to the previous picture, the write frame coming

from the master (into the SDI) is composed from the

following fields:

• Bit[15] (MSB): CMD bit = 1 for write operation,

Once an SPI error occurs, the <SPI> flag can be reset only

by reading the status register in which it is contained (using

in the read frame the right communication parity bit).

• Bits[14:11]: 4 bits WRITE ADDRESS field,

• Bit[10]: frame parity bit. It is ODD parity formed by the

negated XOR of all other bits in the frame,

• Bits[9:0]: 10 bit DATA to write

www.onsemi.com

25

NCV78723

SPI ADDRESS MAP

Table 9. NCV78723 SPI ADDRESS MAP

ADDR

0x00

0x01

0x02

0x03

0x04

R/W

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

NA

NOP Register (Read/Write Operation Ignored)

BUCK1_VTHR[7:0]

R/W

BUCK1_ISENS_THR[1:0]

BUCK2_ISENS_THR[1:0]

BUCK2_VTHR[7:0]

BUCK1_TOFF[4:0]

BUCK2_TOFF[4:0]

BUCK1_OFF_ BUCK2_OFF_

CMP_DIS

(Note 31)

DRV_

SLOW_EN

(Note 31)

BUCKx_OC_OCCMP_

THR[1:0]

FSO_MD[2:0]

BUCK1_EN

BUCK2_EN

CMP_DIS

(Note 31)

0x05

0x06

R/W

BUCK1_

TSD_AUT_

RCVR_EN

BUCK2_

TSD_AUT_

RCVR_EN

THERMAL_WARNING_THR[7:0]

VTEMP_

OFF_COMP

ODD PAR

(Note 30)

LED_SEL_DUR[8:0]

0x07

0x08

0x09

R/W

VTEMP_OFF_COMP[2:0] (Note 30)

VTEMP_OFF_COMP[5:3] (Note 30)

BUCK1_ISENS_TRIM[6:0]

BUCK2_ISENS_TRIM[6:0]

OTP_BIAS_H OTP_BIAS_L OTP_ADDR[1:0]

ADC_VLED1_RNG_

SEL[1:0]

ADC_VLED2_RNG_

SEL[1:0]

OTP_OPERATION[1:0]

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

R

0x0

ODD PARITY

VLED1ON[7:0]

VLED2ON[7:0]

VLED1[7:0]

VLED2[7:0]

VTEMP[7:0]

VBOOST[7:0]

VDD[7:0]

ODD PARITY

BUCK1_TON_DUR[7:0]

BUCK2_TON_DUR[7:0]

0x0

OPENLED1

SHORTLED1

LED1VAL

OCLED1

LED2VAL

OPENLED2

SPIERR

SHORTLED2

TSD

OCLED2

TW

OTP_FAIL

FSO

0x0

HWR

OTP_

ACTIVE

BUCK1_

MIN_TON

BUCK2_

MIN_TON

BUCK1_

STATUS

BUCK2_

STATUS

0x16

0x17

R

0x0

ODD PARITY

0x0

BUCK1_ISENS_RNG[6:0]

BUCK2_ISENS_RNG[6:0]

0x18

BUCK2_ISENS_D1[3:0]

BUCK2_ISENS_D2[3:0]

BUCK2_ISENS_D3[3:0]

BUCK_ISENS_TC1[3:0]

BUCK_ISENS_TC3[3:0]

BUCK1_ISENS_D1[3:0]

BUCK1_ISENS_D2[3:0]

BUCK1_ISENS_D3[3:0]

BUCK_ISENS_TC0[3:0]

BUCK_ISENS_TC2[3:0]

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

OTHER

0x0

OTP_DATA[9:0]

TC_VERSION

0x0

REVID[7:0]

0x0

30.Read Only.

31.Available only on N78723−2 device.

www.onsemi.com

26

NCV78723

Table 10. BIT DEFINITION

Symbol

MAP Position

Description

REGISTER 0X00 (CR): NOP REGISTER, RESET VALUE (POR) = 0000000000

2

NOP

Bits [9:0] – ADDR_0x00

NOP Register (Read/Write Operation Ignored)

REGISTER 0X01 (CR): BUCK 1 PEAK CURRENT SETTINGS, RESET VALUE (POR) = 0000000000

2

BUCK1_ISENS_THR[1:0]

BUCK1_VTHR[7:0]

Bits [9:8] – ADDR_0x01

Bits [7:0] – ADDR_0x01

Peak Current: Selection of the Range 1, 2, 3 or 4

Peak Current Comparator Threshold Value

REGISTER 0X02 (CR): BUCK 2 PEAK CURRENT SETTINGS, RESET VALUE (POR) = 0000000000

2

BUCK2_ISENS_THR[1:0]

BUCK2_VTHR[7:0]

Bits [9:8] – ADDR_0x02

Bits [7:0] – ADDR_0x02

Peak Current: Selection of the Range 1, 2, 3 or 4

Peak Current Comparator Threshold Value

REGISTER 0X03 (CR): BUCK 1 AND 2 TOFF SETTINGS, RESET VALUE (POR) = 0000000000

2

BUCK1_TOFF[4:0]

BUCK2_TOFF[4:0]

Bits [9:5] – ADDR_0x03

Bits [4:0] – ADDR_0x03

Buck 1 TOFF·VLED Constant Settings

Buck 2 TOFF·VLED Constant Settings

REGISTER 0X04 (CR): BUCK SETTINGS, RESET VALUE (POR) = 0000000000

2

BUCK1_OFF_CMP_DIS

BUCK2_OFF_CMP_DIS

DRV_SLOW_EN

Bit 9 – ADDR_0x04

Bit 8 – ADDR_0x04

Bit 7 – ADDR_0x04

Bits [6:5] – ADDR_0x04

Bits [4:2] – ADDR_0x04

Bit 1 – ADDR_0x04

Bit 0 – ADDR_0x04

Buck 1 Offset Cancellation Disable

Buck 2 Offset Cancellation Disable

Slow Driver Slope Enable

BUCKx_OC_OCCMP_THR[1:0]

FSO_MD[2:0]

Overcurrent Detection Settings

FSO Mode Selection

BUCK1_EN

Buck Regulator Channel 1 Enable Bit

Buck Regulator Channel 2 Enable Bit

BUCK2_EN

REGISTER 0X05 (CR): BUCK SETTINGS, RESET VALUE (POR) = 0010110011

2

BUCK1_TSD_AUT_RCVR_EN

BUCK2_TSD_AUT_RCVR_EN

THERMAL_WARNING_THR[7:0]

Bit 9 – ADDR_0x05

Bit 8 – ADDR_0x05

Bits [7:0] – ADDR_0x05

Buck 1 Automatic Recovery after TSD

Buck 2 Automatic Recovery after TSD

Thermal Warning Threshold Settings

REGISTER 0X06 (CR): BUCK SETTINGS, RESET VALUE (POR) = X000000000

2

VTEMP_OFF_COMP ODD PAR.

LED_SEL_DUR[8:0]

Bit 9 – ADDR_0x06

ADC VTEMP Trimming Parity Bit

VLED Measurement Settings

Bits [8:0] – ADDR_0x06

REGISTER 0X07 (CR): BUCK SETTINGS, RESET VALUE (POR) = XXX0000000

2

VTEMP_OFF_COMP[2:0]

BUCK1_ISENS_TRIM[6:0]

Bits [9:7] – ADDR_0x07

Bits [6:0] – ADDR_0x07

ADC VTEMP Trimming

Compensation of the Buck 1 Peak Current

REGISTER 0X08 (CR): BUCK SETTINGS, RESET VALUE (POR) = XXX0000000

2

VTEMP_OFF_COMP[5:3]

BUCK2_ISENS_TRIM[6:0]

Bits [9:7] – ADDR_0x08

Bits [6:0] – ADDR_0x08

ADC VTEMP Trimming

Compensation of the Buck 2 Peak Current

REGISTER 0X09 (CR): BUCK SETTINGS, RESET VALUE (POR) = 0000000000

2

ADC_VLED1_RNG_SEL[1:0]

ADC_VLED2_RNG_SEL[1:0]

OTP_BIAS_H

Bits [9:8] – ADDR_0x09

Bits [7:6] – ADDR_0x09

Bit 5 – ADDR_0x09

Range Select for VLED ADC, Channel 1

Range Select for VLED ADC, Channel 2

OTP Bias High

OTP_BIAS_L

Bit 4 – ADDR_0x09

OTP Bias Low

OTP_ADDR[1:0]

Bits [3:2] – ADDR_0x09

Bits [1:0] – ADDR_0x09

OTP Address

OTP_OPERATION[1:0]

OTP Operation

REGISTER 0X0A (SR): VLED1ON, RESET VALUE (POR) = 0100000000

2

ODD PARITY

VLED1ON[7:0]

Bit 8 – ADDR_0x0A

Odd Parity over Data

Output of VLED 1 ADC

Bits [7:0] – ADDR_0x0A

REGISTER 0X0B (SR): VLED2ON, RESET VALUE (POR) = 0100000000

2

ODD PARITY

VLED2ON[7:0]

Bit 8 – ADDR_0x0B

Odd Parity over Data

Output of VLED 2 ADC

Bits [7:0] – ADDR_0x0B

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27

NCV78723

Table 10. BIT DEFINITION (continued)

Symbol

MAP Position

Description

REGISTER 0X0C (SR): VLED1, RESET VALUE (POR) = 0100000000

2

ODD PARITY

VLED1[7:0]

Bit 8 – ADDR_0x0C

Odd Parity over Data

Output of VLED 1 ADC

Bits [7:0] – ADDR_0x0C

REGISTER 0X0D (SR): VLED2, RESET VALUE (POR) = 0100000000

2

ODD PARITY

VLED2[7:0]

Bit 8 – ADDR_0x0D

Odd Parity over Data

Output of VLED 2 ADC

Bits [7:0] – ADDR_0x0D

REGISTER 0X0E (SR): VTEMP, RESET VALUE (POR) = 0XXXXXXXXX

2

ODD PARITY

VTEMP[7:0]

Bit 8 – ADDR_0x0E

Odd Parity over Data

Output of VTEMP ADC

Bits [7:0] – ADDR_0x0E

REGISTER 0X0F (SR): VBOOST, RESET VALUE (POR) = 0XXXXXXXXX

2

ODD PARITY

VBOOST[7:0]

Bit 8 – ADDR_0x0F

Odd Parity over Data

Bits [7:0] – ADDR_0x0F

Output of VBOOST ADC

REGISTER 0X10 (SR): VDD, RESET VALUE (POR) = 0XXXXXXXXX

2

ODD PARITY

VDD[7:0]

Bit 8 – ADDR_0x10

Odd Parity over Data

Output of VDD ADC

Bits [7:0] – ADDR_0x10

REGISTER 0X11 (SR): BUCK1_TON_DUR, RESET VALUE (POR) = 0100000000

2

ODD PARITY

Bit 8 – ADDR_0x11

Odd Parity over Data

Buck 1 Ton Duration

BUCK1_TON_DUR[7:0]

Bits [7:0] – ADDR_0x11

REGISTER 0X12 (SR): BUCK2_TON_DUR, RESET VALUE (POR) = 0100000000

2

ODD PARITY

Bit 8 – ADDR_0x12

Odd Parity over Data

Buck 2 Ton Duration

BUCK2_TON_DUR[7:0]

Bits [7:0] – ADDR_0x12

REGISTER 0X13 (SR): BUCK DIAGNOSTICS, RESET VALUE (POR) = 0X000X00X0

2

ODD PARITY

OPENLED1

SHORTLED1

OCLED1

Bit 8 – ADDR_0x13

Bit 5 – ADDR_0x13

Bit 4 – ADDR_0x13

Bit 3 – ADDR_0x13

Bit 2 – ADDR_0x13

Bit 1 – ADDR_0x13

Bit 0 – ADDR_0x13

Odd Parity over Data

Buck 1 Open LED Flag, Latched

Buck 1 Short LED Flag, Latched

Buck 1 Overcurrent Flag, Latched

Buck 2 Open LED Flag, Latched

Buck 2 Short LED Flag, Latched

Buck 2 Overcurrent Flag, Latched

OPENLED2

SHORTLED2

OCLED2

REGISTER 0X14 (SR): BUCK DIAGNOSTICS, RESET VALUE (POR) = 0X001XXXXX

2

ODD PARITY

OTP_FAIL

FSO

Bit 8 – ADDR_0x14

Bit 7 – ADDR_0x14

Bit 6 – ADDR_0x14

Bit 5 – ADDR_0x14

Bit 4 – ADDR_0x14

Bit 3 – ADDR_0x14

Bit 2 – ADDR_0x14

Bit 1 – ADDR_0x14

Bit 0 – ADDR_0x14

Odd Parity over Data

OTP Failure Flag, Latched

Chip being in FSO Mode Flag, Non-Latched

Hardware Reset Flag, Latched

HWR

LED1VAL

LED2VAL

SPIERR

TSD

Actual Status of LEDCTRL1 Pin, Non-Latched

Actual Status of LEDCTRL2 Pin, Non-Latched

SPI Error Flag, Latched

Thermal Shutdown Flag, Latched

Thermal Warning Flag, Latched

TW

REGISTER 0X15 (SR): BUCK DIAGNOSTICS, RESET VALUE (POR) = 0100000000

2

ODD PARITY

Bit 8 – ADDR_0x15

Bit 4 – ADDR_0x15

Bit 3 – ADDR_0x15

Bit 2 – ADDR_0x15

Bit 1 – ADDR_0x15

Bit 0 – ADDR_0x15

Odd Parity over Data

OTP_ACTIVE

OTP Active Flag, Non-Latched

BUCK1_MIN_TON

BUCK2_MIN_TON

BUCK1_STATUS

BUCK2_STATUS

Minimal Ton Detected on Buck 1, Latched

Minimal Ton Detected on Buck 2, Latched

Actual Status of Buck 1 Regulator, Non-Latched

Actual Status of Buck 2 Regulator, Non-Latched

www.onsemi.com

28

NCV78723

Table 10. BIT DEFINITION (continued)

Symbol

MAP Position

Description

REGISTER 0X16: BUCK TRIMMING, RESET VALUE (POR) = 0X0XXXXXXX

2

ODD PARITY

Bit 8 – ADDR_0x16

Odd Parity over Data

BUCK1_ISENS_RNG[6:0]

Bits [6:0] – ADDR_0x16

Trimming Constant for Highest Range on Hot for Buck 1 Peak

Current

REGISTER 0X17: BUCK TRIMMING, RESET VALUE (POR) = 0X0XXXXXXX

2

ODD PARITY

Bit 8 – ADDR_0x17

Odd Parity over Data

BUCK2_ISENS_RNG[6:0]

Bits [6:0] – ADDR_0x17

Trimming Constant for Highest Range on Hot for Buck 2 Peak

Current

REGISTER 0X18: BUCK TRIMMING, RESET VALUE (POR) = 0XXXXXXXXX

2

ODD PARITY

Bit 8 – ADDR_0x18

Odd Parity over Data

BUCK2_ISENS_D1[3:0]

BUCK1_ISENS_D1[3:0]

Bits [7:4] – ADDR_0x18

Bits [3:0] – ADDR_0x18

Delta Trimming Constant for Buck 2 Peak Current

Delta Trimming Constant for Buck 1 Peak Current

REGISTER 0X19: BUCK TRIMMING, RESET VALUE (POR) = 0XXXXXXXXX

2

ODD PARITY

Bit 8 – ADDR_0x19

Odd Parity over Data

BUCK2_ISENS_D2[3:0]

BUCK1_ISENS_D2[3:0]

Bits [7:4] – ADDR_0x19

Bits [3:0] – ADDR_0x19

Delta Trimming Constant for Buck 2 Peak Current

Delta Trimming Constant for Buck 1 Peak Current

REGISTER 0X1A: BUCK TRIMMING, RESET VALUE (POR) = 0XXXXXXXXX

2

ODD PARITY

Bit 8 – ADDR_0x1A

Odd Parity over Data

BUCK2_ISENS_D3[3:0]

BUCK1_ISENS_D3[3:0]

Bits [7:4] – ADDR_0x1A

Bits [3:0] – ADDR_0x1A

Delta Trimming Constant for Buck 2 Peak Current

Delta Trimming Constant for Buck 1 Peak Current

REGISTER 0X1B: BUCK TRIMMING, RESET VALUE (POR) = 0XXXXXXXXX

2

ODD PARITY

Bit 8 – ADDR_0x1B

Odd Parity over Data

BUCK_ISENS_TC1[3:0]

BUCK_ISENS_TC0[3:0]

Bits [7:4] – ADDR_0x1B

Bits [3:0] – ADDR_0x1B

Temperature Coefficient Trimming Constant for Buck Peak Current

REGISTER 0X1C: BUCK TRIMMING, RESET VALUE (POR) = 0XXXXXXXXX

2

ODD PARITY

Bit 8 – ADDR_0x1C

Odd Parity over Data

BUCK_ISENS_TC3[3:0]

BUCK_ISENS_TC2[3:0]

Bits [7:4] – ADDR_0x1C

Bits [3:0] – ADDR_0x1C

Temperature Coefficient Trimming Constant for Buck Peak Current

REGISTER 0X1D: BUCK TRIMMING, RESET VALUE (POR) = 0X0000000X

2

ODD PARITY

TC_VERSION

Bit 8 – ADDR_0x1D

Bit 0 – ADDR_0x1D

Odd Parity over Data

Usage of BUCK_ISENS_TCx[3:0] Constants

REGISTER 0X1E: OTP DATA, RESET VALUE (POR) = 0000000000

2

OTP_DATA[9:0]

Bits [9:0] – ADDR_0x1E

OTP Data

REGISTER 0X1F: REVID, RESET VALUE (POR) = 00000XXXXXXX

2

REVID[7:0]

Bits [7:0] – ADDR_0x1F

Revision ID

POR values of status registers are shown in situation that

FSO mode is not entered after POR. All latched flags are

“cleared by read”. ‘x’ means that value after reset is defined

during reset phase (diagnostics) or is trimmed during

manufacturing process.

• SPI_REVID[4:3]: Full Mask Version <0 to 3>

• SPI_REVID[2]: N78723−0/N78723−2 Distinguishing

Bit (REVID[2] = 0 means N78723−0)

• SPI_REVID[1:0]: Metal Tune <0 to 3>

SPI register SPI_REVID[7:0] is used to track the silicon

version, following encoding mechanism is used:

REVID[7:0] for N78723−0 device is 11hex (723 = 0,

Full Mask Version = 2, N78723−0 = 0, Metal Tune = 1)

• SPI_REVID[7:6]: Constant 00 [binary]

REVID[7:0] for N78723−2 device is 14hex (723 = 0,

Full Mask Version = 2, N78723−2 = 1, Metal Tune = 0)

• SPI_REVID[5]: 713/723 Distinguishing Bit

(REVID[5] = 0 means 723)

www.onsemi.com

29

NCV78723

OTP MEMORY

Description

The OTP (Once Time Programmable) memory contains

40 bits which bear the most important application dependant

parameters and is user programmable via SPI interface.

The programming of these bits is typically done at the end

of the module manufacturing line.

OTP memory serves to store configuration data for

Fail-Safe or Stand-Alone functionality or default

configuration of the chip after power-up.

Table 11) and OTP Lock Bit are programmed into OTP

memory. OTP Zap operation is allowed to be performed

only once − when OTP Lock Bit is unprogrammed

SPI status bit OTP_ACTIVE is set to “log. 1” when an

OTP operation is in progress.

OTP Programming Procedure

Following procedure should be applied to program OTP

memory:

• VBOOST voltage has to be in range between 15 V and

20 V with current capability at least 50 mA

• VDD voltage has to be kept in range for normal mode

operation

• The junction temperature has to stay in range from 0°C to

125°C during OTP programming

• SPI registers listed in Table 11 have to be written with

required content

The OTP bits can be programmed only once, this is

ensured by dedicated OTP Lock Bit which is set during

programming.

Table 11. OTP MAP

OTP Bits

OTP[7:0]

Connection to SPI Register

BUCK1_VTHR[7:0]

OTP[9:8]

BUCK1_ISENS_THR[1:0]

BUCK2_VTHR[7:0]

OTP[17:10]

OTP[19:18]

OTP[24:20]

OTP[29:25]

OTP[30]

BUCK2_ISENS_THR[1:0]

BUCK1_TOFF[4:0]

• Content of the SPI registers (those listed in Table 11) is

programmed

into

the

OTP

memory

by

BUCK2_TOFF[4:0]

OTP_OPERATION[1:0] = 0x2 SPI write command.

OTP Lock Bit is programmed automatically at the same

time to prevent any further OTP programming

BUCK1_EN

OTP[31]

BUCK2_EN

OTP[34:32]

OTP[35]

FSO_MD[2:0]

OTP Programming Verification

BUCK1_TSD_AUT_RCR_EN

BUCK2_TSD_AUT_RCR_EN

BUCKx_OC_OCCMP_THR[1:0]

OTP Lock Bit

OTP_FAIL bit in the SPI status register is set when

VBOOST under-voltage (see OTP_UV parameter) is

detected during OTP Zap operation. It is clear by read flag.

The OTP_BIAS_H and OTP_BIAS_L registers are used

to check proper OTP programming. After OTP

programming, the OTP content has to be the same as

programmed when OTP is read with OTP_BIAS_H = 1 and

OTP_BIAS_L = 1.

OTP[36]

OTP[38:37]

OTP[39]

The OTP bits addressed by SPI register OTP_ADDR[1:0]

are accessible (read only) in the SPI register

OTP_DATA[9:0] after OTP Refresh operation

(OTP_OPERATION[1:0] = 0x1) in the following way:

Following procedure should be applied to verify OTP

content:

OTP_ADDR[1:0] = 0x0: OTP_DATA[9:0] = OTP[9:0]

OTP_ADDR[1:0] = 0x1: OTP_DATA[9:0] = OTP[19:10]

OTP_ADDR[1:0] = 0x2: OTP_DATA[9:0] = OTP[29:20]

OTP_ADDR[1:0] = 0x3: OTP_DATA[9:0] = OTP[39:30]

• VDD voltage has to be kept in range for normal mode

operation

• Write

SPI

registers

OTP_BIAS_L = 1 and

OTP_BIAS_H = 0

OTP Operations

The NCV78723 supports following operations with OTP

memory:

• OTP_OPERATION[1:0] = 0x0 or 0x3:

NOP (no operation)

• Write SPI register OTP_OPERATION[1:0] = 0x1 (OTP

Refresh) for all OTP_ADDR[1:0] values and check

corresponding OTP_DATA[9:0] content which has to

match with previously programmed data

• Write

SPI

registers

OTP_BIAS_L = 0 and

• OTP_OPERATION[1:0] = 0x1:

OTP_BIAS_H = 1

OTP Refresh – refresh of the whole OTP memory

• Write SPI register OTP_OPERATION[1:0] = 0x1 (OTP

Refresh) for all OTP_ADDR[1:0] values and check

corresponding OTP_DATA[9:0] content which has to

match with previously programmed data

(40 bits).

Data

addressed

by

SPI

register

OTP_ADDR[1:0] are available in SPI register

OTP_DATA[9:0] after the end of OTP Refresh operation

• OTP_OPERATION[1:0] = 0x2:

• Programming is considered as successful when no

OTP Zap – data from SPI register (those listed in

mismatch is observed

www.onsemi.com

30

NCV78723

Table 12. ORDERING INFORMATION

†

Device**

Marking

Package*

Shipping

NCV78723MW0CR2G

N78723−0

N78723−2

QFN24 5 × 5 with Wettable Flank

5,000 / Tape & Reel

(Pb-Free)

NCV78723MW0R2G

NCV78723MW2R2G

QFN24 5 × 5 with Wettable Flank

(Pb-Free)

QFNW24 5 × 5 with Step-cut Wettable Flank

(Pb-Free)

**NCV78723MW2 & NCV78723MW0 have different package mold compound. Please contact ON Semiconductor for technical details.

*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

31

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFNW24 5x5, 0.65P

CASE 484AF

ISSUE A

DATE 07 AUG 2018

24

1

SCALE 2:1

D

A

B

NOTES:

L3

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

LOCATION

L

DETAIL A

ALTERNATE

CONSTRUCTION

E

MILLIMETERS

DIM MIN

NOM

0.85

−−−

0.20 REF

−−−

0.30

5.00

3.50

5.00

3.50

MAX

0.90

0.05

A

A1

A3

A4

b

D

D2

E

0.80

−−−

EXPOSED

COPPER

TOP VIEW

A4

A1

0.10

0.25

4.90

3.40

4.90

3.40

−−−

0.35

5.10

3.60

5.10

3.60

DETAIL B

0.10

0.08

C

PLATING

A1

A4

C

ALTERNATE

CONSTRUCTION

A

E2

e

C

A3

DETAIL B

0.65 BSC

0.35 REF

0.40

SEATING

PLANE

A1

C

K

NOTE 4

SIDE VIEW

L

0.30

0.50

L3

0.05 REF

M

0.10

C A B

A4

GENERIC

MARKING DIAGRAM*

D2

DETAIL A

24X

L

7

L3

M

PLATED

0.10

C A B

SURFACES

13

SECTION C−C

XXXXXXXX

AWLYYWWG

G

E2

K

1

24

19

24X b

e

M

0.10

C A B

XXXXXX = Specific Device Code

e/2

BOTTOM VIEW

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

M

0.05

C

NOTE 3

WL

YY

WW

G

RECOMMENDED

SOLDERING FOOTPRINT

5.30

3.66

24X

0.62

(Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present. Some products

may not follow the Generic Marking.

1

3.66

5.30

24X

0.65

PITCH

0.40

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON30093G

QFNW24 5x5, 0.65P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFN24 5x5, 0.65P

CASE 485CS

ISSUE O

DATE 24 OCT 2012

24

SCALE 2:1

1

NOTES:

L

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

D

A B

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

REFERENCE

L1

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

E

MILLIMETERS

DIM MIN

MAX

0.90

0.05

2X

0.15

C

A

A1

A3

b

0.80

−−−

0.20 REF

0.25

EXPOSED Cu

2X

C

MOLD CMPD

TOP VIEW

0.35

3.60

D

5.00 BSC

A

D2 3.40

DETAIL B

E

5.00 BSC

(A3)

A1

0.10

C

E2 3.40

e

K

L

0.65 BSC

0.20 MIN

0.30

A3

A1

DETAIL B

0.08

0.50

0.15

ALTERNATE

L1

−−−

CONSTRUCTION

SEATING

PLANE

NOTE 4

C

SIDE VIEW

D2

M

GENERIC

MARKING DIAGRAM*

0.10

C A B

DETAIL A

K

13

7

1

M

0.10

C A B

XXXXXXXX

AWLYYWWG

G

E2

1

24

24X

b

0.10

XXXXX = Specific Device Code

24X

L

e

M

C A B

A

= Assembly Location

= Wafer Lot

e/2

M

WL

YY

WW

G

NOTE 3

0.05

C

= Year

BOTTOM VIEW

= Work Week

= Pb−Free Package

SOLDERING FOOTPRINT*

5.30

(Note: Microdot may be in either location)

24X

3.66

0.62

*This information is generic. Please refer

to device data sheet for actual part

marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

3.66

5.30

24X

0.40

0.65

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON84592E

QFN24, 5x5, 0.65P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

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TECHNICAL SUPPORT

North American Technical Support:

Voice Mail: 1 800−282−9855 Toll Free USA/Canada

Phone: 011 421 33 790 2910

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◊

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1


型号：	NCV78723MW0R2G
厂家：	ONSEMI
描述：	High Efficiency Buck Dual LED Driver with Integrated Current Sensing for Automotive Front Lighting
文件：	总34页 (文件大小：470K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV78723MW0R2G [ONSEMI]

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