NCV78763MW0R2G_技术文档

NCV78763

Power Ballast and Dual LED

Driver for Automotive Front

Lighting 2^ndGeneration

The NCV78763 is a single−chip and high efficient smart Power

ballast and Dual LED DRIVER designed for automotive front lighting

applications like high beam, low beam, daytime running light (DRL),

turn indicator, fog light, static cornering and so on.

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The NCV78763 is a best fit for high current LEDs and provides a

complete solution to drive two strings up to 60 V, by means of two

internal independent buck switch channel outputs, with a minimum of

external components. For each individual LED channel, the output

current and voltage can be customized according to the application

requirements. An on−chip diagnostic feature for automotive front

lighting is provided, easing the safety monitoring from the

microcontroller. The device integrates a current−mode voltage booster

controller, realizing a unique input current filter with a limited BOM.

When more than two LED channels are required on one module, then

two, three or more NCV78763 devices can be combined, with the

possibility for the booster circuits to operate in multiphase−mode. This

helps to further optimize the filtering effect of the booster circuit and

allows a cost effective dimensioning for mid to high power LED systems.

Due to the SPI programmability, one single hardware setup can support

multiple system configurations for a flexible platform solution approach.

1

32

SSOP36 EP

CASE 940AB

QFN32 7x7

CASE 485J

32

1

QFN32

CASE 488AM

MARKING DIAGRAMS

NV78763−x

FAWLYYWWG

Features

• Single Chip Boost−Buck Solution

• Two LED Strings up to 60 V

• High Current Capability up to 1.6 A DC per Output

• High Overall System Efficiency

• Minimum of External Components

SSOP36

1

• Active Input Filter with Low Current Ripple from Battery

• Integrated Switched Mode Buck Current Regulator

• Integrated Boost Current−mode Controller

• Programmable Input Current Limitation

• Average Current Regulation Through the LEDs

• High Operating Frequencies to Reduce Inductor Sizes

• Integrated PWM Dimming with Wide Frequency Range

• Low EMC Emission for LED switching and dimming

• SPI Interface for Dynamic Control of System Parameters

• These are Pb−Free Devices

N78763−x

AWLYYWWG

QFN32

F

A

WL

YY

WW

G

= Fab Location

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

ORDERING INFORMATION

See detailed ordering, marking and shipping information on

Typical Applications

• Front Lighting High Beam and Low Beam

• Day time Running Light (DRL)

• Position or Park light

page 45 of this data sheet.

• Turn Indicator

• Fog Light and Static Cornering

1

Publication Order Number:

March, 2018 − Rev. 6A

NCV78763/D

NCV78763

VDRIVE

VBB

VBOOST VBOOSTBCK

VBOOSTM3V

VBOOST_AUXSUP

VREGM3V

VREG10V

IBCKxSENSE+

VDD

VREG3V

I sense

IBCKxSENSE−

VINBCKx

Buck regulator X 2

POWER STAGE

Driver

Booster

controller

Level

shifter

VGATE

Vsf

VFB

Boost

predrive

Over

BOOST PREDRV

VDD

current

LBCKSWx

VREF

detection

IBSTSENSE+

IBSTSENSE−

V

REF

I_sense

Comp

OTA

gain

f_BST

VLEDx

Fixed Toff

time

COMP

BSTSYNC

5V input

Channel

selector

LEDCTRLx

SPI bus

V_BOOST

V_BB

8

MUX

ADC

V_LED1

5V in / OD out

V_LED2

VDD

POR3V

VDD

OSC 8MHz

VDD

BIAS

BGAP

TEMPdet

Figure 1. Internal Block Diagram

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2

NCV78763

1

2

IBSTSENS –

IBSTSENS +

GNDP

VBOOST

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

32

31

30

29

28

27

26

25

VBOOSTM3V

3

VBOOSTBCK

IBCK1SENS+

IBCK1SENS–

VINBCK1

4

VGATE

VDRIVE

VBB

5

24

23

22

21

20

19

18

1

IBCK1SENS+

IBCK1SENS–

VINBCK1

VBB

6

2

3

4

5

6

7

8

TST

7

VINBCK1

TST

COMP

GND

8

COMP

GND

LBCKSW1

LBCKSW2

VINBCK2

LBCKSW1

9

LBCKSW2

VINBCK2

VDD

10

11

12

13

14

15

16

17

18

VDD

TST1

BSTSYN

TST1

IBCK2SENS–

BSTSYN

LEDCTRL1

IBCK2SENS+ 17

LEDCTRL1

LEDCTRL2

SCLK

VINBCK2

IBCK2SENS–

IBCK2SENS+

VLED1

CSB

SDI

VLED2

9

10

11

12

13

14

15

16

SDO

TST2

Figure 3. Pin Connections (QFN32)

Figure 2. Pin Connections (SSOP36 EP)

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3

NCV78763

Table 1. PIN DESCRIPTION

Pin No.

SSOP36−EP

Pin No.

QFN32

Pin Name

IBSTSENSE−

IBSTSENSE+

GNDP

Function

I/O Type

LV in/out

Ground

MV out

MV supply

HV supply

LV in/out

Ground

LV supply

LV in/out

MV in

1

28

29

30

31

32

1

Battery current negative feedback input

Battery current positive feedback input

Power ground

2

3

4

VGATE

Booster MOSFET gate pre−driver

10V supply

5

VDRIVE

6

VBB

Battery supply

7

2

TST

Internal function. To be tied to GND.

Compensation for the Boost regulator

Ground

8

3

COMP

9

4

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

5

VDD

3V logic supply

6

TST1

Internal function. To be tied to GND.

External clock for the boost regulator

LED string 1 enable

7

BSTSYN

LEDCTRL1

LEDCTRL2

SCLK

8

MV in

9

LED string 2 enable

MV in

10

11

12

13

14

15

16

17

18

19

X

SPI clock

MV in

CSB

SPI chip select (chip select bar)

SPI data input

MV in

SDI

MV in

SDO

SPI data output

MV open−drain

LV in/out

HV in

TST2

Internal function. To be tied to GND.

LED string 2 forward voltage input

LED string 1 forward voltage input

Buck 2 positive sense input

Buck 2 negative sense input

Buck 2 high voltage supply

Buck 2 switch output

VLED2

VLED1

HV in

IBCK2SENSE+

IBCK2SENSE−

VINBCK2

LBCKSW2

LBCKSW1

VINBCK1

IBCK1SENSE−

IBCK1SENSE+

VBOOSTBCK

VBOOSTM3V

VBOOST

HV in

20

X

HV out

Buck 2 switch output

HV out

21

X

Buck 1 switch output

HV out

Buck 1 switch output

HV out

22

X

Buck 1 high voltage supply

Buck 1 negative sense input

Buck 1 positive sense input

High voltage for the BUCK switches

VBOOST−3V regulator output

Boost voltage feedback input

HV in

23

24

25

26

27

HV in

HV supply

HV out (supply)

HV in

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NCV78763

Figure 4. NCV78763 Application Diagram

Note A: as reported in the application diagram, the device pins TST, TST2 & TST1 must be connected to the signal ground GND.

Note B: external capacitors or RC may be added to these SPI lines for stable communication in case of application noise. The selection

of these components must be done so that the resulting waveforms are respecting the limits reported in Table 19.

Note C: recommended values for the external MOSFET pull down resistor RPD_BST range from 10 kW to 33 kW.

Note D: the minimum value for the LED feedback resistors R_VLED_1 and R_VLED_2 is 1 kW.

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NCV78763

Table 2. ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Min

−0.3

−1.0

Max

60

Unit

V

Battery Supply voltage (Note 1)

LED supply voltage (Note 2)

V

BB

V

68

V

BOOST

Logic Supply voltage (Note 3)

V

DD

3.6

12

V

MOSFET Gate driver supply voltage (Note 4)

Input current sense voltage pins

V

DRIVE

V

IBSTSENSE+,

IBSTSENSE−

12

V

Medium voltage IO pins (Note 5)

Relative voltage IO pins (Note 6)

Buck switch low side (Note 7)

IOMV

−0.3

VBOOSTM3V

−2.0

7.0

V

DV_IO

VBOOSTBCK

LBCKSW1,

LBCKSW2

Current into or out of the VLED pin

Series resistor on the VLED pin

Storage Temperature (Note 8)

I

−30

1

30

mA

kW

°C

VLEDpin

R

VLEDx

T

strg

−50

150

260

Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free

Versions (Note 9)

T

SLD

°C

Electrostatic discharge on component level (Note 10)

V

ESD

−2

+2

kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Absolute maximum rating for pin VBB.

2. Absolute maximum rating for pins: VBOOST, VBOOSTM3V, IBCK1SENSE+, IBCK1SENSE−, VINBCK1, VLED1, IBCK2SENSE+,

IBCK2SENSE−, VINBCK2, VLED2.

3. Absolute maximum rating for pins: VDD, TEST1, TEST2, COMP.

4. Absolute maximum rating for pins: VDRIVE, VGATE.

5. Absolute maximum rating for pins: SCLK, CSB, SDI, SDO, LEDCTRL1, LEDCTRL2, BSTSYNC. The device tolerates 5 V coming from the

external logics (MCU) when in off state.

6. Relative maximum rating for pins: VINBCK1, VINBCK2, IBCK1SENSE+, IBCK2SENSE+, IBCK1SENSE−, IBCK2SENSE−.

7. Requirement: V(VINBCKx − LBCKSWx) < 70 V.

8. For limited time up to 100 hours, otherwise the max. storage temperature < 85°C.

9. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

10.This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)

Latch−up Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78

Table 3. RECOMMENDED OPERATING RANGES

The recommended operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the

functionality of the device outside the operating ranges described in this section is not warranted. Operating outside the recommended

operating ranges for extended periods of time may affect device reliability. A mission profile (Note 11) is a substantial part of the

operation conditions; hence the Customer must contact ON Semiconductor in order to mutually agree in writing on the allowed missions

profile(s) in the application.

Characteristic

Symbol

Min

Max

40

Unit

V

Battery Supply voltage

V

BB

4

Gate driver supply current (Note 12)

I

40

mA

°C

A

DRIVE

Functional operating junction temperature (Note 13)

Parametric operating junction temperature range

Buck switch output current peak

T

JF

−45

−40

155

150

1.9

T

JP

I

LBUCKpeak

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

11. The parametric characteristics of the circuit are not guaranteed outside the Parametric operating junction temperature range. A mission

profile describes the application specific conditions such as, but not limited to, the cumulative operating conditions over life time, the system

power dissipation, the system’s environmental conditions, the thermal design of the customer’s system, the modes, in which the device is

operated by the customer, etc.

12.I

Q

F

(external MOSFET total gate charge multiplied by booster driving frequency).

DRIVE = Tgate x BOOST

13.The circuit functionality is not guaranteed outside the functional operating junction temperature range. The maximum functional operating

range can be limited by thermal shutdown “Tsd” (ADC_Tsd, see Table 10). Also please note that the device is verified on bench for operation

up to 170°C but that the production test guarantees 155°C only.

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NCV78763

Table 4. THERMAL RESISTANCE

Characteristic

Package

SSOP36−EP

QFN32 7x7

QFN32 5x5

Symbol

qJcbot

Value

3.5

Unit

°C/W

Thermal resistance package to Exposed Pad (Note 14)

3.4

14.Includes also typical solder thickness under the Exposed Pad (EP).

ELECTRICAL CHARACTERISTICS NOTE: Unless differently specified, all device Min and Max parameters boundaries are

given for the full supply operating ranges and junction temperature (T ) range (−40°C; +150°C).

JP

Table 5. VBB: BATTERY SUPPLY INPUT

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

Nominal Operating

Supply Range

V

BB

5

40

V

Device Current

Consumption

I

buck regulators off, gate drive off, outputs unloaded

8

mA

BB_0

Table 6. VDRIVE: SUPPLY FOR BOOSTER MOSFET GATE DRIVE CIRCUIT

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

V

− V

> 1.65 V VDRIVE_ SETPOINT[3:0] =

BB

DRIVE

V

9.7

10.1

10.7

V

DRV_BB_15

@I

= 25 mA

1111

DRIVE

VDRIVE reg. voltage

from VBB (Note 15)

− V

> 1.65 V

= 25 mA

VDRIVE_ SETPOINT[3:0] =

0000

BB

DRIVE

4.8

5

5.3

V

DRV_BB_00

@I

DRIVE

VDRIVE from VBB

increase per code

(Note 15)

DV

Linear increase, 4Bits

0.34

DRV_BB

V

− V

DRIVE

> 3 V

= 40 mA

VDRIVE_SETPOINT[3:0] =

1111

BOOST

@I

DRIVE

V

9.5

4.7

10.1

5

10.7

5.3

V

DRV_BST_15

VDRIVE reg. voltage

from VBOOST

(Note 15)

V

− V

> 3 V

= 40 mA

VDRIVE_SETPOINT[3:0] =

0000

BOOST

DRIVE

V

DRV_BST_00

@I

DRIVE

VDRIVE from

VBOOST increase per

code (Note 15)

D

Linear increase, 4 Bits

0.34

V

VDRV_BST

DRV_BB_IL

VDRIVE Output

current limitation from

VBB input

V

40

400

200

mA

VDRIVE Output

current limitation from

VBOOST input

V

VDRIVE decoupling

capacitor

C

470

nF

VDRIVE

VDRIVE decoupling

capacitor ESR

C

100

mW

VDRIVE_ESR

15.The VDRIVE voltage setpoint is in the same range if the current is either provided by VBB or VBOOST pin. The voltage headroom between

VBB and VDRIVE or VDRIVE and VBOOST needs to be sufficient. For what concerns VDRIVE from VBB, in case of 25 mA current, the

worst case headroom is 1.65V. The VBOOST_AUX regulator can be enabled by SPI (bit VDRIVE_BST_EN[0]).

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NCV78763

Table 7. VDD: 3V LOW VOLTAGE ANALOG AND DIGITAL SUPPLY

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

VBB to VDD switch

disconnection

V

3.65

3.9

V

BB_LOW

VDD regulator output

voltage

V

> 4 V

3.15

3.4

15

V

DD

BB

DC total current

consumption including

output

V

> 4 V

mA

DD_IOUT

BB

DC current limitation

V

15

240

2.2

mA

DD_ILIM

BB

VDD external

decoupling cap.

C

0.3

0.47

mF

VDD

VDD ext. decoupling

cap. ESR

C

200

3.05

2.8

mW

VDD_ESR

POR Toggle level on

VDD rising

POR

2.7

V

3V_H

3V_L

POR Toggle level on

VDD falling

2.45

V

POR Hysteresis

POR

0.2

3V_HYST

Table 8. VBOOSTM3: HIGH SIDE MOSFETS AUXILIARY SUPPLY

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

VBSTM3 regulator

output voltage

V

−3.6

−3.3

−3.0

V

BSTM3

VBSTM3 DC output

current consumption

V

5

mA

mF

BSTM3_IOUT

VBSTM3 Output

current limitation

V

200

2.2

BSTM3_ILIM

VBSTM3 external

decoupling capacitor

C

0.3

0.47

VBSTM3

VBSTM3 external

decoupling cap. ESR

C

200

mW

VBSTM3_ESR

Table 9. OSC8M: SYSTEM OSCILLATOR CLOCK

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

System oscillator

frequency

FOSC8M

After device factory trimming

7.1

8.0

8.9

MHz

Table 10. ADC FOR MEASURING VBOOST, VBB, VLED1, VLED2, VTEMP

Characteristic

Symbol

ADC

Conditions

Min

Typ

Max

Unit

ADC Resolution

8

Bits

RES

Integral Nonlinearity

(INL)

ADC

−1.5

−2.0

+1.5

+2.0

LSB

INL

Differential

Nonlinearity (DNL)

ADC

DNL

Full path gain error for

measurements via

VBB, VLEDx,

ADC

−3.25

−2

3.25

2

%

GAINERR

VBOOST

Offset at output of

ADC

LSB

ms

OFFSET

Time for 1 SAR

conversion

ADC

8

CONV_TIME

ADC full scale for VBB

measurement

ADC

39.7

V

FS_VBB

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NCV78763

Table 10. ADC FOR MEASURING VBOOST, VBB, VLED1, VLED2, VTEMP (continued)

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

ADC full scale for

VLED

ADC

69.5

V

FS_VLED

FS_VBST

ADC full scale for

Vboost

ADC

69.5

169

V

ADC internal

temperature

measurement for

thermal shutdown

ADC

163

255

175

710

°C

kW

TSD

VLED input

impedance

VLED

R_IN

Table 11. BOOSTER CONTROLLER − VOLTAGE REGULATION PARAMETERS

Characteristic

Symbol

Conditions

SPI Setting

Min

Typ

Max

Unit

V

DV to the reg. level, DC

BST_OV_07

[BOOST_OV_SD = 111]

5.3

5.8

6.3

level

DV to the reg. level, DC

V

BST_OV_06

BST_OV_05

BST_OV_04

BST_OV_03

BST_OV_02

BST_OV_01

BST_OV_00

[BOOST_OV_SD = 110]

[BOOST_OV_SD = 101]

[BOOST_OV_SD = 100]

[BOOST_OV_SD = 011]

[BOOST_OV_SD = 010]

[BOOST_OV_SD = 001]

[BOOST_OV_SD = 000]

4.3

3.4

2.4

1.9

1.5

1.2

0.6

4.85

3.9

2.9

2.4

2

5.3

4.3

3.3

2.8

2.3

1.8

1.3

level

DV to the reg. level, DC

V

level

DV to the reg. level, DC

level

Booster overvoltage

shutdown (Note 16)

DV to the reg. level, DC

level

DV to the reg. level, DC

level

DV to the reg. level, DC

1.5

1

level

DV to the reg. level, DC

V

level

Booster overvoltage

shutdown increase per

code

Linear increase, 2 bits,

DC level

DBST_OV

BST_RA_3

BST_RA_0

DBST_RA

0.5/1 0.6/1.2

DV to the VBOOST reg.

overvoltage protection,

DC level

Booster overvoltage

re−activation

[BOOST_OV_REACT = 11]

[BOOST_OV_REACT = 00]

−1.8

−1.4

0

−1

V

DV to the VBOOST reg.

overvoltage protection,

DC level

Booster overvoltage

re−activation

Booster overvoltage

re−activation decrease

per code

Linear decrease, 2 bits,

DC level

−0.6

−0.5

[BOOST_VSETPOINT =

1111111]

BST_REG_127

BST_REG_001

BST_REG_000

DC level

62.8

14.4

10.5

64.1

15

66

V

[BOOST_VSETPOINT =

0000001]

Booster regulation

setpoint voltage

15.6

11.5

[BOOST_VSETPOINT =

0000000]

11

Booster regulation

setpoint increase step

per code

DBST_REG

Linear increase, 7 bits

0.39

0.55

V

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NCV78763

Table 11. BOOSTER CONTROLLER − VOLTAGE REGULATION PARAMETERS

Characteristic

Symbol

Conditions

SPI Setting

Min

Typ

Max

Unit

Seen from VBOOST pin

input, DC value

EA

[BOOST_OTA_GAIN = 11]

63

90

117

mS

_Gm_3

_Gm_2

_Gm_1

Seen from VBOOST pin

input, DC value

[BOOST_OTA_GAIN = 10]

[BOOST_OTA_GAIN = 01]

42

21

60

30

78

39

mS

Booster Error Amplifier

(EA)

Trans−conductance

Seen from VBOOST pin

input, DC value

Gain G

m

Seen from VBOOST pin

input, High impedance

tri−state

EA

[BOOST_OTA_GAIN = 00]

0

mS

_Gm_0

EA

is set

[BOOST_OTA_GAIN = 11]

[BOOST_OTA_GAIN = 10]

[BOOST_OTA_GAIN = 01]

[BOOST_OTA_GAIN = 11]

[BOOST_OTA_GAIN = 10]

[BOOST_OTA_GAIN = 01]

150

100

50

180

120

60

mA

_Iout_pos_max_03

_Iout_pos_max_02

_Iout_pos_max_01

_Iout_neg_max_03

_Iout_neg_max_02

_Iout_neg_max_01

_Gm_03

_Gm_02

_Gm_01

_Gm_03

_Gm_02

_Gm_01

EA max output current

(positive/source)

−180

−120

−60

−150

−100

−50

EA max output current

(negative/sink)

EA max output

leakage current in

tri−state

EA

is set (EA

_Gm_00

disabled, high impedance

tri−state)

EA

[BOOST_OTA_GAIN = 00]

−1

1

mA

_Iout_leak

EA equivalent output

resistance

EA

0.7

2.9

MW

_ROUT

(BST_SLPCTRL_3 or

BST_SLPCTRL_2) &

(BST_VLIMTH_3 or

BST_VLIMTH_2)

[BOOST_SLP_CTRL = 1x] &

[BOOST_VLIMTH = 1x]

COMP

2.1

1.8

1.5

1.2

2.26

1.98

1.64

1.35

V

_CLH3

_CLH2

_CLH1

_CLH0

BST_SLPCTRL_3 or

BST_SLPCTRL_2) &

(BST_VLIMTH_1 or

BST_VLIMTH_0)

[BOOST_SLP_CTRL = 1x] &

[BOOST_VLIMTH = x1]

EA max output voltage

(at VCOMP pin)

BST_SLPCTRL_1 or

BST_SLPCTRL_0) &

(BST_VLIMTH_3 or

BST_VLIMTH_2)

[BOOST_SLP_CTRL = x1] &

[BOOST_VLIMTH = 1x]

BST_SLPCTRL_1 or

BST_SLPCTRL_0 ) &

(BST_VLIMTH_1 or

BST_VLIMTH_0)

[BOOST_SLP_CTRL = x1] &

[BOOST_VLIMTH = x1]

V

EA min output voltage

(at VCOMP pin)

COMP

0.4

_CLL

_DIV

Division factor of

VCOMP voltage

towards the Current

comparator input

COMP

7

Voltage shift (offset)

on VCOMP on Current

comparator input

COMP

0.5

V

_VSF

0.7 or

0.8

BST_SKCL_3

BST_SKCL_2

BST_SKCL_1

[BOOST_SKCL = 11]

[BOOST_SKCL = 10]

[BOOST_SKCL = 01]

0.625

or

Booster skip cycle for

low currents (Note 17)

V

0.7

0.55 or

0.6

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NCV78763

Table 11. BOOSTER CONTROLLER − VOLTAGE REGULATION PARAMETERS

Characteristic

Symbol

Conditions

SPI Setting

Min

Typ

1.2

Max

Unit

V

BST

[VBOOST_VGATE_THR = 1]

[VBOOST_VGATE_THR = 0]

[BOOST_FREQ = 11111]

[BOOST_FREQ = 00001]

[BOOST_FREQ = 00000]

_VGATE_THR_1

_VGATE_THR_0

VGATE comparator to

start BST_TOFF time

0.4

V

BST

FOSC8M / 38

FOSC8M / 8

187

890

210

1000

0

234

kHz

_FREQ_31

_FREQ_01

_FREQ_00

Booster PWM

frequency (when from

internal generation)

BST

1110

PWM clock disabled

Booster PWM freq.

increase per code

DBST

Nonlinear increase, 5 bits

5−112

kHz

_FREQ

BST

[VBOOST_TOFFMIN = 11]

[VBOOST_TOFFMIN = 10]

[VBOOST_TOFFMIN = 01]

[VBOOST_TOFFMIN = 00]

[VBOOST_TONMIN = 11]

[VBOOST_TONMIN = 10]

[VBOOST_TONMIN = 01]

[VBOOST_TONMIN = 00]

100

140

30

155

195

75

210

250

120

160

365

320

250

200

ns

_TOFF_MIN_3

_TOFF_MIN_2

_TOFF_MIN_1

_TOFF_MIN_0

Booster minimum OFF

time (Note 18)

70

115

300

260

200

150

BST

235

200

150

100

_TON_MIN_3

_TON_MIN_2

_TON_MIN_1

_TON_MIN_0

Booster minimum ON

time (Note 18)

16.The following condition must always be respected: BST_REG_XX + BST_OV_X < 68 V.

17.The higher levels indicated in the cells are valid for BST_VLIMTH_2 and BST_VLIMTH_3 selection (BOOST_VLIMTH<1> = 1).

18.Rise and fall time of the VGATE is not included.

Table 12. BOOSTER CONTROLLER − CURRENT REGULATION PARAMETERS

Characteristic

Symbol

Conditions

SPI setting

Min

95

75

57

45

−5

Typ

100

80

Max

105

85

Unit

mV

Current comparator for

Imax detection

BST

[BOOST_VLIMTH = 11]

[BOOST_VLIMTH = 10]

[BOOST_VLIMTH = 01]

[BOOST_VLIMTH = 00]

_VLIMTH_3

_VLIMTH_2

_VLIMTH_1

_VLIMTH_0

BST

62.5

50

67

55

Current comparator for

VBOOST regulation,

offset voltage

BST

0

5

_OFFS

Booster slope

compensation

BST

[BOOST_SLPCTRL = 11]

[BOOST_SLPCTRL = 10]

[BOOST_SLPCTRL = 01]

[BOOST_SLPCTRL = 00]

20

10

5

mV/ ms

V

_SLPCTRL_3

_SLPCTRL_2

_SLPCTRL_1

_SLPCTRL_0

BST

(no slope control)

0

Booster Current

Sense voltage

CMVSENSE

−0.1

1

common mode range

Table 13. BOOSTER CONTROLLER − MOSFET GATE DRIVER

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

High−side switch

impedance

RON

2.5

4

W

HI

Low−side switch

impedance

RON

2.5

4

W

LO

Table 14. BUCK REGULATOR − INTERNAL SWITCHES CHARACTERISTICS

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

Buck switch On

resistance

R

At room−temperature, I(VINBCKx) pin = 1.5 A,

(VBOOST−VINBCKx) = 0.2 V

0.65

W

DS(on)

R

At Tj = 150°C, I(VINBCKx) pin = 1.5 A,

0.9

W

DS(on)_hot

(VBOOST−VINBCKx) = 0.2 V

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11

NCV78763

Table 14. BUCK REGULATOR − INTERNAL SWITCHES CHARACTERISTICS

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

Buck Overcurrent

detection

OCD

1.9

3

A

Buck Switching slope

(ON phase)

Trise

Tfall

3

2

V/ns

Buck Switching slope

(OFF phase)

Table 15. BUCK REGULATOR − CURRENT REGULATION PARAMETERS

Characteristic

Symbol

Conditions

[BUCKx_VTHR = 11111111]

Min

Typ

Max

Unit

Buck current sense

threshold voltage

VTHR_255

412

mV

Buck current sense

threshold voltage

VTHR_000

[BUCKx_VTHR = 00000000]

31.5

mV

%

Buck current sense

threshold voltage

increase per code

DVTHR

exponential increase,

7.5 bits equivalent, DC

level

1.013

1.5

Buck threshold voltage

temperature stability

VTHR

Without chopper function

−1.5 &

−2

+1.5 & % &

_TEMP

+2

mV /

100°C

Buck threshold voltage

accuracy (Note 21)

VTHR

Without chopper function

−3 &

−6

+3 &

+6

% &

mV

_ERR

Buck TOFFxVLED

constant setting for

shortest OFF time

T

[BUCKx_TOFFVLED = 1111]

[BUCKx_TOFFVLED = 0000]

10

50

ms V

OFF_VLED_15

Buck TOFFxVLED

constant setting for

longest OFF time

ms V

OFF_VLED_00

Buck OFF time

relative error

BCK

T

xVLED @VLED >

−10

−35

0

10

35

%

ns

%

V

_TOFF_ERR_REL

OFF

2 V & T

> 0.35 ms

OFF

Buck OFF time

absolute error

BCK_

T

OFF

xVLED @VLED >

TOFF_ERR_ABS

2 V & T

≤ 0.35 ms

OFF

Buck OFF time setting

decrease per code

DTC

exponential increase,

4 bits, DC level

11.33

1.8

50

Detection level for low

VLED voltages

VLED_

1.62

44.3

1.98

55.7

LMT

Buck ON too long time

detection (OPEN

LOAD)

BCK_

ms

TON_OPEN

Buck minimum ON

time mask in

regulation (Note 20)

BCK_

50

63

250

90

ns

ms

ns

TON_MIN

Buck OFF time for

short circuit detected

on VLEDx

BCK_

VLEDx < VLED

_LMT

TOFF_SHORT

Delay from BUCK

BCK_

ISENS comparator

over−drive ramp >

1 mV/10 ns

70

CMP_DEL

ISENS comparator

input to BUCK switch

going OFF (Note 21)

19.Without use of buck chopper function (for sufficient coil current ripple, see buck section in the datasheet). With the buck chopper function,

the offset is reduced to a level lower than |3 mV|.

20.The buck ISENSE comparator is active at the end of this mask time.

21.BCK_CMP_DEL < 120 ns, guaranteed by laboratory measurement, not tested in production.

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12

NCV78763

Table 16. 5V TOLERANT DIGITAL INPUTS (SCLK, CSB, SDI, LEDCTRL1, LEDCTRL2, BSTSYNC)

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

High−level input

voltage

VINHI

2

V

Low−level input

voltage

VINLO

0.8

160

4.9

V

Input digital in leakage

current (Note 22)

R

40

kW

ms

PULL

LEDCTRLx to PWM

dimming propagation

delay

BUCKx

3.6

4

_SW_DEL

22.Pull down resistor (R

) for LEDCTRLx, BSTSYNC, SDI and SCLK, pull up resistor (R

) for CSB to VDD.

pulldown

pullup

Table 17. 5V TOLERANT OPEN−DRAIN DIGITAL OUTPUT (SDO)

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

Low−voltage output

voltage

VOUTLO

I

= −10 mA (current flows into the pin)

0.4

V

out

Equivalent output

resistance

R

Low−side switch

20

10

40

2

W

DS(on)

SDO pin leakage

current

SDO

mA

pF

ns

_ILEAK

SDO pin capacitance

(Note 23)

SDO

_C

CLK to SDO

propagation delay

(Note 24)

SDO

Low−side switch activation/deactivation time

320

_DL

23.Guaranteed by bench measurement, not tested in production.

24.Values valid for 1 kW external pull−up connected to 5 V and 100 pF to GND, when in case of falling edge the voltage on the SDO pin goes

below 0.5 V. This delay is internal to the chip and does not include the RC charge at pin level when the output goes to high impedance.

Table 18. 3V TOLERANT DIGITAL PINS (TST1, TST2)

Characteristic

Symbol

Conditions

Min

Typ

Max

Unit

High−level input

voltage

VINHI

2

V

Low−level input

voltage

VINLO

0.8

47

V

Input leakage current

TST1 pin

TST1

Internal pull−down resistance

19

32

4

kW

_Rpulldown

Input leakage current

TST2 pin

TST2

1.6

5.9

_Rpulldown

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13

NCV78763

Table 19. SPI INTERFACE

Characteristic

Symbol

tCSS

Conditions

Min

500

250

500

250

Typ

Max

Unit

ns

CSB setup time

CSB hold time

tCSH

tWL

ns

SCLK low time

ns

SCLK high time

tWH

ns

Data−in (DIN) setup

time

tSU

ns

Data−in (DIN) hold

time

tH

275

110

ns

SDO disable time

tDIS

320

ns

SDO valid for high lo

low transition

t

SDO_HL

SDO valid for low lo

high transition

(Note 25)

320 +

t(RC)

ns

SDO_LH

SDO hold time

CSB high time

tHO

tCS

110

ns

1000

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-

formance may not be indicated by the Electrical Characteristics if operated under different conditions.

25.Time depends on the SDO load and pull–up resistor.

t_CS

V_IH

CSB

V_IL

t_CSS

t_WH

t_WL

t_CSH

V_IH

SCLK

V_IL

t_SU

t_H

V_IH

DIN

DIN13

DIN15

DIN14

DIN1

DIN0

V_IL

V_IH

t_DIS

t_HO

t_V

HI−Z

DOUT

DOUT15

DOUT14

DOUT13

DOUT1

DOUT0

HI−Z

V_IL

Figure 5. NCV78763 SPI Communication Timing

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14

NCV78763

TYPICAL CHARACTERISTICS

Figure 6. Buck Peak Comparator Threshold (Note 26)

Figure 7. Buck MOSFET Typical R_DS(on)Over Silicon Junction Temperature

26.Curve obtained by applying the typical exponential increase from the min value VTHR_000. Please see Table 15 for details.

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15

NCV78763

DETAILED OPERATING AND PIN DESCRIPTION

SUPPLY CONCEPT IN GENERAL

Low operating voltages become more and more required

due to the growing use of start stop systems. In order to

respond to this necessity, the NCV78763 is designed to

support power−up starting from V = 5 V.

BB

Figure 8. Cranking Pulse (ISO7637−1): System has to be Fully Functional (Grade A) from Vs = 5 V to 28 V

VDRIVE Supply

guaranteed for VBB voltages lower than 4 V and that for

very low voltages a reset will be generated (see Table 7).

The VDRIVE supply voltage represents the power for the

complete the BOOST PREDRV block, which generates the

VGATE, used to switch the booster MOSFET. The voltage

is programmable via SPI in 16 different values (register

VDRIVE_SETPOINT[3:0], ranging from a minimum of

5 V typical to 10 V typical: see Table 6). This feature allows

having the best switching losses vs. resistive losses trade off,

according to the MOSFET selection in the application, also

versus the minimum required battery voltage. The lowest

settings can be exploited to drive logic gate drive MOSFETs.

In order to support low VBB battery voltages and long crank

pulse drops, the VDRIVE supply can take its energy from

the source with the highest output voltage, either from (refer

to Figure 1):

Note: powering the device via the VBOOST_AUXSUP will

produce an extra power dissipation linked to the related

linear drop (VBOOST − VBOOST_AUXSUP), which must

be taken into account during the thermal design.

VDD Supply

The VDD supply is the low voltage digital and analog

supply for the chip and derives energy from VBB. Due to the

low dropout regulator design, VDD is guaranteed already

from low VBB voltages. The Power−On−Reset circuit

(POR) monitors the VDD voltage and the VBB voltage to

control the out−of−reset and reset entering state: an internal

switch disconnects the VDD regulator from the VBB input

as its voltage drops below the admitted threshold

VBB_LOW (Table 7); this originates a VDD discharge that

will result in a device reset either if the voltage falls below

the PORL level or in general, if due to the drop, the VDD

regulation target cannot be kept for more than typically

100 ms. At power-up, the chip will exit from reset state when

VBB > VBB_LOW and VDD > PORH.

• the VREG10V supply, which derives its energy from

the VBB input.

• the VBOOST_AUXSUP, which gets its energy from

the VBOOST path. In order to enable this condition the

bit VDRIVE_BST_EN[0] = 1. It is highly

recommended to enable this function at module running

mode in order to insure proper MOSFET gate drive

even in case of large battery drop transients.

VBOOSTM3V Supply

Under normal operating conditions, when the voltage

headroom between VBB and VREG10V is sufficient, the

gate driver energy is entirely supplied via the VBB path. In

case the VBOOST_AUX regulator is enabled, it will start to

draw part of the required current starting as from when the

headroom reduces below the minimum requirement, then

linearly increasing, until bearing 100% of the IDRIVE

current when the VBB drops close or below the VDRIVE

target and still enough energy can be supplied by the booster

circuit. Please note that the full device functionality is not

The VBOOSTM3V is the high side auxiliary supply for

the gate drive of the buck regulators’ integrated high−side

P−MOSFET switches. This supply receives energy directly

from the VBOOSTBCK pin.

INTERNAL CLOCK GENERATION − OSC8M

An internal RC clock named OSC8M is used to run all the

digital functions in the chip. The clock is trimmed in the

factory prior to delivery. Its accuracy is guaranteed under

full operating conditions and is independent from external

component selection (refer to Table 9 for details).

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16

NCV78763

ADC

Referring to the figure above, the typical rate for a full

SAR plus digital conversion per channel is 8 ms (Table 10).

For instance, each new V ADC converted sample

General

BOOST

The built−in analog to digital converter (ADC) is an 8−bit

occurs at 16 ms typical rate, whereas for both the V and

BB

capacitor based successive approximation register (SAR).

This embedded peripheral can be used to provide the

following measurements to the external Micro Controller

Unit (MCU):

V

TEMP

channel the sampling rate is typically 32 ms, that is

to say a complete cycle of the depicted sequence. This time

is referred to as T

.

ADC_SEQ

If the SPI setting LED_SEL_DUR[8:0] is not zero, then

interrupts for the VLEDx measurements are allowed at the

points marked with a rhombus, with a minimum cadence

corresponding to the number of the elapsed ADC sequences

(forced interrupt). In formulas:

• V

voltage: sampled at the VBOOST pin;

BOOST

• V voltage (linked to the battery line);

BB

• VLED1 , VLED2 voltages;

ON

• VLED1 and VLED2 voltages;

T_{VLEDx_INT_forced}+ LED_SEL_DUR[8 : 0] T_{ADC_SEQ}

• VTEMP measurement (chip temperature).

The internal NCV78763 ADC state machine samples all

the above channels automatically, taking care for setting the

analog MUX and storing the converted values in memory.

The external MCU can readout all ADC measured values via

the SPI interface, in order to take application specific

decisions. Please note that none of the MCU SPI commands

interfere with the internal ADC state machine sample and

conversion operations: the MCU will always get the last

available data at the moment of the register read.

In general, prior to the forced interrupt status, the

VLEDx

ADC interrupts are generated when a falling

ON

edge on the control line for the buck channel ”x” is detected

by the device. In case of external dimming, this interrupt

start signal corresponds to the LEDCTRLx falling edge

together with a controlled phase delay (Table 16). When in

internal dimming, the phase delay is also internally created,

in relation with the falling edge of the dimming signal. The

purpose of the phase delay is to allow completion the

ongoing ADC conversion before starting the one linked to

the VLEDx interrupt: if at the moment of the conversion

LEDCTRLx pin is logic high, then the updated registers are

VLEDxON[7:0] and VLEDx[7:0]; otherwise, if

LEDCTRLx pin is logic low, the only register refreshed is

VLEDx[7:0]. This mechanism is handled automatically by

the NCV78763 logic without need of intervention from the

user, thus drastically reducing the MCU cycles and

embedded firmware and CPU cycles overhead that would be

otherwise required.

The state machine sampling and conversion scheme is

represented in the figure below.

V_BBsample & convert

V_BOOSTsample & convert

To avoid loss of data linked to the ADC main sequence,

one LED channel is served at a time also when interrupt

requests from both channels are received in a row and a full

sequence is required to go through to enable a new interrupt

VLEDx. In addition, possible conflicts are solved by using

a defined priority (channel pre−selection). Out of reset, the

default selection is given to channel “1”. Then an internal

flag keeps priority tracking, toggling at each time between

channels pre−selection. Therefore, up to two dimming

periods will be required to obtain a full measurement update

of the two channels. This not considered however a

limitation, as typical periods for dimming signals are in the

order of 1 ms period, thus allowing very fast failure

detection.

Update LED_SEL_DUR count;

When counter ripples, trigger

VLEDx interrupt for once

V_TEMPsample & convert

sample & convert

V_BOOST

Figure 9. ADC Sample and Conversion Main

Sequence

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17

NCV78763

Boost voltage ADC: V_BOOST

A flow chart referring to the ADC interrupts is also

displayed (Figure 10).

This measure refers to the boost voltage at the VBOOST

pin, with an 8 bit conversion ratio of 70/255 (V/dec) =

0.274 (V/dec) typical, inside the SPI register

VBOOST[7:0]. This measurement can be used by the MCU

for diagnostics and booster control loop monitoring. The

measurement is protected by parity (ODD) in bit

VBOOST[8].

VLEDx

Synchronization

signal?

YES

NO

Interrupts Enabled?

NO

YES

Device Temperature ADC: V_TEMP

By means of the VTEMP measurement, the MCU can

V_LEDxsample & convert

monitor the device junction temperature (T ) over time. The

J

conversion formula is:

Toggle channel “x” selection

(

)

)[

]

T_J+ VTEMP[7 : 0] dec * 20 ° C

VTEMP[7:0] is the value read out directly from the

related 8bit−SPI register (please refer to the SPI map). The

value is also used internally by the device to for the

thermal warning and thermal shutdown functions. More

details on these two can be found in the dedicated sections

in this document. The parity protection (ODD) is found on

bit VTEMP[8].

In case of interrupt on

second channel do not serve

immediately and complete

the ADC sequence first

Proceed to next step in the ADC sequence

LED String Voltages ADC: V_LEDx,V_LEDxON

Figure 10. ADC VLEDx Interrupt Sequence

The voltage at the pins VLEDx (1, 2) is measured. Their

conversion ratio is 70/255 (V/dec) = 0.274 (V/dec) typical.

This information, found in registers VLEDxON[7:0] and

VLEDx[7:0], can be used by the MCU to infer about the

LED string status. For example, individual shorted LEDs, or

dedicated Open string and short to GND or short to battery

algorithms. As for the other ADC registers, the values are

protected by ODD parity, respectively in VLEDxON[8] and

VLEDx[8].

All NCV78763 ADC registers data integrity is protected

by ODD parity on the bit 8 (that is to say the 9th bit if

counting from the LSbit named “0”). Please refer to the SPI

map section for further details.

Battery voltage ADC: V_BB

The battery voltage is sampled making use of the device

supply

V

BB

pin. The (8−bit) conversion ratio is

Please note that in the case of constant LEDCTRLx inputs

and no dimming (in other words dimming duty cycle equals

to 0% or 100%) the VLEDx interrupt is forced with a rate

40/255 (V/dec) = 0.157 (V/dec) typical. The converted

value can be found in the SPI register VBB[7:0], with ODD

parity protection bit in VBB[8]. The external MCU can

make use of the measured VBB value to monitor the status

of the module supply, for instance for a power de−rating

algorithm.

equal to T

, given in the ADC general

VLEDx_INT_forced

section. This feature can be exploited by MCU embedded

algorithm diagnostics to read the LED channels voltage

even when in OFF state, before module outputs activation

(module startup pre−check).

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18

NCV78763

BOOSTER REGULATOR

the same time be lower, there will be no impact on the

thermal design.

General

On top of the cascaded configuration shown in the

previous figure, the booster can be operated in multi−phase

mode by combining more NCV78763 in the application.

More details about the multiphase mode can be found in the

dedicated section.

The NCV78763 features one common booster stage for

the two high−current integrated buck current regulators. In

addition, optional external buck regulators, belonging to

other NCV78x63 devices, can be cascaded to the same boost

voltage source as exemplified in the picture below.

Booster Regulation Principles

The NCV78763 features a current−mode voltage

Vboost

NCV78763 #dev1

Boost regulator

NCV78763 #dev1

2x Buck regulators

controller, which regulates the V

line used by the buck

BOOST

converters. The regulation loop principle is shown in the

following picture. The loop compares the reference voltage

(V

) with the actual measured voltage at the

pin, thus generating an error signal which is treated

BOOST_SETPOINT

NCV78x63 #dev2

2xBuck regulators

V

BOOST

internally by the error trans−conductance amplifier (block

A1). This amplifier transforms the error voltage into current

NCV78x63 #devN

by means of the trans−conductance gain G . The amplifier’s

m

2xBuck regulators

output current is then fed into the external compensation

network impedance (A2), so that it originates a voltage at the

Figure 11. Cascading Multiple NCV78x63 Buck

Channels on a Common Boost Voltage Source

V

COMP

pin, this last used as a reference by the current

control block (B).

The current controller regulates the duty cycle as a

The booster stage provides the required voltage source for

the LED string voltages out of the available battery voltage.

Moreover, it filters out the variations in the battery input

current in case of LED strings PWM dimming.

consequence of the V

reference, the sensed inductor

COMP

peak current via the external resistor R

and the slope

SENSE

compensation used. The power converter (block C)

represents the circuit formed by the boost converter

externals (inductor, capacitors, MOSFET and forward

diode). The load power (usually the LED power going via

the buck converters) is applied to the converter.

The controlled variable is the boost voltage, measured

directly at the device VBOOST pin with a unity gain

feedback (block F). The picture highlights as block G all the

elements contained inside the device. The regulation

parameters are flexibly set by a series of SPI commands

indicated in Tables 11 and 12. A detailed internal boost

controller block diagram is presented in the next section.

For nominal loads, the boost controller will regulate in

continuous mode of operation, thus maximizing the system

power efficiency at the same time having the lowest possible

input ripple current (with “continuous mode” it is meant that

the supply current does not go to zero while the load is

activated). Only in case of very low loads or low dimming

duty cycle values, discontinuous mode can occur: this means

the supply current can swing from zero when the load is off,

to the required peak value when the load is on, while keeping

the required input average current through the cycle. In such

situations, the total efficiency ratio may be lower than the

theoretical optimal. However, as also the total losses will at

Current

control

voltage

VCOMP(t)

Boost PWM

duty cycle

D(t)

Vboost Target Vboost Target

Boost voltage

Vboost(t)

Reference

error

+

VREF

e(t)

Current

Controller

(B)

Power Converter

(C)

Error Amp

(A1)

Compensation

Network

(A2)

Load

−

Compensator (A)

Rsense

(E)

Current sense voltage

Boost inductor current

VSENSE(t)

IL(t)

Feedback voltage

VF(t) = Vboost(t)

Boost voltage

Vboost(t)

Unity gain

Feedback network

(F)

NCV78763 Boost Controller Block (G)

Figure 12. NCV78763 Boost Control Loop − Principle Block Diagram

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19

NCV78763

Boost Controller Detailed Internal Block Diagram

A detailed NCV78763 boost controller block diagram is

provided in this section. The main signals involved are

The blocks referring to the principle block diagram are

also indicated. In addition, the protectionspecific blocks can

be found (see dedicated sections for details).

indicated, with

a particular highlight on the SPI

programmable parameters.

Overvoltage shutdown protection

V

BOOST_SETPOINT

Reactivation from overvoltage protection

VBB

VBOOST

VBOOST_VSETPOINT<6:0>

Current limiter protection

PWM control

BOOSTER

BOOST_OV_SD[2:0]

OV

BOOST_OV_REACT[1:0]

S

Ref.

IMAX

R

BOOST_VLIMTH[1:0]

RA

BOOST_SLPCTRL[1:0]

Slope

comp.

&

COMP

_VSF

IBSTSENS+

SCLK

BOOST_SCKL[1:0]

BOOST_VLIMTH[1]

BOOST_SLPCTRL[1]

IREG

R_BST_SENS

IBSTSENS−

COMP_CLH

COMP

BOOST_VLIMTH[1]

EA

1/COMP_DIV

COMP_CLL

Current control (B)

VGATE control (H)

DIG. control

VBOOST_TOFF_SET[1:0]

VGATE_LOW

Error Amp (A1)

VBOOST_VGATE_THR

TOFF

generator

VGATE

BOOST_TOFF

S

BOOST_SYN

BOOST_SYN_PK

Peak

gen.

R

rst

GND

VBOOST_TON_SET[1:0]

BOOST_TON

TON

generator

GATE

Compensation

Network (A2)

Figure 13. NCV78763 Boost Controller Internal Detailed Block Diagram

Booster Regulator Setpoint (V_{BOOST_SETPOINT}

)

same time, the boost overvoltage flag in the status register

will be set (BOOST_OV = 1), together with the

BOOST_STATUS flag equals to zero. The PWM runs again

The booster voltage V

is regulated around the target

BOOST

programmable

by

the

7−bit

SPI

setting

VBOOST_SETPOINT[6:0], ranging from a minimum of

11 V to a maximum of typical 64.1 V (please refer to

Table 11 for details). Due to the step−up only characteristic

of any boost converter, the boost voltage cannot obviously

be lower than the supply battery voltage provided. Therefore

a target of 11 V would be used only for systems that require

the activation of the booster in case of battery drops below

the nominal level.

as from the moment the V

will fall below the

BOOST

reactivation

hysteresis

defined

by

the

BOOST_OV_REACT[1:0] SPI parameter. Therefore,

depending on the voltage drop and the PWM frequency, it

might be that more than one cycle will be skipped. A

graphical interpretation of the protection levels is given in

the figure below, followed by a summary table (Table 20).

At power−up, the booster is disabled and the setpoint is

per default the minimum (all zeroes).

[V]

Booster Overvoltage Shutdown Protection

Boost overvoltage shutdown

An integrated comparator monitors V

in order to

BOOST

Boost overvoltage reactivation

protect the external booster components and the led driver

device from overvoltage. When the voltage rises above the

V_{BOOST SETPOINT}

threshold defined by the sum of the V

BOOST_SETPOINT

(VBOOST_SETPOINT[6:0]) and the overvoltage

shutdown value (BOOST_OV_SD[2:0]), the MOSFET gate

is switched−off at least for the current PWM cycle and at the

Figure 14. Booster Voltage Protection Levels with

Respect to the Setpoint

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20

NCV78763

Table 20. NCV78763 BOOSTER OVERVOLTAGE PROTECTION LEVELS AND RELATED SPI DIAGNOSTICS

SPI FLAGS

BOOST_STATUS

BOOST_OV

ID

A

Description

< V

PWM VGATE Condition

Normal (not disabled)

Disabled until case “C”

V

1

0

BOOST

BOOST_SETPOINT

B

V

> V

+

1

BOOST

BOOST_SETPOINT

BOOST_OV_SD

(latched)

C

V

< V

+

Re−enables the PWM,

normal mode resumed if

from case “B”

1

BOOST

BOOST_SETPOINT

BOOST_OV_SD BOOST_OV_REACT

(latched, if read in this

condition it will go back to “0”)

After POR, the BOOST_OV flag may be set at first read

out. Please note that the booster overvoltage detection is also

active when Booster is OFF (booster disabled by SPI related

bit). Please note that the tolerances of the booster setpoint

level and the booster overvoltage and reactivation are given

in Table 11.

the MOSFET GATE as V

reaches its maximum

SENSE

threshold V

defined by the BST_VLIMTH[1:0]

SENSE_MAX

register (see IMAX comparator in Figure 13 and Table 12

for more details). Therefore, the maximum allowed peak

current will be defined by the ratio I

=

PEAK_MAX

V

/ R . The maximum current must be set

SENSE

SENSE_MAX

in order to allow the total desired booster power for the

lowest battery voltage. Warning: setting the current limit too

low may generate unwanted system behavior as

uncontrolled de−rating of the LED light due to insufficient

power.

Booster Current Regulation Loop

The peak−current level of the booster is set by the voltage

of the compensation pin COMP (output of the

trans−conductance error amplifier, “block B” of Figure 13).

This reference voltage is fed to the current comparator

Booster PWM Frequency and Disable

through a divider by 7 and compared to the voltage V

SENSE

The NCV78763 allows a flexible set of the booster PWM

frequency. Two modes are available: internal generation or

external drive, selectable by SPI bit setting

BOOST_SRC[0]. In either case, the booster must be enabled

via the dedicated SPI bit to allow PWM generation

(BOOST_EN = 1). When BOOST_EN = 0, the peripheral is

off and the GATE drive is disabled. Please note that the error

amplifier is not shut off automatically and to avoid voltage

on the external sense resistor R

, connected to the pins

SENSE

IBSTSENSE+ and IBSTSENSE−. The sense voltage is

created by the booster inductor coil current when the

MOSFET is switched on and is summed up to an additional

offset of +0.5 V (see COMP_

in Table 11) and on top of

VSF

that a slope compensation ramp voltage is added. The slope

compensation is programmable by SPI via the setting

(BOOST_SLP_CTRL[1:0]) and can also be disabled. Due

generation on the VCOMP pin the G gain must be put to

m

to the offset, current can start to flow in the circuit as V

COMP

zero as well.

> COMP_

.

VSF

Booster PWM Internal Generation

Offset plus slope compensation

ramp

This mode activated by BOOST_SRC = 0, creates the

PWM frequency starting from the internal clock FOSC8M.

A fine selection of frequencies is enabled by the register

BOOST_FREQ[4:0], ranging from typical 210 kHz to

typical 1 MHz (Table 11). The frequency generation is

disabled by selecting the value “zero”; this is also the POR

default value.

Current peak reached trigger

(duty cycle regulation)

to IBST

+

sense+pin

V

= I x R

L

SENSE

+

−

+

I_L

R

SENSE

+

V_COMP

1 / 7

GND

to IBST

sense−pin

Figure 15. Booster Peak Current Regulator Involved

in Current Control Loop

Booster PWM External Generation

When BOOST_SRC = 1, the booster PWM external

generation mode is selected and the frequency is taken

directly from the BOOST_SYNC device pin. There is no

actual limitation in the resolution, apart from the system

clock for the sampling and a debounce of two clock cycles

on the signal edges. The gate PWM is synchronized with

either the rising or falling edge of the external signal

depending on the BOOST_SRCINV bit value. The default

POR value is “0” and corresponds to synchronization to the

rising flank. BOOST_SRCINV equals “1” selects falling

edge synchronization.

The maximum booster peak−current is limited by a

dedicated comparator, presented in the next section.

Booster Current Limitation Protection

On top of the normal current regulation loop comparator,

an additional comparator clamps the maximum physical

current that can flow in the booster input circuit while the

MOSFET is driven. The aim is to protect all the external

components involved (boost inductor from saturation, boost

diode and boost MOSFET from overcurrent, etc…). The

protection is active PWM cycle−by−cycle and switches off

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21

NCV78763

BSTSYNC pin

1

0

DEBOUNCE

BOOST_SYN

(PWM synch)

MUX

0

1

BOOST_CLK_GENERATOR

MUX

BOOST_SRC

BOOST_EN

BOOST SRCINV

Figure 16. NCV78763 Booster Frequency Generation Block

Booster PWM Min TOFF and Min TON protection

As additional protection, the PWM duty cycle is

constrained between a minimum and a maximum, defined

per means of two parameters available in the device. The

PWM minimum on−time is programmable via

BOOST_TONMIN[1:0]: its purpose is to guarantee a

minimum activation interval for the booster MOSFET

GATE, to insure full drive of the component and avoiding

switching in the linear region. Please note that this does not

imply that the PWM is always running even when not

required by the control loop, but means that whenever the

MOSFET should be activated, then its on time would be at

least the one specified. At the contrary When no duty cycle

at all is required, then it will be zero.

protection mechanisms around are not taken into account. A

type “2” network is taken into account at the VCOMP pin.

The equivalent circuit is shown below:

V_COMP(t)

R₁

C_P

R_OUT

G_me(t)

R_P

C₁

The PWM minimum off−time is set via the parameter

BOOST_TOFFMIN[1:0]: this parameter is limiting the

maximum duty cycle that can be used in the regulation loop

Figure 17. Booster Compensator Circuit with Type

“2” Network

for a defined period T

:

In the Figure, e(t) represents the control error, equals to the

PWM

difference V

trans−conductance error amplifier gain, while “R

amplifier internal output resistance. The values of these two

parameters can be found in Table 11 in this datasheet.

By solving the circuit in Laplace domain the following

(t) − V

(t). “G ” is the

BOOST_SETPOINT

BOOST m

ǒ_T

_OFFMINǓ

* T

PWM

” is the

OUT

Duty

MAX

+

T

PWM

The main aim of a maximum duty cycle is preventing

MOSFET shoot−through in cases the (transient) duty cycle

would get too close to 100% of the MOSFET real switch−off

characteristics. In addition, as a secondary effect, a limit on

the duty cycle may also be exploited to minimize the inrush

current when the load is activated.

error to V

transfer function is obtained:

COMP

V

(s)

COMP

e(s)

H

(s) +

COMP

ǒ_{1 ) t s}

Ǔ

1

+ G

Warning: a wrong setting of the duty cycle constraints may

result in unwanted system behavior. In particular, a too big

^COMPǒ_{1 )}ǒ_t

_1PǓ_{s )}ǒ_t

_PǓ_sǓ

2

) t

t

1

P

T

may prevent the system to regulate the V

OFFMIN

BOOST

The explanation of the parameters stated in the equation

above follows:

with low battery voltages (V

the simplified formula for booster steady state continuous

mode:

). This can be explained by

BAT

G

+ G R

m

COMP

T

R

P

OUT

V

* V

BAT

V

BOOST

V

BAT

R

+

T

V

^

à Duty ^

R

) R

BOOST

ǒ

Ǔ

1 * Duty

BOOST

t

+ R C

1

So in order to reach a desired V

for a defined supply

BOOST

+ R C

₊ǒ_R^T

Ǔ_C

P

voltage a certain duty cycle must be guaranteed.

,

t

) R

T

1

1P

Booster Compensator Model

A linear model of the booster controller compensator

(block “A” Figure 13) is provided in this section. The

This transfer function model can be used for closed loop

stability calculations.

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22

NCV78763

Booster PWM skip cycles

mode. For hardware point of view, it is assumed that in

multiphase mode (N boosters), each stage has the same

external components. In particular, the values of the sense

resistors have to match as much as possible to have a

balanced current sharing. The following features have to be

considered as well:

In case of light booster load, it may be useful to reduce the

number of effective PWM cycles in order to get a decrease

of the input current inrush bursts and a less oscillating boost

voltage. This can be obtained by using the “skip cycles”

feature, programmable by SPI via BOOST_SKCL[1:0] (see

Table 11 and SPI map). BOOST_SKCL[1:0] = ‘00’ means

skip cycle disabled.

1. The compensation pin (COMP) of all boosters is

connected together to the same compensation

network, to equalize the power distribution of each

booster. For the best noise rejection, the

The selection defines the VCOMP voltage threshold

below which the PWM is stopped, thus avoiding V

BOOST

oscillations in a larger voltage window.

compensation network area has to be surrounded

by the GND plane. Please refer to the PCB Layout

recommendations section for more general

advices.

Booster Monophase or Multiphase Mode Principles

The NCV78763 booster can be operated in two main

modes: single phase (N = 1), or “multiphase” (N ≥ 2).

In single phase mode, a unique NCV78763 booster is

used, in the configuration shown in the standard application

diagram (Figure 4).

2. To synchronize the MOSFET gate PWM clock and

needed phase shifts, the boosters must use the

external clock generation (BSTSYNC), generated

by the board MCU or external logic, according to

the user−defined control strategy. The generic

number of lines needed is “N” equivalent to the

number of stages. Please note that in case of a

bi−phase system (N = 2) and an electrical phase

shift of 180°, it is possible to use only one external

clock line, exploiting the integrated NCV78763

features: the slave device shall have

In multiphase mode, more NCV78763 boosters can be

connected together to the same V

node, sharing the

BOOST

boost capacitor block. Multiphase mode shows to be a cost

effective solution in case of mid to high power systems,

where bigger external BOM components would be required

to bear the total power in one phase only with the same

performances and total board size. In particular, the boost

inductor could become a critical item for very high power

levels, to guarantee the required minimum saturation current

and RMS heating current.

Another advantage is the benefit from EMC point of view,

due to the reduction in ripple current per phase and ripple

voltage on the module input capacitor and boost capacitor.

The picture below shows the (very) ideal case of 50% duty

BOOST_SRCINV bit to “1” (clock polarity

internal inversion active), whereas the master

device will keep the BOOST_SRCINV bit to “0”

(= no inversion, default).

3. Only the master booster error amplifier OTA must

be active, while the other (slave) boosters must

have all their own OTA block disabled

cycle, the ripple of the total module current (I

=

Lmp_sum

(BOOST_OTA_GAIN[1:0] = ‘00’). For each of

the devices in the chain, the register

BOOST_MULTI_MD[1:0] must be kept to zero,

default (‘00’)

I

+ I

) is reduced to zero. The equivalent single

L1mp

L2mp

phase current (I ) is provided as a graphical comparison.

Lsp

4. In order to let the slave device(s) detect locally the

boost over-voltage condition thus disabling the

correspondent phase, the slave(s) must have the

same (or higher) booster overvoltage shutdown

level of the master device (see also section

“Booster overvoltage shutdown protection” for

more details on the protection mechanism and

threshold). The MCU shall monitor the

I_Lsp

I_{Lmp_sum}

I_L1mpI_L2mp

t

Figure 18. Booster Single Phase vs. Multiphase

Example (N = 2)

BOOST_OV flags to insure that all devices are

properly operating in the application.

Booster Multiphase Diagram and Programming

This section describes the steps both from hardware and

SPI programming point of view to operate in multiphase

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23

NCV78763

L

BOOST

D

BOOST

C

BOOST_IN

C

/ 3

BOOST

C

M3V

R

BOOST_SENSE

VGATE

VBB

C

VBB

BSTSYNC

COMP

NCV78763 #2

V _BAT

L

D

BOOST

(After rev. pol. prot.)

C

/

3

BOOST

C

BOOST_IN

C

M3V

R

BOOST_SENSE

VGATE

VBB

IBCK1SENSE+

IBCK1SENSE−

C

VBB

R

BUCK_SENSE_01

LED−string

1

VINBCK1

C

VDRIVE

VDD

VDRIVE

VDD

L

BUCK_01

LBCKSW1

VLED1

ON Semiconductor

LED driver

C

BUCK_01

Front Lighting

IBCK2SENSE+

IBCK2SENSE−

VINBCK2

R

L

BUCK_SENSE_02

BSTSYNC_01

BSTSYNC

COMP

LED−string

2

NCV78763 #1

C

P

SPI_MASTER_VDD

(Booster MASTER)

BUCK_02

R

C1

C

C1

LBCKSW2

VLED2

MCU

CTRL1

CTRL2

LEDCTRL1

LEDCTRL2

C

BUCK_02

SPI Master In Slave Output (MISO)

SPI Master Out Slave Input (MOSI)

SPI_MASTER_CLK

SDO

SDI

SCLK

SCSB

SPI_MASTER_CSB

TST

TST2

GNDP

EP

GND

PWR GND

Sig GND

Figure 19. Booster Bi−phase Application Diagram (N = 2)

L

BOOST

D

BOOST

L

BOOST

D

BOOST

C

BOOST_IN

C

/ 3

BOOST

C

BOOST_IN

C

/

3

BOOST

C

M3V

R

BOOST_SENSE

C

M3V

R

BOOST_SENSE

VGATE

VBB

C

VBB

VGATE

VBB

C

VBB

BSTSYNC

COMP

NCV78763 #3

BSTSYNC

COMP

NCV78763 #2

V _BAT

(After rev. pol. prot.)

L

D

BOOST

C

/ 3

BOOST

C

BOOST_IN

C

M3V

R

BOOST_SENSE

VGATE

VBB

IBCK1SENSE+

IBCK1SENSE−

C

VBB

R

BUCK_SENSE_01

LED−string

1

VINBCK1

C

VDRIVE

VDD

VDRIVE

VDD

L

BUCK_01

LBCKSW1

VLED1

ON Semiconductor

LED driver

C

BUCK_01

BSTSYNC_03

BSTSYNC_02

BSTSYNC_01

Front Lighting

IBCK2SENSE+

IBCK2SENSE−

VINBCK2

R

BUCK_SENSE_02

BSTSYNC

COMP

LED−string

2

NCV78763 #1

C

P

SPI_MASTER_VDD

(Booster MASTER)

L

BUCK_02

R

C1

C

C1

LBCKSW2

VLED2

MCU

CTRL1

CTRL2

LEDCTRL1

LEDCTRL2

C

BUCK_02

SPI Master In Slave Output (MISO)

SPI Master Out Slave Input (MOSI)

SPI_MASTER_CLK

SDO

SDI

SCLK

SCSB

SPI_MASTER_CSB

TST

TST2

GND

GNDP

EP

PWR GND

Sig GND

Figure 20. Booster Three−Phase Application Diagram (N = 3)

Booster Enable Control

happen that despite the user wanted activation, the booster

is stopped by the device in two main cases:

a. Whenever the boost overvoltage detection triggers

in the control loop. The booster is automatically

activated when the voltage falls below the

hysteresis (Figure 14).

The NCV78763 booster can be enabled/disabled directly

by SPI via the bit BOOST_EN[0]. The enable signal is the

transition from “0” to “1”; the disable function is vice−versa.

The status of the physical activation is contained in the flag

BOOST_STATUS: whenever the booster is running, the

value of the flag is one, otherwise zero. It might in fact

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24

NCV78763

b. When a voltage setpoint level plus overvoltage

protection higher than the maximum allowed by

the max ratings is entered, to avoid electrical

damage. In other notations, the following relation

must be respected to avoid disabling the booster

by wrong SPI setting:

The parameter I

device by means of the internal comparator threshold

is programmable through the

BUCK_peak

(V , Table XX) over the external sense resistor R

THR

:

BUCK

V

THR

I

+

BUCKpeak

R

BUCK

The formula that defines the total ripple current over the

buck inductor is also hereby reported:

{65 V − (127 − BOOST_VSETPOINT[6:0]) x

0.4 V + BOOST_OV_SD [V]} >

{67.8 V + (1 − 2 x VBOOST_OFF_COMP[3]) x

0.4 V x VBOOST_OFF_COMP[2:0]}

The value in register VBOOST_OFF_COMP[3:0] Is

stored by factoring trimming by ON Semiconductor,

individually per each device, to achieve maximum accuracy

with respect to the maximum voltage setting allowed.

ǒ_V

_DIODEǓ

T

) V

LED

OFF

DI

+

BUCKpkpk

L

BUCK

T

V

OFF_VLED_i

OFF

L

LED

^

+

L

BUCK

In the formula above, TOFF represents the buck switch off

time, VLED is the LED voltage feedback sensed at the

BUCK REGULATOR

NCV78763 VLED pin and LBUCK is the buck inductance

General

X

value. The parameter T

is programmable by SPI

The NCV78763 contains two high−current integrated

buck current regulators, which are the sources for the LED

strings. The bucks can be powered by the device own boost

regulator, or by a booster regulator linked to another

NCV78x63 device. Each buck controls the individual

OFF_VLED_i

(BUCKx_TOFFVLED[3:0]), with values related to Table 15.

In order to achieve a constant ripple current value, the device

varies the TOFF time inversely proportional to the VLED

sensed at the device pin, according to the selected factor

T

. As a consequence to the constant ripple

inductor peak current (I

) and incorporates a

OFF_VLED_i

BUCK_peak

control and variable off time, the buck switching frequency

is dependent on the boost voltage and LED voltage in the

following way:

constant ripple (DI

) control circuit to ensure also

BUCK_pkpk

stable average current through the LED string,

independently from the string voltage. The buck average

current is in fact described by the formula:

ǒ_V

_LEDǓ

* V

BOOST

V

1

f

+

DI

BUCK

BUCKpkpk

T

BOOST

OFF

I

+ I

*

BUCKpeak

BUCKAVG

2

ǒ_V

_LEDǓ

* V

V

BOOST

LED

This is graphically exemplified by Figure 21:

+

V

T

OFF_VLED_i

BOOST

Buck peak current

Buck

current

The LED average current in time (DC) is equal to the buck

time average current. Therefore, to achieve a given LED

current target, it is sufficient to know the buck peak current

and the buck current ripple. A rule of thumb is to count a

minimum of 50% ripple reduction by means of the capacitor

Buck average current

Buck current ripple

= T /L

OFF_V_BUCK BUCK

T_OFF

C_BUCKand this is normally obtained with a low cost ceramic

time

component ranging from 100 nF to 470 nF (such values are

typically used at connector sides anyway, so this is included

in a standard BOM). The following figure reports a typical

example waveform:

Figure 21. Buck Regulator Controlled Average

Current

Figure 22. LED Current AC Components Filtered Out by the Output Impedance (oscilloscope snapshot)

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25

NCV78763

The use of C

is a cost effective way to improve EMC

The complete buck circuit diagram follows:

BUCK

performances without the need to increase the value of

, which would be certainly a far more expensive

L

BUCK

solution.

C fil

BUCKx_OFF_COMP

VBSTM3

VBOOSTBCK

IBCKxSENSE -

R_sense

DC_DC

I-sense

IBCKxSENSE +

VINBCKx

POWER STAGE

Driver

I

BUCK

LBCKSWx

LED string

Over current

detect

L

C

D

I

LED

VLEDx

Digital

Control

Constant Ripple

Control

Figure 23. Buck Regulator Circuit Diagram

Different buck channels can be paralleled at the module

output (after the buck inductors) for higher current

capability on a unique channel, summing up together the

individual DC currents. Please note that for each channel,

the maximum buck allowed peak current is defined by the

buck overcurrent detection circuit, see dedicated section for

details.

cancellation is very effective in case of high precision levels

for low currents.

2 x I−sense comparator offset

Fixed peak level

Typical LED current

Toff = constant

In case of a non−used ”x” channel, it is suggested to short

circuit together the pins IBCKxSENSE+, IBCKxSENSE−,

VINBCKx and VBOOST. The pins LBCKSWx and VLEDx

can be left open.

Figure 24. Buck Offset Compensation Feature

Buck Overcurrent Protection

Being a current regulator, the NCV78763 buck is by

nature preventing overcurrent in all normal situations.

However, in order to protect the system from overcurrent

even in case of failures, two main mechanisms are available:

1. Internal sensing over the buck switch: when the

peak current rises above the maximum limit

(situated above 1.9 A, see Table 14), an internal

counter starts to increment at each period, until the

count written in

Buck Offset Compensation

The NCV78763 buck features a peak current offset

compensation that can be enabled by the SPI parameter

BUCKx_OFF_CMP_EN[0]. When this bit is “1”, the offset

changes polarity each buck period, so that the average effect

over time on the peak current is minimized (ideally zero). As

a consequence of the polarity change, the peak current is

toggling between two threshold values, one high value and

one low, as shown in the picture below. The related

sub−harmonic frequency (half the buck switching

frequency) will appear in the spectrum. This has to be taken

into account from EMC point of view. The use of the offset

BUCKx_OC_OCCMP_COUNT[2:0]+1 is

attained. The count is reset if the buck channel is

disabled and also at each dimming cycle. From the

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26

NCV78763

External Dimming

moment the count is reached onwards, the buck is

kept continuously off, until the SPI error flag

OCLEDx is read. After reading the flag, the buck

channel “x” is automatically re−enabled and will

try to regulate the current again. The failure related

to this protection mechanism is a short circuited

sense resistor on the “x” channel. In these

conditions in fact the voltage drop over the sensing

element (short circuit) will be very low even in

case of high currents.

The two independent control inputs LEDCTRLx handle

the dimming signals for the related channel “x”. This mode

is selected independently for buck channel ”1” by

DIM_SRC[0] = 1 and for channel 2 by DIM_SRC[1] = 1. In

external dimming, the buck activation is transparently

linked to the logic status of the LEDCTRLx pins. The only

difference is the controlled phase shift of typical 4 ms

(Table 16) that allows synchronized measurements of the

VLEDx pins via the ADC (see dedicated section for more

details). As the phase shift is applied both to rising edges and

falling edges, with a very limited jitter, the PWM duty cycle

is not affected. Apart from the phase shift and the system

clock OSC8M, there is no limitation to the PWM duty cycle

values or resolutions at the bucks, which is a copy of the

reference provided at the inputs.

2. Sensed voltage “I−sense” above the threshold:

when the voltage produced over the sense resistor

exceeds the desired threshold, another protection

counter increases at each switching period, until

the count defined by the SPI setting

BUCKx_OC_ISENSCMP_COUNT[6:0]+1 is

reached. As for the previous protection, the count

is reset if the buck channel is disabled and also at

each dimming cycle. The failure linked to this

protection mechanism is a short circuit at the LED

channel output and at the same time, a wrong

feedback voltage at the VLEDx pin (or higher than

the short circuit detection voltage typical 1.8 V,

Internal Dimming

This mode is selected independently for buck channel ”1”

by DIM_SRC[0] = 0 and for channel “2” by DIM_SRC[1]

= 0.

The register saturation value is per choice 1000 decimal,

corresponding to 100% (register values between 1000 and

1023 will all provide a 100% duty cycle). Each least

significant bit (lsb) change corresponds to a 0.1% duty cycle

change.

VLED_

in Table 15).

LMT

DIMMING

The dimming PWM frequency is common between the

channels and is programmable via the SPI parameter

PWM_FREQ[1:0], as displayed in the table below. All

frequencies are chosen sufficiently high to avoid the beads

effect in the application. Please also note that the higher the

frequency, the lower the voltage drop on the booster output

due to the lower load power step.

General

The NCV78763 supports both analog and digital

dimming (or so called PWM dimming). Analog dimming is

performed by controlling the LED amplitude current during

operation. This can be done by means of changing the peak

current level and/or the Toff_VLED_i constants by SPI

commands (see Buck Regulator section).

In this section, we only describe PWM dimming as this is

the preferred method to maintain the desired LED color

temperature for a given current rating. In PWM dimming,

the LED current waveform frequency is constant and the

duty cycle is set according to the required light intensity. In

order to avoid the beats effect, the dimming frequency

should be set at “high enough” values, typically above

300 Hz.

Table 21. INTERNAL PWM DIMMING

PROGRAMMABLE FREQUENCIES

PWM_FREQ[1:0]

PWM Frequency [Hz]

00

01

10

11

500

1000

2000

4000

The device handles two distinct PWM dimming modes:

external and internal, depending on the SPI parameter

DIM_SRC[1:0].

SPI INTERFACE

General

ZOOM: buck inductor switching current

The serial peripheral interface (SPI) allows the external

microcontroller (MCU) to communicate with the device to

read−out status information and to program operating

parameters after power−up. The NCV78763 SPI transfer

packet size is 16 bits. During an SPI transfer, the data is

simultaneously transmitted (shifted out serially) and

received (shifted in serially). A serial clock line (CLK)

synchronizes shifting and sampling of the information on

DIM_DUTY = DIM_T_ON/ DIM_T = DIM_T_ON× F

DIM_T _ON

DIM_T

Figure 25. Buck Current Digital or PWM Dimming

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27

NCV78763

the two serial data lines: SDO and SDI. The SDO signal is

the output from the Slave (LED Driver), and the SDI signal

is the output from the Master.

A slave or chip select line (CSB) allows individual

selection of a slave SPI device in a time multiplexed

multiple−slave system.

The CSB line is active low. If an NCV78763 is not

selected, SDO is in high impedance state and it does not

interfere with SPI bus activities. Since the NCV78763

always clocks data out on the falling edge and samples data

in on rising edge of clock, the MCU SPI port must be

configured to match this operation.

The SPI CLK idles low between transferred frames. The

diagram below is both a master and a slave timing diagram

since CLK, SDO and SDI pins are directly connected

between the Master and the Slave.

Figure 26. NCV78763 SPI Transfer Format

Note: The data transfer from the shift register into the locally

used registers, interpretation of the data is only done at the

rising edge of CSB.

means of both star connection (one individual CSB per

Slave, while SDI, SDO, CLK are common) or by means of

daisy chain (common CSB signal and clock, while the data

lines are cascaded as in the figure). An SPI star connection

requires a bus = (3 + N) total lines, where N is the number

of Slaves used, the SPI frame length is 16 bits per

communication. Regarding the SPI daisy chain connection,

the bus width is always four lines independently on the

number of slaves. However, the SPI transfer frame length

will be a multiple of the base frame length so N x 16 bits per

communication: the data will be interpreted and read in by

the devices at the moment the CSB rises.

The Data that is send over to the shift register to be

transmitted to the external MCU is sampled at the falling

edge of CSB, just at the moment the transmission starts.

The implemented SPI block allows interfacing with

standard MCUs from several manufacturers. When

interfaced, the NCV78763 acts always as a Slave and it

cannot initiate any transmission. The MCU is instead the

master, able to send read or write commands. The

NCV78763 SPI allows connection to multiple slaves by

MOSI

NCV78x63 dev#1

MCU

(SPI Master)

MISO

SDO1

(SPI Slave)

CSB1

SDI2

NCV78x63 dev#2

CSB2

MCU

(SPI Master)

NCV78x63 dev#2

SDO2

(SPI Slave)

SDIN

CSBN

NCV78x63 dev#N

SDON

(SPI Slave)

(SPISlave)

Figure 27. SPI Star vs. Daisy Chain Connection

A diagram showing the data transfer between devices in

daisy chain connection is given on the right: CMDx

represents the 16−bit command frame on the data input line

transmitted by the Master, shifting via the chips’ shift

registers through the daisy chain. The chips interpret the

command once the chip select line rises.

Figure 28. SPI Daisy Chain Data Shift Between

Slaves. The symbol ‘x’ represents the previous

content of the SPI shift register buffer.

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28

NCV78763

The NCV78763 default power up communication mode

• Bits [9:0]: 10−bit data to write. The control register

field is in fact 10 bits wide. See SPI Map for details.

Still referring to the picture, at the same time of the

exchange, the device replies on the SDO line either with:

• If the previous command was a write and no SPI error

had occurred, a copy of the address and data written; in

case of previous SPI error, or at power−on−reset (POR),

the response will be frame containing with only the msb

equals to one;

is “star”. In order to enable daisy chain mode, a multiple of

16 bits clock cycles must be sent to the devices, while the

SDI line is left to zero. Note: to come back to star mode the

NOP register (address 0x0000) must be written with all

ones, with the proper data parity bit and parity framing bit:

see SPI protocol for details about parity and write operation.

SPI Protocol: Write / Read

Two main actions are performed by the NCV78763 SPI:

write to control register and read from register (status or

control). Control registers contain the parameters for the

device operations to flexibly adapt to the application system

requirements (control loop settings, voltage settings,

dimming modes, etc…), while status registers bear the

system information interpreted by the NCV78763 logic,

such as diagnostics flags and ADC values. Each

communication frame is protected by parity (ODD) for a

more robust data transfer.

• If the precedent command was a read, the response

frame summarizes the address used and an overall

diagnostic check (copy of the main detected errors, see

diagnostic section for details).

The parity bit plays a fundamental role in each

communication frame; would the parity be wrong, the

NCV78763 will not store the data to the designated address

and the SPIERR flag will be set.

The frame protocol for the read operation is:

For the rest, the general transfer rules are:

• Commands and data are shifted; MSB first, LSB last.

• Each output data bit from the device into the SDO line

are shifted out on the falling (detected) edge of the

CLK signal;

Read: CMD = ‘0’

CSB

High

LED1 = OPENLED1 or SHORTLED1

Low

LED2 = OPENLED2 or SHORTLED2

BUCKOC = OCLED1 or OCLED2

−> immediate value of STATUS BITS; dedicated

SPI READ Command of STATUS Register has

to be performed to clear the value of

read-by-clear STATUS bits

C

M

D

A A A A A

4 3 2 1 0

DIN

P

Low

• Each input bit on the SDI line is sampled in on the

S

P

I

E

R

B

Low

U

C

K

O

C

L

E

D

2

L

E

D

1

T

S

D

D D D D D D D D D D

9 8 7 6 5 4 3 2 1 0

T

W

rising (detected) edge of CLK;

Data at [4:0] shall be

returned

DOUT

Low

HIGH−Z

• Data transfer out from SDO starts with the (detected)

falling edge of CSB; prior to that, the SDO open−drain

transistor is High−Z (the voltage will be the one

provided through the external pull−up);

Low

SCLK

• All SPI timing rules are defined by Table 19.

The frame protocol for the write operation is hereby

provided:

P =

n0t (A4 xor cmd xor A3 xor A2 xor A1 xor A0)

Figure 30. SPI Read Frame

Taking the figure above into account, the read frame

coming from the master (into the chip SDI) is formed by:

• Bit [15] (msb): CMD bit = 0;

Write; CMD = ‘1’

High

CSB

Low

• Bits [14:10]: 5−bits READ ADDRESS field;

• Bit [9]: read frame parity bit. It is ODD, formed by the

negated XOR of all the other bits in the frame;

C

M

D

A A A A D D D D D D D D D D

P

DIN

Low

3 2 1 0

9 8 7 6 5 4 3 2 1 0

Previous SPI WRITE

command resp. “SPIERR

+0x000hex” (after POR)

or in case of SPI

Low

S

P

I

E

R

C

M

D

A A A A D D D D D D D D D D

3 2 1 0 9 8 7 6 5 4 3 2 1 0

DOUT

Low

• Bits [8:0]: 9−bits zeroes field.

Command

HIGH−Z

PARITY/FRAMING Error

Previous SPI READ

command & L763

bits resp. “SPIERR +

0x000hex” after POR or in

case of SPI Command

PARITY/FRAMING Error

The device answers immediately via the SDO in the same

read frame with the register’s content thus achieving the

lowest communication latency.

S

P

I

E

R

B

C

M

D

U

C

K

O

C

L

E

D

2

L

E

D

1

T

S

D

A A A A A

4 3 2 1 0

T

W

P 1 1 1

Low

SCLK

Note: all status registers that are ”cleared by read” (latched

information) require a proper parity bit in order to execute

the clearing out. Please be aware that the device will still

send the information even if the parity is wrong. The MCU

can still take action based on the value of the SPIERR bit.

The SPIERR state can be reset only by reading the related

status register. See SPI map and the next section for more

details.

P

=

not(CMD xor A3 xor A2 xor A1 xor A0 xor D9 xor D8 xor D7 xor

D6 xor D5 xor D4 xor D3 xor D2 xor D1 xor D0)

Figure 29. SPI Write Frame

Referring to the previous picture, the write frame coming

from the master (into the chip SDI) is composed as follows:

• Bit [15] (msb): CMD bit = 1;

• Bits [14:11]: 4−bits WRITE ADDRESS field;

• Bit [10]: frame parity bit. It is ODD, formed by the

negated XOR of all the other bits in the frame;

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29

NCV78763

SPI Protocol: Framing and Parity Error

SPI ADDRESS MAP

SPI communication framing error is detected by the

NCV78763 in the following situations:

• Not an integer multiple of 16 CLK pulses are received

during the active−low CSB signal;

Starting from the left column, the table shows the address

in (byte hexadecimal format), the access type (Read = R /

Write = W) and the bits’ indexes.

Details for the single registers are provided in the

following section.

• LSB bits (8..0) of a read command are not all zero;

• SPI parity errors, either on write or read operation.

Once an SPI error occurs, the SPI ERR flag can be reset

only by reading the status register in which it is contained

(using in the read frame the right communication parity bit).

Table 22. NCV78763 SPI ADDRESS MAP

ADDR

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

OTHERS

R/W

NA

R/W

R

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

NOP register (read/write operation ignored)

BOOST_FREQ[4:0]

BOOST_OTA_GAIN[1:0]

BOOST_TOFF_MIN[1:0]

BOOST_SLPCTRL[1:0]

BOOST_OV_SD[2:0]

BOOST_SRC

VBOOST_VGATE_THR

BOOST_SRCINV

BOOST_EN

BOOST_OV_REACT[1:0]

BOOST_VSETPOINT[6:0]

VDRIVE_BST_EN

BOOST_VLIMTH[1:0]

BUCK2_OFF_CMP_EN

BUCK1_OFF_CMP_EN

BUCK1_VTHR[7:0]

BUCK2_VTHR[7:0]

BOOST_TON_MIN[1:0]

BUCK1_TOFF_VLED[3:0]

BUCK2_TOFF_VLED[3:0]

THERMAL_WARNING_THR[7:0]

BUCK1_EN

BUCK2_EN

BOOST_SKCL[1:0]

VDRIVE_VSETPOINT[3:0]

BOOST_MULTI_MD[1:0]

PWM_DUTY1[9:0]

PWM_DUTY2[9:0]

DIM_SRC[1:0]

PWM_FREQ[1:0]

BUCK1_OC_OCCMP_COUNT[2:0]

BUCK1_OC_ISENSCMP_COUNT[6:0]

BUCK2_OC_ISENSCMP_COUNT[6:0]

BUCK2_OC_OCCMP_COUNT[2:0]

0x0

LED_SEL_DUR[8:0]

VLED1ON[7:0]

ODD PARITY

0x0

R

VLED2ON[7:0]

VLED1[7:0]

R

VLED2[7:0]

R

VTEMP[7:0]

R

VBOOST[7:0]

R

VBAT[7:0]

R

BUCK1_TON_DUR[7:0]

BUCK2_TON_DUR[7:0]

SHORTLED1

R

BUCKACTIVE1

BUCKACTIVE2

BOOST_OV

OPENLED1

OCLED1

LEDCTRL2VAL

OPENLED2

SPIERR

SHORTLED2

TSD

OCLED2

TW

R

BOOST_STATUS

TEST1_FAIL

HWR

LEDCTRL1VAL

R

0x0

VBOOST_OFF_COMP[4:0]

R

REVID[7:0]

R

0x0

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30

NCV78763

SPI REGISTERS DETAILS

ID: Register 0 /CR00: No Operation

Bit#

9

8

0

7

6

5

0

4

3

0

2

0

1

0

Field

NOP[9:0]

Reset Value (POR)

POR

0

Address

0x00hex

Access: N.A. (Not Applicable)

Bit

Name

NOP[9:0]

Description

No Operation register. Always reads zero and cannot be written. When in daisy chain

mode, trying to write all ones in the data field will force a change to SPI star mode.

9..0

ID: Register 1 /CR01: Booster Settings 01

Bit#

9

8

7

0

6

5

4

3

0

2

1

0

Field

BOOST_OTA_GAIN[1:0]

BOOST_FREQ[4:0]

BOOST_SLPCTRL[1:0]

BOOST_SRC[0]

Reset Value (POR)

POR

0

Address

0x01hex

Access: Read/Write

Bit

Name

Description

Booster Settings register, group 01:

•

Bit [0] − BOOST_SRC[0]: booster clock selection. When this bit equals one, external

clock is selected. Otherwise, internal clock in combination with the register

BOOST_FREQ[4:0].

9..0

BST_SET_01[9:0]

•

Bits [2:1] − BOOST_SLPCTRL[1:0]: booster slope compensation selection.

Bits [7:3] − BOOST_FREQ[4:0]: booster frequency programming with internal gener-

ation (BOOST_SRC[0] = 0)

•

Bits [9:8] − BOOST_OTA_GAIN[1:0]: booster error amplifier gain. Zero means output

in high impedance.

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31

NCV78763

ID: Register 2 /CR02: Booster Settings 02

Bit#

9

8

7

6

5

4

3

2

1

0

Field

BOOST_MIN_TOFF[1:0]

BOOST_VGATE_THR[0]

BOOST_SRC_INV[0]

Reset Value (POR)

0

BOOST_EN[0]

BOOST_OV_REACT[1:0]

BOOST_OV_SD[2:0]

POR

0

Address

0x02hex

Access: Read/Write

Bit

Name

Description

Booster Settings register, group 02:

•

Bits [2:0] − BOOST_OV_SD[2:0]: booster overvoltage shutdown. Controls the maximum allowed overshoot with respect to the regula-

tion target.

•

Bits [4:3] − BOOST_OV_REACT[1:0]: booster overvoltage reactivation. Defines the hysteresis for the reactivation once the overvolt-

age shutdown is triggered.

9..0

BST_SET_02[9:0]

•

Bit [5] − BOOST_EN[0]: booster enable. Controls the activation status of the booster (enabled when the bit is one).

Bit [6] − BOOST_SRC_INV[0]: booster clock inversion. Controls the polarity of the clock source (“1” = inverted).

Bit [7] − BOOST_VGATE_THR[0]: booster gate voltage threshold: defines the minimum voltage below which the MOSFET is consid-

ered off, allowing next start of the on time

•

Bit [9:8] − BOOST_MIN_TOFF[1:0]: booster minimum off−time setting.

ID: Register 3 /CR03: Booster Settings 03

Bit#

9

8

7

6

0

5

0

4

3

2

1

0

Field

VDRIVE_BST_EN[0]

BOOST_VLIMTH[1:0]

BOOST_VSETPOINT[6:0]

Reset Value (POR)

POR

0

Address

0x03hex

Access: Read/Write

Bit

Name

Description

Booster Settings register, group 03:

•

Bits [6:0] − BOOST_VSETPOINT[6:0]: booster regulation setpoint voltage.

Bits [8:7] − BOOST_VLIMTH[1:0]: booster current limitation peak value. Defines

the threshold for the current cycle by cycle peak comparator across the external

sense resistor.

9..0

BST_SET_03[9:0]

•

Bit [9] − VDRIVE_BST_EN[0]: controls the activation of the

VBOOST_AUX_SUPPLY (VDRIVE powered via the booster for low battery

voltages)

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NCV78763

ID: Register 4 /CR04: Buck Settings 01

Bit#

9

8

7

0

6

0

5

4

3

2

1

0

Field

BUCK1_OFF_CMP_EN[0]

BUCK2_OFF_CMP_EN[0]

Reset Value (POR)

0

BUCK1_VTHR[7:0]

POR

0

Address

0x04hex

Access: Read/Write

Bit

Name

Description

Buck Settings register, group 01:

•

Bits [7:0] − BUCK1_VTHR[7:0]: buck regulator channel 1 comparator threshold volt-

age setting.

Bit [8] − BUCK2_OFF_CMP_EN[0]: when programmed to one, the offset compensa-

tion for buck 2 is activated.

Bit [9] − BUCK1_OFF_CMP_EN[0]: when programmed to one, the offset compensa-

tion for buck 1 is activated.

9..0

BCK_SET_01[9:0]

ID: Register 5 /CR05: Buck Settings 02

Bit#

9

8

0

7

6

5

0

4

3

2

0

1

0

Field

BOOST_TON_SET[1:0]

BUCK2_VTHR[7:0]

Reset Value (POR)

POR

0

Address

0x05hex

Access: Read/Write

Bit

Name

Description

Buck Settings register, group 02:

9..0

BCK_SET_02[9:0]

•

Bits [7:0] − BUCK2_VTHR[7:0]: buck regulator channel 2 comparator threshold voltage setting.

Bit [9:8] − BOOST_TON_SET[1:0]: booster minimum on time setting.

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NCV78763

ID: Register 6 /CR06: Buck Settings 03

Bit#

9

8

7

6

4

3

2

1

0

Field

BUCK1_TOFF_VLED[3:0]

BUCK2_TOFF_VLED[3:0]

Reset Value (POR)

BUCK_1_EN

BUCK_2_EN

POR

0

Address

0x06hex

Access: Read/Write

Bit

Name

Description

Buck Settings register, group 03:

•

Bit [0] − BUCK1_EN[0]: buck regulator channel 1 enable bit.

Bit [1] − BUCK2_EN[0]: buck regulator channel 2 enable bit.

Bits [5:2] − BUCK2_TOFF_SET[3:0]: tunes the Toff x VLED value for channel 2.

Bits [9:6] − BUCK1_TOFF_SET[3:0]: tunes the Toff x VLED value for channel 1.

9..0

BCK_SET_03[9:0]

ID: Register 7 /CR07: General Settings 01

Bit#

9

8

7

1

6

5

4

3

2

1

0

Field

BOOST_SKCL[1:0]

THERMAL_WARNING_THR[7:0]

Reset Value (POR)

POR

0

1

0

Address

0x07hex

Access: Read/Write

Bit

Name

Description

General settings register, group 01:

•

Bits [7:0] − THERMAL_WARNING_THR[7:0]: thermal warning threshold setting. At POR,

the register value equals the thermal shutdown value (factory trimmed) minus 10° Celsius.

The formula between the SPI value and the temperature physical value is TEMP [°C] =

SPI_VALUE (dec) − 20.

9..0

GEN_SET_01[9:0]

•

Bit [9:8] − BOOST_SKCL[1:0]: booster skip clock cycles setting.

ID: Register 8 /CR08: General Settings 02

Bit#

9

8

7

6

5

4

3

2

1

0

Field

VDRIVE_SETPOINT[3:0]

BOOST_MULTI_MD[1:0]

Reset Value (POR)

DIM_SRC[1:0]

PWM_FREQ[1:0]

POR

0

Address

0x08hex

Access: Read/Write

Bit

Name

Description

General settings register, group 02:

•

Bits [1:0] − PWM_FREQ[1:0]: frequency selection for internal LED dimming generation.

Bits [3:2] − DIM_SRC[1:0]: dimming external vs. internal generation selection.

Bits [5:4] − BOOST_MULTI_MD[1:0]: reserved combination. Must be kept to zero.

Bits [9:6] − VDRIVE_SETPOINT[3:0]: setpoint voltage for VDRIVE regulator.

9..0

GEN_SET_02[9:0]

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NCV78763

ID: Register 9 /CR09: PWM DUTY 01

Bit#

9

8

7

6

5

4

3

0

2

0

1

0

Field

PWM_DUTY_01[9:0]

Reset Value (POR)

POR

0

Address

0x09hex

Access: Read/Write

Bit

Name

Description

PWM duty cycle setting for channel 1:

9..0

PWM_DUTY_01[9:0]

•

Bits [9:0] − PWM_DUTY_01[9:0]: PWM duty cycle programming for channel 1 in

case of internal dimming (1023dec = 100% duty cycle)

ID: Register 10 /CR10: PWM DUTY 02

Bit#

9

8

0

7

6

5

4

3

0

2

0

1

0

Field

PWM_DUTY_02[9:0]

Reset Value (POR)

POR

0

Address

0x0Ahex

Access: Read/Write

Bit

Name

Description

PWM duty cycle setting for channel 2:

9..0

PWM_DUTY_02[9:0]

•

Bits [9:0] − PWM_DUTY_02[9:0]: PWM duty cycle programming for channel21 in

case of internal dimming (1023dec = 100% duty cycle)

ID: Register 11 /CR11: Overcurrent Settings 01

Bit#

9

8

7

6

5

0

4

3

2

1

0

Field

BUCK1_OC_OCCMP_COUNT[2:0]

BUCK1_OC_ISENSCMP_COUNT[6:0]

Reset Value (POR)

POR

0

Address

0x0Bhex

Access: Read/Write

Bit

Name

Description

Overcurrent settings register, group 01:

•

Bits [6:0] − BUCK1_OC_ISENSCMP_COUNT[6:0]: overcurrent via the ISENSE 1

comparator − counter settings.

9..0

OVC_SET_01[9:0]

•

Bits [9:7] − BUCK1_OC_OCCMP_COUNT[2:0]: overcurrent via internal switch 1

comparator − counter settings.

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NCV78763

ID: Register 12 /CR12: Overcurrent Settings 02

Bit#

9

8

7

6

0

5

4

3

2

1

0

Field

BUCK2_OC_OCCMP_COUNT[2:0]

Reset Value (POR)

BUCK2_OC_ISENSCMP_COUNT[6:0]

POR

0

Address

0x0Chex

Access: Read/Write

Bit

Name

Description

Overcurrent settings register, group 02:

•

Bits [6:0] − BUCK2_OC_ISENSCMP_COUNT[6:0]: overcurrent via the

ISENSE 2 comparator − counter settings.

9..0

OVC_SET_02[9:0]

•

Bits [9:7] − BUCK2_OC_OCCMP_COUNT[2:0]: overcurrent via internal

switch 2 comparator − counter settings.

ID: Register 13 /CR13: LED channel sampling selection time

Bit#

9

0

8

7

6

5

4

3

0

2

0

1

0

Field

LED_SEL_DUR[8:0]

Reset Value (POR)

POR

0

Address

0x0Dhex

Access: Read/Write

Bit

Name

Description

LED channel sampling duration

•

Bits [8:0] − LED_SEL_DUR[8:0]: LED sampling duration selection (linked to the ADC

functioning, see details in ADC section).

9..0

LED_SEL_DUR[8:0]

•

Bit [9] − Not used (will be always read out as zero).

ID: Register 14 / ADC 01: LED voltage ON measurement for channel 01

Bit#

9

0

8

7

6

5

0

4

3

2

0

1

0

Field

ODD Parity

VLED1ON[7:0]

Reset Value (POR)

POR

0

1

0

Address

0x0Ehex

Access: Read only

Bit

Name

Description

VLED channel 1 ON measurement

•

Bits [7:0] − VLED1ON[7:0]: LED channel 1 on measurement − byte value.

Bit [8] − VLED1ON[8]: LED channel 1 on measurement − parity bit (ODD).

Bit [9] − Not Used.

9..0

VLED1ON[8:0]

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36

NCV78763

ID: Register 15 / ADC 02: LED voltage ON measurement for channel 02

Bit#

9

0

8

7

6

5

0

4

3

2

0

1

0

Field

ODD Parity

VLED2ON[7:0]

Reset Value (POR)

POR

0

1

0

Address

0x0Fhex

Access: Read only

Bit

Name

VLED2ON[8:0]

Description

9..0

VLED channel 2 ON measurement

•

Bits [7:0] − VLED2ON[7:0]: LED channel 2 on measurement − byte value.

Bit [8] − VLED2ON[8]: LED channel 2 on measurement − parity bit (ODD).

Bit [9] − Not Used.

ID: Register 16 / ADC 03: LED voltage measurement for channel 01

Bit#

9

0

8

7

6

5

0

4

3

2

0

1

0

Field

ODD Parity

VLED1[7:0]

Reset Value (POR)

POR

0

1

0

Address

0x10hex

Access: Read only

Bit

Name

Description

VLED channel 1 measurement

•

Bits [7:0] − VLED1[7:0]: LED channel 1 on measurement − byte value.

Bit [8] − VLED1[8]: LED channel 1 on measurement − parity bit (ODD).

Bit [9] − Not Used.

9..0

VLED1[8:0]

ID: Register 17 / ADC 04: LED voltage measurement for channel 02

Bit#

9

0

8

7

6

5

0

4

3

2

0

1

0

Field

ODD Parity

VLED2[7:0]

Reset Value (POR)

POR

0

1

0

Address

0x11hex

Access: Read only

Bit

Name

Description

VLED channel 2 measurement

•

Bits [7:0] − VLED2[7:0]: LED channel 2 on measurement − byte value.

Bit [8] − VLED2[8]: LED channel 2 on measurement − parity bit (ODD).

Bit [9] − Not Used.

9..0

VLED2[8:0]

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37

NCV78763

ID: Register 18 / ADC 05: on−chip temperature measurement

Bit#

9

0

8

7

6

5

4

3

2

1

0

Field

ODD Parity

VTEMP[7:0]

Reset Value (POR)

POR

0

X

Address

0x12hex

Access: Read only

Bit

Name

Description

On−chip temperature measurement

•

Bits [7:0] − VTEMP[7:0]: on chip temperature measurement − byte value.

Bit [8] − VTEMP[8]: on chip temperature − parity bit (ODD).

Bit [9] − Not Used.

9..0

VTEMP[8:0]

ID: Register 19 / ADC 06: boost voltage measurement

Bit#

9

0

8

7

6

5

4

3

2

1

0

Field

ODD Parity

VBOOST[7:0]

Reset Value (POR)

POR

0

X

Address

0x13hex

Access: Read only

Bit

Name

Description

Boost voltage measurement

•

Bits [7:0] − VBOOST[7:0]: boost voltage measurement − byte value.

Bit [8] − VBOOST[8]: boost voltage measurement − parity bit (ODD).

Bit [9] − Not Used.

9..0

VBOOST[8:0]

ID: Register 20 / ADC 07: battery voltage measurement

Bit#

9

0

8

7

6

5

4

3

2

1

0

Field

ODD Parity

VBB[7:0]

Reset Value (POR)

POR

X

Address

0x14hex

Access: Read only

Bit

Name

Description

Battery voltage measurement (on VBB pin)

•

Bits [7:0] − VBB[7:0]: battery voltage measurement − byte value.

Bit [8] − VBB[8]: battery voltage measurement − parity bit (ODD).

Bit [9] − Not Used.

9..0

VBB[8:0]

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38

NCV78763

ID: Register 21 / BUCK1_TON: buck 01 on−time measurements

Bit#

9

0

8

7

6

5

0

4

3

2

0

1

0

Field

ODD Parity

BUCK1_TON_DUR[7:0]

Reset Value (POR)

POR

0

1

0

Address

0x16hex

Access: Read only

Bit

Name

Description

Buck 01 on−time duration measurement

•

Bits [7:0] − BUCK1_TON_DUR[7:0]: buck 01 on−time measurement − byte value

(multiples of 250ns typ.)

9..0

BUCK1_TON_DUR[8:0]

•

Bit [8] − BUCK1_TON_DUR[8]: buck 01 on−time measurement − parity bit (ODD).

Bit [9] − Not Used.

ID: Register 22 / BUCK2_TON: buck 02 on−time measurements

Bit#

9

0

8

7

6

5

0

4

3

2

0

1

0

Field

ODD Parity

BUCK2_TON_DUR[7:0]

Reset Value (POR)

POR

0

1

0

Address

0x16hex

Access: Read only

Bit

Name

Description

Buck 02 on−time duration measurement

•

Bits [7:0] − BUCK2_TON_DUR[7:0]: buck 02 on−time measurement − byte value

(multiples of 250ns typ.)

9..0

BUCK2_TON_DUR[8:0]

•

Bit [8] − BUCK2_TON_DUR[8]: buck 02 on−time measurement − parity bit (ODD).

Bit [9] − Not Used.

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39

NCV78763

ID: Register 23 / Status Register 01

Bit#

9

8

7

6

5

4

3

2

1

0

ODD

PARITY

Field

0

BUCKACTIVE1

BUCKACTIVE2

OPENLED1

SHORTLED1

OCLED1

OPENLED2

SHORTLED2

OCLED2

Reset Value (POR)

POR

0

X

R

0

X

0

L

X

L

0

L

Flags type (Latched = L; Non−latched = R; Not applicable = N.A.)

Type

N.A.

R

L

Address

0x17hex

Access: R

Bit

Name

Description

Status register 01

•

Bit [0] − OCLED2[0]: buck channel 02 overcurrent flag (1 = overcurrent detected)

Bit [1] − SHORTLED2[0]: buck channel 02 shorted LED string detection flag (1 = short detected)

Bit [2] − OPENLED2[0]: buck channel 02 open LED string detection flag (1 = open detected)

Bit [3] − OCLED1[0]: buck channel 01 overcurrent flag (1 = overcurrent detected)

Bit [4] − SHORTLED1[0]: buck channel 01 shorted LED string detection flag (1 = short detected)

Bit [5] − OPENLED1[0]: buck channel 01 open LED string detection flag (1 = open detected)

Bit [6] − BUCKACTIVE2[0]: buck 02 active channel flag (1 = active)

Bit [7] − BUCKACTIVE1[0]: buck 01 active channel flag (1 = active)

Bit [8] − Status 01 parity bit (ODD).

9..0

STATUS_REG_01[9:0]

Bit [9] − Not Used.

ID: Register 24 / Status Register 02

Bit#

9

0

8

7

6

5

4

3

2

1

0

Field

ODD PARITY

BOOST_STATUS

BOOST_OV

RESERVED

LEDCTRL1VAL

LEDCTRL2VAL

SPIERR

TSD

TW

Reset Value (POR)

POR

0

X

R

0

X

R

X

L

X

L

Flags type (Latched = L ; Non latched = R; Not applicable = N.A.)

Type

N.A.

R

L

N.A.

R

L

Address

0x18hex

Access: R

Bit

Name

Description

Status register 02

•

Bit [0] − TW[0]: thermal warning flag (1 = thermal warning detected).

Bit [1] − TSD[0]: thermal shutdown flag (1 = thermal shutdown detected).

Bit [2] − SPIERR[0]: SPI error (1 = error detected).

Bit [3] − LEDCTRL2VAL[0]: LEDCTRL2 input pin logic value (1 = input high)

Bit [4] − LEDCTRL1VAL[0]: LEDCTRL1 input pin logic value (1 = input high)

Bit [5] − RESERVED[0]: reserved bit. Read as zero.

Bit [6] − BOOST_OV[0]: boost overvoltage flag (1 = overvoltage detected)

Bit [7] − BOOST_STATUS[0]: booster activation physical status (1 = active)

Bit [8] − Status 01 parity bit (ODD).

9..0

STATUS_REG_02[9:0]

Bit [9] − Not Used.

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40

NCV78763

ID: Register 25 / Status Register 03

Bit#

9

0

8

7

0

6

0

5

4

3

2

1

0

Field

ODD PARITY

HWR

VBOOST_OFF_COMP[4:0]

Reset Value (POR)

POR

Type

0

X

0

1

X

R

X

R

X

R

Flags type (Latched = L ; Non latched = R; Not applicable = N.A.)

N.A. N.A. R

N.A.

R

L

R

Address

0x19hex

Access: R

Bit

Name

Description

Status register 02

•

Bit [4:0] − VBOOST_OFF_COMP[4:0]: booster measurement compensa-

tion code (result of factory trimming)

•

Bit [5] − HWR: hardware reset flag (1 = device is out of reset / after power

up).

9..0

STATUS_REG_03[9:0]

•

Bit [7:6] − Not Used. Read as zero.

Bit [8] − Status 03 parity bit (ODD).

Bit [9] − Not Used. Read as zero.

ID: Register 26 / REVISION ID

Bit#

9

0

8

0

7

6

5

0

4

3

2

1

0

Field

REVID[7:0]

Reset Value (POR)

POR

0

1

0

Flags type (Latched = L ; Non latched = R; Not applicable = N.A.)

N.A.

Type

N.A.

R

Address

0x1Ahex

Access: R

Bit

Name

Description

Revision ID

•

Bit [7:0] − REV_ID[4:0]: revision ID information register. Reports the device

revision number. Please note that this register is not protected by parity

and it is read only. The REV ID can be exploited by the by the microcon-

troller to recognize the device and its revision, thus adapting the firmware

parameters.

9..0

REV_ID[7:0]

•

Bit [9:8] − Not Used. Read as zero.

NOTE: All other registers addresses are read only and report zeroes.

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41

NCV78763

DIAGNOSTICS

means of the flag SHORTLEDx (latched, STATUS 01).

The detection is based on the voltage measured at the

VLEDx pins via a dedicated internal comparator: when

The NCV78763 features a wide range of embedded

diagnostic features. Their description follows. Please also

refer to the previous SPI section for more details.

the voltage drops below the VLED

minimum

_LMT

threshold (typical 1.8 V, see Table 15) the related flag is

set. Together with the detection, a fixed TOFF is used.

Note that the detection is active also when the LEDx

channel is off (in this case the fixed TOFF does not

play any role).

Diagnostics Description

• Thermal Warning: this mechanism detects a

user−programmable junction temperature which is in

principle close, but lower, to the chip maximum

allowed, thus providing the information that some

action (power de−rating) is required to prevent

overheating that would cause Thermal Shutdown. A

typical power de−rating technique consists in reducing

the output dimming duty cycle in function of the

temperature: the higher the temperature above the

thermal warning, the lower the duty cycle. The thermal

warning flag (TW) is given in STATUS register 02 and

is latched. At power up the default thermal warning

threshold is typically 159°C (SPI code 179).

• Thermal Shutdown: this safety mechanism intends to

protect the device from damage caused by overheating,

by disabling the booster and both buck channels, main

sources of power dissipation. The diagnostic is

displayed per means of the TSD bit in STATUS 02

(latched). Once occurred, the thermal shutdown

condition is automatically exited when the temperature

falls below the thermal warning level. The TSD flag is

instead latched and cleared by SPI reading. The

application thermal design should be made as such to

avoid the thermal shutdown in the worst case

conditions. The thermal shutdown level is not user

programmable and factory trimmed (see ADC_TSD in

Table 10).

• Overcurrent on Channel x: this diagnostics protects

the LEDx and the buck channel x electronics from

overcurrent. As the overcurrent is detected, the

OCLEDx flag (latched, STATUS 01) is raised and the

related buck channel is disabled. More details about the

detection mechanisms and parameters are given in

section “Buck Overcurrent Protection”.

• Buck Active x: these flags report the actual status of

the buck channels (BUCKACTIVEx, non−latched,

STATUS 01). The MCU can exploit this information in

real time to check whether the channels responded to its

activation commands, or at the contrary, they were for

some reasons disabled.

• Boost Status: the physical activation of the booster is

displayed by the BOOST_STATUS flag (non−latched,

STATUS 01). Please note this is different from the

BOOST_EN control bit, which reports instead the

willing to activate the booster. See also section ”Booster

Enable Control”.

• Boost Overvoltage: an overvoltage is detected by the

booster control circuitry: BOOST_OV flag (latched,

STATUS 01). More details can be found in the booster

chapter.

• LEDCTRLx pins Status: the actual logic status read at

the LEDCTRLx pin is reported by the flag

LEDCTRLxVAL (non−latched, STATUS 02). Thanks

to this diagnostic, the MCU can double−check the

proper connection to the led driver at PCB level, or

MCU pin stuck.

• Hard Reset: the out of reset condition is reported

through the HWR bit (STATUS 03, latched). This bit is

set only at each Power On Reset (POR) and indicates

the device is ready to operate.

• SPI Error: in case of SPI communication errors the

SPIERR bit in STATUS 02 is set. The bit is latched. For

more details, please refer to section “SPI protocol:

framing and parity error”.

• Open LEDx string: individual open LED diagnostic

flags indicate whether the “x” string is detected open.

The detection is based on a counter overflow of typical

50μs when the related channel is activated. Both

OPENLED1 and OPENLED2 flags (latched) are

contained in STATUS 01. Please note that the open

detection does not disable the buck channel(s).

A short summary table of the main diagnostic bits related

to the LED outputs follows.

• Short LEDx string: a short circuit detection is

available independently for each LED channel per

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42

NCV78763

Table 23. LED OUTPUTS DIAGNOSTIC TABLE SUMMARY

Diagnose

Description

Flag

TW

Detection Level

LED Output

Latched

Thermal Warning

SPI register

Not Disabled

Yes

programmable

(if no TSD, otherwise disabled)

Disabled

TSD

Thermal Shutdown

Factory trimmed

Yes

(automatically re−enabled when temp falls below TW)

BUCK ON time >

BCK_TON_OPEN

(50 ms typical)

LED string open

circuit

OpenLEDx

Not Disabled

LED string short

circuit

Not Disabled

(buck fixed TOFF applied when output is on)

ShortLEDx

OCLEDx

VLEDx < VLED_LMT

I_Buckswitch > OCD

Yes

LED string

overcurrent

Disabled

PCB LAYOUT RECOMMENDATIONS

developer to reduce application noise impact and insuring

the best system operation. All important areas are

highlighted in the following picture:

This section contains instructions for the NCV78763 PCB

layout application design. Although this guide does not

claim to be exhaustive, these directions can help the

(C)

L_BST

D_BST

V_Batt

(after rev. pol. Prot.)

C_BST_IN

C_BST

(A) (G)

C_M3V

R_BST_SENS

(F)

C_BC2

(B1)

R_BC1

VGATE

COMP

IBCK1SENSE+

C_BC1

RBUCK_1

L_BCK_1

IBCK1SENSE−

VINBCK1

LED−string 1

BSTSYNC

VBB

C_BB

LBCKSW1

C_BCK_1

LBCKSW1

D_BCK_1

R_VLED_1

C_DRIVE

C_DD

ON Semiconductor

LED driver

VDRIVE

VDD

VLED1

Front Lighting

IBCK2SENSE+

RBUCK_2

NCV78763 ^{IBCK2SENSE−}

LED−string 2

(B2)

5V (5V MCU assumed)

R_SDO

VINBCK2

C_BCK_2

L_BCK_2

D_BCK_2

LBCKSW2

VLED2

μC

LEDCTRL1

LEDCTRL2

SPI_SCLK

SPI_SDI

R_VLED_2

SPI_SDO

PWR GND

Sig GND

SPI_CSB

(E)

TST TST1 TST2

GND GNDP EP

(D)

Figure 31. NCV78763 Application Critical PCB Areas

PCB Layout: Booster Current Sensing − Area (A)

affected by the MOSFET switching noise if no specific care

is taken. The following recommendations are given:

a. Use a four terminals current sense method as

depicted in the figure below. The measurement

PCB tracks should run in parallel and as close as

possible to each other, trying to have the same

length. The number of vias along the measurement

path should be minimized;

The booster current sensing circuit used both by the loop

regulation and the current limitation mechanism, relies on a

low voltage comparator, which triggers with respect to the

sense voltage across the external resistor R_BST_SENS. In

order to maximize power efficiency (=minimum losses on

the sense resistor), the threshold voltage is rather low, with

a maximum setting of 100 mV typical. This area may be

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43

NCV78763

b. Place R_BST_SENS sufficiently close to the

MOSFET source terminal;

c. The MOSFET’s dissipation area should be

stretched in a direction away from the sense

resistor to minimize resistivity changes due to

heating;

this target, it is suggested to make a star connection between

these three points, close to the device pins. The width of the

tracks should be large enough (>40 mils) and as short as

possible to limit the PCB parasitic parameters.

VBOOST PCB TRACK

d. If the current sense measurement tracks are

interrupted by series resistors or jumpers (once as

a maximum) their value should be matched and

low ohmic (pair of 0 W to 47 W max) to avoid

errors due to the comparator input bias currents.

However, in case of high application noise, a PCB

re−layout without RC filters is always

recommended.

(from boost power diode)

NCV78763

VBOOSTBCK

IBCK1SENSE+

IBCK2SENSE+

e. Avoid using the board GND as one of the

measurement terminals as this would also

introduce errors.

Figure 33. PCB Star Connection Between

VBOOSTBCK, IBCK1SENSE+ and IBCK2SENSE+

(simplified drawing)

POWER PCB TRACK

(from MOSFET SOURCE)

NCV78763

PCB Layout: GND Connections − Area (D)

The NCV78763 GND and GNDP pins must be connected

together. It is suggested to perform this connection directly

close to the device, behaving also as the cross−junction

between the signal GND (all low power related functions)

and the power GNDP (ground of VGATE driver). The

device exposed pad should be connected to the GND plane

for dissipation purposes.

It is recommended to place the VDD capacitor as close as

possible to the device pins and connected with specific

tracks, respectively to the VDD pin and to the GND pin (not

connected to the general ground plane, to avoid ground

shifts and application noise coupling directly into the chip).

Sensing PCB track (+)

IBSTSENSE+

Rboost

sense

IBSTSENSE−

Sensing PCB track (−)

MOSFET DRAIN to source current flow

POWER PCB TRACK

(from sense resistor to Power GND)

Figure 32. Four Wires Method for Booster Current

Sensing Circuit

PCB Layout: Buck Current Sensing − Areas (B1) &

(B2)

The blocks (B1) and (B2) control the buck peak currents

by means, respectively, of the external sense resistors

R_BCK1/2_SENS. As the regulation is performed with a

comparator, the considerations explained in the previous

section remain valid. In particular, the use of a four terminals

current sense method is required, this time applied on

(IBCKxSENSE+, IBCKxSENSE−). Sense resistors should

be outside of the device PCB heating area in order to limit

measurement errors produced by temperature drifts.

PCB Layout: Buck Power Lines − Area (E)

To avoid power radiation and crosstalk between BUCK1

and BUCK2 regulators the VINBCKx and LBCKSWx

tracks have to be as short as possible. They should also be

symmetrical and the straightest. It is also recommended to

insert a ground plate between them, especially between

LBCKSW1 and LBCKSW2 track. See area “1” in the figure

below.

PCB Layout: Booster Compensation Network − Area (F)

The compensation network must be placed very close to

the chip and avoid noise capturing. It is recommended to

connect its ground directly to the chip ground pin to avoid

noise coming from other portions of the PCB ground. In

PCB Layout: Vboost related Tracks − Area (C)

The three NCV78763 device pins VBOOSTBCK,

IBCK1SENSE+ and IBCK2SENSE+ must be at the same

individual voltage potential to guarantee proper functioning

of the internal buck current comparator (whose supply rails

are VBOOSTBCK and VBOOSTM3V). In order to achieve

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44

NCV78763

addition a ground ring shall provide extra shielding ground

around. See area “2” in the figure.

highest. In fact, would the tracks be too long, the loop

antenna may capture a higher noise level, with the risk of

downgrading the chip’s performances.

PCB Layout: Additional EMC Recommendations on

Loops

It is suggested in general to have a good metal connection

to the ground and to keep it as continuous as possible, not

interrupted by resistors or jumpers.

In additions, PCB loops for power lines should be

minimized. A simplified application schematic is shown in

the next figure to better focus on the theoretical explanation.

When a DC voltage is applied to the VBB, at the left side of

the boost inductor L_BST, a DC voltage also appears on the

right side of L_BCK and on the C_BCK. However, due to

the switching operation (boost and buck), the applied

voltage generates AC currents flowing through the red area

(1). These currents also create time variable voltages in the

area marked in green (2). In order to minimize the radiation

due to the AC currents in area 1, the tracks’ length between

L_BST and the pair L_BCK plus C_BCK must be kept low.

At the contrary, if long tracks would be used, a bigger

parasitic capacitance in area 2 would be created, thus

increasing the coupled EMC noise level.

Figure 34. NCV78763 PCB Layout Example: areas (E)

and (F)

PCB Layout: High Frequency Loop on Capacitors −

Area (G)

All high frequency loops (with serial capacitor) have to be

very short, with the capacitor as close as possible to the chip,

to set the created loop antenna radiating frequency to the

Figure 35. PCB AC Current Lines (Area 1) and AC Voltage Nodes (Area 2)

ORDERING INFORMATION

Device

†

Marking

Package

Shipping

NCV78763DQ6AR2G (Notes 27 and 28)

NCV78763DQ6R2G (Note 27)

NCV78763DQ0AR2G (Note 28)

NCV78763DQ0R2G

NV78763−6

SSOP36 EP

(Pb−Free)

1500 / Tape & Reel

NV78763−0

NCV78763MW4R2G (Note 29)

NCV78763MW0R2G (Note 29)

NCV78763MW1R2G

N78763−4

N78763−0

N78763−1

QFN32 5x5

(Pb−Free)

5000 / Tape & Reel

2500 / Tape & Reel

QFN32 7x7

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

27.Recommended for new design for improved conducted emissions in the low frequency range typically between 100 kHz and 200 kHz.

28.NCV78763DQ6AR2G & NCV78763DQ0AR2G are Dual Fab and Assembly OPNs. Please contact ON Semiconductor for technical details.

29.NCV78763MW4 & NCV78763MW0 have different package mold compound. Please contact ON Semiconductor for technical details.

www.onsemi.com

45

NCV78763

PACKAGE DIMENSIONS

SSOP36 EP

CASE 940AB

ISSUE A

NOTES:

0.20 C A-B

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

D

4X

DETAIL B

D

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN

EXCESS OF THE b DIMENSION AT MMC.

4. DIMENSION b SHALL BE MEASURED BE-

TWEEN 0.10 AND 0.25 FROM THE TIP.

5. DIMENSIONS D AND E1 DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. DIMENSIONS D AND E1 SHALL BE

DETERMINED AT DATUM H.

A

X

36

19

X = A or B

e/2

E1

E

DETAIL B

6. THIS CHAMFER FEATURE IS OPTIONAL. IF

IT IS NOT PRESENT, A PIN ONE IDENTIFIER

MUST BE LOACATED WITHIN THE INDICAT-

ED AREA.

36X

0.25 C

PIN 1

REFERENCE

MILLIMETERS

1

18

DIM MIN

MAX

2.65

0.10

2.60

0.30

0.32

e

A

A1

A2

b

---

36X b

B

M

S

0.25

T A

B

2.15

0.18

0.23

NOTE 6

TOP VIEW

c

h

DETAIL A

A

A2

D

10.30 BSC

H

D2

E

5.70

5.90

10.30 BSC

7.50 BSC

3.90 4.10

0.50 BSC

0.25 0.75

0.90

c

E1

E2

e

h

0.10 C

h

A1

SEATING

PLANE

END VIEW

M1

36X

C

SIDE VIEW

D2

L

0.50

L2

M

0.25 BSC

0

8

_

M1

5

15

_

GAUGE

PLANE

M

E2

L2

SEATING

PLANE

C

36X

L

DETAIL A

BOTTOM VIEW

SOLDERING FOOTPRINT*

36X

1.06

5.90

4.10

10.76

1

36X

0.36

0.50

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

46

NCV78763

PACKAGE DIMENSIONS

QFN32 5x5, 0.5P

CASE 488AM

ISSUE A

A

B

D

NOTES:

L

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

L1

LOCATION

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

E

A

MILLIMETERS

DIM

A

A1

A3

b

MIN

0.80

−−−

0.20 REF

0.18

MAX

1.00

0.05

0.15

C

0.15

C

EXPOSED Cu

MOLD CMPD

0.30

TOP VIEW

D

5.00 BSC

D2

E

2.95

5.00 BSC

3.25

DETAIL B

E2

2.95

3.25

(A3)

A1

0.10

C

e

0.50 BSC

DETAIL B

K

L

L1

0.20

0.30

−−−

0.50

0.15

ALTERNATE

CONSTRUCTION

0.08

SEATING

PLANE

C

NOTE 4

SIDE VIEW

RECOMMENDED

SOLDERING FOOTPRINT*

DETAIL A

32X L

K

D2

5.30

9

32X

0.63

17

3.35

8

E2

1

3.35 5.30

32

25

32X

b

e

M

0.10

C A B

e/2

NOTE 3

0.05

C

BOTTOM VIEW

0.50

PITCH

32X

0.30

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

47

NCV78763

PACKAGE DIMENSIONS

QFN32 7x7, 0.65P

CASE 485J−02

ISSUE E

NOTES:

B

E

D

A

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

SCALE 2:1

L

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.25MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN 1

INDICATOR

L1

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

MILLIMETERS

DIM MIN

0.80

A1 0.00

MAX

1.00

0.05

A

0.15

C

2X

A3

b

0.20 REF

0.25

0.35

D

7.00 BSC

5.36

7.00 BSC

EXPOSED Cu

MOLD CMPD

2X

0.15 C

D2 5.16

E

TOP VIEW

E2 5.16

5.36

DETAIL B

A3

e

K

L

0.65 BSC

0.20

0.30

0.10

C

DETAIL B

−−−

0.50

0.15

ALTERNATE

A

CONSTRUCTION

L1 0.00

0.08

A1

SIDE VIEW

D2

SEATING

PLANE

NOTE 4

C

RECOMMENDED

MOUNTING FOOTPRINT*

DETAIL A

32X

L

7.30

5.46

K

9

16

32X

0.63

PACKAGE

OUTLINE

17

8

1

E2

5.46

7.30

24

32

25

32X

b

e

0.10 C A B

32X

0.40

e/2

BOTTOM VIEW

0.65

PITCH

0.05 C

NOTE 3

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

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48


型号：	NCV78763MW0R2G
厂家：	ONSEMI
描述：	Power Ballast and Dual LED Driver 驱动接口集成电路
文件：	总48页 (文件大小：575K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV78763MW0R2G [ONSEMI]

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