NCV81277AMNTXG_技术文档

4/3/2/1 Phase Buck

Controller with PWM_VID

and I²C Interface

NCV81277A

The NCV81277A is a multiphase synchronous controller optimized

for new generation computing and graphics processors. The device is

capable of driving up to 4 phases and incorporates differential voltage

and phase current sensing, adaptive voltage positioning and

PWM_VID interface to provide and accurately regulated power for

computer or graphic controllers. The integrated power saving

interface (PSI) allows for the processors to set the controller in one of

three modes, i.e. all phases on, dynamic phases shedding or fixed low

phase count mode, to obtain high efficiency in light-load conditions.

The dual edge PWM multiphase architecture ensures fast transient

response and good dynamic current balance.

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1

40

QFNW40

CASE 484AK

MARKING DIAGRAM

Features

1

ON

®

• Compliant with NVIDIA OVR4+ Specifications

NCV

81277A

AWLYYWW

G

• Supports Up to 4 Phases

• 4.5 V to 20 V Supply Voltage Range

• 250 kHz to 1.2 MHz Switching Frequency (4 Phase)

• Power Good Output

NCV81277A = Specific Device Code

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb-Free Package

• Under Voltage Protection (UVP)

WL

YY

WW

G

• Over Voltage Protection (OVP)

• Over Current Protection (OCP)

• Per Phase Over Current Protection

• Startup into Pre-Charged Loads while Avoiding False OVP

• Configurable Adaptive Voltage Positioning (AVP)

• High Performance Operational Error Amplifier

• True Differential Current Balancing Sense Amplifiers for Each Phase

• Phase-to-Phase Dynamic Current Balancing

PIN CONNECTIONS

1

30

29

28

COMP

FB

REFIN

2

3

• Current Mode Dual Edge Modulation for Fast Initial Response to

VREF

VRMP

DIFF

Transient Loading

NCV81277A

4

5

27

FSW

SS

26

LLTH/I2C_ADD

IOUT

• Power Saving Interface (PSI)

OCP

(TOP VIEW)

6

7

8

25

LPC1

• Automatic Phase Shedding with User Settable Thresholds

24

ILIM

LPC2

Tab: GROUND

23

22

21

2

CSCOMP

CSSUM

CSREF

PWM4/PHTH1

PWM3/PHTH2

PWM2/PHTH3

• PWM_VID and I C Control Interface

9

10

• Compact 40 Pin QFN Wettable Flank Package

• Operating Temperature Range: −40°C to +105°C

• AEC−Q100 Grade 2 Approved

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

ORDERING INFORMATION

†

Device

Package

Shipping

Typical Applications

• GPU and CPU Power

• Automotive Applications

NCV81277AMNTXG QFNW40 5000/Tape & Reel

(Pb-Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

1

Publication Order Number:

March, 2021 − Rev. 4

NCV81277A/D

NCV81277A

R 1 2 5

R 1 2 4

R 5 7

R 5 6

0 R

2 0 k

1 0 k

C 2 1 4 7 0 p F

R 5 5

R 1 2 6

C 2 0

3 . 3 n

R 5 4

R 1 2 7

C 1 9

1 n

1 0 0 k

1

R T

4 9 . 9 k

R 5 1

2 4 . 9 k

R 5 0

1 0 R

C S N 1

C S N 2

C S N 3

C S N 4

R 1 4 9 0 R

R 1 4 8

R 4 7

1 0 R

R 4 5

R 4 6

0 R

1 0 R

R 4 4

7

0 R 1 4

R

1 0 R

R 1 4 6 0 R

V S P

V S N

V C C

S D A

S C L

C S P 1

2 0

3 1

3 2

3 3

3 4

3 5

3 6

3 7

3 8

3 9

4 0

C S P 2

1 9

C S P 3

1 8

C S P 4

1 7

N C

1 6

1 5

1 4

1 3

E N

P S I

P G O O D

P W M _ V I D

V I D _ B U F F

D R O N

1 2

P W M 1 / P H T H 4

1 1

2 0 . 5 k

S W N 1

R 2 8

R 2 7

2 . 9 4 k

S W N 2

R 2 6

2 . 9 4 k

4 . 1 2 k

R 2 5

S W N 3

S W N 4

R 2 4

R 2 3

2 . 9 4 k

5

3

Figure 1. Typical Controller Application Circuit

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2

NCV81277A

VIN

VRMP

NCV81277A/5A

NCV3025833

VIN

DrMOS

VCORE_SNS

DRON

VIN

SW

VSP

DRON

PWM1

EN

SW1

VCORE

VSN

PWM

VCORE_GND_SNS

DIFF

FB

CSP1

CSREF

COMP

SW1

CSSUM

...

SWn

NTC

NCV3025833

VIN

CSCOMP

DrMOS

DRON

VIN

SW

EN

PWM

SWn

ILIM

PWMn

CSPn

IOUT

CSREF

Figure 2. Typical Phase Application Circuit (5x5 DrMOS with no IMON)

VIN

VRMP

NCV81277A/5A

NCV303150

VIN

DrMOS

VCORE_SNS

DRON

VSP

DRON

VIN

SW

EN

SW1

VCORE

VSN

VCORE_GND_SNS

PWM1

CSP1

PWM

CSP1

IMON REFIN

DIFF

FB

CSREF

COMP

CSP1

CSSUM

...

CSPn

NCV303150

VIN

CSCOMP

DrMOS

DRON

VIN

SW

EN

ILIM

SWn

PWMn

CSPn

PWM

IOUT

IMON REFIN

CSREF

Figure 3. Typical Phase Application Circuit (6x5 DrMOS with IMON)

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3

NCV81277A

Table 1. PIN FUNCTION DESCRIPTION

Number

Name

Type

Description

1

2

REFIN

VREF

I

Reference voltage input for output voltage regulation.

O

2.0 V output reference voltage. A 10 nF ceramic capacitor is required to connect this pin

to ground.

3

4

VRMP

SS

I

Feed-forward input of VIN for the ramp slope compensation. The current fed into this pin

is used to control of the ramp of PWM slope.

I/O

Soft Start setting. During startup it is used to program the soft start time with a resistor to

ground.

5

OCP

Per OCP setting. During startup it is used to program the OCP level per phase and latch

off time with a resistor to ground.

6

LPC1

Low phase count 1. During startup it is used to program the power zone (when PSI is set

low) with a resistor to ground.

7

LPC2

Low phase count 2. During startup it is used to program boot-up power zone (when PSI

is set low) with a resistor to ground.

8

PWM4/PHTH1

PWM3/PHTH2

PWM2/PHTH3

PWM1/PHTH4

PWM 4 output/Phase Shedding Threshold 1. During startup it is used to program the

phase shedding threshold 1 (PSI set to mid state) with a resistor to ground.

9

PWM 3 output/Phase Shedding Threshold 2. During startup it is used to program the

phase shedding threshold 2 (PSI set to mid state) with a resistor to ground.

10

11

PWM 2 output/Phase Shedding Threshold 3. During startup it is used to program the

phase shedding threshold 3 (PSI set to mid state) with a resistor to ground.

PWM 1 output/Phase Shedding Threshold 4. During startup it is used to program the

phase shedding threshold 4 (PSI set to mid state) with a resistor to ground.

12

13

14

15

16

17

DRON

NC

I/O

N/A

I

Bidirectional gate driver enable for external drivers.

No connect pin. Please leave floating.

NC

CSP4

Non-inverting input to current balance sense amplifier for phase 4. Pull-up to VCC via a

2K to disable the PWM4 output.

18

19

20

CSP3

CSP2

CSP1

I

Non-inverting input to current balance sense amplifier for phase 3. Pull-up to VCC via a

2K to disable the PWM3 output.

Non-inverting input to current balance sense amplifier for phase 2. Pull-up to VCC via a

2K to disable the PWM2 output.

Non-inverting input to current balance sense amplifier for phase 1. Pull-up to VCC via a

2K to disable the PWM1 output.

21

22

23

24

CSREF

CSSUM

CSCOMP

ILIM

I

Total output current sense amplifier reference voltage input.

Inverting input of total current sense amplifier.

Output of total current sense amplifier.

I

O

Over current shutdown threshold setting output. The threshold is set by a resistor be-

tween ILIM and to CSCOMP pins.

25

IOUT

O

Total output current. A resistor to GND is required to provide a voltage drop of 2 V at the

maximum output current.

2

26

27

28

29

30

31

LLTH/I2C_ADD

FSW

I

Load line selection from 0% to 100% and I C address pin.

Resistor to ground form this pin sets the operating frequency of the regulator.

Output of the regulators differential remote sense amplifier.

Error amplifier inverting (feedback) input.

DIFF

O

I

FB

COMP

VSP

O

I

Output of the error amplifier and the inverting input of the PWM comparator.

Differential Output Voltage Sense Positive terminal.

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4

NCV81277A

Table 1. PIN FUNCTION DESCRIPTION (continued)

Number

Name

Type

Description

32

33

VSN

VCC

I

Differential Output Voltage Sense Negative terminal.

Power for the internal control circuits. A 1 mF decoupling capacitor is requires from this

pin to ground.

34

35

36

37

SDA

SCL

EN

I/O

Serial Data bi-directional pin, requires pull-up resistor to VCC.

Serial Bus clock signal, requires pull-up resistor to VCC.

I

Logic input. Logic high enables regulator output logic low disables regulator output.

PSI

Power level control 3 level control. Use a current limiting resistor of 100 kW when driving

the pin with 5 V logic.

38

39

40

41

PGOOD

PWM_VID

VID_BUFF

AGND

O

I

Open Drain power good indicator.

PWM_VID buffer input.

O

PWM_VID pulse output from internal buffer.

Analog ground and thermal pad, connected to system ground.

GND

Table 2. MAXIMUM RATINGS

Rating

Pin Symbol

Min

Typ

Max

Unit

Pin Voltage Range (Note 1)

VSN

GND−0.3

GND + 0.3

V

VCC

VRMP

−0.3

6.5

25

V

PWM_VID

−0.3

(−2, < 50 ns)

VCC + 0.3

All Other Pins

with the

−0.3

VCC + 0.3

2

V

Pin Current Range

COMP

CSCOMP

DIFF

−2

mA

PGOOD

VSN

−1

1

mA

−

Moisture Sensitivity Level

MSL

1

Lead Temperature Soldering Reflow (SMD Styles Only),

Pb-Free Versions (Note 2)

T

SLD

260

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. All signals referenced to GND unless noted otherwise.

2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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5

NCV81277A

Table 3. THERMAL CHARACTERISTICS

Rating

Symbol

Min

Typ

Max

Unit

Thermal Characteristics, (QFN40, 5 × 5 mm)

R

°C/W

θJA

Thermal Resistance, Junction-to-Air (Note 1)

−

68

−

Process Junction Temperature Range (Note 2)

Operating Ambient Temperature Range

Maximum Storage Temperature Range

T

−40

−55

150

105

150

_C

J

T

−

A

T

STG

−

1. JESD 51−5 (1S2P Direct-Attach Method) with 0 LFM.

2. JESD 51−7 (1S2P Direct-Attach Method) with 0 LFM.

Table 4. ELECTRICAL CHARACTERISTICS

(Unless otherwise stated: −40°C < T < 105°C; 4.6 V < VCC < 5.4 V; C

= 0.1 mF)

A

VCC

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

VRMP

Supply Range

UVLO

VRMP

4.5

3

20

V

VRMP Rising

V

4.2

RMPrise

VRMP Falling

V

RMPfall

VRMP UVLO Hysteresis

BIAS SUPPLY

V

800

mV

RMPhyst

Supply Voltage Range

VCC Quiescent current

VCC

ICC

4.6

5.4

40

V

mA

V

Enable Low

4 Phase Operation

1 Phase-DCM Operation

VCC Rising

32

10

UVLO

4.5

UVLO Threshold

Rise

VCC Falling

UVLO

4

V

Fall

VCC UVLO Hysteresis

UVLO

200

mV

Hyst

SWITCHING FREQUENCY

Switching Frequency Range

Switching Frequency Accuracy

4 Phase Configuration

F

250

−4

1200

+4

kHz

%

SW

F

SW

= 810 kHz

DF

SW

all range

−10

+10

ENABLE INPUT

Input Leakage

Upper Threshold

Lower Threshold

DRON

EN = 0 V or VCC

I

−1.0

1.0

0.6

mA

V

L

V

1.2

IH

V

IL

Output High Voltage

Output Low Voltage

Rise Time

Sourcing 500 mA

Sinking 500 mA

Cl(PCB) = 20 pF,

V

3.0

V

OH

V

0.1

OL

t

160

3

ns

R

DV = 10% to 90%

O

Fall Time

Cl(PCB) = 20 pF,

t

ns

F

DV = 10% to 90%

O

Internal Pull-up Resistance

R

2.0

70

kW

PULL−UP

Internal Pull-down Resistance

VCC = 0 V

R

PULL_DOWN

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6

NCV81277A

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −40°C < T < 105°C; 4.6 V < VCC < 5.4 V; C

= 0.1 mF)

VCC

A

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

PGOOD

Output Low Voltage

I

= 10 mA (Sink)

= 5 V

V

0.4

0.2

1.5

V

PGOOD

OL

Leakage Current

P

I

mA

ms

GOOD

L

Output Voltage Initialization Time

From EN to DRON

REFIN = 1.0 V

T_init

Minimum Output Voltage Ramp

Time

T_ramp

0.15

10

MIN

Maximum Output Voltage Ramp

Time

REFIN = 1.0 V

T_ramp

ms

MAX

PROTECTION-OCP, OVP, UVP

Under Voltage Protection (UVP)

Threshold

Relative to REFIN Voltage

UVP

250

360

9.5

300

5

350

430

10.5

mV

ms

Under Voltage Protection (UVP)

Delay

T

UVP

Over Voltage Protection (OVP)

Threshold

Relative to REFIN Voltage

internal current source

OVP

400

5

mV

ms

Over Voltage Protection (OVP)

Delay

T

OVP

Over Current Protection (ILIM)

PWM OUTPUTS

ILIM

10

mA

th

Output High Voltage

Output Mid Voltage

Output Low Voltage

Rise and Fall Time

Sourcing 500 mA

Sinking 500 mA

V

VCC − 0.2

V

OH

V

MID

1.9

2.0

10

2.1

0.7

V

OL

C (PCB) = 50 pF, DV = 10% to

t , t

R F

ns

L

O

90% of VCC

Tri-state Output Leakage

Minimum On Time

0% Duty Cycle

G = 2.0 V, x = 1−8, EN = Low

I

−1.0

1.0

mA

ns

V

x

L

FSW = 600 kHz

Ton

12

Comp Voltage when PWM Outputs

Remain LOW

VCOMP

1.3

0%

100% Duty Cycle

Comp Voltage when PWM Outputs VCOMP

Remain HIGH

2.5

15

V

100%

PWM Phase Angle Error

Between Adjacent Phases

ø

°

PHASE DETECTION

Phase Detection Threshold Volt-

age

CSP2 to CSP4

V

T

VCC − 0.1

V

PHDET

Phase Detect Timer

1.1

ms

PHDET

ERROR AMPLIFIER

Input Bias Current

I

−400

400

nA

dB

BIAS

Open Loop DC Gain

C = 20 pF to GND,

L

G

80

20

5

L

OL

R = 10 kW to GND

Open Loop Unity Gain Bandwidth

Slew Rate

C = 20 pF to GND,

GBW

SR

MHz

L

R = 10 kW to GND

L

DV = 100 mV, G = −10 V/V,

V/ms

IN

OUT

DV

= 0.75–1.52 V, C = 20 pF

L

to GND, R = 10 kW to GND

Maximum Output Voltage

Minimum Output Voltage

I

= 2 mA

V

3.5

V

SOURCE

OUT

= 2 mA

1

SINK

OUT

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7

NCV81277A

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −40°C < T < 105°C; 4.6 V < VCC < 5.4 V; C

= 0.1 mF)

VCC

A

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

DIFFERENTIAL SUMMING AMPLIFIER

Input Bias Current

I

−400

0

400

2

nA

V

BIAS

VSP Input Voltage

V

IN

VSN Input Voltage

−0.3

0.3

V

IN

−3dB Bandwidth

C = 20 pF to GND,

L

BW

27

1

MHz

L

R = 10 kW to GND

Closed Loop DC Gain

(VSP−VSN to DIFF)

VSP to VSN = 0.5 to 1.3 V

G

V/V

mV

Droop accuracy

CSREF − DROOP = 80 mV,

DDROOP

78

3

82

V

REFIN

= 0.8 V to 1.2 V

Maximum Output Voltage

Minimum Output Voltage

CURRENT SUMMING AMPLIFIER

Offset Voltage

I

= 2 mA

V

SOURCE

OUT

= 2 mA

0.8

SINK

OUT

V

OS

−500

−7.5

500

7.5

mV

mA

Input Bias Current

CSSUM = CSREF = 1 V

I

L

Open Loop Gain

G

80

10

dB

Current sense Unity Gain Band-

width

C = 20 pF to GND,

L

GBW

MHz

L

R = 10 kW to GND

Maximum CSCOMP Output Volt-

age

I

= 2 mA

V

3.5

V

SOURCE

OUT

Minimum CSCOMP Output Voltage

CURRENT BALANCE AMPLIFIER

Input Bias Current

I

= 2 mA

0.1

SINK

OUT

CSP − CSP

= 1.2 V

I

−50

50

2

nA

V

X

X+1

BIAS

Common Mode Input Voltage

Range

CSP = CSREF

V

0

X

CM

Differential Mode Input Voltage

Range

CSREF = 1.2 V

V

DIFF

−100

−1.5

100

1.5

mV

Closed Loop Input Offset Voltage

Matching

CSP = 1.2 V, Measured from the

X

Average

Current Sense Amplifier Gain

0 V < CSP < 0.1 V

G

5.7

6.0

8

V/V

%

X

Multiphase Current Sense Gain

Matching

CSREF = CSP = 10 mV to 30 mV

DG

−3

3

−3dB Bandwidth

BW

MHz

IOUT

Input Reference Offset Voltage

Output Current Max

Current Gain

ILIM to CSREF

V

−3

+3

mV

mA

OS

ILIM Sink Current 20 mA

I

200

10

OUT

IOUT/ILIM, R

IOUT

= 20 kW,

G

9.5

10.5

A/A

LIM

R

= 5 kW

VOLTAGE REFERENCE

VREF Reference Voltage

VREF Reference accuracy

I

= 1 mA

VREF

1.98

2

1

2.02

V

REF

T

< T < T

JMAX

DVREF

%

JMIN

J

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8

NCV81277A

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(Unless otherwise stated: −40°C < T < 105°C; 4.6 V < VCC < 5.4 V; C

= 0.1 mF)

VCC

A

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

PSI

PSI High Threshold

PSI Mid threshold

V

1.45

0.8

V

IH

V

MID

1

0.575

1

PSI Low threshold

V

IL

PSI Input Leakage Current

PWM_VID BUFFER

Upper Threshold

V

= 0 V

I

L

−1

mA

PSI

V

IH

1.21

400

V

Lower Threshold

V

0.575

5000

IL

PWM_VID

PWM_VID Switching Frequency

Output Rise Time

F

kHz

ns

t

R

3

Output Fall Time

t

F

Rising and Falling Edge Delay

Propagation Delay

Propagation Delay Error

REFIN

Dt = t − t

Dt

0.5

8

R

F

t

= t

PDHL

= t

t

PD

PDLH

Dt = t

− t

Dt

PD

0.5

PD

PDHL

PDLH

REFIN Discharge Switch

ON-Resistance

I

= 2 mA

= 400 kHz,

= 1000 kHz,

R

10

30

W

REEFIN(SINK)

DISCH

F

V

Ratio of Output Voltage Ripple

Transferred from REFIN/REFIN

Voltage Ripple

%

PWM_VID

ORP/VREFIN

V

ORP/VREFIN

≤ 600 kHz

SW

F

PWM_VID

≤ 600 kHz

SW

2

I C

Logic High Input Voltage

Logic Low Input Voltage

Hysteresis (Note 4)

From 10% to 90%

V

1.7

V

IH

V

0.5

IL

80

5

mV

V

Output Low Voltage

I

= −6 mA

V

OL

0.4

1

SDA

Input Current

I

L

−1

mA

pF

kHz

ms

ns

Input Capacitance (Note 4)

Clock Frequency

C

, C

SDA

SCL

f

400

See Figure 4

SCL

SCL Low Period (Note 4)

SCL High Period (Note 4)

SCL/SDA Rise Time (Note 4)

SCL/SDA Fall Time (Note 4)

t

1.3

0.6

LOW

t

HIGH

t

R

300

t

F

Start Condition Setup Time

(Note 4)

t

600

SU;STA

Start Condition Hold Time

(Note 1, 4)

t

ns

HD;STA

Data Setup Time (Note 2, 4)

Data Hold Time (Note 2, 4)

100

300

600

ns

SU;DAT

HD;DAT

SU;STO

t

Stop Condition Setup Time

(Note 3, 4)

t

Bus Free Time between Stop

and Start (Note 4)

t

1.3

ms

BUF

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. Time from 10% of SDA to 90% of SCL.

2. Time from 10% or 90%of SDA to 10% of SCL.

3. Time from 90% of SCL to 10% of SDA.

4. Guaranteed by design, not production tested.

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9

NCV81277A

t

R

t

F

t

HD:STA

t

LOW

SCLK

t

HIGH

t

HD:STA

SU:STA

t

SU:STO

t

HD:DAT

SU:DAT

SDATA

t

BUF

STOP START

START

STOP

Figure 4. I²C Timing Diagram

EN

VOUT

PGOOD

T_ramp

T_init

Figure 5. Soft Start Timing Diagram

Applications Information

The NCV81277A is a buck converter controller

optimized for the next generation computing and graphic

processor applications. It contains four PWM channels

which can be individually configured to accommodate buck

converter configurations up to four phases. The controller

regulates the output voltage all the way down to 0 V with no

load. Also, the device is functional with input voltages as

low as 3.3 V.

The output voltage is set by applying a PWM signal to the

PWM_VID input of the device. The controller converts the

PWM_VID signal with variable high and low levels into

a constant amplitude PWM signal which is then applied to

the REFIN pin. The device calculates the average value of

this PWM signal and sets the regulated voltage accordingly.

The output voltage is differentially sensed and subtracted

from the REFIN average value. The result is biased up to

1.3 V and applied to the error amplifier. Any difference

between the sensed voltage and the REFIN pin average

voltage will change the PWM outputs duty cycle until the

two voltages are identical. The load current is current is

continuously monitored on each phase and the PWM

outputs are adjusted to ensure adjusted to ensure even

distribution of the load current across all phases. In addition,

the total load current is internally measured and used to

implement a programmable adaptive voltage positioning

mechanism.

The device incorporates overcurrent, under and

overvoltage protections against system faults.

The communication between the NCV81277A and the

user is handled with two interfaces, PWM_VID to set the

2

output voltage and I C to configure or monitor the status of

the controller. The operation of the internal blocks of the

device is described in more details in the following sections.

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10

NCV81277A

VID_BUFF

VREF

VCC

EN

REF

UVLO & EN

PWM_VID

1.3V

EN

+

VSP

VSN

S

DIFFOUT

PGOOD

−

EN

PGOOD

Comparator

VSP

VSN

LLTH

REFIN

FB

Soft start

−

CSCOMP

CSREF

+

OVP

VSP

VSN

+

1.3V

−

CSSUM

ILIM

COMP

OVP

PSI

Total Output Current

Measurment , ILIM & OCP

OCP

Mux

IOUT

IPH1

Current Balance

Amplifiers

CSP1

CSP2

CSP3

IPH2

IPH3

IPH4

Data

Registers

and

per Phase OCP

Comparators

CSP4

SDA

SCL

Control

Interface

PWM1/PHTH4

PWM2/PHTH3

PWM3/PHTH2

PWM4/PHTH1

LPC2

FSW

VRMP

PSI

Ramp1

Ramp2

Ramp3

Ramp4

Ramp

Generators

PWM

Generators

Power State

Stage

LPC1

OCP

SS

DRON

GND

LLTH/I2C_ADD

Figure 6. NCV81277A Functional Block Diagram

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11

NCV81277A

PWM_VID Interface

The output voltage ramp-up time is user settable by

connecting a resistor between pin SS and GND. The

controller will measure the resistance value at power-up by

sourcing a 10 mA current through this resistor and set the

PWM_VID is a single wire dynamic voltage control

interface where the regulated voltage is set by the duty cycle

of the PWM signal applied to the controller.

The device controller converts the variable amplitude

PWM signal into a constant 2 V amplitude PWM signal

while preserving the duty cycle information of the input

signal. In addition, if the PWM_VID input is left floating,

the VID_BUFF output is tri-stated (floating).

The constant amplitude PWM signal is then connected to

the REFIN pin through a scaling and filtering network (see

Figure 7). This network allows the user to set the minimum

and maximum REFIN voltages corresponding to 0% and

100% duty cycle values.

ramp time (t

) as shown in Table 16. When a fast SS ramp

ramp

is selected, external filtering should ensure REFIN signal

settled before the PGOOD signal asserted.

Remote Voltage Sense

A high performance true differential amplifier allows the

controller to measure the output voltage directly at the load

using the VSP (VOUT) and VSN (GND) pins. This keeps

the ground potential differences between the local controller

ground and the load ground reference point from affecting

regulation of the load. The output voltage of the differential

amplifier is set by the following equation:

VCC

0.1 mF

ǒ

Ǔ

ǒ

Ǔ

V_DIFOUT+ V_VSP* V_VSN) 1.3 V * V_REFIN)

Internal

precision

reference

VREF

(eq. 4)

₎ǒ_V

Ǔ

_DROOP) V_CSREF

V

REF

= 2 V

10nF

C1

R1

R2

Where:

VID_BUFF

V

is the output voltage of the differential amplifier.

DIFOUT

PWM_VID

R3

GND

V

VSP

−V

is the regulated output voltage sensed at the

VSN

load.

V

is the voltage at the output pin set by the

REFIN

PWM_VID interface.

Controller

V

− V is the expected drop in the regulated

DROOP

CSREF

voltage as a function of the load current (load-line).

Figure 7. PWM_VID Interface

1.3 V is an internal reference voltage used to bias the

amplifier inputs to allow both positive and negative

The minimum (0% duty cycle), maximum (100% duty

cycle) and boot (PWM_VID input floating) voltages can be

calculated with the following formulas:

output voltage for V

.

DIFOUT

Error Amplifier

1

V_MAX+ V_REF

@

(eq. 1)

(eq. 2)

(eq. 3)

R₁@R₃

A high performance wide bandwidth error amplifier is

provided for fast response to transient load events. Its

inverting input is biased internally with the same 1.3 V

reference voltage as the one used by the differential sense

amplifier to ensure that both positive and negative error

voltages are correctly handled.

An external compensation circuit should be used (usually

type III) to ensure that the control loop is stable and has

adequate response.

1 )

ǒ

Ǔ

R₂@ R₁)R₃

1

V_MIN+ V_REF

@

ǒ

Ǔ

R₁@ R₂)R₃

R₂@R₃

1

V_BOOT+ V_REF

@

R₁

R₂

1 )

Ramp Feed-Forward Circuit

Soft Start

The ramp generator circuit provides the ramp used to

generate the PWM signals using internal comparators (see

Figure 8) The ramp generator provides voltage

feed-forward control by varying the ramp magnitude with

respect to the VRMP pin voltage. The PWM ramp time is

changed according to the following equation:

Soft start is defined as the transition from Enable assertion

high to the assertion of Power good as shown in Figure 5.

The output is set to the desired voltage in two steps, a fixed

initialization step of 1.5 ms followed by a ramp-up step

where the output voltage is ramped to the final value set by

the PWM_VID interface. During the soft start phase,

PGOOD pin is initially set low and will be set high when the

output voltage is within regulation and the soft start ramp is

complete. The PGOOD signal only de-asserts (pull low)

when the controller shuts down due to a fault condition

(UVLO, OVP or OCP event).

V_RAMPpk+pk+ 0.1 @ V_VRMP

(eq. 5)

pp

The VRMP pin also has a UVLO function. The VRMP

UVLO is only active after the controller is enabled. The

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12

NCV81277A

VRMP pin is high impedance input when the controller is

IOUT pin at the maximum load current is 2 V. Any PHTH

X

disabled.

threshold can be disabled if the voltage drop across the

PHTH resistor is ≥ 2 V for a 10 mA current, the pin is left

X

floating or 0xFF is written to the appropriate PHTH

V

IN

X

configuration register.

V

ramp_pp

Comp-IL

Duty

At power-up, the automatic phase shedding mode is only

enabled after the output voltage reaches the nominal

regulated voltage.

When PSI = Low, the controller is set to a fixed power

zone regardless of the load current. The LPC2 hardware

setting controls the power zone when EN is turned on and

PSI=low. If PSI stays low, its power zone can be further

changed by the I2C register 0x36, Bit[5:3] if the secondary

function is enabled. If PSI transitions to other levels (Mid or

High) and back to Low level when the device is enabled, the

power zone control will switch to LPC1 configuration

hardware setting or I2C register 0x36, Bit[2:0] if the

secondary function is enabled.

Figure 8. Ramp Feed-Forward Circuit

PWM Output Configuration

By default the controller operates in 4 phase mode,

however with the use of the CSP pins the phases can be

disabled by connecting the CSP pin to VCC. At power-up

the NCV81277A measures the voltage present at each CSP

pin and compares it with the phase detection threshold. If the

voltage exceeds the threshold, the phase is disabled. The

phase configurations that can be achieved by the device are

listed in Table 6. The active phase (PWM ) information is

also available to the user in the phase status register.

X

LLTH/I2C_ADD

The LLTH/I2C_ADD pin enables the user to change the

percentage of the externally programmed droop that takes

effect on the output. In addition, the LLTH/I2C_ADD pin

PSI, LPC_X, PHTH_X

The NCV81277A incorporates a power saving interface

(PSI) to maximize the efficiency of the regulator under

various loading conditions. The device supports up to six

distinct operation modes, called power zones using the PSI,

2

sets the I C slave address of the NCV81277A. The

maximum load line is controlled externally by setting the

gain of the current sense amplifier. On power up a 10 mA

current is sourced from the LLTH/I2C_ADD pin through a

resistor and the resulting voltage is measured. The load line

LPC and PHTH pins (see Table 7). At power-up the

X

controller reads the PSI pin logic state and sources a 10 mA

current through the resistors connected to the LPC and

2

and I C slave address configurations achievable using the

X

external resistor is listed in the table below. The percentage

PHTH pins, measures the voltage at these pins and

X

2

load line can be fine-tuned over the I C interface by writing

configures the device accordingly.

The configuration can be changed by the user by writing

to the LL configuration register.

to the LPC and PHTH configuration registers.

X

Table 5. LLTH/I2C_ADD PIN SETTING

After EN is set high, the NCV81277A ignores any change

in the PSI pin logic state until the output voltage reaches the

nominal regulated voltage.

Resistor

Load Line

(%)

Slave Address

(Hex)

(kW)

When PSI = High, the controller operates with all active

phases enabled regardless of the load current. If PSI = Mid,

the NCV81277A operates in dynamic phase shedding mode

where the voltage present at the IOUT pin (the total load

current) is measured every 10 ms and compared to the

100

0

0x20

0x30

0x40

0x50

10

23.2

37.4

100

0

54.9

PHTH thresholds to determine the appropriate power

X

78.7

100

0

zone.

110

The resistors connected between the PHTH and GND

X

147

249

100

0

should be picked to ensure that a 10 mA current will match

the voltage drop at the IOUT pin at the desired load current.

Please note that the maximum allowable voltage at the

NOTE: 1% tolerance.

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13

NCV81277A

Table 6. PWM OUTPUT CONFIGURATION

Phase

CSP Pin Configuration

(3 = Normal Connection, X = Tied to VCC)

Enabled

PWM Outputs

Configuration

CSP1

CSP2

3

CSP3

3

CSP4

(PWM Pins)

Configuration

X

1

2

3

4

4 Phase

3

X

1, 2, 3, 4

1, 2, 3

1, 2

3 Phase

3

2 Phase

3

X

1 Phase

3

X

1

Table 7. PSI, LPC_X, PHTH_XCONFIGURATION (Note 1)

PSI

Logic

State

LPC

X

Resistor

(kW)

Power Zone (Note 2)

4 Phase

3 Phase

2 Phase

1 Phase

IOUT vs. PHTH Comparison

X

High

Low

Disabled

10

Function Disabled

0

2

3

4

0

2

3

4

0

3

4

0

3

4

0

3

4

0

3

4

0

4

0

4

23.2

37.4

54.9

78.7

Mid

Function

Disabled

IOUT > PHTH4

PTHT4 > IOUT > PHTH3

PHTH3 > IOUT > PHTH2

PHTH2 > IOUT > PHTH1

IOUT < PHTH1

1. 1% tolerance.

2. Power zone 4 is DCM @100 kHz switching frequency, while zones 0 to 3 are CCM.

Table 8. PHASE SHEDDING CONFIGURATIONS

PWM Output Status (3 = Enabled, X = Disabled)

PWM1

3

PWM2

PWM3

PWM4

Power Zone

PWM Output Configuration

0

2

3

4

0

3

4

0

3

4

0

4

4 Phase

3

X

3

X

3

X

3

X

3

X

3

X

3

3 Phase

2 Phase

1 Phase

3

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14

NCV81277A

Power Zone Transition/Phase Shedding

Total Current Sense Amplifier

The power zones supported by the NCV81277A are set by

the resistors connected to the LPC pins (PSI = Low) or

The controller uses a patented approach to sum the phase

currents into a single temperature compensated total current

signal (Figure 9).

X

PHTH pins (PSI = Mid).

X

When PSI is set to the Mid-state, the NCV81277A

employs a phase shedding scheme where the power zone is

automatically adjusted for optimal efficiency by

continuously measuring the total output current (voltage at

This signal is then used to generate the output voltage

droop, total current limit, and the output current monitoring

functions. The total current signal is floating with respect to

CSREF. The current signal is the difference between

CSCOMP and CSREF. The REF(n) resistors sum the signals

from the output side of the inductors to create a low

impedance virtual ground.

The amplifier actively filters and gains up the voltage

applied across the inductors to recover the voltage drop

across the inductor series resistance (DCR). RTH is placed

near an inductor to sense the temperature of the inductor.

This allows the filter time constant and gain to be a function

of the NTC’s resistance (RTH) and compensate for the

change in the DCR with temperature.

the IOUT pin) and compare it with the PHTH thresholds.

X

When the comparison result indicates that a lower power

zone number is required (an increase in the IOUT value), the

controller jumps to the required power zone immediately.

A decrease in IOUT that indicates that the controller needs

to switch into a higher power zone number, the transition

will be executed with a delay of 200 ms set by the phase shed

delay configuration register. The value of the delay can be

adjusted by the user in steps of 10 ms if required. To avoid

excessive ripple on the output voltage, all power zone

changes are gradual and include all intermediate power

zones between the current zone and the target zone set by the

The DC gain equation for the current sensing:

(eq. 6)

RCS1@RTH

RCS1)RTH

RPH

RCS2 )

comparison of the output current with the PHTH

X

V_CSCOMP*CSREF+ *

@ I_OUT

@ DCR

thresholds, each transition introducing a programmable

200 ms delay. To avoid false changes from one power zone

to another caused by noise or short IOUT transients, the

Total

VCC

1:10

comparison between IOUT and PHTH threshold uses

X

CREF

Controller

RREF1

CSN1

hysteresis. The switch to a lower power zone is executed if

IOUT exceeds the PHTH threshold values while

a transition to a higher power zone number is only executed

X

CSN4

+

CSREF

RREF4

if IOUT is below PHTH -Hysteresis value. The hysteresis

−

X

value is set to 0x10h and can be changed by the user by

writing to the phase shedding configuration register. If

RPH1

RPH4

SWN1

SWN4

+

CSSUM

a power zone/PHTH threshold is disabled, the controller

X

−

will skip it during the power zone transition process.

When PSI = Low and the user requires to change the

power zone, the transition to the new power zone is identical

to the transition process used when PSI is set to the

Mid-state. The only exception is when the target power zone

is disabled in automatic phase shedding mode. In this case,

the controller will automatically enable the target power

zone and allow the transition. When the controller is set to

automatic phase shedding, the power zone will be

automatically disabled.

IOUT

ILIM

CSCOMP

CCS

RIMON

RILIM

RCS2

RCS1

RTH

Figure 9. Total Current Summing Amplifier

Set the gain by adjusting the value of the RPH resistors.

The DC gain should be set to the output voltage droop. If the

voltage from CSCOMP to CSREF is less than 100 mV at the

Switching Frequency

maximum output current IOUT

then it is recommend

MAX

A programmable precision oscillator is provided. The

clock oscillator serves as the master clock to the ramp

generator circuit. This oscillator is programmed by a resistor

to ground on the FSW pin. The FSW pin provides

approximately 2 V out and the source current is mirrored

into the internal ramp oscillator. The oscillator frequency is

approximately proportional to the current flowing in the

resistor. Table 19 lists the switching frequencies that can be

set using discrete resistor values for each phase

configuration. Also, the switching frequency information is

available in the FSW configuration register and it can be

changed by the user by writing to the FSW configuration

register.

increasing the gain of the CSCOMP amp. This is required to

provide a good current signal to offset voltage ratio for the

ILIMIT pin. The NTC should be placed near the inductor

used by phase 1. The output voltage droop should be set with

the droop filter divider.

The pole frequency in the CSCOMP filter should be set

equal to the zero from the output inductor. This allows the

circuit to recover the inductor DCR voltage drop current

signal. It is best to fine tune this filter during transient

testing.

DCR@25C

F_Z

+

(eq. 7)

2 @ p @ L_Phase

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15

NCV81277A

Programming the Current Limit ILIM

the value of the current limit resistor based on the

CSCOMP−CSREF voltage as shown in the Programming

the Current Limit ILIM section.

The current limit thresholds are programmed with

a resistor between the ILIMIT and CSCOMP pins. The

ILIMIT pin mirrors the voltage at the CSREF pin and

mirrors the sink current internally to IOUT (reduced by the

IOUT Current Gain) and the current limit comparators. The

100% current limit (CLIM1) trips if the ILIMIT sink current

exceeds 10 mA for 50 ms. The 150% current limit (CLIM2)

trips with minimal delay if the ILIMIT sink current exceeds

15 mA. Set the value of the current limit resistor based on the

CSCOMP−CSREF voltage as shown below.

In addition to the total current protection, the device

incorporates an OCP function on a per phase basis

(CLIM_phase) by continuously monitoring the

CSPX−CSREF voltage. The per-phase OCP limit is selected

on startup when a 10 mA current is sourced from the OCP.

The resulting voltage read on the pin selects both the max per

phase current and delay time (see Table 9). These can also

2

be programmed over I C (see Table 17).

V_{CSCOMP*CSREF@ILIMIT}

Table 9. PER PHASE OCP SETTINGS

RILIM +

(eq. 8)

10 mA

Resistance

Per Phase Voltage

(mV)

Latch Off Delay

(ms)

(kW)

or

RCS1@RTH

10

65

75

4

RCS2)

RCS1)RTH

@ I_OUT

@ DCR

LIMIT

14.7

RPH

(eq. 9)

RILIM +

20

100

134

65

4

10 mA

26.1

4

When PSI=low, current limit threshold will be scaled

down according to its remaining phase count in the power

zone: e.g. Iout_limit_2ph=2*Iout_limit/N. In this case total

phase number N=4.

33.2

6

41.2

75

6

49.9

100

134

65

6

Programming DROOP

60.4

6

The signals CSCOMP and CSREF are differentially

summed with the output voltage feedback to add precision

voltage droop to the output voltage.

71.5

8

84.5

75

8

ǒ

Ǔ

100

134

65

8

RCS1 ø RTH ) RCS2

Droop + DCR @

(eq. 10)

118.3

8

RPH

136.6

10

Programming IOUT

157.7

182.1

75

The IOUT pin sources a current in proportion to the

ILIMIT sink current. The voltage on the IOUT pin is

monitored by the internal A/D converter and should be

scaled with an external resistor to ground such that a load

equal to system max current generates a 2 V signal on IOUT.

A pull-up resistor to VCC can be used to offset the IOUT

signal positive if needed.

100

134

249

NOTE: 1% tolerance.

Under Voltage Lock-Out (VCC UVLO)

VCC is constantly monitored for the under voltage

lockout (UVLO) During power up both the VRMP and the

VCC pin are monitored Only after both pins exceed their

individual UVLO threshold will the full circuit be activated

and ready for the soft start ramp.

2.0 V @ RILIM

(eq. 11)

R_IOUT

+

RCS1@RTH

RCS1)RTH

RPH

RCS2)

10 @

@ I_OUT

@ DCR

MAX

PROTECTIONS

OCP

The device incorporates an over current protection

mechanism to shut down and latch off to protect against

damage due to an over current event. The current limit

threshold set by the ILIM pin on a full system basis.

The current limit thresholds are programmed with

a resistor between the ILIMIT and CSCOMP pins. The

ILIMIT pin mirrors the voltage at the CSREF pin and

mirrors the sink current internally to IOUT (reduced by the

IOUT Current Gain) and the current limit comparators. Set

Over Voltage Protection

An output voltage monitor is incorporated into the

controller. Over voltage protection will be tripped under the

following situations: for REFIN below 1.6V, if the output

voltage is 400 mV over the REFIN value; for REFIN over

1.6 V, as long as the output is above 2 V, the output will be

clamped to 2 V before being discharged. Once the over

voltage protection trips, the PGOOD pin will be pulled low,

but DRON will stay high. PWM outputs will only be

allowed to toggle between mid and low to discharge the

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16

NCV81277A

output. The PWM output high will remain disabled until the

power is cycled or the EN pin is toggled.

limited only by what the master and slave devices

can handle.

3. When all data bytes have been read or written, stop

conditions are established. In WRITE mode, the

Under Voltage Protection

An under voltage protection will be tripped if the output

is 300 mV below the REFIN voltage. When under voltage

protection trips, the PGOOD pin will be pulled low, the

DRON will stay high. PWM outputs will only be allowed to

toggle between mid and low to discharge the output. The

PWM output high will remain disabled until the power is

cycled or the EN pin is toggled.

th

master will pull the data line high during the 10

clock pulse to assert a STOP condition. In READ

mode, the master device will override the

acknowledge bit by pulling the data line high during

the low period before the ninth clock pulse. This is

known as No Acknowledge. The master will then

take the data line low during the low period before

the tenth clock pulse, then high during the tenth

clock pulse to assert a STOP condition.

I²C Interface

The controller is connected to this bus as a slave device,

under the control of a master controller.

4. Any number of bytes of data may be transferred over

the serial bus in one operation, but it is not possible

to mix read and write in one operation because the

type of operation is determined at the beginning and

cannot subsequently be changed without starting

a new operation. To write data to one of the device

data registers or read data from it, the Address

Pointer Register must be set so that the correct data

register is addressed, and then data can be written

into that register or read from it. The first byte of

a write operation always contains an address that is

stored in the Address Pointer Register. If data is to be

written to the device, the write operation contains

a second data byte that is written to the register

selected by the address pointer register. The device

address is sent over the bus followed by R/W set to

0. This is followed by two data bytes. The first data

byte is the address of the internal data register to be

written to, which is stored in the Address Pointer

Register. The second data byte is the data to be

written to the internal data register.

Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit

from the slave device. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period, because a low-to-high

transition when the clock is high might be interpreted as

a stop signal. The number of data bytes that can be

transmitted over the serial bus in a single read or write

operation is limited only by what the master and slave

devices can handle.

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing

a START condition, defined as a high-to-low

transition on the serial data line SDA while the serial

clock line, SCL, remains high. This indicates that an

address/data stream will follow. All slave

peripherals connected to the serial bus respond to the

START condition, and shift in the next eight bits,

consisting of a 7-bit address (MSB first) plus an R/W

bit, which determines the direction of the data

transfer, i.e., whether data will be written to or read

from the slave device. The peripheral whose address

corresponds to the transmitted address responds by

pulling the data line low during the low period before

the ninth clock pulse, known as the Acknowledge

Bit. All other devices on the bus now remain idle

while the selected device waits for data to be read

from or written to it. If the R/W bit is a 0, the master

will write to the slave device. If the R/W bit is a 1, the

master will read from the slave device.

2. Data is sent over the serial bus in sequences of nine

clock pulses, eight bits of data followed by an

Acknowledge Bit from the slave device. Transitions

on the data line must occur during the low period of

the clock signal and remain stable during the high

period, as a low-to-high transition when the clock is

high may be interpreted as a STOP signal. The

number of data bytes that can be transmitted over the

serial bus in a single READ or WRITE operation is

READ A SINGLE WORD

The master device asserts the start condition. The master

then sends the 7-bit slave address. It is followed by a R/W

bit that indicates the direction of operation, which will be

a write operation in this case. The slave whose address is on

the bus acknowledges it by an ACK signal on the bus (by

holding SDA line low). The master then sends register

address on the bus. The slave device accepts it by an ACK.

The master then asserts a repeated start condition followed

by a 7-bit slave address. The master then sends a direction

bit R/W which is Read for this case. Controller

acknowledges it by an ACK signal on the bus. This will start

the read operation and controller sends the high byte of the

register on the bus. Master reads the high byte and asserts an

ACK on the SDA line. Controller now sends the low byte of

the register on the SDA line. The master acknowledges it by

a no acknowledge NACK on the SDA line. The master then

asserts the stop condition to end the transaction.

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17

NCV81277A

S

Slave Address

0

ACK Register Address ACK Sr Slave Address

1 ACK Register Data NACK P

= Generated by the Master

= Generated by the Slave

S = Start Condition

P = Stop Condition

Sr = Repeated Start Condition

ACK/NACK = Acknowledge/No Acknowledge

Figure 10. Single Register Read Operation

READING THE SAME REGISTERS

MULTIPLE TIMES

1. The slave device sends the high byte of the register

on the bus.

2. The master reads the high byte and asserts an ACK

on the SDA line.

3. The slave device now sends the low byte of the

register on the SDA line.

4. The master acknowledges it by an ACK signal on the

SDA line.

5. The master and slave device keeps on repeating steps

1−4 until the low byte of the last reading is

transferred. After receiving the low byte of the last

register, the master asserts a not acknowledge

NACK on the SDA. The master then asserts a stop

condition to end the transaction.

The master device asserts the start condition. The master

then sends the 7-bit slave address. It is followed by a R/W

bit that indicates the direction of operation, which will be

a write operation in this case. The slave whose address is on

the bus acknowledges it by an ACK signal on the bus

(holding SDA line low). The master then sends register

address on the bus. The slave device accepts it by an ACK.

The master then asserts a repeated start condition followed

by a 7-bit slave address. The master then sends a direction

bit R/W which is Read for this case. Slave device

acknowledges it by an ACK signal on the bus. This will start

the read operation:

S

Slave Address 0 ACK Register Address ACK Sr Slave Address 1 ACK RD1 ACK RD2 ACK

RDN NACK P

= Generated by the Master

= Generated by the Slave

S = Start Condition

P = Stop Condition

Sr = Repeated Start Condition

RD1…N = Register Data 1…N

ACK/NACK = Acknowledge/No Acknowledge

Figure 11. Multiple Register Read Operation

WRITING A SINGLE WORD

The master device asserts the start condition. The master

then sends the 7-bit to the slave address. It is followed by a

R/W bit that indicates the direction of operation, which will

be a write operation in this case. The slave whose address is

on the bus acknowledges it by an ACK signal on the bus (by

holding SDA line low). The master then sends register

address on the bus. The slave device accepts it by an ACK.

The master then sends a data byte of the high byte of the

register. The slave device asserts an acknowledge ACK on

the SDA line. The master then sends a data byte of the low

byte of the register. The slave device asserts an acknowledge

ACK on the SDA line. The master asserts a stop condition

to end the transaction.

S

Slave Address

0

ACK Register Address ACK Register Data ACK

P

= Generated by the Master

= Generated by the Slave

S = Start Condition

P = Stop Condition

ACK = Acknowledge

Figure 12. Single Register Write Operation

WRITING MULTIPLE WORDS TO

DIFFERENT REGISTERS

The master device asserts the start condition. The master

then sends the 7-bit slave address. It is followed by a bit

(R/W) that indicates the direction of operation, which will

be a write operation in this case. The slave whose address is

on the bus acknowledges it by an ACK signal on the bus (by

holding SDA line low).

The master then sends first register address on the bus.

The slave device accepts it by an ACK. The master then

www.onsemi.com

18

NCV81277A

sends a data byte of the high byte of the first register. The

slave device asserts an acknowledge ACK on the SDA line.

The master then sends a data byte of the low byte of the

second register. The slave device asserts an acknowledge

ACK on the SDA line.

A complete word must be written to a register for proper

operation. It means that both high and low bytes must be

written.

slave device asserts an acknowledge ACK on the SDA line.

The master then sends a data byte of the low byte of the first

register. The slave device asserts an acknowledge ACK on

the SDA line.

The master then sends the second register address on the

bus. The slave device accepts it by an ACK. The master then

sends a data byte of the high byte of the second register. The

S

Slave Address

0

ACK RA1 ACK RD1 ACK RA2 ACK RD2 ACK

RAN ACK RDN ACK

ACK = Acknowledge

P

= Generated by the Master

= Generated by the Slave

S = Start Condition

P = Stop Condition

RA1…N = Register Address 1…N

RD1…N = Register Data 1…N

Figure 13. Multiple Register Write Operation

Table 10. REGISTER MAP

Address

0x20

0x21

0x22

0x23

0x24

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x44

R/W

R

Default Value

Description

0xFF

0x00

0x1A

0x76

0x04

0x00

IOUT_OC_WARN_LIMIT

STATUS BYTE

Fault Mask

R/W

R

STATUS Fault

STATUS Warning

READ_IOUT

MFR_ID

R

MFR_MODEL

MFR_REVISION

Lock/Reset

R

R/W

R

Soft Start Status

Reserved

N/A

R

Per phase OCP Status

R/W

R

0x00

Per phase OCP Configuration

Switching Frequency Status

Switching Frequency Configuration

Reserved

R/W

N/A

R

0x00

PSI Status

R

Phase Status

R/W

R

0x1F

0x00

LPC_Zone_enable

LPC Status

R/W

R

LPC Configuration

LL Status

R/W

RW

R

0x03

0x00

LL Configuration

PHTH1 Configuration

PHTH1 Status

R/W

R

0x00

0x08

PHTH2 Configuration

PHTH2 Status

R/W

R

PHTH3 Configuration

PHTH3 Status

R/W

R

PHTH4 Configuration

PHTH4 Status

R/W

Phase Shedding Hysteresis

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19

NCV81277A

Table 10. REGISTER MAP (continued)

Address

0x45

R/W

R

Default Value

0x14

Description

Phase Shedding Delay

0x46

0x00

Second Function Configuration Register Latch A

Second Function Configuration Register Latch B

DLT_READBACK_1, Die Level Traceability

DLT_READBACK_2, Die Level Traceability

DLT_READBACK_3, Die Level Traceability

DLT_READBACK_4, Die Level Traceability

DLT_READBACK_5, Die Level Traceability

0x47

0x00

0x48

0x49

R

0x4A

0x4B

0x4C

R

IOUT_OC_WARN_LIMIT Register (0x20)

This sets the high current limit. Once the READ_IOUT

register value exceeds this limit IOUT_OC_WARN_LIMIT

bit is set in the Status Warning register and an ALERT is

generated.

STATUS Fault Register (0x23)

Table 13. STATUS FAULT REGISTER SETTINGS

Bits

7:5

4

Name

Reserved

Clim1

Description

N/A

If not masked, this bit gets set when

IOUT exceeds the ILIM value.

STATUS BYTE Register (0x21)

Table 11. STATUS BYTE REGISTER SETTINGS

3

2

Clim2

If not masked, this bit gets set when

IOUT exceeds the ILIM value.

Bits

7:6

5

Name

Description

Clim_phase

If not masked, this bit gets set when

Reserved

VOUT_OV

N/A

the phase Current (V

−V

)

CSN

CSREF

exceeds the OCP configuration value.

This bit gets set whenever the

NCV81277A goes into OVP mode.

1

0

OVP

UVP

If not masked, this bit is set when an

OVP event is detected.

4

IOUT_OC

Reserved

This bit gets set whenever the

NCV81277A latches off due to an over

current event.

If not masked, this bit is set when an

UVP event is detected.

0:3

N/A

STATUS Warning Register (0x24)

Fault Mask Register (0x22)

Table 14. STATUS WARNING REGISTER SETTINGS

Table 12. FAULT MASK REGISTER SETTINGS

Bits

Name

Description

Bits

Name

Description

7:1

Reserved

N/A

7:5

Reserved

0

IOUT Overcurrent

Warning Reserved

This bit gets set if IOUT ex-

ceeds its programmed high

warning limit(register 0x20).

This bit is only cleared when

EN is toggled.

4

3

2

1

0

Clim1

Clim2

When this bit is set, the Clim1 bit from

the STATUS FAULT register will not

be set.

When this bit is set, the Clim2 bit from

the STATUS FAULT register will not

be set.

READ_IOUT Register (0x26)

Read back output current. ADC conversion 0xFF = 2 V

on IOUT pin which should equate to max current.

Clim_phase

OVP

When this bit is set, the Clim_phase

bit from the STATUS FAULT register

will not be set.

Lock/Reset Register (0x2A)

When this bit is set, the OVP bit from

the STATUS FAULT register will not

be set.

Table 15. LOCK/RESET REGISTER SETTINGS

Bits

Name

Description

UVP

When this bit is set, the UVP bit from

the STATUS FAULT register will not

be set.

7:1

Reserved

N/A

0

Lock

Logic 1 locks all limit values to their

current settings. Once this bit is set,

all lockable registers become

read-only and cannot be modified un-

til the NCV81277A is powered down

and powered up again. This prevents

rogue programs such as viruses from

modifying critical system limit settings

(Lockable).

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20

NCV81277A

Soft Start Status Register (0x2B)

Table 17. OCP STATUS AND CONFIGURATION

REGISTER SETTINGS

This register contains the value that sets the slew rate of

the output voltage during power-up. When EN is set high,

the controller reads the value of the resistor connected to the

SS pin and sets the slew rate. The codes corresponding to

each resistor setting are shown in Table 16. The resistor

settings are updated on every rising edge of the EN signal.

Bits

Name

Description

7:4

Reserved

N/A

3:2

Per Phase OCP Limit

00 = 65 mV

01 = 75 mV

10 = 100 mV

11 = 134 mV

Table 16. SOFT START STATUS REGISTER SETTINGS

1:0

OCP_latch Off Delay

00 = 4 ms

01 = 6 ms

10 = 8 ms

11 = 10 ms

T_ramp

(ms) ,

REFIN

=1 V

T_ramp

(ms),

REFIN

=0.8 V

T

RAMP

Resistor

(kW)

Bits

7:4

Name

Value

N/A

Switching Frequency Status and Configuration

Registers (0x2F, 0x30)

−

Reserved

T_Ramp

N/A

0.15

0.3

0.45

0.6

0.75

0.9

1

N/A

0.12

0.24

0.36

0.48

0.6

0.72

0.8

1.6

2.4

3.2

4

10

3:0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

These registers contain the values that set the switching

frequency of the controller. When EN is set high, the

controller reads the value of the resistor connected to the

FSW pin and sets the switching frequency according to

Table 19. The codes corresponding to each setting are also

shown in Table 19. The resistor settings are updated on

every rising edge of the EN signal.

14.7

20

26.1

33.2

41.2

49.9

60.4

71.5

84.5

100

The switching frequency configuration register allows the

user to dynamically change the switching frequency through

2

the I C interface provided that the FSW bits from the second

function configuration registers A and B (0x46, 0x47) are

set.

3

4

5

PSI Status Register (0x32)

The PSI status register provides the information regarding

the current status of the PSI pin though the I C interface as

shown in Table 18.

118.3

136.6

157.7

182.1

249

6

4.8

5.6

6.4

7.2

8

2

7

8

Table 18. PSI STATUS REGISTER SETTINGS

9

Bits

Description

10

7:2

Reserved

NOTE: 1% tolerance.

1:0

00 = PSI MID

01 = PSI LOW

10 = PSI HIGH

Per Phase OCP Status Register and Configuration

Register (0x2D, 0x2E)

These registers contain the values that set the per phase

OCP current levels for each phase individually as well as the

latch off delay time for the OCP event. When EN is set high,

the controller reads the value of the resistor connected to the

OCP pin and sets the OCP threshold and latch off delay time

according to Table 9. The codes corresponding to each

setting are shown in Table 17. The resistor settings are

updated on every rising edge of the EN signal.

The OCP configuration register (0x2E) allows the user to

dynamically change the OCP threshold and latch off delay

2

through the I C interface provided that the OCP bits from

the second function configuration registers A and B (0x46,

0x47) are set. In addition, the OCP levels and latch off delay

times can be adjusted independently when the OCP

configuration register is used. The achievable switching

frequency settings are listed in Table 17.

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21

NCV81277A

Table 19. SWITCHING FREQUENCY STATUS AND CONFIGURATION REGISTER SETTINGS

Value

Switching Frequency (kHz)

FSW Pin

Resistor

Value (kW)

Status

Register

Configuration

4

3

2

1

Register

Phase

Bits

7:5

Reserved

0000

−

Reserved

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

N/A

221

244

266

293

307

333

351

373

394

421

449

469

479

509

518

543

581

649

708

751

799

866

919

964

993

1059

1098

1141

1200

1236

1291

1312

N/A

293

N/A

223

243

264

294

317

335

352

380

399

420

436

454

483

508

526

543

583

656

698

771

807

860

899

950

1003

1052

1096

1154

1205

1227

1274

1316

N/A

232

252

272

297

322

340

361

385

413

435

456

478

500

509

518

540

578

638

698

758

818

878

938

972

1014

1067

1106

1155

1201

1245

1280

1330

10

4:0

329

14.7

20

0001

−

358

381

0010

−

407

450

26.1

33.2

41.2

49.9

60.4

71.5

84.5

100

0011

−

480

510

0100

−

530

562

0101

−

600

614

0110

−

631

663

0111

−

688

722

1000

−

789

859

1001

−

930

1010

1095

1147

1233

1260

1341

1372

1450

1539

1619

1618

1674

1724

1010

−

118.3

136.6

157.7

182.1

249

1011

−

1100

−

1101

−

1110

−

1111

−

NOTE: 1% tolerance.

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22

NCV81277A

Phase Status Register (0x33)

Table 22. CONFIGURATION REGISTER SETTINGS

The Phase Status register provides the information about

the status of each of the four available phases as shown in

Table 20.

Bits

7:6

Name

Value

N/A

Level

N/A

0

Reserved

5:3

LPC2

Configuration

000 (default)

001

Table 20. PHASE STATUS REGISTER SETTINGS

N/A

2

010

Bits

7:4

3

Name

Reserved

Phase 4

Description

011

3

N/A

100

4

0 = Disabled

1 = Enabled

101 = Reserved

110 = Reserved

111 = Reserved

000 (default)

001

N/A

0

2

1

0

Phase 3

Phase 2

Phase 1

0 = Disabled

1 = Enabled

2:0

LPC1

Configuration

0 = Disabled

1 = Enabled

N/A

2

010

0 = Disabled

1 = Enabled

011

3

100

4

101 = Reserved

110 = Reserved

111 = Reserved

N/A

LPC_Zone_enable Register (0x34)

The LPC_Zone_enable register allows the user to enable

or disable power zones while the controller has the PSI set

2

LL Status and Configuration Registers (0x38, 0x39)

These registers contain the values that set the fraction of

the externally configured load line (see Total Current Sense

Amplifier section) to be used during the normal operation of

the device. When EN is set high, the controller reads the

value of the resistor connected to the LL/I2C_ADD pin and

sets the load line according to Table 5. The codes

corresponding to each setting are shown in Table 23. The

load line resistor setting is updated on every rising edge of

the EN signal.

The LL configuration register allows the user to

dynamically change the load line settings through the I C

interface provided that the LL bits from the second function

configuration registers A and B (0x46, 0x47) are set. The

achievable load line settings are listed in Table 23.

low using the I C interface as shown in Table 21.

Table 21. LPC_ZONE_ENABLE REGISTER SETTINGS

Bits

Name

Description

7:4

Reserved

N/A

4

3

2

Zone 4

Zone 3

Zone 2

0 = Disabled

1 = Enabled

0 = Disabled

1 = Enabled

0 = Disabled

1 = Enabled

2

1

0

Reserved

Zone 0

N/A

0 = Disabled

1 = Enabled

Table 23. LL STATUS AND CONFIGURATION

REGISTER SETTINGS

LPC Status and Configuration Registers (0x35, 0x36)

These registers contain the values that set the operating

power zone when the PSI pin is set low. When EN is set high,

the controller reads the value of the resistor connected to the

LPC1 and LPC2 pins and sets the power zone according to

Bits

7:2

Description

Reserved

1:0

00 = 100% of externally set load line (default)

01 = 50% of externally set load line

10 = 25 of externally set load line

Table 7. The LPC resistor settings are updated on every

X

rising edge of the EN signal. LPC status register 0x35

records the status of LPC2(Bit[2:0]) and LPC1(Bit[5:3])

resistor setting during startup. The status register value

won’t change afterwards.

11 = 0% of externally set load line

PHTH1 to PHTH4 Configuration Registers (0x3A, 0x3C,

0x3E, 0x40)

These registers contain the values that control the phase

shedding thresholds and are active when the PHTH bits

from the second function configuration registers A and B

(0x46 and 0x47) are set be set. These thresholds allow the

The LPC configuration register (0x36) allows the user to

dynamically change the power zone (PSI = Low) through

X

2

the I C interface provided that the LPC bits from the second

function configuration registers A and B (0x46, 0x47) are

set. The achievable power zone settings are listed in

Table 22.

2

user to dynamically change the thresholds through the I C

interface. The values written to these registers should match

the value of the READ_IOUT register (0x26) at the desired

load current. If 0xFF is written to a register, the phase

shedding threshold corresponding to that register is

disabled.

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23

NCV81277A

PHTH1 to PHTH4 Status Registers

(0x3B, 0x3D, 0x3F 0x41)

These registers contain the phase shedding threshold

Table 24. SECOND CONFIGURATION LATCH

REGISTER A AND B

Second Function

Configuration

Register

values set by the resistors connected to the PHTH pins. The

X

values of the thresholds are updated on every rising edge of

the EN signal. The resistor values should be chosen to ensure

that the voltage drop across them developed by the 10 mA

current sourced by the NCV81277A during power-up (EN

set high) matches the value of the READ_IOUT register

(0x26) at the desired load current. Setting the resistors to

Bits

7:6

5

Description

Reserved

FSW

N/A

0 = set by external resistor

(see Table 19)

1 = set by register 0x30

(see Table 19)

generate a voltage above 2 V will disable the PHTH

threshold for that pin.

X

4

LL

0 = set by external resistor

(see Table 5)

1 = set by register 0x39

Phase Shedding Hysteresis Register (0x44)

This register sets the hysteresis during a transition from

a high count phase to a low count phase configuration. The

hysteresis is expressed in codes (LSBs) of the PHTH

threshold values, by default its value is 08H. .

3

2

Reserved

OCP

N/A

0 = set by external resistor

(see Table 9)

1= set by register 0x2E

X

1

0

LPC1, LPC2

0 (default) = low power zone set

by external resistor

1 = low power zone set by regis-

ter 0x36

Phase Shedding Delay Register (0x45)

This register sets the delay during a transition from a high

count phase to a low count phase configuration. The

power-up default value is 200 ms (14H) and it can be

dynamically changed in steps of 10 ms (1 LSB) through the

PHTH

0 = set by external resistors con-

X

nected between PHTH pins and

X

GND

2

I C interface.

1 = set by registers 0x3A, 0x3C,

0x3E and 0x40

Second Function Configuration Register

Latch A and B Registers (0x46, 0x47)

These registers allow the user to select whether the second

functions settings (LL, Soft Start, OCP, LPC and PHTH )

X

are controlled by the external resistors or the configuration

registers (see Table 24). When/EN is toggled the default

control mode for the second functions is the external resistor.

Switching between the two modes can be done by simply

writing the appropriate byte (the same byte) to both registers

(the order doesn’t matter).

NVIDIA is a registered trademark of of NVIDIA Corporation in the U.S. and/or other countries. All other brand names and product names appearing in this

document are registered trademarks or trademarks of their respective holders.

www.onsemi.com

24

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFNW40 5x5, 0.4P

CASE 484AK

ISSUE B

DATE 19 FEB 2020

EXPOSED

COPPER

GENERIC

MARKING DIAGRAM*

1

XXXXX = Specific Device Code

XXXXXXXX

AWLYYWWG

G

A

= Assembly Location

= Wafer Lot

WL

YY

WW

G

*This information is generic. Please refer to

= Year

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present. Some products

may not follow the Generic Marking.

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

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QFNW40 5x5, 0.4P

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


型号：	NCV81277AMNTXG
厂家：	ONSEMI
描述：	4/3/2/1 Phase Buck Controller with PWM_VID and I2C Interface
文件：	总26页 (文件大小：365K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV81277AMNTXG [ONSEMI]

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