NCV84140DR2G [ONSEMI]
Self Protected Very Low Iq High Side Driver with Analog Current Sense;型号: | NCV84140DR2G |
厂家: | ONSEMI |
描述: | Self Protected Very Low Iq High Side Driver with Analog Current Sense |
文件: | 总27页 (文件大小:519K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
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Self Protected Very Low Iq
High Side Driver with
Analog Current Sense
8
1
SOIC−8
CASE 751−07
STYLE 11
NCV84140
The NCV84140 is a fully protected single channel high side driver
that can be used to switch a wide variety of loads, such as bulbs,
solenoids, and other actuators. The device incorporates advanced
protection features such as active inrush current management,
over−temperature shutdown with automatic restart and an overvoltage
active clamp. A dedicated Current Sense pin provides precision analog
current monitoring of the output as well as fault indication of short to
MARKING DIAGRAM
8
84140
ALYWG
G
1
V , short circuit to ground and OFF state open load detection. An
D
active high Current Sense Enable pin allows all diagnostic and current
sense features to be enabled.
84140 = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Features
Y
W
G
= Year
= Work Week
= Pb−Free Package
• Short Circuit Protection with Inrush Current Management
• CMOS (3 V / 5 V) Compatible Control Input
• Very Low Standby Current
(Note: Microdot may be in either location)
• Very Low Current Sense Leakage
• Proportional Load Current Sense
• Current Sense Enable
PIN CONNECTIONS
1
IN
CS_EN
GND
VD
• Off State Open Load Detection
OUT
OUT
VD
• Output Short to V Detection
D
• Overload and Short to Ground Indication
• Thermal Shutdown with Automatic Restart
• Undervoltage Shutdown
CS
(Top View)
• Integrated Clamp for Inductive Switching
• Loss of Ground and Loss of V Protection
D
ORDERING INFORMATION
• ESD Protection
†
Device
NCV84140DR2G
Package
Shipping
• Reverse Battery Protection with External Components
• AEC−Q100 Qualified
SOIC−8
(Pb−Free)
2500 / Tape &
Reel
• This is a Pb−Free Device
Typical Applications
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Switch a Variety of Resistive, Inductive and Capacitive Loads
• Can Replace Electromechanical Relays and Discrete Circuits
• Automotive / Industrial
FEATURE SUMMARY
R
(typical) T = 25°C
R
140
12
mW
A
DSon
J
ON
Output Current Limit (typical)
I
lim
OFF−state Supply Current (max)
I
0.5
mA
D(off)
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
September, 2022 − Rev. 2
NCV84140/D
NCV84140
BLOCK DIAGRAM & PIN CONFIGURATION
VD
Overvoltage
Protection
Undervoltage
Protection
IN
Output
Clamping
Regulated
Charge Pump
í
CS_
EN
Current Limit
Overtemperature
and
Power Protection
OFF State Open
Load Detection
Analog Fault
OUT
Control
CS
Logic
Current
Sense
GND
Figure 1. Block Diagram
Table 1. SO8 PACKAGE PIN DESCRIPTION
Pin #
Symbol
IN
Description
Logic Level Input
1
2
3
4
5
6
7
8
CS_EN
GND
CS
Current Sense Enable
Ground
Analog Current Sense Output
Supply Voltage
Output
V
D
OUT
OUT
Output
V
D
Supply Voltage
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2
NCV84140
ID
VDS
IIN
VD
IN
IOUT
OUT
ICS
CS
ICS_EN
D
V
CS_EN
V
IN
VOUT
GND
VCS
_
CS EN
V
IGND
Figure 2. Voltage and Current Conventions
Table 2. Connection suggestions for unused and or unconnected pins
Connection
Floating
Input
Output
X
Current Sense
Current Sense Enable
X
X
Not Allowed
To Ground
Through 10 kW resistor
Not Allowed
Through 1 kW Resistor
Through 10 kW resistor
IN
1
2
8
VD
7
OUT
CS _ EN
GND
CS
6
5
3
4
OUT
VD
Figure 3. Pin Configuration (Top View)
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NCV84140
ELECTRICAL SPECIFICATIONS
Table 3. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
DC Supply Voltage
V
D
−0.3
38
45
Max Transient Supply Voltage (Note 1)
Load Dump − Suppresses
U *
S
−
V
Input Voltage
V
−10
−5
−
10
V
mA
mA
A
IN
Input Current
I
IN
5
−200
Reverse Ground Pin Current
Output Current (Note 2)
Reverse CS Current
CS Voltage
I
GND
I
−6
−
Internally Limited
−200
OUT
I
mA
V
CS
V
CS
V
− 41
V
D
D
CS_EN Voltage
V
−10
10
5
V
CS_EN
CS_EN
CS_EN Current
I
−5
mA
W
Power Dissipation Tc = 25°C (Note 6)
P
tot
1.17
Electrostatic Discharge (Note 3)
(HBM Model 100 pF / 1500 W)
Input
V
ESD
DC
4
4
4
4
4
−
−
−
−
−
kV
kV
kV
kV
kV
Current Sense
Current Sense Enable
Output
V
D
Charged Device Model
CDM−AEC−Q100−011
750
−
V
Single Pulse Inductive Load Switching Energy
E
AS
−
36.8
mJ
(L = 5 mH, I = 3.84 A, T
= 150°C, V tied to GND
L
Jstart
D
during inductive discharge) (Note 4)
Operating Junction Temperature
Storage Temperature
T
−40
−55
+150
+150
°C
°C
J
T
storage
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class C (or A, B) according to ISO16750−1.
2. Reverse Output current has to be limited by the load to stay within absolute maximum ratings and thermal performance.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JS−001−2017)
Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes smaller than
2 x 2 mm due to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current
waveform characteristic defined in JEDEC JS−002−2018
4. Not subjected to production testing
Table 4. THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max. Value
Units
Thermal Resistance
°C/W
Junction−to−Lead (Note 5)
Junction−to−Ambient (Note 5)
Junction−to−Ambient (Note 6)
R
29
65
106
q
JL
JA
JA
R
R
q
q
2
5. 645 mm pad size, mounted on four−layer 1s2p PCB − FR4, 2 oz. Cu thickness for top layer and 1 oz. Cu thickness for inner layers (planes
not electrically connected)
2
6. 2 cm pad size, mounted on single−layer 1s0p PCB − FR4, 2 oz. Cu thickness
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NCV84140
ELECTRICAL CHARACTERISTICS (7 V ≤ V ≤ 28 V; −40°C ≤ T ≤ 150°C unless otherwise specified)
D
J
Table 5. POWER
Value
Typ
−
Min
4
Max
28
4
Rating
Symbol
Conditions
Unit
V
Operating Supply Voltage
Undervoltage Shutdown
V
D
V
−
3.5
V
UV
UV_hyst
Undervoltage Shutdown
Hysteresis
V
−
0.4
−
V
On Resistance
R
I
= 1 A, T = 25°C
−
−
−
−
140
−
−
mW
ON
OUT
J
I
= 1 A, T = 150°C
295
210
0.5
OUT
J
I
= 1 A, V = 4.5 V, T = 25°C
−
OUT
D
J
Supply Current (Note 7)
I
OFF−state: V = 13 V,
IN
0.2
mA
mA
D
D
V
= V
= 0 V, Tj = 25°C
OUT
OFF−state: V = 13 V,
OUT
−
−
−
−
0.2
−
0.5
3
D
V
= V
= 0 V, Tj = 85°C (Note 8)
IN
OFF−state: V = 13 V,
= V
mA
D
V
IN
= 0 V, Tj = 125°C
OUT
ON−state: V = 13 V,
V
1.9
−
3.5
6
mA
mA
mA
D
OUT
= 5 V, I
= 0 A
IN
On State Ground Current
Output Leakage Current
I
V
= 13 V, V
= 5 V
GND(ON)
D
V
CS_EN
OUT
= 5 V, I
= 1 A
IN
I
V
= V
= 0 V, V = 13 V, Tj = 25°C
−
−
−
−
0.5
3
L
IN
OUT
OUT
D
V
= V
= 0 V, V = 13 V, Tj = 125°C
D
IN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Includes PowerMOS leakage current.
8. Not subjected to production testing
Table 6. LOGIC INPUTS (V = 13.5 V; −40°C ≤ T ≤ 150°C)
D
J
Value
Typ
−
Min
−
Max
0.9
−
Rating
Input Voltage − Low
Input Current − Low
Input Voltage − High
Input Current − High
Input Hysteresis Voltage
Input Clamp Voltage
Symbol
Conditions
Unit
V
V
IN_low
I
V
V
= 0.9 V
= 2.1 V
= 1 mA
1
−
mA
V
IN_low
IN
IN
IN
V
2.1
−
−
−
IN_high
IN_high
I
−
10
−
mA
V
V
−
0.2
13
−13
−
IN_hyst
V
IN_cl
I
12
−14
−
14
−12
0.9
−
V
I
IN
= −1 mA
CS_EN Voltage − Low
CS_EN Current − Low
CS_EN Voltage − High
CS_EN Current − High
CS_EN Hysteresis Voltage
CS_EN Clamp Voltage
V
_
V
mA
V
CSE low
I
_
V
V
= 0.9 V
= 2.1 V
= 1 mA
1
−
CSE low
CS_EN
CS_EN
CS_EN
V
_
2.1
−
−
−
CSE high
I
−
10
−
mA
V
CSE_high
V
_
−
0.2
13
−13
CSE hyst
V
_
I
12
−14
14
−12
V
CSE cl
I
= −1 mA
CS_EN
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NCV84140
Table 7. SWITCHING CHARACTERISTICS (V = 13 V, −40°C ≤ T ≤ 150°C)
D
J
Value
Typ
70
Min
5
Max
120
100
0.7
Rating
Turn−On Delay Time
Turn−Off Delay Time
Slew Rate On
Symbol
Conditions
Unit
ms
t
V
high to 20% V , R = 13 W, T = 25°C
OUT L J
d_on
d_off
IN
t
V
low to 80% V
, R = 13 W, T = 25°C
5
40
ms
IN
OUT
L
J
dV /dt
out on
20% to 80% V
, R = 13 W, T = 25°C
0.1
0.1
−
0.27
0.35
0.15
V / ms
V / ms
mJ
OUT
L
J
Slew Rate Off
dV /dt
out off
80% to 20% V
, R = 13 W, T = 25°C
0.7
OUT
L
J
Turn−On Switching Loss
(Note 9)
E
on
R = 13 W
L
0.18
Turn−Off Switching Loss
E
R = 13 W
−
0.1
0.18
50
mJ
off
L
(Note 9)
Differential Pulse Skew, (t
t
R = 13 W
L
−50
−
ms
(OFF)
skew
− t
) see Figure 4 (Switching
(ON)
Characteristics)
9. Not subjected to production testing.
Table 8. OUTPUT DIODE CHARACTERISTICS
Value
Typ
−
Min
Max
Rating
Forward Voltage
Symbol
Conditions
Unit
V
F
I
= −1 A, T = 150°C
−
0.7
V
OUT
J
Table 9. PROTECTION FUNCTIONS (Note 10) (7 V ≤ V ≤ 18 V, −40°C ≤ T ≤ 150°C)
D
J
Value
Typ
175
7
Min
150
−
Max
200
−
Rating
Symbol
Conditions
Unit
°C
Temperature Shutdown (Note 11)
T
SD
SD_hyst
Temperature Shutdown
T
°C
Hysteresis (T − T ) (Note 11)
SD
R
Reset Temperature (Note 11)
Thermal Reset of Status (Note 11)
Delta T Temperature Limit (Note 11)
DC Output Current Limit
T
T
+1
T
+7
−
−
°C
°C
°C
A
R
RS
RS
T
RS
135
−
T
T = −40°C, V = 13 V
−
8
−
−
60
12
−
−
DELTA
J
D
I
V
D
= 13 V
16
16
−
limH
4 V < V < 18 V
A
D
Short Circuit Current Limit during
Thermal Cycling (Note 11)
I
V
R
= 13 V
4
A
limTCycling
D
T
< Tj < T
TSD
Switch Off Output Clamp Voltage
Overvoltage Protection
V
I
= 0.2 A, V = 0 V, L = 20 mH
V
D
− 41
V
D
− 46
V − 52
D
V
V
OUT_clamp
OUT
IN
V
OV
V
IN
= 0 V, I = 20 mA
41
46
20
52
D
Output Voltage Drop Limitation
V
I
= 0.07 A
−
−
mV
DS_ON
OUT
10.To ensure long term reliability during overload or short circuit conditions, protection and related diagnostic signals must be used together
with a fitting hardware & software strategy. If the device operates under abnormal conditions, this hardware & software solution must limit
the duration and number of activation cycles.
11. Not subjected to production testing.
Table 10. OPEN−LOAD DETECTION (7 V ≤ V ≤ 18 V, −40°C ≤ T ≤ 150°C)
D
J
Value
Typ
−
Min
Max
Rating
Symbol
Conditions
Unit
Open−load Off State
Detection Threshold
V
OL
V
IN
= 0 V, V = 5 V
CS_EN
2
4
V
Open−load Detection
Delay at Turn Off
t
100
350
700
ms
d_OL_off
Off State Output Current
I
V
= 0 V, V
= V
OL
−3
−
3
mA
ms
OLOFF1
IN
OUT
Output rising edge to CS rising
edge during open load
t
V
= 4 V, V = 0 V
−
5
30
d_OL
OUT
IN
V
CS
= 90% of V
CS_High
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NCV84140
Table 11. CURRENT SENSE CHARACTERISTICS (7 V ≤ V ≤ 18 V, −40°C ≤ T ≤ 150°C)
D
J
Value
Typ
−
Min
260
265
−25
270
−20
275
−15
375
−10
420
−5
Max
800
720
25
Rating
Symbol
Conditions
= 0.010 A, V = 0.5 V, V
Unit
Current Sense Ratio
K
I
I
I
= 5 V
= 5 V
= 5 V
0
1
OUT
OUT
OUT
CS
CS_EN
CS_EN
CS_EN
Current Sense Ratio
K
= 0.025 A, V = 0.5 V, V
490
−
CS
Current Sense Ratio Drift (Note 13)
Current Sense Ratio
DK / K
= 0.025 A, V = 0.5 V, V
%
%
%
%
1
1
2
3
4
5
CS
K
2
I
= 0.07 A, V = 4 V, V = 5 V
CS_EN
475
−
675
20
OUT
CS
Current Sense Ratio Drift (Note 13)
Current Sense Ratio
DK / K
I
= 0.07 A, V = 5 V
CS_EN
2
OUT
K
3
I
= 0.15 A, V = 4V, V
= 5 V
475
−
625
15
OUT
CS
CS_EN
Current Sense Ratio Drift (Note 13)
Current Sense Ratio
DK / K
I
= 0.15 A, V
= 5 V
3
OUT
CS_EN
K
4
I
= 0.7 A, V = 4 V, V = 5 V
CS_EN
475
−
540
10
OUT
CS
Current Sense Ratio Drift (Note 13)
Current Sense Ratio
DK / K
I
= 0.7 A, V
= 5 V
4
OUT
CS_EN
K
5
I
= 2 A, V = 4 V, V = 5 V
CS_EN
450
−
480
5
OUT
CS
Current Sense Ratio Drift (Note 13)
Current Sense Leakage Current
DK / K
I
= 2 A, V = 5 V
CS_EN
%
5
OUT
CS
I
= 0 A, V = 0 V
−
−
1
mA
Ilkg
OUT
CS
V
= 5 V, V = 0 V
CS_EN
IN
I
= 0 A, V = 0 V
−
−
5
−
7
2
−
−
−
−
−
−
−
2
0.5
7
OUT
CS
V
= 5 V, V = 5 V
CS_EN
IN
I
= 1 A, V = 0 V
CS
OUT
V
= 0 V, V = 5 V,
CS_EN
IN
CS Max Voltage
CS
V
OUT
= 7 V, V = 5 V, R = 15 kW,
= 2 A, T = 150°C, V
−
V
V
Max
D
IN
CS
I
= 5 V
J
CS_EN
Current Sense Voltage in Fault Con-
dition (Note 12)
V
V
= 13 V, V = 0 V, R = 1 k,
OUT
10
20
−
−
CS_fault
CS_fault
OUT_sat
D
IN
CS
= 5 V
V
= 4 V, V
CS_EN
Current Sense Current in Fault Con-
dition (Note 12)
I
V
= 13 V, V = 5 V, V = 0 V,
OUT
30
−
mA
A
D
CS
= 4 V, V
IN
= 5 V
V
CS_EN
Output Saturation Current (Note 13)
CS_EN High to CS High Delay Time
CS_EN Low to CS Low Delay Time
I
V = 7 V, V = 4 V, V = 5 V,
D CS IN
T = 150°C, V
J
= 5 V
CS_EN
t
V
= 5 V, V = 0 to 5 V,
CS_EN
R
−
100
25
250
250
100
ms
ms
ms
ms
ms
CS_High1
IN
IN
IN
IN
= 1 kW, R = 13 W
CS
L
t
V
V
V
= 5 V, V
R
= 5 to 0 V,
5
CS_Low1
CS_EN
= 1 kW, R = 13 W
CS
L
V
V
High to CS High Delay Time
Low to CS Low Delay Time
t
= 0 to 5 V, V
R
= 5 V,
100
50
−
in
CS_High2
CS_EN
= 1 kW, R = 13 W
CS
L
t
= 5 to 0 V, V
R
= 5 V,
in
CS_Low2
CS_EN
= 1 kW, R = 13 W
CS
L
Delay Time I Rising Edge to Rising
Dt
CS_High2
R = 13 W, R = 1 kW, V = 5 V,
D
L
CS
IN
Edge of CS
I
= 200 mA, I = 50% of I
OUT
CS
CSMAX
12.The following fault conditions included are: Over−temperature, Power Limitation, and OFF State Open−Load Detection.
13.Not subjected to production testing.
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NCV84140
Table 12. TRUTH TABLE
Conditions
Input
Output
CS (V
= 5 V) (Note 14)
CS_EN
Normal Operation
L
H
L
H
0
I
= I
/K
CS
OUT NOMINAL
Overtemperature
Undervoltage
L
L
L
0
H
V
CS_fault
L
H
L
L
0
0
Overload
H
H
H (no active current mgmt)
Cycling (active current mgmt)
I
= I
/K
CS_fault
CS
OUT NOMINAL
V
Short circuit to Ground
OFF State Open Load
L
L
L
0
H
V
V
CS_fault
L
H
CS_fault
14.If V
is low, the Current Sense output is at a high impedance, its potential depends on leakage currents and external circuitry.
CS_EN
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NCV84140
WAVEFORMS AND GRAPHS
Resistive Switching Characteristics
V
OUT
80%
80%
dVOUT/ dt
(off)
dVOUT/dt
(on)
20%
20%
td
(on)
td
(off)
V
IN
t
(on)
t
(off)
Figure 4. Switching Characteristics
V
IN
Normal Operation
t
t
t
t
t
I
t
ON
OFF
t
OUT
ON
V
CS_EN
t
Δt
CS_High2
CS_Low1
I
t
CS
CS_High1
t
CS_High2
Figure 5. Normal Operation with Current Sense Timing Characteristics
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NCV84140
V
IN
Dt
CS_High2
t
I
OUT
I
OUTMAX
90% I
OUTMAX
t
I
CS
I
CSMAX
90% I
CSMAX
t
Figure 6. Delay Response from Rising Edge of IOUT and Rising Edge of CS (for VCS_EN = 5 V)
Off−State Open − Load Delay Timing
V
IN
t
V
OUT
V
OL
t
t
V
CS
V
CS_FAULT
t
d_OL_off
Figure 7. OFF−State Open−Load Flag Delay Timing
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NCV84140
V
IN
V
OUT
V
OL
I
OUT
V
CS
V
CS_Fault
t
d_OL_off
t
CS_Low1
V
CS_EN
Figure 8. Off−State Open−Load with Added External Components
V
D
− V
OUT
T = 150°C
J
T = 25°C
J
T = −40°C
J
V
DS_ON
V
/R
(T)
DS_ON DS_ON
I
OUT
Figure 9. Voltage Drop Limitation for VDS_ON
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NCV84140
850
800
750
700
650
600
550
500
450
400
350
30
25
20
15
10
5
A. Max, −40°C ≤ T ≤ 150°C
J
A. Max, −40°C ≤ T ≤ 150°C
J
0
−5
−10
−15
−20
−25
−30
B. Typ, −40°C ≤ T ≤ 150°C
J
B. Min, −40°C ≤ T ≤ 150°C
J
C. Min, −40°C ≤ T ≤ 150°C
J
300
250
200
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
(A)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
I
I
(A)
OUT
OUT
Figure 10. IOUT/ICS vs. IOUT
Figure 11. Maximum Current Sense Ratio Drift
vs. Load Current
V
IN
I
OUT
I
limH
I
limTCycling
I
CS
I
CS_Fault
V
CS_EN
Figure 12. Short to GND or Overload
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12
NCV84140
V
IN
t
t
Overload
DC Output Current Limit
I
OUT
Current Limit during
thermal cycling
I
LIMH
I
LIMTCycling
T
J
T
TSD
T
R
T
RS
ΔT
J
ΔT
J_RST
T
J_Start
t
Figure 13. How TJ progresses During Short to GND or Overload
V
IN
Overload
I
OUT
I
NOMINAL
I
limH
I
limTCycling
I
CS
I
CS_Fault
I
/K
NOM
V
CS_EN
Figure 14. Discontinuous Overload or Short to GND
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13
NCV84140
Resistive short
from OUT to VD
Short from OUT
to VD
V
OUT
V
OL
I
OUT
V
CS
V
CS_Fault
t
t
d_OL_off
d_OL_off
V
CS_EN
Figure 15. Short Circuit from OUT to VD
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14
NCV84140
TYPICAL CHARACTERISTICS
7.5
7.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
V
= 0 V
IN
= 0 V
OUT
V
= 5 V
T = 150°C
IN
J
6.5
6.0
5.5
5.0
4.5
4.0
3.5
V
D
= 13 V
T = 125°C
J
V
IN
= 0.9 V
= 2.1 V
T = 25°C
J
T = −40°C
J
3.0
2.5
2.0
V
IN
0
−0.5
−2
2
6
10
14
18
(V)
22
26
30
34
−50 −30 −10 10 30 50 70 90 110 130 150
V
D
TEMPERATURE (°C)
Figure 16. Output Leakage Current vs. VD
Voltage & Temperature, VOUT = 0 V
Figure 17. Input Current vs. Temperature
14.0
13.5
13.0
12.5
−11.0
−11.5
−12.0
−12.5
−13.0
I
IN
= 1 mA
I
IN
= −1 mA
12.0
11.5
−13.5
−14.0
−50 −30 −10 10 30 50 70 90 110 130 150
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Input Clamp Voltage (Positive) vs.
Temperature
Figure 19. Input Clamp Voltage (Negative) vs.
Temperature
2.1
1.7
2.0
1.9
1.8
1.7
1.6
1.5
1.4
V = 13 V
D
1.6
1.5
1.4
1.3
1.2
V
D
= 13 V
1.1
1.0
1.3
1.2
−50 −30 −10 10 30 50 70 90 110 130 150
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 20. VIN Threshold High vs. Temperature
Figure 21. VIN Threshold Low vs. Temperature
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15
NCV84140
TYPICAL CHARACTERISTICS
0.40
0.35
0.30
400
V
= 13.5 V
= 1 A
D
350
300
250
200
150
100
I
OUT
0.25
0.20
0.15
0.10
0.05
0
50
0
−50 −30 −10 10 30 50 70 90 110 130 150
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. Hysteresis Input Voltage vs.
Temperature
Figure 23. RON vs. Temperature
3.50
650
600
550
500
450
400
350
300
250
200
150
I
= 1 A
OUT
3.45
3.40
3.35
3.30
T = 150°C
J
T = 125°C
J
T = 25°C
J
3.25
3.20
T = −40°C
J
100
50
3
5
7
9
11 13 15 17 19 21 23 25 27 29
(V)
−50 −30 −10 10 30 50 70 90 110 130 150
V
D
TEMPERATURE (°C)
Figure 24. RON vs. VD Voltage
Figure 25. Undervoltage Shutdown vs.
Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.8
0.7
0.6
0.5
0.4
0.3
0.2
V
R
= 13 V
D
V
R
= 13 V
D
= 13 W
LOAD
= 13 W
LOAD
0.1
0
0.1
0
−50 −30 −10 10 30 50 70 90 110 130 150
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 26. Slew Rate ON vs. Temperature
Figure 27. Slew Rate OFF vs. Temperature
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16
NCV84140
TYPICAL CHARACTERISTICS
16
15
14
13
12
11
10
2.2
V
D
= 13 V
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
V
D
= 13 V
9
8
1.3
1.2
−50 −30 −10 10 30 50 70 90 110 130 150
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 28. Current Limit vs. Temperature
Figure 29. CS_EN Threshold High vs.
Temperature
14.0
1.8
1.7
1.6
1.5
1.4
V
D
= 13 V
13.5
13.0
12.5
12.0
I
= 1 mA
CS_EN
1.3
1.2
1.1
1.0
11.5
11.0
0.9
0.8
−50 −30 −10 10 30 50 70 90 110 130 150
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 30. CS_EN Threshold Low vs.
Temperature
Figure 31. CS_EN Clamp Voltage (Positive) vs.
Temperature
−11.0
−11.5
−12.0
−12.5
−13.0
I
= −1 mA
CS_EN
−13.5
−14.0
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
Figure 32. CS_EN Clamp Voltage (Negative)
vs. Temperature
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17
NCV84140
Table 13. ISO 7637−2: 2011(E) PULSE TEST RESULTS
ISO
Test Severity Levels
7637−2:2011
III
IV
Test Pulse
Delays and Impedance
2 ms, 10 W
# of Pulses or Test Time
Pulse / Burst Rep. Time
1
−112
55
−150
112
500 pulses
500 pulses
1 h
0.5 s
0.5 s
2a
3a
3b
0.05 ms, 2 W
−165
112
−220
150
0.1 ms, 50 W
100 ms
100 ms
0.1 ms, 50 W
1 h
ISO
Test Results
7637−2:2011
III
IV
A
E
A
A
Test Pulse
1
2a
3a
3b
C
Class
Functional Status
All functions of a device perform as designed during and after exposure to disturbance.
A
B
All functions of a device perform as designed during exposure. However, one or more of them can go beyond speci−
fied tolerance. All functions return automatically to within normal limits after exposure is removed. Memory functions
shall remain class A.
C
D
E
One or more functions of a device do not perform as designed during exposure but return automatically to normal op-
eration after exposure is removed.
One or more functions of a device do not perform as designed during exposure and do not return to normal operation
until exposure is removed and the device is reset by simple “operator/use” action.
One or more functions of a device do not perform as designed during and after exposure and cannot be returned to
proper operation without replacing the device.
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18
NCV84140
APPLICATION INFORMATION
+5 V
VD
RμC
ZCS
CS
IN
Output
Clamping
Dld
RμC
ZVD
Micro
Controller
RμC
VBAT
Control
Logic
CS_EN
ZBody
OUT
Cexternal
RCS
ZESD
GND
ZL
RGND
Figure 33. Application Schematic
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19
NCV84140
Loss of Ground Protection
* VD
RGND
When device or ECU ground connection is lost and load
is still connected to ground, the device will turn the output
OFF. In loss of ground state, the output stage is held OFF
independent of the state of the input. Input resistors are
recommended between the device and microcontroller.
* IGND
+
(eq. 1)
Since this resistor can be used amongst multiple
High−Side devices, please take note the sum of the
maximum active GND currents (I
) for each
GND(On)max
device when sizing the resistor. Please note that if the
microprocessor GND is not shared by the device GND, then
Reverse Battery Protection
Solution 1: Resistor in the GND line only
(no parallel Diode)
The following calculations are true for any type of load.
In the case for no diode in parallel with R
calculations below explain how to size the resistor.
Consider the following parameters:
R
GND
produces a shift of (I
× R
) in the input
GND(On)max
GND
thresholds and CS output values. If the calculated power
dissipation leads to too large of a resistor size or several
devices have to share the same resistor, please look at the
second solution for Reverse Battery Protection. Refer to
, the
GND
Figure 35 for selecting the proper R
.
GND
–I
Maximum = 200 mA for up to −V = 32 V.
GND
D
Where –I
is the DC reverse current through the GND
GND
pin and –V is the DC reverse battery voltage.
D
Figure 34. Reverse Battery RGND Considerations
Solution 2: Diode (D
ground line.
A resistor value of R
) in parallel with RGND in the
the input threshold and current sense values if the micro
controller ground is not common to the device ground. This
shift will not vary even in the case of multiple high−side
devices using the same resistor/diode network.
GND
= 1 kOhm should be selected and
if the device drives an inductive
GND
placed in parallel to D
GND
load. The diode (D
) provides a ~600−700 mV shift in
GND
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20
NCV84140
Undervoltage Protection
The device has two under−voltage threshold levels,
and V . Switching function (ON/OFF) requires
remain in ON state. While all protection functions are
guaranteed when the switch is ON, diagnostic functions are
V
D_MIN
UV
supply voltage to be at least V
. The device features a
operational only within nominal supply voltage range V
D_MIN
D.
lower supply threshold V , above which the output can
UV
VOUT
V
UV
V
D_MIN
VD
Figure 35. Undervoltage Behavior
Overvoltage Protection
The NCV84140 has two Zener diodes Z
which provide integrated overvoltage protection. Z
automatic recovery after the supply voltage comes back to
the normal operating range. The specified parameters as
well as short circuit robustness and energy capability cannot
be guaranteed during overvoltage exposure.
and Z
,
VD
CS
VD
protects the logic block by clamping the voltage between
supply pin V and ground pin GND to V . Z limits
D
ZVD CS
Overload Protection
voltage at current sense pin CS to V – V . The output
power MOSFET’s output clamping diodes provide
protection by clamping the voltage across the MOSFET
D
ZCS
Current limitation as well as overtemperature shutdown
mechanisms are integrated into NCV84140 to provide
protection from overload conditions such as bulb inrush or
short to ground.
(between V pin and OUT pin) to V
. During
CLAMP
D
overvoltage protection, current flowing through Z , Z
VD CS
and the output clamp must be limited. Load impedance Z
L
Current Limitation
limits the current in the body diode Z . In order to limit
Body
In case of overload, NCV84140 limits the current in the
output power MOSFET to a safe value. Due to high power
dissipation during current limitation, the device’s junction
temperature increases rapidly. In order to protect the device,
the output driver is shut down by one of the two
overtemperature protection mechanisms. The output current
limit is dependent on the device temperature, and will fold
back once the die reaches thermal shutdown. If the input
remains active during the shutdown, the output power
MOSFET will automatically be re−activated after a
minimum OFF time or when the junction temperature
returns to a safe level.
the current in Z a resistor, R
the GND path. External resistors R and R
(150 W), is required in
VD
GND
limit the
CS
SENSE
current flowing through Z and out of the CS pin into the
CS
micro−controller I/O pin. With RGND, the GND pin voltage
is elevated to V – V
when the supply voltage V rises
D
ZVD
D
above V
. ESD diodes Z
pull up the voltage at logic
ZVD
ESD
pins IN, CS_EN close to the GND pin voltage V – V
.
D
ZVD
External resistors R , and R
are required to limit the
IN
CS_EN
current flowing out of the logic pins into the
micro−controller I/O pins. During overvoltage exposure, the
device transitions into a self−protection state, with
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21
NCV84140
Output Clamping with Inductive Load Switch Off
relative to the supply voltage VBAT. During output clamping
with inductive load switch off, the energy stored in the
inductance is rapidly dissipated in the device resulting in
high power dissipation. This is a stressful condition for the
device and the maximum energy allowed for a given load
inductance should not be exceeded in any application.
The output voltage VOUT drops below GND potential
when switching off inductive loads. This is because the
inductance develops a negative voltage across the load in
response to a decaying current. The integrated clamp of the
device clamps the negative output voltage to a certain level
V
IN
t
t
t
I
OUT
V
OUT
V
BAT
V
CLAMP
V
BAT
− V
CLAMP
Figure 36. Inductive Load Switching
10
V
= 13.5 V
D
T
= 150°C,
JSTART
Single Pulse
R = 0 W
L
T
= 100°C,
JSTART
Repetitive Pulse
T
= 125°C,
JSTART
Repetitive Pulse
1
1
10
100
L (mH)
Figure 37. Maximum Switch−Off Current vs. Load Inductance, VD = 13.5 V, RL = 0 W
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22
NCV84140
Open Load Detection in OFF State
Open load diagnosis in OFF state can be performed by
activating an external resistive pull−up path (R ) to V
currents (designed pull−down resistance, humidity−induced
.
leakage etc) as well as the open load threshold voltage V
have to be taken into account.
PU
BAT
OL
To calculate the pull−up resistance, external leakage
V
BAT
V
D
V
OL_OFF
IN
Z
R
BODY
PU
I
CS_FAULT
OUT
CS
R
R
LEAK
PD
GND
Z
L
R
CS
R
GND
Figure 38. Open Load Detection in Off State
Current Sense in PWM Mode
sense output (Dt
) also needs to be considered. When
CS_High2
When operating in PWM mode, the current sense
functionality can be used, but the timing of the input signal
and the response time of the current sense need to be
considered. When operating in PWM mode, the following
performance is to be expected. The CS_EN pin should be
held high to eliminate any unnecessary delay time to the
V
IN
switches from high to low a delay time (t
) needs
CS_Low1
to be considered. As long as these timing delays are allowed,
the current sense pin can be operated in PWM mode.
EMC Performance
If better EMC performance is needed, connect a C =
1
100 nF, C = C = 10 nF ceramic capacitors to the pins as
2
3
circuit. When V switches from low to high, there will be
IN
close to the device as possible according to Figure 39.
a typical delay (t
) before the current sense responds.
CS_High2
Once this timing delay has passed, the rise time of the current
C
1
V
D
CS_EN
IN
OUT
+
CS
GND
R
L
C
3
C
R
CS
2
Figure 39. EMC Capacitors Placement
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23
NCV84140
PACKAGE AND PCB THERMAL DATA
1000
100
10
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
NCV84140, 8−SOIC, PCB Copper
Area = 2 cm , PCB:80x80x1.6 mm,
FR4, single−layer 1s0p
2
1
0.01
0.1
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
TIME (s)
0.1
1
10
100
1000
Figure 40. Junction to Ambient Transient Thermal Impedance (2 cm2 Cu Area)
100
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
NCV84140, 8−SOIC, PCB Copper
2
Area = 645 mm , PCB:80x80x1.6 mm,
0.1
FR4, four−layer 1s2p
Single Pulse
0.01
0.001
0.000001 0.00001
0.0001
0.001
0.01
TIME (s)
0.1
1
10
100
1000
Figure 41. Junction to Ambient Transient Thermal Impedance (645 mm2 Cu Area)
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24
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
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