NCV8415DTRKG [ONSEMI]
Self-Protected Low Side Driver with In-Rush Current Management;
| 型号： | NCV8415DTRKG |
| 厂家： | 
ONSEMI |
| 描述： | Self-Protected Low Side Driver with In-Rush Current Management |
| 文件： | 总14页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Self-Protected Low Side
Driver with In-Rush Current
Management
NCV8415
The NCV8415 is a three terminal protected Low−Side Smart
Discrete FET. The protection features include Delta Thermal
Shutdown, overcurrent, overtemperature, ESD and integrated
Drain−to−Gate clamping for overvoltage protection. The device also
offers fault indication via the gate pin. This device is suitable for harsh
automotive environments.
www.onsemi.com
V
I MAX
D
(Limited)
DSS
(Clamped)
R
TYP
DS(ON)
42 V
80 mW @ 10 V
11 A
Features
• Short−Circuit Protection with In−Rush Current Management
• Delta Thermal Shutdown
• Thermal Shutdown with Automatic Restart
• Overvoltage Protection
SOT−223
CASE 318E
STYLE 3
DPAK
CASE 369C
STYLE 2
• Integrated Clamp for Overvoltage Protection and Inductive
Switching
MARKING DIAGRAMS
• ESD Protection
• dV/dt Robustness
• Analog Drive Capability (Logic Level Input)
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101 Grade 1
Qualified and PPAP Capable
4
AYW
8415G
G
Pin Marking
Information
1
2
3
• These Devices are Pb−Free and are RoHS Compliant
SOT−223
1 = Gate
2 = Drain
3 = Source
4 = Drain
Typical Applications
1
3
• Switch a Variety of Resistive, Inductive and Capacitive Loads
• Can Replace Electromechanical Relays and Discrete Circuits
AYWW
NCV
8415G
2
4
• Automotive / Industrial
Drain
DPAK
A
Y
= Assembly Location
= Year
Overvoltage
Protection
Gate
Input
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ESD Protection
ORDERING INFORMATION
Temperature
Limit
Current
Limit
Current
Sense
†
Device
Package
Shipping
NCV8415DTRKG
DPAK
2500 /
Source
(Pb−Free)
Tape & Reel
Figure 1. Block Diagram
NCV8415STT1G
NCV8415STT3G
SOT−223
(Pb−Free)
1000 /
Tape & Reel
SOT−223
(Pb−Free)
4000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
January, 2021 − Rev. 0
NCV8415/D
NCV8415
MAXIMUM RATINGS
Rating
Symbol
Value
42
Unit
V
Drain−to−Source Voltage Internally Clamped
Drain−to−Gate Voltage Internally Clamped
Gate−to−Source Voltage
V
DSS
V
42
V
DG
GS
V
14
V
Drain Current − Continuous
I
D
Internally Limited
Total Power Dissipation (SOT−223)
P
D
W
@ T = 25°C (Note 1)
1.29
2.20
A
@ T = 25°C (Note 2)
A
Total Power Dissipation (DPAK)
@ T = 25°C (Note 1)
1.54
2.99
A
@ T = 25°C (Note 2)
A
°C/W
Thermal Resistance (SOT−223)
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Junction−to−Case (Soldering Point)
R
R
R
96.4
56.8
10.6
q
JA
JA
JS
q
q
Thermal Resistance (DPAK)
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Junction−to−Case (Soldering Point)
80.8
41.8
3.2
R
R
R
q
q
q
JA
JA
JS
Single Pulse Inductive Load Switching Energy (L = 10 mH, I
Jstart
= 4.2 A, V = 5 V, R = 25 W,
E
AS
88
mJ
Lpeak
GS
G
T
= 25°C)
Load Dump Voltage (V = 0 and 10 V, R = 10 W) (Note 3)
U *
S
52
V
GS
L
Operating Junction Temperature
T
−40 to 150
−55 to 150
°C
°C
J
Storage Temperature
T
storage
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted onto a 80 × 80 × 1.6 mm single layer FR4 board (100 sq mm, 1 oz. Cu, steady state).
2. Mounted onto a 80 × 80 × 1.6 mm single layer FR4 board (645 sq mm, 1 oz. Cu, steady state).
3. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class C according to ISO16750−1.
ESD ELECTRICAL CHARACTERISTICS (Note 4, 5)
Parameter
Test Condition
Human Body Model (HBM)
Charged Device Model (CDM)
Symbol
Min
4000
1000
Typ
−
Max
−
Unit
Electro−Static Discharge Capability
ESD
V
−
−
4. Not tested in production.
5. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JS−001−2017).
Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes smaller than
2 × 2 mm due to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current
waveform characteristic defined in JEDEC JS−002−2018.
+
I
D
DRAIN
I
G
V
DS
GATE
+
SOURCE
V
GS
−
−
Figure 2. Voltage and Current Convention
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2
NCV8415
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
V
= 0 V, I = 10 mA
42
42
46
44
51
51
(BR)DSS
GS
D
V
V
= 0 V, I = 10 mA, T = 150°C
D J
GS
(Note 6)
Zero Gate Voltage Drain Current
I
mA
V
GS
= 0 V, V = 32 V
−
−
0.6
2.4
2.0
10
DSS
DS
= 0 V, V = 32 V, T = 150°C
GS
DS
(Note 6)
J
Gate Input Current
V
GS
= 5 V, V = 0 V
I
GSS
−
50
70
DS
ON CHARACTERISTICS
Gate Threshold Voltage
V
= V , I = 150 mA
V
GS(th)
1.0
−
1.6
−4.0
80
2.0
−
V
GS
DS
D
Gate Threshold Temperature Coefficient
Static Drain−to−Source On Resistance
V
= V , I = 150 mA (Note 6)
V /T
GS(th) J
mV/°C
mW
GS
DS
D
R
V
= 10 V, I = 1.4 A
−
100
190
DS(ON)
GS
D
V
= 10 V, I = 1.4 A, T = 150°C
−
150
GS
GS
GS
D
J
(Note 6)
V
= 5.0 V, I = 1.4 A
−
−
105
185
120
210
GS
D
V
V
= 5.0 V, I = 1.4 A, T = 150°C
D
J
(Note 6)
V
= 5.0 V, I = 0.5 A
−
−
105
185
120
210
GS
D
= 5.0 V, I = 0.5 A, T = 150°C
D
J
(Note 6)
Source−Drain Forward On Voltage
I
= 7 A, V = 0 V
V
t
−
0.88
1.10
V
S
GS
SD
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Time (10% V to 90% I )
V
= 0 V to 5 V, V = 12 V,
ms
−
−
30
44
35
55
20
90
15
40
−
GS
DD
GS
D
ON
I
D
= 1 A
Turn−Off Time (90% V to 10% I )
t
GS
D
OFF
V
GS
= 0 V to 10 V, V = 12 V,
DD
Turn−On Time (10% V to 90% I )
t
−
13
GS
D
ON
I
D
= 1 A
Turn−Off Time (90% V to 10% I )
t
−
70
GS
D
OFF
Turn−On Rise Time (10% I to 90% I )
t
rise
−
9
D
D
Turn−Off Fall Time (90% I to 10% I )
t
fall
−
29
D
D
V/ms
Slew Rate On (80% V to 50% V
)
−dV /dt
DS ON
0.5
0.4
1.63
0.55
DS
DS
Slew Rate Off (50% V to 80% V
)
dV /dt
DS OFF
−
DS
DS
SELF PROTECTION CHARACTERISTICS
Current Limit
I
A
V
= 5 V, V = 10 V
7.0
6.4
8.8
7.9
11
LIM
GS
DS
V
GS
= 5 V, V = 10 V, T = 150°C
9.1
DS
J
(Note 6)
V
= 10 V, V = 10 V (Note 6)
5.2
5.0
8.2
7.4
11
10
GS
DS
V
= 10 V, V = 10 V, T = 150°C
DS J
GS
(Note 6)
V
= 5.0 V (Note 6)
°C
mA
Temperature Limit (Turn−Off)
Thermal Hysteresis
T
150
−
175
15
185
−
GS
LIM(OFF)
DT
LIM(ON)
V
= 10 V (Note 6)
Temperature Limit (Turn−Off)
Thermal Hysteresis
T
150
−
185
15
200
−
GS
LIM(OFF)
DT
LIM(ON)
GATE INPUT CHARACTERISTICS (Note 6)
Device ON Gate Input Current
I
GON
V
GS
= 5 V, V = 10 V, I = 1 A
35
50
70
DS
D
V
GS
= 10 V, V = 10 V, I = 1 A
250
45
310
76
450
95
DS
D
Current Limit Gate Input Current
Thermal Limit Gate Input Current
I
GCL
V
GS
= 5 V, V = 10 V
DS
V
= 10 V, V = 10 V
320
210
620
450
240
700
550
260
830
GS
DS
I
V
= 5 V, V = 10 V, I = 0 A
DS D
GTL
GS
V
GS
= 10 V, V = 10 V, I = 0 A
DS
D
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Not subject to production testing.
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3
NCV8415
TYPICAL PERFORMANCE CURVES
10
1000
T
= 25°C
J(start)
T
= 25°C
J(start)
100
T
= 150°C
J(start)
T
= 150°C
J(start)
1
10
10
100
10
5
10
100
L (mH)
L (mH)
Figure 3. Single Pulse Maximum Switch−Off
Figure 4. Single Pulse Maximum Switching
Energy vs. Load Inductance
Current vs. Load Inductance
1000
10
T
= 25°C
J(start)
T
= 25°C
J(start)
100
T
= 150°C
J(start)
T
= 150°C
J(start)
1
10
1
1
10
t
(ms)
t
(ms)
av
av
Figure 5. Single Pulse Maximum Inductive
Switch−Off Current vs. Time in Avalanche
Figure 6. Single Pulse Maximum Inductive
Switching Energy vs. Time in Avalanche
12
10
8
10
8
7 V
9 V
V
DS
= 10 V
T = 25°C
6 V
A
6
4 V
3 V
6
8 V
5 V
10 V
4
−40°C
25°C
105°C
150°C
4
2
2
V
= 2.5 V
GS
0
0
0
1
2
3
4
1
1.5
2
2.5
3
3.5
4
4.5
5
V
DS
(V)
V
GS
(V)
Figure 7. On−State Output Characteristics
Figure 8. Transfer Characteristics
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4
NCV8415
TYPICAL PERFORMANCE CURVES
300
250
200
150
100
50
210
190
170
150
150°C, V = 5 V
GS
105°C, V = 5 V
GS
150°C, V = 10 V
GS
130
110
90
150°C, I = 1.4 A
D
105°C, V = 10 V
GS
150°C, I = 0.5 A
D
105°C, I = 1.4 A
D
25°C, V = 5 V
GS
105°C, I = 0.5 A
−40°C, I = 1.4 A
D
D
25°C, V = 10 V
GS
25°C, I = 1.4 A
D
70
−40°C, V = 5 V
GS
25°C, I = 0.5 A
−40°C, V = 10 V
D
GS
−40°C, I = 0.5 A
D
50
3
4
5
6
V
7
(V)
8
9
10
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6
I (A)
D
1.8
2
GS
Figure 9. RDS(ON) vs. Gate−Source Voltage
Figure 10. RDS(ON) vs. Drain Current
2.0
1.75
1.5
12
11.5
11
V
DS
= 10 V
I
D
= 1.4 A
−40°C
10.5
10
25°C
V
GS
= 5 V
1.25
1.0
9.5
9
105°C
150°C
V
= 10 V
GS
8.5
8
0.75
0.5
7.5
7
−40 −20
0
20
40
T (5C)
60
80 100 120 140
5
5.5
6
6.5
7
7.5
(V)
8
8.5
9
9.5 10
V
J
GS
Figure 11. Normalized RDS(ON) vs. Temperature
Figure 12. Current Limit vs. Gate−Source
Voltage
10
9.5
9
100
10
V
DS
= 10 V
V
GS
= 0 V
1
150°C
25°C
V
GS
= 10 V
8.5
8
105°C
0.1
V
GS
= 5 V
0.01
0.001
−40°C
7.5
7
−40 −20
0
20
40
60
80 100 120 140
10
15
20
25
(V)
30
35
40
T (5C)
V
J
DS
Figure 13. Current Limit vs. Junction
Temperature
Figure 14. Drain−to−Source Leakage Current
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5
NCV8415
TYPICAL PERFORMANCE CURVES
1.2
1.1
1
1.1
I
V
= 150 mA
V
= 0 V
D
GS
= V
DS
GS
1
0.9
0.8
0.7
0.6
0.5
−40°C
25°C
0.9
0.8
0.7
0.6
105°C
150°C
1
2
3
4
5
6
7
8
9
10
−40 −20
0
20
40
60
80 100 120 140
T (5C)
I
(A)
J
S
Figure 15. Normalized Threshold Voltage vs.
Temperature
Figure 16. Source−Drain Diode Forward
Characteristics
140
2
V
= 12 V
= 1 A
V
= 12 V
= 1 A
DD
DD
I
D
I
D
120
100
80
60
40
20
0
R
= 0 W
R
= 0 W
G
G
−dV /dt
1.5
1.0
0.5
0
DS ON
t
ON
dV /dt
DS OFF
t
r
t
OFF
t
f
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
V
GS
(V)
V
GS
(V)
Figure 17. Resistive Load Switching Time vs.
Figure 18. Resistive Load Switching
Drain−Source Voltage Slope vs. Gate−Source
Gate−Source Voltage
Voltage
2
1.8
1.6
1.4
1.2
1
80
70
60
V
= 12 V
= 1 A
DD
I
D
−dV /dt , V = 10 V
DS ON
GS
t
, V = 10 V
OFF GS
50
40
30
20
10
0
t
, V = 5 V
OFF GS
dV /dt
, V = 5 V
dV /dt
, V = 10 V
DS OFF GS
DS OFF GS
t
, V = 5 V
ON GS
0.8
0.6
0.4
0.2
0
t , V = 5 V
r
GS
−dV /dt , V = 5 V
DS ON
GS
V
= 12 V
DD
I = 1 A
D
t , V = 10 V
r
GS
t , V = 5 V
f
t , V = 10 V
t
, V = 10 V
GS
f
GS
ON GS
0
500
1000
(W)
1500
2000
0
500
1000
(W)
1500
2000
R
R
G
G
Figure 19. Resistive Load Switching Time vs.
Gate Resistance
Figure 20. Resistive Load Switching
Drain−Source Voltage Slope vs. Gate Resistance
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6
NCV8415
TYPICAL PERFORMANCE CURVES
100
90
80
70
60
50
40
90
80
70
PCB Cu thickness, 1.0 oz
60
50
40
30
PCB Cu thickness, 1.0 oz
PCB Cu thickness, 2.0 oz
PCB Cu thickness, 2.0 oz
0
100 200
300
400
500
600
700
800
0
100
200
300
400
500
600
700 800
2
2
Copper Heat Spreader Area (mm )
Copper Heat Spreader Area (mm )
Figure 21. RqJA vs. Copper Area (SOT−223)
Figure 22. RqJA vs. Copper Area (DPAK)
100
10
50% Duty Cycle
20% Duty Cycle
10% Duty Cycle
5% Duty Cycle
2% Duty Cycle
1
1% Duty Cycle
0.1
0.01
Single Pulse
2
80 × 80 × 1.6 mm Single−Layer PCB, 645 mm 1 oz. Copper
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Width (s)
Figure 23. Transient Thermal Resistance (SOT−223)
100
50% Duty Cycle
20% Duty Cycle
10% Duty Cycle
5% Duty Cycle
10
1
2% Duty Cycle
1% Duty Cycle
0.1
0.01
Single Pulse
2
80 × 80 × 1.6 mm Single−Layer PCB, 645 mm 1 oz. Copper
0.1 10 100
Pulse Width (s)
0.000001
0.00001
0.0001
0.001
0.01
1
1000
Figure 24. Transient Thermal Resistance (DPAK)
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7
NCV8415
APPLICATION INFORMATION
Circuit Protection Features
junction temperature is exceeded. When activated at
typically 175°C, the NCV8415 turns off. This feature is
provided to prevent failures from accidental overheating.
The NCV8415 has three main protections. Current Limit,
Thermal Shutdown and Delta Thermal Shutdown. These
protections establish robustness of the NCV8415.
EMC Performance
Current Limit and Short Circuit Protection
The NCV8415 has current sense element. In the event that
the drain current reaches designed current limit level,
integrated Current Limit protection establishes its constant
level.
To improve the EMC performance/robustness, connect
a small ceramic capacitor to the drain pin as close to the
device as possible according to Figure 25.
R
L
Delta Thermal Shutdown
Delta Thermal Shutdown (DTSD) Protection increases
higher reliability of the NCV8415. DTSD consist of two
independent temperature sensors – cold and hot sensors. The
NCV8415 establishes a slow junction temperature rise by
sensing the difference between the hot and cold sensors.
ON/OFF output cycling is designed with hysteresis that
results in a controlled saw tooth temperature profile
(Figure 26). The die temperature slowly rises (DTSD) until
the absolute temperature shutdown (TSD) is reached around
175°C.
+
Gate
D
V
DD
−
DUT
S
G
C
Thermal Shutdown with Automatic Restart
Internal Thermal Shutdown (TSD) circuitry is provided to
protect the NCV8415 in the event that the maximum
Figure 25. EMC Capacitor Placement
TEST CIRCUITS AND WAVEFORMS
Thermal Transient Limitation Phase
Overtemperature
Cycling
Nominal
Load
V
I
G
I
LIM
D
I
NOM
TSD
Delta TSD
activation
T
J
Time
Figure 26. Overload Protection Behavior
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8
NCV8415
TEST CIRCUITS AND WAVEFORMS
R
L
V
IN
+
D
V
DD
R
G
−
DUT
S
G
I
DS
Figure 27. Resistive Load Switching Test Circuit
90%
V
IN
10%
90%
t
t
OFF
ON
t
r
t
f
I
DS
10%
Time
Figure 28. Resistive Load Switching Waveforms
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9
NCV8415
TEST CIRCUITS AND WAVEFORMS
L
V
DS
V
IN
D
+
R
G
V
DD
−
G DUT
S
t
p
I
DS
Figure 29. Inductive Load Switching Test Circuit
5 V
0 V
V
IN
t
av
t
p
V
(BR)DSS
I
pk
V
DD
V
DS
V
DS(on)
I
0
DS
Time
Figure 30. Inductive Load Switching Waveforms
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. ANODE
STYLE 3:
STYLE 4:
PIN 1. SOURCE
STYLE 5:
PIN 1. DRAIN
PIN 1. GATE
2. DRAIN
2. CATHODE
3. NC
2. DRAIN
3. GATE
4. DRAIN
2. GATE
3. SOURCE
4. DRAIN
3. SOURCE
4. GATE
4. CATHODE
STYLE 6:
PIN 1. RETURN
STYLE 7:
STYLE 8:
STYLE 9:
STYLE 10:
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
CANCELLED
PIN 1. INPUT
2. GROUND
3. LOGIC
PIN 1. CATHODE
2. ANODE
2. INPUT
3. OUTPUT
4. INPUT
3. GATE
4. CATHODE
4. GROUND
4. ANODE
STYLE 11:
PIN 1. MT 1
STYLE 12:
STYLE 13:
PIN 1. INPUT
2. OUTPUT
3. NC
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. MT 2
3. GATE
4. MT 2
4. OUTPUT
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
Y
= Assembly Location
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
4
ISSUE F
2
1
DATE 21 JUL 2015
3
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
A
D
E
C
A
b3
B
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
c2
4
2
L3
Z
DETAIL A
H
1
3
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN MAX
0.086 0.094
A1 0.000 0.005
0.025 0.035
b2 0.028 0.045
b3 0.180 0.215
MILLIMETERS
L4
NOTE 7
MIN
2.18
0.00
0.63
0.72
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
c
b2
e
BOTTOM VIEW
A
SIDE VIEW
b
b
M
0.005 (0.13)
C
TOP VIEW
c
0.018 0.024
c2 0.018 0.024
Z
Z
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
H
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
GAUGE
PLANE
SEATING
PLANE
H
L
L1
L2
0.370 0.410
0.055 0.070
0.114 REF
L2
C
0.020 BSC
L3 0.035 0.050
L
BOTTOM VIEW
A1
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
L1
ALTERNATE
CONSTRUCTIONS
DETAIL A
ROTATED 905 CW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. BASE
STYLE 2:
PIN 1. GATE
2. DRAIN
STYLE 3:
STYLE 4:
STYLE 5:
PIN 1. GATE
PIN 1. ANODE
2. CATHODE
3. ANODE
PIN 1. CATHODE
2. ANODE
2. COLLECTOR
2. ANODE
3. CATHODE
4. ANODE
3. EMITTER
3. SOURCE
4. DRAIN
3. GATE
4. ANODE
XXXXXXG
ALYWW
AYWW
XXX
4. COLLECTOR
4. CATHODE
STYLE 6:
PIN 1. MT1
2. MT2
STYLE 7:
STYLE 8:
STYLE 9:
PIN 1. ANODE
2. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
XXXXXG
PIN 1. GATE
PIN 1. N/C
2. COLLECTOR
2. CATHODE
3. GATE
4. MT2
3. EMITTER
3. ANODE
3. RESISTOR ADJUST
4. CATHODE
3. CATHODE
4. ANODE
4. COLLECTOR
4. CATHODE
IC
Discrete
SOLDERING FOOTPRINT*
XXXXXX = Device Code
A
L
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
6.20
0.244
3.00
0.118
2.58
0.102
*This information is generic. Please refer
to device data sheet for actual part
marking.
5.80
0.228
1.60
0.063
6.17
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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