NCV8502PDWADJR2 [ONSEMI]

Micropower 150 mA LDO Linear Regulators with DELAY, Adjustable RESET, and Monitor FLAG; 微150毫安LDO线性稳压器与延迟,可调复位和监视器标志
NCV8502PDWADJR2
型号: NCV8502PDWADJR2
厂家: ONSEMI    ONSEMI
描述:

Micropower 150 mA LDO Linear Regulators with DELAY, Adjustable RESET, and Monitor FLAG
微150毫安LDO线性稳压器与延迟,可调复位和监视器标志

线性稳压器IC 调节器 电源电路 监视器 光电二极管 输出元件
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NCV8502 Series  
Micropower 150 mA LDO  
Linear Regulators with  
DELAY, Adjustable RESET,  
and Monitor FLAG  
http://onsemi.com  
The NCV8502 is a family of precision micropower voltage  
regulators. Their output current capability is 150 mA. The family has  
output voltage options for adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, and 10 V.  
The output voltage is accurate within ±2.0% with a maximum  
dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature  
drawing only 90 mA with a 100 mA load. This part is ideal for any and  
all battery operated microprocessor equipment.  
SO−8  
D SUFFIX  
CASE 751  
8
1
SOIC 16 LEAD  
Microprocessor control logic includes an active RESET (with  
DELAY), and a FLAG monitor which can be used to provide an early  
warning signal to the microprocessor of a potential impending RESET  
signal. The use of the FLAG monitor allows the microprocessor to  
finish any signal processing before the RESET shuts the  
microprocessor down.  
The active RESET circuit operates correctly at an output voltage as  
low as 1.0 V. The RESET function is activated during the power up  
sequence or during normal operation if the output voltage drops  
outside the regulation limits.  
WIDE BODY  
EXPOSED PAD  
PDW SUFFIX  
CASE 751R  
16  
1
MARKING DIAGRAMS  
SO−8  
SOW−16  
E PAD  
8
1
16  
The reset threshold voltage can be decreased by the connection of  
8502x  
ALYW  
external resistor divider to R  
lead.  
ADJ  
8502x  
AWLYYWW  
The regulator is protected against reverse battery, short circuit, and  
thermal overload conditions. The device can withstand load dump  
transients making it suitable for use in automotive environments. The  
device has also been optimized for EMC conditions.  
1
x
= Voltage Ratings as Indicated Below:  
Features  
A = Adjustable  
2 = 2.5 V  
3 = 3.3 V  
Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, 10 V  
±2.0% Output  
5 = 5.0 V  
Low 90 mA Quiescent Current  
Fixed or Adjustable Output Voltage  
Active RESET  
Adjustable Reset  
150 mA Output Current Capability  
8 = 8.0 V  
1 = 10 V  
= Assembly Location  
A
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
Fault Protection  
ORDERING INFORMATION  
+60 V Peak Transient Voltage  
−15 V Reverse Voltage  
Short Circuit  
See detailed ordering and shipping information in the package  
dimensions section on page 12 of this data sheet.  
Thermal Overload  
Early Warning through FLAG/MON Leads  
NCV Prefix for Automotive and Other Applications Requiring Site  
and Change Control  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
June, 2004 − Rev. 19  
NCV8502/D  
NCV8502 Series  
PIN CONNECTIONS, ADJUSTABLE OUTPUT  
SO−8  
SOW−16 E PAD  
1
8
1
16  
FLAG  
V
IN  
V
OUT  
V
ADJ  
V
NC  
NC  
GND  
NC  
NC  
NC  
NC  
MON  
NC  
V
OUT  
NC  
NC  
NC  
NC  
ADJ  
FLAG  
NC  
GND  
V
IN  
MON  
PIN CONNECTIONS, FIXED OUTPUT  
SO−8  
SOW−16 E PAD  
1
8
1
16  
V
V
OUT  
FLAG  
RESET  
NC  
IN  
V
OUT  
MON  
FLAG  
RESET  
GND  
NC  
NC  
GND  
NC  
R
ADJ  
NC  
NC  
NC  
DELAY  
NC  
V
IN  
DELAY  
MON  
R
ADJ  
V
BAT  
V
IN  
V
R
V
DD  
OUT  
10 mF  
10 mF  
ADJ  
NCV8502  
R
R
RST  
FLG  
10 k  
10 k  
DELAY  
MON  
C
DELAY  
V
ADJ  
(Adjustable  
Output Only)  
RESET  
I/O  
FLAG  
I/O  
GND  
Figure 1. Application Diagram  
Rating  
MAXIMUM RATINGS*  
Value  
−15 to 45  
60  
Unit  
V
V
IN  
(dc)  
Peak Transient Voltage (46 V Load Dump @ V = 14 V)  
V
IN  
Operating Voltage  
45  
V
V
OUT  
(dc)  
16  
V
Voltage Range (RESET, FLAG)  
−0.3 to 10  
V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit  
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,  
damage may occur and reliability may be affected.  
*During the voltage range which exceeds the maximum tested voltage of V , operation is assured, but not specified. Wider limits may apply.  
IN  
Thermal dissipation must be observed closely.  
http://onsemi.com  
2
NCV8502 Series  
MAXIMUM RATINGS* (continued)  
Rating  
Value  
−0.3 to 10  
2.0  
Unit  
V
Input Voltage Range (MON, V  
)
ADJ  
ESD Susceptibility (Human Body Model)  
kV  
°C  
°C  
Junction Temperature, T  
−40 to +150  
−55 to 150  
J
Storage Temperature, T  
S
Package Thermal Resistance, SO−8:  
Junction−to−Case, R  
q
JC  
45  
165  
°C/W  
°C/W  
Junction−to−Ambient, R  
q
JA  
Package Thermal Resistance, SOW−16 E PAD:  
Junction−to−Case, R  
Junction−to−Ambient, R  
15  
56  
35  
°C/W  
°C/W  
°C/W  
q
JC  
q
JA  
Junction−to−Pin, R  
(Note 1)  
q
JP  
240 peak  
(Note 3)  
Lead Temperature Soldering:  
Reflow: (SMD styles only) (Note 2)  
°C  
1. Measured to pin 16.  
2. 60 second maximum above 183°C.  
3. −5°C / +0°C allowable conditions.  
*During the voltage range which exceeds the maximum tested voltage of V , operation is assured, but not specified. Wider limits may apply.  
IN  
Thermal dissipation must be observed closely.  
ELECTRICAL CHARACTERISTICS (I  
= 1.0 mA, −40°C T 125°C; V = dependent on voltage option (Note 4); unless  
OUT  
J
IN  
otherwise specified.)  
Characteristic  
Output Stage  
Test Conditions  
Min  
Typ  
Max  
Unit  
Output Voltage for 2.5 V Option  
Output Voltage for 3.3 V Option  
Output Voltage for 5.0 V Option  
6.5 V < V < 16 V, 100 mA I  
150 mA  
150 mA  
2.450  
2.425  
2.5  
2.5  
2.550  
2.575  
V
V
IN  
OUT  
OUT  
5.5 V < V < 26 V, 100 mA I  
IN  
7.3 V < V < 16 V, 100 mA I  
150 mA  
150 mA  
3.234  
3.201  
3.3  
3.3  
3.366  
3.399  
V
V
IN  
OUT  
OUT  
5.5 V < V < 26 V, 100 mA I  
IN  
9.0 V < V < 16 V, 100 mA I  
150 mA  
150 mA  
4.90  
4.85  
5.0  
5.0  
5.10  
5.15  
V
V
IN  
OUT  
OUT  
6.0 V < V < 26 V, 100 mA I  
IN  
Output Voltage for 8.0 V Option  
Output Voltage for 10 V Option  
9.0 V < V < 26 V, 100 mA I  
150 mA  
150 mA  
7.76  
9.7  
8.0  
10  
8.24  
10.3  
V
IN  
OUT  
11 V < V < 26 V, 100 mA I  
V
V
IN  
OUT  
Output Voltage for Adjustable  
Option  
V
= V  
(Unity Gain)  
OUT  
ADJ  
6.5 V < V < 16 V, 100 mA < I  
5.5 V < V < 26 V, 100 mA < I  
< 150 mA  
< 150 mA  
1.254  
1.242  
1.280  
1.280  
1.306  
1.318  
V
V
IN  
OUT  
IN  
OUT  
Dropout Voltage (V − V  
(5.0 V, 8.0 V, 10 V and  
)
I
I
= 150 mA  
= 1.0 mA  
400  
100  
600  
150  
mV  
mV  
IN  
OUT  
OUT  
OUT  
Adj. > 5.0 V Options Only)  
Load Regulation  
V
= 14 V, 5.0 mA I  
150 mA  
−30  
5.0  
15  
30  
60  
mV  
mV  
IN  
OUT  
Line Regulation  
[V  
(Typ) + 1.0] < V < 26 V, I  
OUT  
= 1.0 mA  
IN  
OUT  
Quiescent Current, Low Load  
2.5 V Option  
3.3 V Option  
5.0 V Option  
8.0 V Option  
I
= 100 mA, V = 12 V, MON = V  
OUT IN OUT  
90  
90  
125  
125  
125  
150  
150  
75  
mA  
mA  
mA  
mA  
mA  
mA  
90  
100  
100  
50  
10 V Option  
Adjustable Option  
Quiescent Current, Medium Load  
All Options  
I
= 75 mA, V = 14 V, MON = V  
OUT  
4.0  
6.0  
19  
mA  
mA  
mA  
OUT  
IN  
Quiescent Current, High Load  
All Options  
I
= 150 mA, V = 14 V, MON = V  
12  
OUT  
IN  
OUT  
Current Limit  
151  
300  
4. Voltage range specified in Output Stage of the Electrical Characteristics in boldface type.  
http://onsemi.com  
3
 
NCV8502 Series  
ELECTRICAL CHARACTERISTICS (continued) (I  
= 1.0 mA; −40°C T 150°C; V = dependent on voltage option (Note 5);  
OUT  
J
IN  
unless otherwise specified.)  
Characteristic  
Output Stage  
Test Conditions  
Min  
Typ  
Max  
Unit  
Short Circuit Output Current  
Thermal Shutdown  
V
= 0 V  
40  
190  
180  
mA  
OUT  
(Guaranteed by Design)  
150  
°C  
Reset Function (RESET)  
RESET Threshold for 2.5 V Option  
5.5 V V 26 V (Note 6)  
IN  
HIGH (V  
)
V
OUT  
V
OUT  
Increasing  
Decreasing  
2.28  
2.25  
2.350  
2.300  
0.98 × V  
0.97 × V  
V
V
RH  
)
OUT  
LOW (V  
RL  
OUT  
RESET Threshold for 3.3 V Option  
HIGH (V  
5.5 V V 26 V (Note 6)  
IN  
)
V
OUT  
V
OUT  
Increasing  
Decreasing  
3.00  
2.97  
3.102  
3.036  
0.98 × V  
0.97 × V  
V
V
RH  
OUT  
LOW (V  
)
RL  
OUT  
RESET Threshold for 5.0 V Option  
HIGH (V  
)
V
OUT  
V
OUT  
Increasing  
Decreasing  
4.55  
4.50  
4.70  
4.60  
0.98 × V  
0.97 × V  
V
V
RH  
OUT  
LOW (V  
)
RL  
OUT  
RESET Threshold for 8.0 V Option  
HIGH (V  
)
V
OUT  
V
OUT  
Increasing  
Decreasing  
6.86  
6.80  
7.52  
7.36  
0.98 × V  
0.97 × V  
V
V
RH  
OUT  
LOW (V  
)
RL  
OUT  
RESET Threshold for 10 V Option  
HIGH (V  
)
V
OUT  
V
OUT  
Increasing  
Decreasing  
8.60  
8.50  
9.40  
9.20  
0.98 × V  
0.97 × V  
V
V
RH  
OUT  
LOW (V  
)
RL  
OUT  
Output Voltage  
Low (V  
)
1.0 V V  
V , R  
= 10 k  
1.4  
0.1  
1.8  
0.4  
2.2  
0.1  
3.5  
V
V
RLO  
OUT  
RL  
RESET  
DELAY Switching Threshold (V  
DELAY Low Voltage  
)
DT  
V
OUT  
< RESET Threshold Low(min)  
V
DELAY Charge Current  
DELAY = 1.0 V, V  
DELAY = 1.0 V, V  
> V  
1.5  
5.0  
1.23  
2.5  
mA  
mA  
V
OUT  
OUT  
RH  
DELAY Discharge Current  
= 1.5 V  
Reset Adjust Switching Voltage  
1.31  
1.39  
(V  
R(ADJ)  
)
FLAG/Monitor  
Monitor Threshold  
Hysteresis  
Increasing and Decreasing  
1.10  
20  
1.20  
50  
1.31  
100  
0.5  
V
mV  
mA  
V
Input Current  
MON = 2.0 V  
−0.5  
0.1  
0.1  
Output Saturation Voltage  
MON = 0 V, I  
= 1.0 mA  
0.4  
FLAG  
Voltage Adjust (Adjustable Output only)  
Input Current  
5. Voltage range specified in Output Stage of the Electrical Characteristics in boldface type.  
V
ADJ  
= 1.28 V  
−0.5  
0.5  
mA  
6. For V 5.5 V, a RESET = Low may occur with the output in regulation.  
IN  
http://onsemi.com  
4
 
NCV8502 Series  
PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT  
Package Pin Number  
SOW−16  
E PAD  
SO−8  
1
Pin Symbol  
Function  
7
8
V
IN  
Input Voltage.  
2
MON  
NC  
Monitor. Input for early warning comparator. If not needed connect to V  
No connection.  
OUT.  
3, 4  
3−6, 9−12,  
14, 15  
5
6
7
8
13  
16  
1
GND  
Ground. All GND leads must be connected to Ground  
Open collector output from early warning comparator.  
.
FLAG  
V
ADJ  
Voltage Adjust. A resistor divider from V  
to this lead sets the output voltage.  
OUT  
2
V
OUT  
±2.0%, 150 mA output.  
PACKAGE PIN DESCRIPTION, FIXED OUTPUT  
Package Pin Number  
SOW−16  
E PAD  
SO−8  
Pin Symbol  
Function  
1
2
3
4
5
6
7
8
7
8
V
Input Voltage.  
IN  
MON  
Monitor. Input for early warning comparator. If not needed connect to V  
Reset Adjust. If not needed connect to ground.  
Timing capacitor for RESET function.  
OUT.  
9
R
ADJ  
10  
13  
16  
1
DELAY  
GND  
Ground. All GND leads must be connected to Ground  
.
RESET  
FLAG  
Active reset (accurate to V  
1.0 V)  
OUT  
Open collector output from early warning comparator.  
±2.0%, 150 mA output.  
2
V
OUT  
3−6, 11, 12,  
14, 15  
NC  
No connection.  
http://onsemi.com  
5
NCV8502 Series  
TYPICAL PERFORMANCE CHARACTERISTICS  
5.01  
5.00  
4.99  
4.98  
3.35  
V
V
= 3.3 V  
= 14 V  
= 5.0 mA  
OUT  
V
V
= 5.0 V  
= 14 V  
= 5.0 mA  
OUT  
3.34  
3.33  
3.32  
3.31  
3.30  
3.29  
3.28  
3.27  
IN  
IN  
I
OUT  
I
OUT  
−40 −25 −10  
5
20 35 50 65 80 95 110 125  
−40 −25 −10  
5
20 35 50 65 80 95 110 125  
Temperature (°C)  
Temperature (°C)  
Figure 2. Output Voltage vs. Temperature  
Figure 3. Output Voltage vs. Temperature  
1.2  
14  
12  
10  
8
V
= 12 V  
V
IN  
= 12 V  
IN  
1.0  
0.8  
0.6  
0.4  
0.2  
0
+125°C  
+125°C  
+25°C  
+25°C  
−40°C  
6
−40°C  
4
2
0
0
5
10  
I
15  
(mA)  
20  
25  
0
15 30 45 60 75 90 105 120 135 140  
(mA)  
I
OUT  
OUT  
Figure 4. Quiescent Current vs. Output Current  
Figure 5. Quiescent Current vs. Output Current  
7
120  
T = 25°C  
T = 25°C  
6
100  
80  
60  
49  
20  
0
I
= 100 mA  
OUT  
I
= 100 mA  
OUT  
5
4
3
2
1
0
I
I
= 50 mA  
= 10 mA  
OUT  
OUT  
6
8
10 12 14 16 18 20 22 24 26  
(V)  
6
8
10 12 14 16 18 20 22 24 26  
(V)  
V
V
IN  
IN  
Figure 6. Quiescent Current vs. Input Voltage  
Figure 7. Quiescent Current vs. Input Voltage  
http://onsemi.com  
6
NCV8502 Series  
TYPICAL PERFORMANCE CHARACTERISTICS  
450  
400  
350  
300  
250  
200  
150  
100  
50  
1000  
Unstable Region  
100  
10 V  
+125°C  
8 V  
10  
1.0  
+25°C  
5 V  
−40°C  
2.5 V  
3.3 V  
Stable Region  
0.1  
V
OUT  
= 5.0 V, 8.0 V, or 10 V  
C
= 10 mF  
VOUT  
0.01  
0
0
25  
50  
75  
100  
125  
150  
0
10  
20 30 40 50 60 70 80 90 100  
OUTPUT CURRENT (mA)  
I
(mA)  
OUT  
Figure 8. Dropout Voltage vs. Output Current  
Figure 9. Output Stability with Output  
Voltage Change  
1000  
C
= 10 mF  
Unstable Region  
Vout  
100  
10  
C
= 0.1 mF  
Vout  
1.0  
Stable Region  
0.1  
0.01  
0
10 20 30 40 50 60 70 80 90 100 110  
OUTPUT CURRENT (mA)  
Figure 10. Output Stability with Output  
Capacitor Change  
http://onsemi.com  
7
NCV8502 Series  
V
OUT  
V
IN  
Current Source  
(Circuit Bias)  
I
BIAS  
Current Limit  
Sense  
+
+
R
ADJ  
I
BIAS  
+
V
BG  
Error Amplifier  
V
BG  
RESET  
+
Fixed Voltage only  
1.8 V  
Thermal  
Protection  
3.0 mA  
V
ADJ  
Bandgap  
Reference  
20 k  
Adjustable  
Version only  
Delay  
MON  
I
V
BG  
BIAS  
GND  
V
BG  
I
BIAS  
FLAG  
+
Figure 11. Block Diagram  
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8
NCV8502 Series  
CIRCUIT DESCRIPTION  
REGULATOR CONTROL FUNCTIONS  
The NCV8502 contains the microprocessor compatible  
control function RESET (Figure 12).  
1. During Power Up (once the regulation threshold  
has been verified).  
2. After a reset event has occurred and the device is  
back in regulation. The DELAY capacitor is  
discharged when the regulation (RESET threshold)  
has been violated. This is a latched incident. The  
capacitor will fully discharge and wait for the  
device to regulate before going through the delay  
time event again.  
V
IN  
RESET  
V
OUT  
Threshold  
DELAY  
RESET  
DELAY  
Threshold  
FLAG/Monitor Function  
An on−chip comparator is provided to perform an early  
warning to the microprocessor of a possible reset signal. The  
reset signal typically turns the microprocessor off  
instantaneously. This can cause unpredictable results with  
the microprocessor. The signal received from the FLAG pin  
will allow the microprocessor time to complete its present  
task before shutting down. This function is performed by a  
comparator referenced to the bandgap reference. The actual  
trip point can be programmed externally using a resistor  
divider to the input monitor (MON) (Figure 14). The typical  
threshold is 1.20 V on the MON pin.  
(V  
)
DT  
T
T
d
d
Figure 12. Reset and Delay Circuit Wave Forms  
RESET Function  
A RESET signal (low voltage) is generated as the IC  
powers up until V is within 6.0% of the regulated output  
voltage, or when V  
than 8.0% below the regulated output voltage. Hysteresis is  
included in the function to minimize oscillations.  
OUT  
drops out of regulation,and is lower  
OUT  
The RESET output is an open collector NPN transistor,  
controlled by a low voltage detection circuit. The circuit is  
functionally independent of the rest of the IC thereby  
V
BAT  
V
OUT  
V
V
CC  
IN  
mP  
NCV8502  
C
OUT  
guaranteeing that the RESET signal is valid for V  
as 1.0 V.  
as low  
OUT  
I/O  
MON  
FLAG  
Adjustable Reset Function  
The reset threshold can be made lower by connecting an  
external resistor divider to the R lead from the V  
R
RESET  
ADJ  
RESET  
GND  
DELAY  
ADJ  
OUT  
lead, as displayed in Figure 13. This lead is grounded to  
select the default value of 4.6 V.  
Figure 14. FLAG/Monitor Function  
Voltage Adjust  
to mP and  
System  
Power  
Figure 15 shows the device setup for a user configurable  
output voltage. The feedback to the V pin is taken from  
ADJ  
V
R
OUT  
ADJ  
a voltage divider referenced to the output voltage. The loop  
is balanced around the Unity Gain threshold (1.28 V  
typical).  
NCV8502  
C
OUT  
R
RST  
RESET  
5.0 V  
DELAY  
to mP and  
RESET  
Port  
V
OUT  
C
OUT  
15 k  
NCV8502  
C
DELAY  
V
ADJ  
1.28 V  
5.1 k  
Figure 13. Adjustable RESET  
DELAY Function  
The reset delay circuit provides a programmable (by  
external capacitor) delay on the RESET output lead.  
The DELAY lead provides source current (typically 2.5 mA)  
to the external DELAY capacitor during the following  
proceedings:  
Figure 15. Adjustable Output Voltage  
http://onsemi.com  
9
 
NCV8502 Series  
APPLICATION NOTES  
V
IN  
V
OUT  
C
0.1 mF  
*
IN  
C
10 mF  
**  
NCV8502  
OUT  
R
NCV8502  
RST  
MJD31C  
V
IN  
V
OUT  
RESET  
5.0 V  
>1 Amp  
V
ADJ  
R1  
294 k  
C2  
0.1 mF  
V
BAT  
C1  
47 mF  
*C required if regulator is located far from the power supply filter  
IN  
R2  
100 k  
**C  
required for stability. Capacitor must operate at minimum  
temperature expected  
OUT  
Figure 18. Test and Application Circuit Showing  
Output Compensation  
Figure 16. Additional Output Current  
Adding Capability  
Figure 16 shows how the adjustable version of parts can  
be used with an external pass transistor for additional current  
capability. The setup as shown will provide greater than 1  
Amp of output current.  
SETTING THE DELAY TIME  
The delay time is controlled by the Reset Delay Low  
Voltage, Delay Switching Threshold, and the Delay Charge  
Current. The delay follows the equation:  
[
C
+
]
(V * Reset Delay Low Voltage)  
DELAY dt  
t
DELAY  
Delay Charge Current  
Example:  
Using C  
Assume reset Delay Low Voltage = 0.  
Use the typical value for V = 1.8 V.  
FLAG MONITOR  
Figure 17 shows the FLAG Monitor waveforms as a result  
of the circuit depicted in Figure 14. As the output voltage  
), the Monitor threshold is crossed. This causes  
the voltage on the FLAG output to go low sending a warning  
signal to the microprocessor that a RESET signal may occur  
= 33 nF.  
DELAY  
dt  
falls (V  
OUT  
Use the typical value for Delay Charge Current = 2.5 mA.  
[
]
33 nF(1.8 * 0)  
t
+
+ 23.8 ms  
DELAY  
2.5 mA  
in a short period of time. T  
is the time the  
WARNING  
microprocessor has to complete the function it is currently  
working on and get ready for the RESET shutdown signal.  
STABILITY CONSIDERATIONS  
The output or compensation capacitor helps determine  
three main characteristics of a linear regulator: start−up  
delay, load transient response and loop stability.  
V
OUT  
The capacitor value and type should be based on cost,  
availability, size and temperature constraints. A tantalum or  
aluminum electrolytic capacitor is best, since a film or  
ceramic capacitor with almost zero ESR can cause  
instability. The aluminum electrolytic capacitor is the least  
expensive solution, but, if the circuit operates at low  
temperatures (−25°C to −40°C), both the value and ESR of  
the capacitor will vary considerably. The capacitor  
manufacturers data sheet usually provides this information.  
MON  
FLAG Monitor  
Ref. Voltage  
RESET  
FLAG  
The value for the output capacitor C  
shown in Figure 18  
OUT  
should work for most applications, however it is not  
necessarily the optimized solution.  
T
WARNING  
Figure 17. FLAG Monitor Circuit Waveform  
http://onsemi.com  
10  
 
NCV8502 Series  
100  
CALCULATING POWER DISSIPATION IN A  
SINGLE OUTPUT LINEAR REGULATOR  
The maximum power dissipation for a single output  
regulator (Figure 19) is:  
90  
80  
70  
60  
P
+ [V  
* V  
]I  
OUT(min) OUT(max)  
D(max)  
IN(max)  
(eq. 1)  
) V  
I
IN(max) Q  
where:  
V
V
I
is the maximum input voltage,  
is the minimum output voltage,  
is the maximum output current for the  
IN(max)  
OUT(min)  
OUT(max)  
50  
40  
application, and  
0
200  
400  
Copper Area (mm )  
600  
800  
I
I
is the quiescent current the regulator consumes at  
Q
2
.
OUT(max)  
Once the value of P  
is known, the maximum  
can be calculated:  
D(max)  
Figure 20. 16 Lead SOW (Exposed Pad), qJA as a  
Function of the Pad Copper Area (2 oz. Cu  
Thickness), Board Material = 0.0625, G−10/R−4  
permissible value of R  
qJA  
T
150°C *  
A
(eq. 2)  
R
+
QJA  
P
D
The value of R  
can then be compared with those in the  
qJA  
package section of the data sheet. Those packages with  
’s less than the calculated value in equation 2 will keep  
the die temperature below 150°C.  
In some cases, none of the packages will be sufficient to  
dissipate the heat generated by the IC, and an external  
heatsink will be required.  
HEAT SINKS  
R
qJA  
A heat sink effectively increases the surface area of the  
package to improve the flow of heat away from the IC and  
into the surrounding air.  
Each material in the heat flow path between the IC and the  
outside environment will have a thermal resistance. Like  
series electrical resistances, these resistances are summed to  
I
I
IN  
OUT  
determine the value of R  
:
qJA  
SMART  
REGULATOR  
V
IN  
V
OUT  
(eq. 3)  
R
+ R  
) R  
) R  
qCS qSA  
qJA  
qJC  
where:  
Control  
R
qJC  
R
qCS  
R
qSA  
= the junction−to−case thermal resistance,  
= the case−to−heatsink thermal resistance, and  
= the heatsink−to−ambient thermal resistance.  
}
Features  
I
Q
R
appears in the package section of the data sheet. Like  
qJC  
Figure 19. Single Output Regulator with Key  
Performance Parameters Labeled  
R
, it too is a function of package type. R  
and R  
are  
qJA  
qCS  
qSA  
functions of the package type, heatsink and the interface  
between them. These values appear in heat sink data sheets  
of heat sink manufacturers.  
http://onsemi.com  
11  
 
NCV8502 Series  
ORDERING INFORMATION  
Device  
Output Voltage  
Package  
Shipping  
NCV8502DADJ  
98 Units/Rail  
SO−8  
SOW−16 Exposed Pad  
SO−8  
NCV8502DADJR2  
NCV8502PDWADJ  
NCV8502PDWADJR2  
NCV8502D25  
2500 Tape & Reel  
47 Units/Rail  
Adjustable  
1000 Tape & Reel  
98 Units/Rail  
NCV8502D25R2  
NCV8502PDW25  
NCV8502PDW25R2  
NCV8502D33  
2500 Tape & Reel  
47 Units/Rail  
2.5 V  
3.3 V  
5.0 V  
8.0 V  
10 V  
SOW−16 Exposed Pad  
SO−8  
1000 Tape & Reel  
98 Units/Rail  
NCV8502D33R2  
NCV8502PDW33  
NCV8502PDW33R2  
NCV8502D50  
2500 Tape & Reel  
47 Units/Rail  
SOW−16 Exposed Pad  
SO−8  
1000 Tape & Reel  
98 Units/Rail  
NCV8502D50R2  
NCV8502PDW50  
NCV8502PDW50R2  
NCV8502D80  
2500 Tape & Reel  
47 Units/Rail  
SOW−16 Exposed Pad  
SO−8  
1000 Tape & Reel  
98 Units/Rail  
NCV8502D80R2  
NCV8502PDW80  
NCV8502PDW80R2  
NCV8502D100  
2500 Tape & Reel  
47 Units/Rail  
SOW−16 Exposed Pad  
SO−8  
1000 Tape & Reel  
98 Units/Rail  
NCV8502D100R2  
NCV8502PDW100  
NCV8502PDW100R2  
2500 Tape & Reel  
47 Units/Rail  
SOW−16 Exposed Pad  
1000 Tape & Reel  
http://onsemi.com  
12  
NCV8502 Series  
PACKAGE DIMENSIONS  
SO−8 NB  
D SUFFIX  
CASE 751−07  
ISSUE AB  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
−X−  
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.127 (0.005) TOTAL  
IN EXCESS OF THE D DIMENSION AT  
MAXIMUM MATERIAL CONDITION.  
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW  
STANDARD IS 751−07.  
S
M
M
B
0.25 (0.010)  
Y
1
K
−Y−  
G
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN  
MAX  
0.197  
0.157  
0.069  
0.020  
A
B
C
D
G
H
J
K
M
N
S
4.80  
3.80  
1.35  
0.33  
5.00 0.189  
4.00 0.150  
1.75 0.053  
0.51 0.013  
C
N X 45  
_
SEATING  
PLANE  
−Z−  
1.27 BSC  
0.050 BSC  
0.10 (0.004)  
0.10  
0.19  
0.40  
0
0.25 0.004  
0.25 0.007  
1.27 0.016  
0.010  
0.010  
0.050  
8
0.020  
0.244  
M
J
H
D
8
0
_
_
_
_
0.25  
5.80  
0.50 0.010  
6.20 0.228  
M
S
S
X
0.25 (0.010)  
Z
Y
http://onsemi.com  
13  
NCV8502 Series  
PACKAGE DIMENSIONS  
SOIC 16 LEAD WIDE BODY  
EXPOSED PAD  
PDW SUFFIX  
CASE 751R−02  
ISSUE A  
−U−  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
A
M
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A AND B DO NOT INCLUDE MOLD  
PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER  
SIDE.  
16  
1
9
P
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE  
0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION  
AT MAXIMUM MATERIAL CONDITION.  
6. 751R−01 OBSOLETE, NEW STANDARD 751R−02.  
B
M
M
W
0.25 (0.010)  
R x 45  
_
8
−W−  
MILLIMETERS  
INCHES  
MIN  
G
14 PL  
DIM MIN  
MAX  
10.45  
7.60  
2.65  
0.49  
0.90  
MAX  
0.411  
0.299  
0.104  
0.019  
0.035  
PIN 1 I.D.  
DETAIL E  
A
B
C
D
F
10.15  
7.40  
2.35  
0.35  
0.50  
0.400  
0.292  
0.093  
0.014  
0.020  
TOP SIDE  
G
H
J
1.27 BSC  
0.050 BSC  
3.76  
0.25  
0.10  
4.58  
0
3.86  
0.32  
0.25  
4.78  
7
0.148  
0.010  
0.004  
0.180  
0
0.152  
0.012  
0.009  
0.188  
7
K
L
C
M
P
R
_
_
_
_
F
−T−  
10.05  
0.25  
10.55  
0.75  
0.395  
0.010  
0.415  
0.029  
0.10 (0.004)  
T
SEATING  
PLANE  
K
D16 PL  
M
S
S
0.25 (0.010)  
T
U
W
J
DETAIL E  
H
1
8
9
EXPOSED PAD  
L
16  
BACK SIDE  
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
ON Semiconductor Website: http://onsemi.com  
Order Literature: http://www.onsemi.com/litorder  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada  
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
Japan: ON Semiconductor, Japan Customer Focus Center  
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051  
Phone: 81−3−5773−3850  
For additional information, please contact your  
local Sales Representative.  
NCV8502/D  

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