NCV91300MNWBTXG [ONSEMI]
Configurable 3.0 A PWM step down converter;
| 型号： | NCV91300MNWBTXG |
| 厂家： | 
ONSEMI |
| 描述： | Configurable 3.0 A PWM step down converter |
| 文件： | 总40页 (文件大小：2196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Configurable 3.0 A PWM
Step Down Converter
NCV91300
The NCV91300 is a synchronous PWM buck converter optimized
to supply the different sub systems of automotive applications post
regulation system from 2.0 V up to 5 V input. The device is able to
deliver up to 3.0 A, with programmable output voltage from 0.6 V to
3.3 V. Operation at up to 2.15 MHz switching frequency allows the
use of small components. Synchronous rectification and automatic
PFM−PWM transitions improve overall solution efficiency. The
NCV91300 is housed in low profile 3.0 x 3.0 mm QFNW−16 package.
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Features
QFNW16 3x3, 0.5P
CASE 484AL
• Power Input Voltage Range from 1.9 V to 5.5 V
• Analog Input Voltage Range from 3.0 V to 5.5 V
• Power Capability: 3.0 A at T = 105°C (R
• Programmable Output Voltage: 0.6 V to 3.3 V in 5 mV, 10 mV and
20 mV Steps
MARKING DIAGRAM
= 40°C/W)
A
qJA
91300
XX
ALYW
G
• Up to 2.15 MHz Switching Frequency with On Chip Oscillator
• Spread Spectrum or Sync Input Pin for EMI Optimization
91300 = Specific Device Code
• Uses 1.0 mH Inductor and at Least 20 mF Capacitors for Optimized
XX
= 2 Fixed Characters Corresponding to the OPN
Footprint and Solution Thickness
• W3 = NCV91300MNWBTXG (V
= Assembly Location
= Wafer Lot
1.1 V)
OUT
A
L
Y
W
G
• PFM/PWM Operation for Optimum Efficiency
• Low 65 mA Quiescent Current
= Year
2
• I C Control Interface with Interrupt and Dynamic Voltage Scaling
= Work Week
= Pb−Free Package
Support
• Enable Pin, Power Good / Interrupt Signaling
• Thermal Protections and Temperature Management
• 3.0 x 3.0 mm / 0.5 mm pitch QFN 16 package
• These are Pb−Free Devices
PIN ASSIGNMENT
Typical Applications
• Automotive Point Of Load (POL)
• Automotive Telematics Clusters – Camera
• Automotive Infotainment − Instrumentation
• Automotive Advanced Driver−Assistance System (ADAS)
♦ Front Camera – Rear View Camera
♦ Surround View
♦ Blind Spot Monitoring
♦ Radar
• Automotive Space−Optimized systems
(Top View)
16 Pins 0.50 mm pitch QFN
ORDERING INFORMATION
See detailed ordering and shipping information on page 37 of
this data sheet.
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
March, 2021 − Rev. 0
NCV91300/D
NCV91300
NCV91300
Supply Input
AVIN
PVIN
BOOT
SW
Power Supply Input
4.7 mF
Core
AGND
10 mF
10 nF
DCDC
3.0 A
Thermal
Protection
Modular
Driver
1.0 mH
2x 10 mF
EN
Enable Control
Input
Enabling
Test / I@C
Clocking
SCL
SDA
PGND
FB
I@C BUS
SYNC
Output
DCDC
External Clock
Power Good
Processor
Core
PG
Monitoring
2.15 MHz
Controller
Sense
INTB
Interrupt
Interrupt
Figure 1. Typical Application Circuit
FUNCTIONAL BLOCK DIAGRAM
BOOTSTRAP
BOOT
PVIN
PVIN
POWER INPUT
SUPPLY INPUT
AVIN
Core
AGND
ANALOG GROUND
3.0 A
DC−DC
SW
SW
SWITCH NODE
Thermal
Protection
Output Voltage
Monitoring
Operating
Up to 2.15 MHz
Mode Control
DC−DC converter
Clocking
PGND
PGND
ENABLE CONTROL INPUT
SYNC INPUT
EN
POWER GROUND
SYNC
Controller
PG
INTB
SCL
SDA
Monitoring
Interrupt
I C
2
PROCESSOR I C
VOUT
CONTROL INTERFACE
FEEDBACK
Sense
2
Figure 2. Simplified Block Diagram
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2
NCV91300
PIN OUT DESCRIPTION
Figure 3. Pin Out (Top View)
PIN FUNCTION DESCRIPTION
Pin
Name
Type
Description
13
AVIN
Analog Input
Analog Supply. This pin is the device analog and digital supply. Could be connected directly to the
VIN plane with a dedicated 4.7 mF decoupling ceramic capacitor
14
6
AGND
INTB
EN
Analog Ground Analog Ground. Analog and digital modules ground. Must be connected to the system ground.
Digital Output Interrupt open drain output. Must be connected to the ground plane if not used.
7
Digital Input
Enable Control. Active high will enable the part. There is an internal pull down resistor on this pin.
9
PG
Digital Output Power Good open drain output. Must be connected to the ground plane if not used.
2
10
SCL
Digital Input
I C interface Clock line. There is an internal pull down resistor on this pin; could be connected to
the ground plane if not used.
2
11
SDA
Digital
Input Output
I C interface Bi−directional Data line. There is an internal pull down resistor on this pin; could be
connected to the ground plane if not used.
12
SYNC
PVIN
Digital Input
Power Input
External synchronization Input.
1, 16
Power Supply. These pins must be decoupled to ground by a 10 mF ceramic capacitor. It should be
placed as close as possible to these pins. All pins must be used with short and large enough
connections.
2, 3
4, 5
SW
Power Output Switch Node. These pins drive power to the inductor. Typical application uses 1.0 mH inductor; refer
to application section for more information.
All pins must be used with short and large enough connections.
PGND
Power Ground Switch Ground. This pin is the power ground and carries the high switching current. High quality
ground must be provided to prevent noise spikes. To avoid high−density current flow in a limited
PCB track, a local ground plane that connects all PGND pins together is recommended. Analog
and power grounds should only be connected together in one location with a trace.
8
FB
Analog Input
Feedback Voltage Input. Must be connected to the output capacitor positive terminal with a trace,
not to a plane. This is the positive input to the error amplifier.
15
BOOT
Analog
Input Output
Bootstrap pin for optimizing output stage R
. Connect a 10 nF capacitor between BOOST
DSON
and SW.
THERMAL Analog Ground Exposed Thermal Pad. Must be soldered to system Ground plane to achieve power dissipation
PAD
performances. This pin is internally connected to the analog ground.
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3
NCV91300
MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
−0.3
−0.3
−0.3
Typ
−
Max
6.0
6.0
7.5
Unit
V
V
A−DC
Analog Pins DC Non Switching: AVIN, PG, INTB, FB (Note 1)
Power Pin DC Non Switching: PVIN, SW (Note 1)
Between PVIN−PGND Pins, Transient 3 ns – 2.15 MHz (Note 1)
BOOT Pin: Between BOOT−SW (Note 1)
V
P−DC
−
V
V
P−TR
−
V
V
BOOT
−
V
+
V
A−DC
0.3 ≤ 6.0
2
V
V
I C Pins: SDA, SCL
−0.3
−0.3
2000
−
−
−
−
−
V
V
V
V
V
I2C
A−DC
Digital Pins Input Voltage: EN, SYNC
V
A−DC
DG
HBM
Human Body Model (HBM) ESD Rating (Note 2)
−
−
CDMc
Charged Device Model (CDM) ESD Rating for Corner Pins (Not Applica-
ble with this Package) (Note 2)
CDMo
Charged Device Model (CDM) ESD Rating for All Other Pins (Applicable
to All Pin with this Package) (Note 2)
500
−
−
V
I
Latch Up Current (Note 3)
Storage Temperature Range
Junction Temperature Range
Moisture Sensitivity (Note 4)
−
100
−
mA
°C
LU
T
STG
−65
−40
−
−
−
150
T
T
SD
°C
JMAX
MSL
Level1
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM) 2 kV per ANSI/ESDA/JEDEC JS−001 standard.
Charged Device Model (CDM) 750 V (corner pins) and 500 V (other pins) per AEC−Q100−011 standard.
3. Latch up Current per JEDEC JESD78 class II standard.
4. Moisture Sensitivity Level (MSL) 1: per IPC/JEDEC J−STD−020 standard.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
AV
Analog Input Supply Range.
Must Be Greater or Equal to PV
3.0
5.0
5.5
V
INR
INR
PV
Power Input Supply Range
1.9
−40
0.67
12.8
6.4
3.3
25
5.5
+150
1.3
150
15
V
INR
JR
T
Junction Temperature Range (Note 6)
Inductor for DC−DC Converter (Note 5)
Output Capacitor for DC−DC Converter (Note 5)
Bootstrap Capacitor (Note 5)
°C
mH
mF
nF
mF
mF
L
OUT
1.0
20
C
OUT
C
10
BOOT
C
Input Capacitor for Analog Supply (Note 5)
Input Capacitor for Power Supply (Note 5)
2.5
4.7
10
−
AVIN
C
4.7
−
PVIN
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Including de−ratings (Refer to the Application Information section of this document for further details)
6. The thermal shutdown set to 167°C (typical) avoids potential irreversible damage on the device due to power dissipation.
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4
NCV91300
THERMAL INFORMATION
Symbol
JEDEC JESD51−3
Demo Board
(Measured)
(Calculated)
Parameter
Unit
°C/W
°C/W
°C/W
q
Thermal Resistance Junction to Ambient (Note 9)
75.3
107
37.9
−
JA
Y
JCTOP
Thermal Characterization Parameter Junction to Case Top (Note 7)
Y
JB
Thermal Characterization Parameter Junction to Board.
Measured on the AGND Footprint (Note 8)
12.6
−
CC
Current Capability T ≤ 85°C (Note 10)
−
−
−
>3.50
>3.50
3.40
A
A
A
85
A
CC
CC
Current Capability T ≤ 105°C (Note 10)
A
105
125
Current Capability T ≤ 125°C (Note 10)
A
7. Calculated with infinite heatsink affixed to case top without any board present.
8. Calculated with infinite heatsink affixed to case bottom without any board present.
9. The Rq is dependent of the PCB heat dissipation. Refer to AND8215/D
JA
10.The current capability (CC) is dependent by input voltage, maximum output current, pcb stack up and layout as well as external components
selected. Filled with AVin = 5 V, PVin = 3.3 V, Vout = 1.1 V
ELECTRICAL CHARACTERISTICS (Refer to the Application Information section of this data sheet for more details.
Min and Max Limits apply for T range (T ), AVIN range (AV ), PVIN range (PV ) and default configuration, unless otherwise specified.
J
JR
INR
INR
Typical values are referenced to T = +25°C, AVIN = 5.0 V, PVIN = 3.3 V and default configuration, unless otherwise specified.)
J
Symbol
Parameter
Min
Typ
Max
Unit
SUPPLY CURRENT: PINS AVIN – PVINx
I
Operating Quiescent Current in PWM Mode
−
−
−
7
−
−
−
mA
mA
mA
Q−PWM
DC−DC Active in Forced PWM, No Load
I
Operating Quiescent Current in PFM Mode}
DC−DC Active in Auto Mode, No Load – Minimal Switching
65
20
Q PFM
SLEEP
I
Product Sleep Mode Current
EN High and DC−DC Off or
EN Low and SLEEP_MODE Bit High
VIN = 5.5 V – T = 105°C
J
I
Product in Off Mode
−
3.0
−
mA
OFF
EN Low and SLEEP_MODE Bit Low
VIN = 5.5 V – T = 105°C
J
DC−DC CONVERTER
I
I
I
Load Current Range: Ipeak[1..0] = 00 (Note 11)
Load Current Range: Ipeak[1..0] = 01 (Note 11)
Load Current Range: Ipeak[1..0] = 10 (Note 11)
Load Current Range: Ipeak[1..0] = 11 (Note 11)
0
0
−
−
−
−
−
2.0
2.5
3.0
3.5
1.5
A
A
OUT00
OUT01
OUT10
0
A
I
0
A
OUT11
DV
DV
DV
Output Voltage DC Error
PWM Mode, PVIN, AVIN Range, No Load
−1.5
%
OUT1
Output Voltage DC Error
PWM Mode, PVIN Range, AVIN Range, I
−2
−3
−
−
−
−
−
2
2
%
%
OUT2
up to I
OUT
OUTxx
Output Voltage DC Error
Auto Mode, PVIN Range, AVIN Range, I
OUT3
up to I
OUT
OUTxx
T
Minimum On Time (Measured at SW) in PWM Mode
AVIN = 5.5 V − PVIN = 3.3 V
95
101
ns
ns
ONMIN1
ONMIN2
T
Minimum On Time (Measured at SW) in PWM Mode
AVIN = 3.3 V − PVIN = 3.3 V
−
F
Switching Frequency (Internal Oscillator, No Spread Spectrum)
Spread Spectrum: FSS[1..0] = 00 (No Spread)
Spread Spectrum: FSS[1..0] = 01
2.00
−
2.15
2.30
−
MHz
%
SW
F
0
0
0
0
SPREAD00
SPREAD01
SPREAD10
F
F
−5
5
%
Spread Spectrum: FSS[1..0] = 10
−10
−10
10
10
%
F
Spread Spectrum: FSS[1..0] = 11
%
SPREAD11
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5
NCV91300
ELECTRICAL CHARACTERISTICS (Refer to the Application Information section of this data sheet for more details.
Min and Max Limits apply for T range (T ), AVIN range (AV ), PVIN range (PV ) and default configuration, unless otherwise specified.
J
JR
INR
INR
Typical values are referenced to T = +25°C, AVIN = 5.0 V, PVIN = 3.3 V and default configuration, unless otherwise specified.) (continued)
J
Symbol
Parameter
Min
Typ
Max
Unit
DC−DC CONVERTER
R
High Side MOSFET On Resistance
AVIN = 5.0 V
30
40
62
65
110
130
mW
mW
ONHS
R
Low Side MOSFET On Resistance
AVIN = 5.0 V
ONLS
R
BOOT Charge Resistance
−
2.3
2.9
−
7.6
3.0
3.5
4.0
4.5
1.3
5
−
3.6
4.1
−
W
A
BOOT
PK00
PK01
PK10
I
I
I
Peak Inductor Current Ipeak[1..0] = 00 (Note 11)
Peak Inductor Current Ipeak[1..0] = 01 (Note 11)
Peak Inductor Current Ipeak[1..0] = 10 (Note 11)
Peak Inductor Current Ipeak[1..0] = 11 (Note 11)
Negative Current Limit: Open Loop (Note 11)
A
A
I
−
−
A
PK11
I
−
−
A
PKN
DC
Load Regulation: I
Range, PWM Mode
−
−
mV
mV
mV
LOAD
OUTxx
DC
Line Regulation: PVIN Range, AVIN Range, PWM Mode
−
5
−
LINE
LOAD1.5A
AC
AC
Transient Load Response: tr = tf = 1 ms, C
Load Step 1.5 A
= 4 x 10 mF
−
32
−
OUT
Load/Line Transient Recovery Time
Time Rail Takes to Come Back to Nominal V
−
40
−
ms
TRECOV
− 10 mV
OUT
AC
Transient Line Response: t = t = 10 ms, Line Step 3.0 V / 3.6 V
−
40
−
mV
LINE
r
f
t
Turn On Time: Time from EN Transitions from Low to High to 90% of Output
Voltage, (DVS[1..0] = 00b), VOUT = 1.10 V
90
110
155
ms
START
R
DC−DC Active Output Discharge: V
= 1.10 V
−
8.5
27
W
DISDCDC
OUT
EN PIN
V
High Input Voltage
Low Input Voltage
1.10
−
−
−
−
−
V
V
ENIH
V
0.4
4.5
ENIL
T
Digital Input EN Filter: Rising and Falling
DBN_Time = 01
0.5
ms
ENFTR
I
EN Input Pull−Down, (Input Bias Current)
−
0.15
1.00
mA
ENPD
INTB PIN
V
INTB Low Output Voltage: I
= 5 mA
−
−
−
−
−
−
0.2
V
V
INTBL
INTBH
INTB
V
INTB High Output Voltage: Open Drain
AV
IN
P
INTB Leakage Current: 3.3 V at INTB Pin when No Interrupt, T = 105°C
100
nA
INTBLK
J
PG PIN
V
Power Good Threshold: Falling Edge as a Percentage of Nominal Output Voltage
Power Good Hysteresis
86
0
90
4
94
7
%
%
ms
ms
V
PGF
V
PGHYS
T
Power Good Reaction Time for DC−DC: Falling
Power Good Reaction Time for DC−DC: Rising
−
2
−
RTF
T
RTR
3.5
−
11
−
14
0.2
V
Power Good Low Output Voltage: I = 5 mA
PGL
PGH
PG
V
Power Good High Output Voltage: Open Drain
−
−
AV
V
IN
P
PGLK
Power Good Leakage Current: 3.3 V at PG Pin when Power Good Valid,
J
−
−
100
nA
T = 105 °C
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6
NCV91300
ELECTRICAL CHARACTERISTICS (Refer to the Application Information section of this data sheet for more details.
Min and Max Limits apply for T range (T ), AVIN range (AV ), PVIN range (PV ) and default configuration, unless otherwise specified.
J
JR
INR
INR
Typical values are referenced to T = +25°C, AVIN = 5.0 V, PVIN = 3.3 V and default configuration, unless otherwise specified.) (continued)
J
Symbol
Parameter
Min
Typ
Max
Unit
SYNC PIN
SYNC
Synchronization Frequency Range
SYNC Low Input Voltage
SYNC High Input Voltage
SYNC Clock Duty Cycle
1.90
−
2.15
−
2.4
0.4
MHz
V
R
SYNC
VIL
VIH
SYNC
SYNC
1.5
40
−
AV
V
IN
−
60
%
DC
2
I C BUS
V
High Level at SCL/SDA Line
1.7
−
−
−
−
−
−
−
4.5
0.4
4.5
4.5
0.4
3.4
V
V
I2CINT
V
SCL, SDA Low Input Voltage (Note 12)
SCL high Input Voltage (Note 12)
SDA high Input Voltage (Note 12)
I2CIL
V
1.6
1.21
−
V
I2CIHSCL
I2CIHSDA
V
V
V
SDA Low Output Voltage: I
= 3 mA
V
I2COL
SINK
2
F
I C Clock Frequency
0.4
MHz
SCL
TOTAL DEVICE
AVIN Under Voltage Lockout: V
V
Falling
AVIN
−
50
−
−
−
2.8
100
−
V
mV
ms
V
AUVLO
V
AVIN Under Voltage Lockout Hysteresis: V
Rising
AVIN
AUVLOH
V
AVIN UVLO Reaction Time
3.5
−
AUVLORT
V
PVIN Under Voltage Protection threshold: V
Falling
−
1.5
200
−
PVINUVP
PVINUVPH
PVINOVPR
PVIN
V
V
PVIN Under Voltage Protection hysteresis: V
Rising
50
−
−
mV
V
PVIN
PVIN Overvoltage Protection: Rising Threshold
PVIN Overvoltage Protection: Falling Threshold
PVIN UVP and OVP Reaction Time
Thermal Shut Down Protection
5.8
5.65
−
V
5.5
1
−
V
PVINOVPF
V
12
−
ms
°C
°C
°C
°C
°C
°C
PVINRT
T
SD
−
168
154
132
24
10
6
T
WAR
Warning Rising Edge
−
−
T
Pre – Warning Threshold: TPWTH[1..0] = 10
Thermal Shut Down Hysteresis
−
−
PWAR
T
−
−
SDH
T
Thermal Warning Hysteresis
−
−
WARH
T
Thermal Pre−Warning Hysteresis
−
−
PWARH
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Junction temperature must be maintained below 150°C. Output load current capability depends on the application thermal capability.
2
12.Devices that use non−standard supply voltages, which do not conform to the intent I C bus system levels, must relate their input levels to
the VDD voltage to which the pull−up resistors RP are connected.
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7
NCV91300
TYPICAL OPERATING CHARACTERISTICS (A = 5.0 V, P = 3.3 V, T = +25°C
VIN
VIN
A
V
OUT
= 1.10 V, I
= 3.5 A (Unless otherwise noted). L = 1.0 mH – C
= 4 x 10 mF, C
= 10 mF, C
= 10 mF)
PEAK
OUT
PVIN
AVIN
Figure 4. Efficiency vs. ILOAD and PVIN
VOUT = 3.3 V, AVIN = 5.0 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 5. Efficiency vs. ILOAD and Temperature
V
OUT = 3.3 V, AVIN = PVIN = 5.0 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 6. Efficiency vs. ILOAD and PVIN
VOUT = 1.8 V, AVIN = 5.0 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 7. Efficiency vs. ILOAD and Temperature
OUT = 1.8 V, AVIN = 5.0 V, PVIN = 3.3 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
V
Figure 8. Efficiency vs. ILOAD and PVIN
VOUT = 1.8 V, AVIN = 3.3 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 9. Efficiency vs. ILOAD and Temperature
OUT = 1.8 V, AVIN = 3.3 V, PVIN = 3.3 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
V
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8
NCV91300
TYPICAL OPERATING CHARACTERISTICS (A = 5.0 V, P = 3.3 V, T = +25°C
VIN
VIN
A
V
OUT
= 1.10 V, I
= 3.5 A (Unless otherwise noted). L = 1.0 mH – C
= 4 x 10 mF, C
= 10 mF, C
= 10 mF) (continued)
PEAK
OUT
PVIN
AVIN
Figure 10. Efficiency vs. ILOAD and PVIN
VOUT = 1.1 V, AVIN = 5.0 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 11. Efficiency vs. ILOAD and Temperature
V
OUT = 1.1 V, AVIN = 5.0 V, PVIN = 3.3 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 12. Efficiency vs. ILOAD and PVIN
VOUT = 1.1 V, AVIN = 5.0 V Forced PWM Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 13. Efficiency vs. ILOAD and Temperature
OUT = 1.1 V, AVIN = 5.0 V, PVIN = 3.3 V Forced PWM Mode
L = TDK TFM252012ALMA1R0MTAA
V
Figure 14. Efficiency vs. ILOAD and PVIN
VOUT = 1.1 V, AVIN = 3.3 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 15. Efficiency vs. ILOAD and VIN
VOUT = 1.1 V, AVIN = 3.3 V, PVIN = 3.3 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
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NCV91300
TYPICAL OPERATING CHARACTERISTICS (A = 5.0 V, P = 3.3 V, T = +25°C
VIN
VIN
A
V
OUT
= 1.10 V, I
= 3.5 A (Unless otherwise noted). L = 1.0 mH – C
= 4 x 10 mF, C
= 10 mF, C
= 10 mF) (continued)
PEAK
OUT
PVIN
AVIN
Figure 16. Efficiency vs. ILOAD and PVIN
VOUT = 0.6 V, AVIN = 5.0 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 17. Efficiency vs. ILOAD and Temperature
V
OUT = 0.6 V, AVIN = 5.0 V, PVIN = 3.3 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 18. Efficiency vs. ILOAD and PVIN
VOUT = 0.6 V, AVIN = 3.3 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 19. Efficiency vs. ILOAD and Temperature
V
OUT = 0.6 V, AVIN = 3.3 V, PVIN = 3.3 V, Auto Mode
L = TDK TFM252012ALMA1R0MTAA
Figure 20. VOUT Accuracy vs. ILOAD and PVIN
VOUT = 3.3 V, AVIN = 5.0 V, Auto Mode
Figure 21. VOUT Accuracy vs. ILOAD and Temperature
V
OUT = 3.3 V; AVIN = 5.0 V, PVIN = 5.0 V, Auto Mode
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NCV91300
TYPICAL OPERATING CHARACTERISTICS (A = 5.0 V, P = 3.3 V, T = +25°C
VIN
VIN
A
V
OUT
= 1.10 V, I
= 3.5 A (Unless otherwise noted). L = 1.0 mH – C
= 4 x 10 mF, C
= 10 mF, C
= 10 mF) (continued)
PEAK
OUT
PVIN
AVIN
Figure 22. VOUT Accuracy vs. ILOAD and PVIN
VOUT = 1.8 V, AVIN = 5.0 V, Auto Mode
Figure 23. VOUT Accuracy vs. ILOAD and Temperature
OUT = 1.8 V; AVIN = 5.0 V, PVIN = 3.3 V, Auto Mode
V
Figure 24. VOUT Accuracy vs. ILOAD and PVIN
VOUT = 1.1 V, AVIN = 5.0 V, Auto Mode
Figure 25. VOUT Accuracy vs. ILOAD and Temperature
OUT = 1.1 V; AVIN = 5.0 V, PVIN = 3.3 V, Auto Mode
V
Figure 26. VOUT Accuracy vs. ILOAD and PVIN
VOUT = 1.1 V, AVIN = 5.0 V, Forced PWM Mode
Figure 27. VOUT Accuracy vs. ILOAD and Temperature
OUT = 1.1 V; AVIN = 5.0 V, PVIN = 3.3 V, Forced PWM Mode
V
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NCV91300
TYPICAL OPERATING CHARACTERISTICS (A = 5.0 V, P = 3.3 V, T = +25°C
VIN
VIN
A
V
OUT
= 1.10 V, I
= 3.5 A (Unless otherwise noted). L = 1.0 mH – C
= 4 x 10 mF, C
= 10 mF, C
= 10 mF) (continued)
PEAK
OUT
PVIN
AVIN
Figure 28. VOUT Accuracy vs. ILOAD and PVIN
VOUT = 0.6 V, AVIN = 5.0 V, Auto Mode
Figure 29. VOUT Accuracy vs. ILOAD and Temperature
OUT = 0.6 V; AVIN = 5.0 V, PVIN = 3.3 V, Auto Mode
V
Figure 30. HSS RDSON vs. VIN and Temperature
Figure 31. LSS RDSON vs. VIN and Temperature
Figure 32. IOFF vs. VIN and Temperature
Figure 33. ISLEEP vs. VIN and Temperature
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NCV91300
TYPICAL OPERATING CHARACTERISTICS (A = 5.0 V, P = 3.3 V, T = +25°C
VIN
VIN
A
V
OUT
= 1.10 V, I
= 3.5 A (Unless otherwise noted). L = 1.0 mH – C
= 4 x 10 mF, C
= 10 mF, C
= 10 mF) (continued)
PEAK
OUT
PVIN
AVIN
Figure 34. IQ PFM vs. VIN and Temperature
OUT = 1.1 V
Figure 35. IQ PWM vs. VIN and Temperature
OUT = 1.1 V
V
V
Figure 36. Switchover Point VOUT = 1.1 V, AVIN = 5.5 V
Figure 37. Switchover Point VOUT = 1.1 V, AVIN = 3.3 V
Figure 38. Switching Frequency vs. ILOAD and AVIN
VOUT = 1.1 V, PVIN = 1.9 V
Figure 39. Switching Frequency vs ILOAD and
Temperature
VOUT = 1.1 V, PVIN = 3.3 V
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NCV91300
TYPICAL OPERATING CHARACTERISTICS (A = 5.0 V, P = 3.3 V, T = +25°C
VIN
VIN
A
V
OUT
= 1.10 V, I
= 3.5 A (Unless otherwise noted). L = 1.0 mH – C
= 4 x 10 mF, C
= 10 mF, C
= 10 mF) (continued)
PEAK
OUT
PVIN
AVIN
Figure 40. Transient Load 0.05 to 1.5 A
Figure 41. Transient Load 0.05 to 1.5 A
Transient Line 3.0 – 3.6 V, Auto Mode, VOUT = 1.1 V
Transient Line 3.0 – 3.6 V, Auto Mode, VOUT = 1.1 V
Figure 42. Transient Load 0.05 to 1.5 A
Figure 43. Transient Load 0.05 to 1.5 A
Transient Line 3.0 – 3.6 V, Forced PWM Mode,
Transient Line 3.0 – 3.6 V, Forced PWM Mode,
V
OUT = 1.1 V
VOUT = 1.1 V
Figure 44. Transient Load 0.05 to 1.5 A
Auto Mode, VOUT = 1.1 V
Figure 45. Transient Load 0.05 to 1.5 A
Forced PWM Mode, VOUT = 1.1 V
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14
NCV91300
DETAILED OPERATING DESCRIPTION
Forced PWM
Detailed Descriptions
The NCV91300 is
a
voltage mode standalone
The PWM bit of the COMMAND register forces the
NCV91300 to only use the PWM mode, meaning the
transition to the PFM mode is no more allowed. This is
generally used when a fixed switching frequency is
mandatory, knowing that current consumption is degraded.
synchronous PWM DC−DC converter optimized to supply
the different sub systems of automotive applications post
regulation system from 2.0V up to 5V input. It can deliver
2
up to 3.0 A at an I C selectable voltage ranging from 0.6 V
to 3.30 V. The switching frequency up to 2.15 MHz allows
the use of small output filter components. Power Good
indicator and external synchronization are available.
Synchronous rectification and automatic PFM−PWM
transitions improve overall solution efficiency. Forced
PWM mode is also configurable.
Output Voltage
The output voltage is internally set by an integrated
resistor bridge and no extra components are needed to set it.
Writing in the Vout [7..0] bits of the PROG register changes
the output voltage by:
• 5 mV steps when V
• 10 mV steps when V
• 20 mV steps when VOUT is between 2.0 V and 3.3 V
is between 0.6 V and 1.0 V,
is between 1.0 V and 2.0 V
OUT
Operating modes, configuration, and output power can be
easily selected by programming a set of registers using an
OUT
2
2
I C compatible interface. Default I C settings are factory
programmable.
The NCV91300 is in low profile 3.0 x 3.0 mm QFN−16
Output Stage
NCV91300 integrates both the High Side and the Low
Side NMOS switches, and associated bootstrap regulator to
provide the right gate drive voltage.
package
DC−DC Converter Operation
The converter integrates both high side and low side
(synchronous) switches. Neither external transistors nor
diodes are required for NCV91300 operation. Feedback and
compensation network are also fully integrated.
It can operate in two different modes: PFM and PWM.
The transition between modes can occur automatically or
Inductor Peak Current Protection, Negative Current
Protection and Short Circuit Protection
During normal operation, peak current limitation
protection monitors and limits the inductor current by
checking the current in the High Side switch. When this
current exceeds the Ipeak threshold, the High Side switch is
immediately opened.
2
the switcher can be placed in forced PWM mode by I C
programming (PWM bit of COMMAND register).
For protecting against excessive load or short circuit to
ground, the DC−DC is powered down and the ISHORT
interrupt is flagged when 2 Ipeak are counted when in power
fail (so when PG is low). The REARM bit (LIMCONF
register) value defines the re−start:
PWM (Pulse Width Modulation) Operating Mode
In medium and high load conditions, NCV91300 operates
in PWM mode from the internal (oscillator) or external
(SYNC) clock. In this mode, the inductor current is in CCM
(Continuous Conduction Mode) and the voltage is regulated
by PWM. The internal Low Side switch operates as
synchronous rectifier and is driven complementary to the
High Side switch.
• If REARM = 0, then NCV91300 does not re−start
automatically, an EN pin toggle is required.
• If REARM = 1, NCV91300 re−starts automatically after
2 ms with register values set prior the fault condition.
This High Side switch current limitation is particularly
useful to protect the inductor. The peak current can be set by
writing IPEAK[1..0] bits in the LIMCONF register.
PFM (Pulse Frequency Modulation) Operating Mode
In order to save power and improve efficiency at low
loads, the NCV91300 operates in PFM mode when the
inductor current drops into DCM (Discontinuous
Conduction Mode). The High Side switch on−time is kept
constant and the switching frequency becomes proportional
to the loading current. As it does in PWM mode, the internal
Low Side switch operates as a synchronous rectifier after
each High Side switch on−pulse until there is no longer
current in the coil.
Table 1. Ipeak VALUES
IPEAK[1..0]
Inductor Peak Current (A)
3.0 – for 2.0 output current
3.5 – for 2.5 output current
4.0 – for 3.0 output current
4.5 – for 3.5 output current
00
01
10
11
When the load increases and the current in the inductor
become continuous again, the controller automatically turns
back to PWM mode.
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15
NCV91300
In addition, to protect the Low Side switch, the negative
current protection (Ipeakn) limits potential excessive
current from output (for example, when fault condition
causes the output voltage to be higher than the nominal
output voltage).For protecting against excessive short to
high voltage, the number of consecutive Ipeakn is counted.
When the counter reaches 8, the DC−DC is powered down
and the ISHORT interrupt is flagged, then
• If REARM = 0, then NCV91300 does not re−start
automatically, an EN pin toggle is required.
• If REARM = 1, NCV91300 re−starts automatically after
2 ms with register values set prior the fault condition.
When PV fails below V
stopped to prevent any cross conduction.
To guaranty a smooth output voltage come back when the
PVIN is recovering, a FPUS is initiated.
, the output stage is also
IN
PVINUVP
Enabling
Under proper supply conditions, the EN pin controls
NCV91300 start up. The EN pin Low to High transition
starts the power up sequencer.
If EN is made low, the DC−DC converter is turned off and
device enters in SLEEP mode when the SLEEP_MODE bit
is high, or in OFF mode when SLEEP_MODE bit is low.
Table 2. MODE OF OPERATION TABLE
Active Output Discharge
To make sure that no residual voltage remains on the
output of the DC−DC when disabled, an active discharge
path can ground the NCV91300 output voltage. For
maximum flexibility, this feature can be disabled or enabled
with the DISCHG bit in the COMMAND register. Note that
whatever the state of the DISCHG bit, the discharge path is
enabled during the Wake−Up time.
EN
Sleep_Mode
ENABLE
Product Mode
OFF
Low
Low
High
High
0
1
x
x
x
x
0
1
SLEEP
SLEEP
ON
When the EN pin is set to a high level, the DC−DC
converter can be enabled / disabled by writing the ENABLE
bit of the COMMAND register.
AVIN Under Voltage Lock Out (UVLO)
NCV91300 Analog core (AV ) does not operate for
IN
voltages below the Under Voltage Lock Out (AUVLO)
threshold. Below this UVLO threshold, all internal
circuitries (both analog and digital) are in reset. To avoid
erratic on / off behavior, a maximum 100 mV hysteresis is
implemented. Restart is guaranteed at 2.9 V when the supply
voltage is recovering or rising. When in OFF mode, to
reduce quiescent current, the UVLO threshold is relaxed.
Table 3. MODE OF OPERATION TABLE
EN
ENABLE
DC−DC
Disabled
Disabled
Enabled
Low
High
High
x
0
1
PVIN Input Power Voltage Protection
To protect the output stages, PV valid range is defined
IN
Power Up Sequence (PUS)
by V
and V
.
PVINOVPR
PVINUVP
In order to power up the circuit, the input voltage AVIN
has to rise above the AUVLO threshold. This triggers the
internal core circuitry power up (=> “Wake Up Time”
including “Bias Time”). This delay is internal and cannot be
bypassed. EN pin transition within this delay corresponds to
the “Initial power up sequence” (IPUS)
When PV exceeds V
(5.8 V), the IC stops
IN
PVINOVPR
switching to protect the circuit from internal spikes above
7.5 V. An internal filter prevents the circuit from shutting
down due to noise spikes.
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NCV91300
AVIN
UVLO
POR
SLEEP
OFF
SLEEP
ON (PFM or PWM)
~15 mA
~2 mA
~15 mA
60 mA or 20 mA
EN
DELAY[2..0]
VOUT
25 ms
32 ms
~300 ms
Wake up
Time
DVS ramp
Time
TFTR Bias
Init
Time
Time
Figure 46. Power Up Sequence
AVIN, PVIN
UVLO
POR
SLEEP
ON (PFM or PWM)
~15 mA
60 mA or 20 mA
EN
DELAY[1..0]
VOUT
~300 ms
32 ms
Wake up
Time
Init
Time
DVS ramp
Time
Figure 47. Initial Power Up Sequence
In addition, a programmable delay will take place
between the Wake Up Time and the Init time: The
DELAY[1..0] bits of the TIME register will set this
programmable delay with a 2 ms resolution. Taking default
delay of 0 ms, the NCV91300 IPUS takes roughly 332 ms,
and the DC−DC converter output voltage will be ready
within 385 ms.
2
NOTE: During the Wake Up time, the I C interface is
2
not active. Any I C request to the IC during this
time period will result in a NACK reply.
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NCV91300
Normal, Quick and Fast Power Up Sequence (PUS)
3 different power up sequences are available depending
on the mode and the trigger:
• Enabling the part by setting the EN pin from Off Mode
will result in “Normal power up sequence” (NPUS, with
DELAY[1..0]).
AVIN, PVIN
UVLO
OFF
SLEEP
ON (PFM or PWM)
POR
EN
~2 mA
~15 mA
60 mA or 20 mA
DELAY[2..0]
VOUT
25 ms
32 ms
DVS ramp
Time
TFTR Bias
Time
Init
Time
Figure 48. Normal Power Up Sequence
• Enabling the part by setting the EN pin from SLEEP
Mode will result in “Quick power up sequence” (QPUS,
with DELAY[1..0]).
AVIN, PVIN
UVLO
SLEEP
POR
ON (PFM or PWM)
~15 mA
60 mA or 20 mA
EN
DELAY[1..0]
VOUT
32 ms
TFTR
Init
Time
DVS ramp
Time
Figure 49. Quick Power Up Sequence
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18
NCV91300
• Enabling the DC−DC converter by setting the ENABLE
bit will results in “Fast power up sequence” (FPUS,
without DELAY[1..0]).
AVIN, PVIN
UVLO
ON (PFM or PWM)
SLEEP
POR
~15 mA
60 mA or 20 mA
ENABLE
VOUT
32 ms
TFTR
DVS ramp
Time
Init
Time
Figure 50. Fast Power Up Sequence
Power Down Sequence
• Forced PWM mode (DVSMODE = 1) when accurate
output voltage control is needed. DVS up and DVS down
ramps are controlled with the DVS[1..0] bits in the TIME
register.
DC−DC converter shutdown is initiated by either
grounding the EN pin (Hardware Shutdown) or by clearing
the ENABLE bit (Software shutdown) in the COMMAND
register: The output voltage is disabled and, depending on
the DISCHG bit state of the COMMAND register, the output
may be discharged.
V2
Internal
Reference
Output
Voltage
DV
In hardware shutdown (EN = 0), the digital is still alive
2
2
and I C accessible when I C pull up are present.
The internal core of the NCV91300 shuts down when:
• EN pin is low and no SLEEP_MODE
Dt
V1
Figure 51. DVS in Forced PWM Mode Diagram
• AVIN falls below UVLO
Dynamic Voltage Scaling (DVS)
• In Auto mode (DVSMODE = 0) when the output voltage
must not be discharged. DVS up ramp is controlled by the
DVS[1..0] as in Forced PWM mode, but the DVS down
is no more controlled: it depends of the load and cannot
be faster than the DVS[1..0] settings.
The NCV91300 supports dynamic voltage scaling (DVS)
allowing the output voltage to be reprogrammed for
providing the different voltages required by the processor.
The change between set points is managed in a smooth
fashion without disturbing the operation of the processor.
The DVS sequence is automatically initiated by changing
the output voltage bits (VOUT[7..0] bits of the PROG
Output
Voltage
V2
Internal
Reference
2
DV
register) via an I C command. The DVSMODE bit in the
COMMAND register defines the DVS transition mode:
Dt
V1
Figure 52. DVS in Auto Mode Diagram
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19
NCV91300
Thermal Management
with the F_SPREAD[1..0] bits of the TIME register. These
features help reduce and / or control the peak emissions at
the switching frequency and harmonics.
Throughout the power−up sequence, the NCV91300
ignores both the signal applied on the SYNC pin and the
selected spread spectrum, to work with the fixed internal
2.15 MHz clock (spread spectrum disabled)
Thermal Shut Down (TSD)
The thermal capability of the NCV91300 can be exceeded
due to the step down converter output stage power level. A
thermal protection circuitry with associated interrupt is
therefore implemented to prevent the IC from damage. This
protection circuitry is only activated when the core is in
active mode (output voltage is turned on). During thermal
shut down, the output voltage is turned off.
When NCV91300 returns from thermal shutdown, it can
re−start in 2 different configurations depending on the
REARM bit in the LIMCONF register:
Once power−up sequence is completed:
• If no clock is applied on the SYNC pin, the DC−DC
continues switching with the internal oscillator, by
activating the selected spread spectrum.
• As soon as a clock is present on the SYNC pin, for
accurate frequency sensing, the internal oscillator is set to
the fixed 2.15 MHz (spread spectrum disabled). Then,
once the clock is sensed valid, the DC−DC mode is
automatically set to Forced PWM, and the switching
clock becomes the SYNC clock in a smooth way. By
default the SYNC clock polarity is kept, but could be
inverted upon request.
The NCV91300 switching reverts to the internal oscillator
within no more than one missing cycle clock, when SYNC
signal is no longer valid or removed. In the same time, the
DC−DC mode returns to the PWM bit state and the
programmed F_SPREAD[1..0] spread spectrum.
• If REARM = 0 then NCV91300 does not re−start after
TSD. To restart, an EN pin toggle is required.
• If REARM = 1, NCV91300 re−starts with register values
set prior to thermal shutdown.
The thermal shut down threshold is set at 167°C (typical)
and a 30°C hysteresis is implemented in order to avoid
erratic on / off behavior. After a typical 167°C thermal shut
down, NCV91300 will resume to normal operation when the
die temperature cools to 140°C.
Thermal Warnings
In addition to the TSD, the die temperature monitoring
circuitry includes
a thermal warning and thermal
CLK interrupt (ACK_CLK bit) indicates if the switching
clocks sources changed, whereas the CLK sense (SNS_CLK
bit) defines the switching clock used by the DC−DC.
pre−warning sensor and interrupts. These sensors can
inform the processor that NCV91300 is close to its thermal
shutdown and preventive measures to cool down die
temperature can be taken by software.
Power Good Pin
The Warning threshold is set by hardware to 150°C
typical. The Pre−Warning threshold is set by default to
130°C but it can be changed by setting the TPWTH[1..0] bits
in the LIMCONF register.
The Power Good monitoring with corresponding PG open
drain pin indicates that the output voltage is up and running
in the valid range.
When disabled (i.e. the PGDCDC bit of the COMMAND
register set low), the PG pin stays in low impedance state.
In operation, when the output drops below 90% of the
programmed level, the PG pin transitions immediately to the
low impedance state, indicating a power failure. When the
voltage returns above 95%, the PG pin becomes again in
high impedance after a 10 ms typical delay (could be change
to 2 ms upon request). For sure when the DCDC is turned off
and during the power−up sequence, the PG is driven low
indicating the output voltage is not ready.
IO Pins
Enable Pin
The EN pin controls NCV91300 start up. A built in pull
down resistor disables the device when this pin is left
unconnected or not driven..
SYNC Pin and Spread Spectrum
The NCV91300 can be synchronized to an external clock
applied to the SYNC pin or use the internal oscillator. When
using the internal oscillator, spread spectrum can be selected
DCDC_EN
Internal
Reference
93%
90%
32 ms
10 ms *
10 ms *
Vout
PG
* Could be 2 ms
upon request
Figure 53. Power Good Signal when PGDCDC = 1
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20
NCV91300
During DVS transitions, the Power Good monitoring is
Table 4. INTERRUPT SOURCES
still active. However, the PGDVS bit of the COMMAND
register forces the PG pin in low impedance during a positive
DVS and it will follow again the state of the monitoring
10 ms typically (could be 2 ms upon request) after DVS
transition completed.
Interrupt Name
UVLO
Description
AV Under Voltage Lock Out
IN
UVP
PV Under Voltage Protection
IN
OVP
PV Over Voltage Protection
IN
IDCDCHS
IDCDCLS
ISHORT
CLK
DC−DC converter Current Protection
DC−DC converter Negative Current Protection
DC−DC converter Short−Circuit Protection
Working Clock Indicator
V2
V3
Internal
Reference
DVS
Up
DVS
Vout V1
PG
Down
10 ms *
PG
Power Good
TSD
Thermal Shut Down
* Could be 2 ms
upon request
TWARN
TPREW
BUS
Thermal Warning
Thermal Pre Warning
Figure 54. Power Good During DVS Transition
(PGDVS = 1)
2
I C Write access error
Individual bits generating interrupts will be set to 1 in the
INT_ACKx register, indicating the interrupt source. The
INT_ACKx bit is automatically reset by writing a “1”. The
INT_SEN register (read only register) contains real time
indicators of interrupt sources.
All interrupt sources can be masked by writing in the
register INT_MSKx. Masked sources will never generate an
interrupt request on the INTB pin (Open drain output).
A non−masked interrupt request will result in the INTB
pin being driven low. When the host writes the INT_ACKx
bits generating interrupt to “1”, the INTB pin is released to
high impedance and the corresponding interrupt bits
INT_ACKx is cleared.
In addition to the above, the state of the synchronization
can optionally be reflected on the PG pin through the
PGCLK bit. This is of interest for RF critical applications
where the switching of the DCDC’s needs to be externally
synchronized. With PGCLK set, the PG pin is forced low
when the DCDC switching frequency is not the SYNC
clock. With PGCLK not set, the state of the synchronization
will have no influence on PG.
DCDC
source
clock
Internal
SYNC
SYNC
Oscillator
10 ms *
TWARN
* Could be 2 ms
upon request
SEN_TWARN
MSK_TWARN
ACK_TWARN
PG
Figure 55. Power Good Behavior (PGCLK = 1)
Interrupt Pin
INTB
Write
to 1
Write
to 1
Write Write
to 1 to 1
The interrupt controller continuously monitors internal
interrupt sources (INT_SENx), generating an interrupt
signal (INT_ACKx) when a system status change is detected
(dual edge monitoring). The interrupt sources include:
2
I C access on INT_ACK
Figure 56. Interrupt Operation TWARN Example
By default no interrupt is associated with the INTB pin.
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21
NCV91300
CONFIGURATION
Default output voltages, DC−DC modes, current limit and
other parameters can be factory programmed upon request.
Below is the default configurations pre−defined:
Table 5. NCV91300 CONFIGURATION
2.5 A
NCV91300B
Configuration
2
Default I C Address
ADD1 – 14h: 0010100R/W
PID Product Identification
RID Revision Identification
FID Feature Identification
93h
85h
01h
Default VOUT
Default MODE
Default IPEAK
OPN
1.1 V
Forced PWM
3.5 A
NCV91300MNWBTXG
W3
Marking
Output Filter
4 x 10 mF
2
I C Compatible Interface
NCV91300 can support a subset of the I C protocol as
detailed below (Read, Write, Write then read sequences).
2
I2C Communication Description
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
START
SLAVE ADDRESS
1
0
ACK
ACK
DATA 1
DATA 1
ACK
ACK
DATA n
DATA n
/ACK STOP
READ OUT FROM PART
WRITE INSIDE PART
1 → READ
/ACK
START
SLAVE ADDRESS
STOP
ACK
If PART does not Acknowledge, the /NACK will be followed by a STOP or Sr (repeated start).
If PART Acknowledges, the ACK can be followed by another data or Stop or Sr.
0 → WRITE
Figure 57. General Protocol Description
The first byte transmitted is the Chip address (with the
LSB bit set to 1 for a read operation, or set to 0 for a Write
operation). The following data will be:
• During a Write operation, the register address (@REG) is
written in, followed by the data. The writing process is
auto−incremental, so the first data will be written in
@REG, the contents of @REG are incremented and the
next data byte is placed in the location pointed to by
@REG + 1 …., etc.
• During a Read operation, the NCV91300 will output the
data from the last register that has been accessed by the
last write operation. Like the writing process, the reading
process is auto−incremental.
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22
NCV91300
Read Sequence
The Master will first make a “Pseudo Write” transaction
with no data to set the internal address register. Then, a Stop
then Start or a Repeated Start will initiate the read
transaction from the register address the initial write
transaction has pointed to:
FROM MCU to NCPxxxx
FROM NCP xxxx to MCU
SETS INTERNAL
REGISTER POINTER
START
SLAVE ADDRESS
0 → WRITE
START
0
ACK
REGISTER ADDRESS
ACK STOP
SLAVE ADDRESS
1
ACK
DATA 1
ACK
DATA n
/ACK STOP
REGISTER ADDRESS
VALUE
REGISTER ADDRESS + (n − 1)
VALUE
n REGISTERS READ
1 → READ
Figure 58. Read Sequence
Write Sequence
The first Write sequence will set the internal pointer to the
register that is selected. Then the read transaction will start
at the address the write transaction has initiated.
Write operation will be achieved by only one transaction.
After chip address, the REG address has to be set, then
following data will be the data we want to write in REG,
REG + 1, REG + 2, …, REG + n.
Write n Registers:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
WRITE VALUE IN
REGISTER REG0 + (n − 1)
WRITE VALUE IN
REGISTER REG0
REGISTER POINTER
REGISTER REG0 ADDRESS
START SLAVE ADDRESS
0
ACK
ACK
REG VALUE
ACK
ACK STOP
REG + (n – 1) VALUE
n REGISTERS WRITE
0 → WRITE
Figure 59. Write Sequence
Write then Read Sequence
With Stop Then Start
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
SETS INTERNAL
REGISTER POINTER
WRITE VALUE IN
REGISTER REG0 + (n − 1)
WRITE VALUE IN
REGISTER REG0
START SLAVE ADDRESS
0
ACK
ACK
REG VALUE
ACK
ACK STOP
REGISTER REG0 ADDRESS
REG + (n – 1) VALUE
n REGISTERS WRITE
0 → WRITE
START SLAVE ADDRESS
1
ACK
DATA 1
ACK
DATA k
/ACK STOP
REGISTER REG + (n – 1)
VALUE
REGISTER ADDRESS + (n – 1)
(k − 1) VALUE
k REGISTERS READ
1 → READ
Figure 60. Write Followed by Read Transaction
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23
NCV91300
Robust I2C Description
NOTE: In case of multi slave, repeated start is highly
recommended to increase robustness of the
protocol. In addition to the double write, a
dedicated interrupt has to be added to signal
improper write attempt.
NCV91300 integrates a two consecutive single byte
writes feature to improve robustness of the communication
against non−systematic bit errors. During a write access, the
NCV91300 compare the two consecutive single byte writes:
• If the second consecutive accesses is identical, the write
is confirmed and executed
I2C Slave Address
The NCV91300 has 8 available I C addresses selectable
2
• If the second consecutive accesses is different, the write
by factory settings (ADD0 to ADD7). Different address
settings can be generated upon request to
is ignores and BUS interrupt is flagged
This feature is controlled with ROBUSTI2C bit of the
LIMCONF register.
ON Semiconductor.
Configuration) for the default I C address.
See
[Table
5
(NCV91300
2
Table 6. I2C SLAVE ADDRESS
2
I C Slave Address
Hex
A7
A6
A5
A4
A3
A2
A1
A0
ADD0
W 0x20
R 0x21
0
0
1
0
0
0
0
R/W
Add
0x10
0
−
ADD1
ADD2
ADD3
ADD4
ADD5
ADD6
ADD7
W 0x28
R 0x29
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
Add
0x14
1
−
W 0x30
R 0x31
R/W
Add
0x18
1
−
W 0x38
R 0x39
R/W
Add
0x1C
0
−
W 0Xc0
R 0xC1
R/W
Add
0x60
0
−
W 0xC8
R 0xC9
R/W
Add
0x64
1
−
W 0xD0
R 0xD1
R/W
Add
0x68
1
−
W 0xD8
R 0xD9
R/W
Add
0x6C
−
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24
NCV91300
Register Map
The tables below describe the I C registers.
2
Registers / Bits Operations:
R
Read only register
W1C
RW
Write to 1 to Clear
Read and Write register
Reserved
Spare
Address is reserved and register / bit is not physically designed
Address is reserved and register / bit is physically designed
In bold default can be factory programmed upon request.
Table 7. I2C REGISTERS MAP CONFIGURATION (NCV91300MNWBTXG)
Add.
00h
Register Name
INT_ACK1
INT_ACK2
INT_SEN1
INT_SEN2
INT_MSK1
INT_MSK2
PID
Type
W1C
W1C
R
Def.
00h
00h
00h
00h
FFh
FFh
93h
85h
01h
5Ah
D7h
2F
Function
Interrupt register 1
01h
Interrupt register 2
02h
Sense register 1 (real time status)
Sense register 2 (real time status)
Mask register 1 to enable or disable interrupt sources (trim)
Mask register 2 to enable or disable interrupt sources (trim)
Product Identification
03h
R
04h
RW
RW
R
05h
06h
07h
RID
R
Revision Identification
08h
FID
R
Features Identification (trim)
09h
PROG
RW
RW
RW
RW
−
Output voltage settings (trim)
0Ah
COMMAND
TIME
Operating mode, Power good and active discharge settings register (trim)
Enabling and DVS timings register (trim)
Reset and limit configuration register (trim)
Reserved. Test Registers
0Bh
0Ch
LIMCONF
−
52h
−
0Dh to FFh
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25
NCV91300
Registers Description
Table 8. INTERRUPT ACKNOWLEDGE REGISTER 1
Name: INTACK1
Type: W1C
Address: 00h
Default: 00000000b (00h)
Trigger: Dual Edge [D7..D0]
D7
D6
D5
D4
ACK_OVP
D3
D2
D1
D0
Spare = 0
ACK_UVLO
ACK_UVP
Spare = 0
ACK_ISHORT ACK_IDCDCHS ACK_IDCDCLS
Bit
Bit Description
ACK_IDCDCLS
ACK_IDCDCHS
ACK_ISHORT
ACK_OVP
DC−DC Negative Over Current Sense Acknowledgement
0: Cleared
1: DC−DC Negative Over Current Event detected
DC−DC Over Current Sense Acknowledgement
0: Cleared
1: DC−DC Over Current Event detected
DC−DC Short−Circuit Protection Sense Acknowledgement
0: Cleared
1: DC−DC Short circuit protection detected
PV Overvoltage Protection Sense Acknowledgement
IN
0: Cleared
1: OVP Event detected
ACK_UVP
PV Undervoltage Protection Sense Acknowledgement
IN
0: Cleared
1: UVP Event detected
ACK_UVLO
Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event detected
Table 9. INTERRUPT ACKNOWLEDGE REGISTER 2
Name: INTACK2
Type: W1C
Address: 01h
Default: 00000000b (00h)
Trigger: Dual Edge [D7..D0]
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 0
ACK_TSD
ACK_TWARN ACK_TPREW
Spare = 0
ACK_BUS
ACK_CLK
ACK_PG
Bit
Bit Description
ACK_PG
ACK_CLK
Power Good Sense Acknowledgement
0: Cleared
1: DC−DC Power Good Event detected
Working Clock Indicator Acknowledgement
0: Cleared
1: DC−DC switching frequency source changed
ACK_BUS
Double write Error Acknowledgement
0: Cleared
1: Invalid double write access
ACK_TPREW
ACK_TWARN
ACK_TSD
Thermal Pre Warning Sense Acknowledgement
0: Cleared
1: Thermal Pre Warning Event detected
Thermal Warning Sense Acknowledgement
0: Cleared
1: Thermal Warning Event detected
Thermal Shutdown Sense Acknowledgement
0: Cleared
1: Thermal Shutdown Event detected
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26
NCV91300
Table 10. INTERRUPT SENSE REGISTER 1
Name: INTSEN1
Type: R
Address: 02h
Default: 00000000b (00h)
Trigger: N/A
D7
D6
D5
D4
SEN_OVP
D3
D2
D1
D0
Spare = 0
SEN_UVLO
SEN_UVP
Spare = 0
Spare = 0
SEN_IDCDCHS SEN_IDCDCLS
Bit
Bit Description
SEN_IDCDCLS
SEN_IDCDCHS
SEN_OVP
DC−DC negative over current sense
0: DC−DC negative current is below limit
1: DC−DC negative current is over limit
DC−DC over current sense
0: DC−DC output current is below limit
1: DC−DC output current is over limit
PV Overvoltage Protection Sense
IN
0: OVP not detected
1: OVP detected
SEN_UVP
PV Undervoltage Protection Sense
0: UVP not detected
1: UVP detected
IN
SEN_UVLO
Under Voltage Sense
0: Input Voltage higher than UVLO threshold
1: Input Voltage lower than UVLO threshold
Table 11. INTERRUPT SENSE REGISTER 2
Name: INTSEN2
Type: R
Address: 03h
Default: 00000000b (00h)
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 0
SEN_TSD
SEN_TWARN SEN_TPREW
Spare = 0
SEN_BUS
SEN_CLK
SEN_PG
Bit
Bit Description
SEN_PG
Power Good Sense
0: DC−DC Output Voltage below target
1: DC−DC Output Voltage within nominal range
SNS_CLK
SEN_BUS
Working Clock Indicator Sense
0: DC−DC switching frequency follows the Internal Oscillator
1: DC−DC switching frequency follows the SYNC pin
Double write Error Sense
0: No error
1: Invalid double write access
SEN_TPREW
SEN_TWARN
SEN_TSD
Thermal Pre Warning Sense
0: Junction temperature below thermal pre−warning limit
1: Junction temperature over thermal pre−warning limit
Thermal Warning Sense
0: Junction temperature below thermal warning limit
1: Junction temperature over thermal warning limit
Thermal Shutdown Sense
0: Junction temperature below thermal shutdown limit
1: Junction temperature over thermal shutdown limit
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NCV91300
Table 12. INTERRUPT MASK REGISTER 1
Name: INTMSK1
Type: RW
Address: 04h
Default: See Register Map
Trigger: N/A
D7
D6
D5
D4
MSK_OVP
D3
D2
D1
D0
Spare = 1
MSK_UVLO
MSK_UVP
Spare = 1
MSK_ISHORT MSK_IDCDCHS MSK_IDCDCLS
Bit
Bit Description
MSK_IDCDCLS
MSK_IDCDCHS
MSK_ISHORT
MSK_OVP
DC−DC negative over current interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked
DC−DC over current interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked
DC−DC Short−Circuit Protection mask
0: Interrupt is Enabled
1: Interrupt is Masked
PV Over Voltage interrupt Mask
IN
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_UVP
PV Under Voltage interrupt Mask
0: Interrupt is Enabled
1: Interrupt is Masked
IN
MSK_UVLO
Under Voltage interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked
Table 13. INTERRUPT MASK REGISTER 2
Name: INTMSK2
Type: RW
Address: 05h
Default: See Register Map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare = 1
MSK_TSD
MSK_TWARN MSK_TPREW
Spare = 1
MSK_BUS
MSK_CLK
MSK_PG
Bit
Bit Description
MSK_PG
MSK_CLK
Power Good interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
Working Clock Indicator interrupt Mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_BUS
Double write Error interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_TPREW
MSK_TWARN
MSK_TSD
Thermal Pre Warning interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked
Thermal Warning interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked
Thermal Shutdown interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked
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NCV91300
Table 14. PRODUCT ID REGISTER
Name: PID
Type: R
Address: 06h
Default: 00011011b (93h)
Reset on N/A
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
PID_7
PID_6
PID_5
PID_4
PID_3
PID_2
PID_1
PID_0
Table 15. PRODUCT ID REGISTER
Name: RID
Type: R
Address: 07h
Default: See Register Map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
RID_7
RID_6
RID_5
RID_4
RID_3
RID_2
RID_1
RID_0
Bit
RID[7..0]
Bit Description
Revision Identification
Table 16. FEATURE ID REGISTER
Name: FID
Type: R
Address: 08h
Default: See Register Map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Spare
Spare
Spare
Spare
FID_3
FID_2
FID_1
FID_0
Bit
FID[3..0]
Bit Description
Feature Identification
Table 17. DC−DC VOLTAGE PROG REGISTER
Name: PROG
Type: RW
Address: 09h
Default: See Register Map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
Vout [7..0]
Bit
Vout [7..0]
Bit Description
Sets the DC−DC converter output voltage
00000000b = 600 mV (5mV step)
00000001b = 605 mV (5 mV step)
…
01001111b = 995 mV (5 mV step)
01010000b = 1000 mV (10 mV step)
01010001b = 1010 mV (10 mV step)
…
10110011b = 1990 mV (10 mV step)
10110100b = 2000 mV (20 mV step)
10110101b = 2020 mV (20 mV step)
…
11110100b = 3280 mV (20 mV step)
11110101b = 3300 mV (20 mV step)
…
11111111b = 3300 mV
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29
NCV91300
Table 18. COMMAND
Name: COMMAND
Address: 0Ah
Type: RW
Default: See Register Map
Trigger: N/A
D7
DVSMODE
Bit
D6
PWM
D5
D4
DISCHG
D3
D2
D1
D0
SLEEP_MODE
PGCLK
ENABLE
PGDVS
PGDCDC
Bit Description
PGDCDC
Power Good Enabling
0 = Disabled
1 = Enabled
PGDVS
ENABLE
PGCLK
Power Good Active On DVS
0 = Disabled
1 = Enabled
EN Pin Gating
0: Disabled
1: Enabled
Power Good CLK Enabling
0 = Disabled
1 = Enabled
DISCHG
Active discharge bit Enabling
0 = Discharge path disabled
1 = Discharge path enabled
SLEEP_MODE Sleep mode
0 = Low Iq mode when EN low
1 = Force product in sleep mode
PWM
Operating mode selection
0 = Auto
1 = Forced PWM
DVSMODE
DVS transition mode selection
0 = Auto
1 = Forced PWM
Table 19. TIMING REGISTER
Name: TIME
Address: 0Bh
Default: See Register Map
Type: RW
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
DELAY[1..0]
Bit
F_SPREAD[1..0]
DVS[1..0]
Bit Description
DBN_Time[1..0]
DBN_Time[1..0]
EN debounce time
00 = 1 − 2 ms
01 = 1 − 2 ms
10 = 2 − 3 ms
11 = 3 − 4 ms
DVS[1..0]
DVS Speed
00 = 10 mV step / 0.465 ms
01 = 10 mV step / 0.930 ms
10 = 10 mV step / 1.860 ms
11 = 10 mV step / 3.720 ms
F_SPREAD[1..0]
DELAY[1..0]
Spread Spectrum
00 = No Spread Spectrum
01 = 5 % spread spectrum
10 = 10 % spread spectrum
11 = 10 % spread spectrum
Delay applied upon enabling (ms)
00b = 0 ms – 11b = 6 ms (Steps of 2 ms)
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30
NCV91300
Table 20. LIMITS CONFIGURATION REGISTER
Name: LIMCONF
Type: RW
Address: 0Ch
Default: See Register Map
Trigger: N/A
D7
D6
D5
D4
D3
D2
D1
D0
IPEAK[1..0]
Bit
TPWTH[1..0]
ROBUSTI2C
FORCERST
RSTSTATUS
REARM
Bit Description
REARM
Rearming of device after TSD / ISHORT
0: No re−arming after TSD / ISHORT
2
1: Re−arming active after TSD / ISHORT with no reset of I C registers: FPUS (Fast power up sequence) is
2
initiated with previously programmed I C registers values
RSTSTATUS
FORCERST
TPWTH[1..0]
Reset Indicator Bit
0: Must be written to 0 after register reset
1: Default (loaded after Registers reset)
Force Reset Bit
0 = Default value. Self−cleared to 0
1: Force reset of internal registers to default
Thermal pre−Warning threshold settings
00 = 110°C
01 = 120°C
10 = 130°C
11 = 140°C
2
ROBUSTI2C
IPEAK
I C protocol setting
2
0: Classic I C protocol
1: Double write access I C protocol
2
Inductor peak current settings
00 = 3.0 A (for 2.0 A output current)
01 = 3.5 A (for 2.5 A output current)
10 = 4.0 A (for 3.0 A output current)
11 = 4.5 A (for 3.5 A output current)
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31
NCV91300
APPLICATION INFORMATION
NCV91300
Supply Input
AVIN
PVIN
BOOT
SW
Power Supply Input
4.7 mF
Core
AGND
10 mF
10 nF
DCDC
3.0 A
Thermal
Protection
Modular
Driver
1.0 mH
2x 10 mF
EN
Enable Control
Input
Enabling
Test / I@C
Clocking
AGND
PGND
FB
SCL
AGND
I@C BUS
SDA
SYNC
Output
DCDC
External Clock
Power Good
Processor
Core
PG
Monitoring
2.15 MHz
Controller
Sense
INTB
Interrupt
Interrupt
Figure 61. Typical Application Schematic
Output Filter Considerations
Components Selection
The output filter introduces a double pole in the system at
a frequency of:
Inductor Selection
The inductance of the inductor is chosen such that the
peak−to−peak ripple current I is approximately 20% to
1
L_PP
fLC
+
(eq. 1)
Ǹ
2 p L C
50% of the maximum output current I
. This
OUT_MAX
provides the best trade−off between transient response and
output ripple. The inductance corresponding to a given
current ripple is:
The NCV91300 internal compensation network is
optimized for a typical output filter comprising a 1.0 mH
inductor and 10 mF capacitor as describes in the basic
application schematic in Figure 61.
(VIN * VOUT) VOUT
L +
(eq. 2)
VIN fSW IL_PP
Voltage Sensing Considerations
In order to regulate the power supply rail, the NCV91300
must sense its output voltage. The IC can support two
sensing methods:
The selected inductor must have a saturation current
rating higher than the maximum peak current which is
calculated by:
• Normal sensing: The FB pin should be connected to the
IL_PP
IL_MAX + IOUT_MAX
)
output capacitor positive terminal (voltage to regulate).
(eq. 3)
2
• Remote sensing: The power supply rail sense should be
made close to the system powered by the NCV91300. The
voltage to the system is more accurate, since the PCB line
impedance voltage drop is within the regulation loop. In
this case, we recommend connecting the FB pin to the
system decoupling capacitor positive terminal.
The inductor must also have a high enough current rating
to avoid self−heating. A low DCR is therefore preferred.
Refer to Table 21 for recommended inductors.
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32
NCV91300
Table 21. INDUCTOR SELECTION
Size (L x l x T)
Saturation
Current Max (A)
DCR Max at 255C
(mW)
(mm)
Supplier
TDK
Part #
Value (mH)
TFM252012ALMA1R0MTAA
DFE2HCAH1R0MJ0
1.0
1.0
1.0
1.0
1.0
2.5 x 2.0 x 1.2
2.5 x 2.0 x 2.0
3.2 x 2.5 x 1.2
3.2 x 2.5 x 2.0
4.0 x 4.0 x 2.1
4.2
3.8
4.6
7.5
8.7
42
42
Murata
TDK
TFM322512ALMA1R0MTAA
DFE322520D−1R0MP2
XAL4020−102ME
37
Murata
CoilCraft
21
14.6
LESL
Output Capacitor Selection
VOUT_PP(ESL)
+
VIN
The output capacitor selection is determined by output
voltage ripple and load transient response requirement. For
high transient load performance a high output capacitor
value must be used. For a given peak−to−peak ripple current
L
Where the peak−to−peak ripple current is given by
(VIN * VOUT) VOUT
IL_PP
)
VIN fSW L
I
in the inductor of the output filter, the output voltage
L_PP
ripple across the output capacitor is the sum of three
components as shown below.
In applications with all ceramic output capacitors, the
main ripple component of the output ripple is V
The minimum output capacitance can be calculated based on
.
OUT_PP(C)
VOUT_PP [ VOUT_PP(C) ) VOUT_PP(ESR) ) VOUT_PP(ESL)
(eq. 4)
a given output ripple requirement V
operation mode.
in PWM
OUT_PP
With:
IL_PP
IL_PP
VOUT_PP(C)
+
CMIN
+
8 C fSW
(eq. 5)
8 VOUT_PP fSW
VOUT_PP(ESR) + IL_PP ESR
Refer to Table 22 for recommended output capacitor.
Table 22. OUTPUT CAPACITOR SELECTION
Supplier
TDK
Part #
Value (mF)
10.0
Case
0805
0805
Size (L x l x T) (mm)
2.0 x 1.25 x 1.25
2.0 x 1.25 x 1.25
CGA4J1X7R0J106K125AC
GCM21BR70J106KE22#
Murata
10.0
Input Capacitor Selection
The input capacitor also must be sufficient to protect the
device from over voltage spikes, and a 10 mF capacitor or
greater is required. The input capacitor should be located as
close as possible to the IC. All PGND pins must be
connected together to the ground terminal of the input cap
which then must be connected to the ground plane. All PVIN
pins must be connected together to the Vbat terminal of the
input cap which then connects to the Vbat plane.
In addition to the proper input capacitor selection, and in
order to damp the ringing effects due to the switching
activity, an RC snubber network can be placed between the
switch node (SW) and the power ground (PGND), which is
of particular interest in applications operating at high input
One of the input capacitor selection requirements is the
input voltage ripple. To minimize the input voltage ripple
and get better decoupling at the input power supply rail, a
ceramic capacitor is recommended due to low ESR and ESL.
The minimum input capacitance with respect to the input
ripple voltage V
is
IN_PP
IOUT_MAX (D * D2)
CIN_MIN
+
(eq. 6)
VIN_PP fSW
Where
VOUT
VIN
D +
voltage levels at P
VIN.
In addition, the input capacitor must be able to absorb the
input current, which has a RMS value of
Refer to Table 23 for recommended input capacitor.
Ǹ
D * D2
IIN_RMS + IOUT_MAX
(eq. 7)
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33
NCV91300
Table 23. INPUT CAPACITOR SELECTION
Supplier
TDK
Part #
Value (mF)
10.0
Case
0805
0805
0805
0805
Size (L x l x T) (mm)
2.0 x 1.25 x 1.60
2.0 x 1.25 x 1.60
2.0 x 1.25 x 1.25
2.0 x 1.25 x 1.25
CGA5L1X7R1E106K160AC
GCM31CR71C106KA64#
CGA4J1X7R0J106K125AC
GCM21BR70J106KE22#
Murata
TDK
10.0
10.0
Murata
10.0
Power Capability and Thermal consideration
The difference in temperature between the junction (T )
Example:
Assuming 3.3 V input voltage and a 1.8 V / 2 A DC output,
the efficiency, according to Figure 8, is 82%.
Then the total dissipated power
J
and ambient (T ), the NCV91300 junction−to−ambient
thermal resistance in the application and the on−chip power
A
dissipation (P ) drive the NCV91300’s power capability.
IC
ǒ1 Ǔ + 790 mW.
PT + VOUT IOUT
* 1
h
The on−chip power dissipation P can be determined as
IC
PIC + PT * PL
(eq. 8)
The TDK TFM252012ALMA1R0MTAA inductor DCR is
comprised between 35 mW (Typical) and 42 mW (max), so
the power dissipated in the inductor
with the total power losses P being
T
ǒ1 Ǔ
2
PT + VOUT IOUT
* 1
h
PL + ILOAD DCR
is within the 168 mW to 140 mW range, giving about
622 mW to 650 mW dissipated in the NCV91300.
Then, the expected junction temperature for a NCV91300
on its standard demo board placed at 125°C ambient
temperature in a natural airflow environment
where h is the efficiency and P the simplified inductor
power losses
L
2
PL + ILOAD DCR.
Now the junction temperature T can easily be calculated
J
as
(TJ + RqJA PIC ) TA)
TJ + RqJA PIC ) TA
(eq. 9)
is in the 149°C range.
To avoid irreversible damage and overheating, the
Thermal Shut Down (TSD) of the NCV91300 will stop the
power stage switching activity as soon as the die temperature
rises up to the 170°C TSD threshold. The dissipation in the
power stage mainly depends on the losses in the HSS (High
Side Switch) and LSS (Low Side Switch) and is then directly
function of the loading current. The NCV91300
specification is guaranteed for a maximum Junction
A thermal simulation of the NCV91300 on the application
board in a 125°C ambient temperature and natural airflow
shows that the above prediction is accurate (~1% error):
Temperature (T
) of 150°C. When the junction
J_MAX
temperature ranges from 150°C to the TSD threshold, the IC
will still operate and will not be damaged, but the
specifications are not guaranteed and the parameters value
may deviate significantly. It is then important to try to keep
the T ≤ 150°C. The THERMAL INFORMATION table
J
provides the thermal parameters (R ) defined by the
qJx
JEDEC JESD51−3 as well as some thermal characterization
parameters. The thermal characterization parameters are the
result of measurements on the standard NCV91300 demo
board, while the thermal parameters are the result of
simulations in the JESD51 defined environment.
The junction−to−ambient thermal resistance is a function
of the PCB layout (number of layers and copper and PCB
size) and the environment. For example, the NCV91300
Figure 62. Simulation of the Die Temperature
(P = 650 mW / ambient T5 = 1255C)
IC
mounted on the EVB has an R
about 38°C/W.
qJAm
www.onsemi.com
34
NCV91300
Based on this model, a maximum power dissipation
versus temperature is given by the Table 24:
Table 24. MAXIMUM POWER DISSIPATION VERSUS EXTERNAL TEMPERATURE
NCV91300 Internal Dissipation (mW)
500
44.1
123
142
600
47.8
126
146
650
49.6
128
147
700
51.5
130
149
800
55.2
133
153
900
58.8
137
156
1000
62.5
140
1100
66.2
143
1200
69.8
147
1300
73.4
150
1400
77.1
154
1500
80.7
157
2000
98.8
175
Ambient Temperature(T ) 25°C
A
Ambient Temperature(T ) 105°C
A
Ambient Temperature(T ) 125°C
159
163
166
170
173
177
A
Layout Considerations
Switching Noise Consideration
VIN
AVIN
PVIN
SW
LOGIC,
CONTROL,
BIASING …
FB
Power Stage
Drivers
PGND
AGND
PGND
AGND
Connect A
& P
GND
in one point
GND
I
I
1
2
I
L
= I + I
1 2
Figure 63. AC Current Flowing Loops
and end of the active time. These sharp edges have fast
rise and fall times (high dI/dt). Therefore they have a lot
of high frequency content.
• The DC/DC buck converter has two main loops where
high AC currents flow.
• When the High−Side Switch (HSS) is on, the current
flows from PVIN via HSS and L to the output capacitor
and the load. The current flows back via ground to the
input. The AC portion of the current will flow via the
input and output capacitors. This current is shown in red
color (I1).
• I1 and I2 share a common path from switch node to
inductor to output capacitor to ground back to the source
of LSS. The sum of I1 and I2 is a relatively smooth
continuous saw−tooth waveform, which has less high
frequency content due to the absence of high dI/dt edges.
• From noise point of view, the current loop with the high
dI/dt current is the red shaded area. This loop will
generate the most high frequencies and should be
considered the most critical loop for noise in buck
converters. The dI/dt of the current in the blue shaded area
is not as high as it is in the other area and generally
generates a lot less noise.
• When HSS switches off, the inductor current will keep
flowing in the same direction, and the Low−Side Switch
(LSS) is switched on. The current flows via LSS, L, load
and output capacitor and back via ground to LSS. This
loop is shown in blue (I2).
• Both I1 and I2 are discontinuous currents, meaning that
they have sharp rising and falling edges at the beginning
www.onsemi.com
35
NCV91300
Electrical Rules
point. Directly connect AGND pin to the exposed pad and
then connect to AGND ground plane through vias. Try
best to avoid overlap of input ground loop and output
ground loop to prevent noise impact on output regulation.
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
• Since the red shaded area is the noisiest loop, it is critical
to identify it and to place the input cap in such a way that
this loop is minimized. It is also important to make sure
that the path between the 2 terminals of the input cap and
the PVIN & PGND pins is as short as possible and free of
any vias to either the VIN or the GND PCB plane. It can
also be a good practice to make a local PGND and VIN
planes and to keep those planes as solid as possible below
and in the input switching loop. Any trace or vias in this
area reduces the plane effectiveness and increase the
plane impedance. Vias from these planes to the other main
planes of the PCB should be placed outside of the critical
loop.
• Arrange a “quiet” path for output voltage sense, and make
it surrounded by a ground plane.
Thermal Rules
Good PCB layout improves the thermal performance and
thus allows for high power dissipation even with a small IC
package. Thermal layout guidelines are:
• A four or more layers PCB board with solid ground planes
is preferred for better heat dissipation.
• Use multiple vias around the IC to connect the inner
ground layers to reduce thermal impedance.
• Use a large and thick copper area especially in the top
layer for good thermal conduction and radiation.
• Use two layers or more for the high current paths (PVIN,
PGND, SW) in order to split current into different paths
and limit PCB copper self−heating.
• Also, it is important to place the output capacitor ground
in an area that does not overlap the input capacitor
switching loop : this could generate extra high frequency
noise in the output voltage
• Connecting the PGND plane to the main PCB GND plane
(to whitch the AGND pin should be connected too) in one
point (doing a kind of “star routing”) is also important to
isolate the AGND and keep them quiet.
Component Placement
• Input capacitor placed as close as possible to the IC.
• PVIN directly connected to Cin input capacitor, and then
connected to the Vin plane. Local mini planes used on the
top layer and the layer just below the top layer with laser
vias.
• Use wide and short traces for power paths (such as P
,
VIN
V
OUT
, SW, and PGND) to reduce parasitic inductance and
• AVIN connected to the Vin plane just after the capacitor.
• AGND directly connected to the GND plane.
high−frequency loop area. It is also good for efficiency
improvement.
• PGND directly connected to Cin input capacitor, and then
connected to the GND plane: Local mini planes used on
the top layer and the layer just below the top layer with
laser vias.
• The device should be well decoupled by input capacitor
and input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission.
• SW connected to the Lout inductor with local mini planes
on the top layer and the layer just below the top layer The
2 local mini planes are connected together by laser vias.
• SW node should be a large copper pour, but compact
because it is also a noise source.
• It would be good to have separated local ground planes for
PGND and AGND and connect the two planes at one
www.onsemi.com
36
NCV91300
Figure 64. Placement Recommendation
Figure 65. Layout Example
ORDERING INFORMATION
Specific Device
Default
Voltage
Default Max
Current
†
Marking
Device Order Number
Default Mode
Package Type
Shipping
NCV91300MNWBTXG
W3
1.1 V
2.5 A
Forced PWM QFNW16 3x3, 0.5P
TBD
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
13.For full details about the configurations, refer to Table 5
www.onsemi.com
37
NCV91300
PACKAGE DIMENSIONS
QFNW16 3x3, 0.5P
CASE 484AL
ISSUE A
EXPOSED
COPPER
www.onsemi.com
38
NCV91300
2
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