NFAL5012L5B [ONSEMI]
Intelligent Power Module, SPM49, 1200 V, 50A;
| 型号： | NFAL5012L5B |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent Power Module, SPM49, 1200 V, 50A |
| 文件： | 总15页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPM 49 Series
Smart Power Module (SPM)
Inverter, 1200 V, 50 A
NFAL5012L5B
General Description
The NFAL5012L5B is a smart power module providing
a fully−featured, high−performance inverter output stage for AC
induction, BLDC, and PMSM motors. These modules integrate
optimized gate drive of the built−in IGBTs to minimize EMI and
losses, while also providing multiple on−module protection features:
under−voltage lockouts, over−current shutdown, temperature sensing,
and fault reporting. The built−in, high−speed HVIC requires only
a single supply voltage and translates the incoming logic−level gate
inputs to high−voltage, high−current drive signals to properly drive the
module’s internal IGBTs. Separate negative IGBT terminals are
available for each phase to support the widest variety of control
algorithms.
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Features
• 1200 V – 50 A 3−Phase IGBT Inverter, Including Control ICs
for Gate Drive and Protections
• Low−Loss, Short−Circuit-Rated IGBTs
• Very Low Thermal Resistance Using Al O DBC Substrate
2
3
3D Package Drawing
(Click to Activate 3D Content)
• Built−In Bootstrap Diodes/Resistors
• Separate Open-Emitter Pins from Low−Side IGBTs for
SPM49−CAA
CASE MODGR
Three−Phase Current Sensing
• Adjustable Over−Current Protection via Integrated Sense−IGBTs
• Isolation Rating of 2500 Vrms/1 min
• These Devices are RoHS Compliant
MARKING DIAGRAM
Typical Applications
• Motion Control − Industrial Motor (AC 400 V Class)
NFAL5012L5B
ZZZ ATYWW
Integrated Power Functions
ON
• 1200 V – 50 A IGBT Inverter for Three−Phase DC/AC Power
Conversion (Refer to Figure 2)
NNNNNNN
Integrated Drive, Protection, and System Control Functions
• For Inverter High−Side IGBTs: gate−drive circuit, high−voltage
isolated high−speed level−shifting control circuit, Under−Voltage
Lock−Out protection (UVLO), available bootstrap circuit example is
given in Figures 4 and 15
• For Inverter Low−Side IGBTs: gate−drive circuit, Short−Circuit
Protection (SCP) control circuit, Under−Voltage Lock−Out protection
(UVLO)
NFAL5012L5B
ZZZ
AT
Y
WW
NNNNNNN
= Specific Device Code
= Lot ID
= Assembly & Test Location
= Year
= Work Week
= Serial Number
• Fault Signaling: corresponding to UV (low−side supply) and
SC faults
• Input Interface: active−HIGH interface, works with 3.3 V/5 V logic,
Schmitt−trigger input
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
April, 2020 − Rev. 0
NFAL5012L5B/D
NFAL5012L5B
PIN CONFIGURATION
(30) LIN(W)
(29) LIN(V)
(28) LIN(U)
(27) VFO
NW (1)
(26) CFOD
(25) CIN
NV (2)
NU (3)
(24) VTS
(23) VSS(L)
(22) VDD(L)
(21) RSC
(20) VS(W)
(19) VB(W)
W (4)
Case Temperature (Tc)
Detecting Point
(18) VSS(H)
(17) VDD(WH)
(16) HIN(W)
V (5)
U (6)
P (7)
(15) VS(V)
(14) VB(V)
(13) VDD(VH)
(12) HIN(V)
(11) VS(U)
(10) VB(U)
(9) VDD(UH)
(8) HIN(U)
17.15
Figure 1. Pin Configuration − Top View
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NFAL5012L5B
PIN DESCRIPTION
Pin Number
Pin Name
NW
Pin Description
1
Negative DC−Link Input for W Phase
Negative DC−Link Input for V Phase
Negative DC−Link Input for U Phase
Output for W Phase
2
NV
3
NU
4
W
5
V
Output for V Phase
6
U
Output for U Phase
7
P
Positive DC−Link Input
8
HIN(U)
VDD(UH)
VB(U)
VS(U)
HIN(V)
VDD(VH)
VB(V)
VS(V)
HIN(W)
VDD(WH)
VSS(H)
VB(W)
VS(W)
RSC
Signal Input for High−Side U Phase
High−Side Bias Voltage for U Phase IC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
High−Side Bias Voltage for U Phase IGBT Driving
High−Side Bias Voltage GND for U Phase IGBT Driving
Signal Input for High−Side V Phase
High−Side Bias Voltage for V Phase IC
High−Side Bias Voltage for V Phase IGBT Driving
High−Side Bias Voltage GND for V Phase IGBT Driving
Signal Input for High−Side W Phase
High−Side Bias Voltage for W Phase IC
High−Side Common Supply Ground, connected to HVIC
High−Side Bias Voltage for W Phase IGBT Driving
High−Side Bias Voltage GND for W Phase IGBT Driving
Resistor for Over and Short−Circuit Current Detection
Low−Side Bias Voltage for IC and IGBTs Driving
Low−Side Common Supply Ground, connected to LVIC
Voltage Output for LVIC Temperature Sensing Unit
Input for Current Protection
VDD(L)
VSS(L)
VTS
CIN
CFOD
VFO
Capacitor for Fault Output Duration Selection
Fault Output
LIN(U)
LIN(V)
LIN(W)
Signal Input for Low−Side U Phase
Signal Input for Low−Side V Phase
Signal Input for Low−Side W Phase
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3
NFAL5012L5B
INTERNAL EQUIVALENT CIRCUIT AND INPUT/OUTPUT PINS
P (7)
(10) VB(U)
VB
OUT
VS
VDD
VSS
(9) VDD(UH)
HVIC
HVIC
HVIC
(8) HIN(U)
(11) VS(U)
IN
U (6)
(14) VB(V)
VB
OUT
VS
(13) VDD(VH)
VDD
VSS
IN
(12) HIN(V)
(15) VS(V)
V (5)
(19) VB(W)
VB
OUT
VS
VDD
VSS
IN
(17) VDD(WH)
(18) VSS(H)
(16) HIN(W)
(20) VS(W)
W (4)
VTS
(24) VTS
OUT1
OUT2
(25) CIN
(26) CFOD
(27) VFO
CIN
NU (3)
CFOD
VFO
LVIC
(28) LIN(U)
(29) LIN(V)
(30) LIN(W)
(22) VDD(L)
(23) VSS(L)
IN1
IN2
NV (2)
IN3
VDD
OUT3
VSS
NW (1)
(21) RSC
NOTES:
1. Inverter high−side is composed of three normal−IGBTs, freewheeling diodes, and one control IC for each IGBT.
2. Inverter low−side is composed of three sense−IGBTs, freewheeling diodes, and one control IC for each IGBT. It has gate drive and
protection functions.
3. Inverter power side is composed of four inverter DC−link input terminals and three inverter output terminals.
Figure 2. Internal Block Diagram
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NFAL5012L5B
ABSOLUTE MAXIMUM RATINGS (Tj = 25°C unless otherwise noted)
Symbol
Rating
Conditions
Rating
Unit
INVERTER PART
VPN
VPN(surge)
Vces
Supply Voltage
Applied between P − NU, NV, NW
Applied between P − NU, NV, NW
900
1000
1200
50
V
V
V
A
A
Supply Voltage (Surge)
Collector−Emitter Voltage
Ic
Each IGBT Collector Current
Each IGBT Collector Current (Peak)
Tc = 25°C, Tj ≤ 150°C
Icp
Tc = 25°C, Tj ≤ 150°C, Under 1 ms
Pulse Width (Note 4)
100
Pc
Collector Dissipation
Tc = 25°C per One Chip (Note 4)
219
W
Tj
CONTROL PART
VDD
Operating Junction Temperature
−40~150
°C
Control Supply Voltage
Applied between VDD(H), VDD(L) − VSS
20
20
V
V
VBS
High−Side Control Bias Voltage
Applied between VB(U) − VS(U),
VB(V) − VS(V), VB(W) − VS(W)
VIN
Input Signal Voltage
Applied between HIN(U), HIN(V), HIN(W),
LIN(U), LIN(V), LIN(W) − VSS
−0.5~VDD+0.5
V
VFO
IFO
VCIN
Tj
Fault Output Supply Voltage
Fault Output Current
Applied between VFO − VSS
Sink Current at VFO pin
−0.5~VDD+0.5
5
V
mA
V
Current Sensing Input Voltage
Operating Junction Temperature
Applied between CIN − VSS
−0.5~VDD+0.5
−40~150
°C
BOOSTSTRAP DIODE PART
VRRM
Maximum Repetitive Reverse
1200
V
Voltage
Tj
Operating Junction Temperature
−40~150
°C
TOTAL SYSTEM
VPN(PROT)
Self−Protection Supply Voltage Limit
(Short−Circuit Protection Capability)
VDD = VBS = 13.5~16.5 V, Tj = 150°C,
Vces < 1200 V, Non-Repetitive, < 2 ms
800
V
Tc
Module Case Operation
Temperature
See Figure 1
−40~125
°C
Tstg
Viso
Storage Temperature
Isolation Voltage
−40~125
2500
°C
60 Hz, Sinusoidal, AC 1 Minute, Connection
Pins to Heat Sink Plate
Vrms
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. These values had been made an acquisition by the calculation considered to design factor.
THERMAL RESISTANCE
Symbol
Rth(j-c)Q
Rth(j-c)F
Parameter
Conditions
Min
−
Typ
−
Max
0.57
1.15
Unit
°C/W
°C/W
Junction−to−Case Thermal
Resistance (Note 5)
Inverter IGBT Part (per 1/6 module)
Inverter FWDi Part (per 1/6 module)
−
−
5. For the measurement point of case temperature (Tc), please refer to Figure 1. DBC discoloration and Picker Circle Printing allowed, please
®
refer to application note AN−9190 (Impact of DBC Oxidation on SPM Module Performance).
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NFAL5012L5B
ELECTRICAL CHARACTERISTICS (Tj = 25°C unless otherwise specified.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
INVERTER PART
VCE(sat)
Collector−Emitter
Saturation Voltage
VDD = VBS = 15 V
IN = 5 V
Ic = 50 A, Tj = 25°C
Ic = −50 A, Tj = 25°C
−
2.00
2.50
V
VF
FWDi Forward Voltage
Switching Times
IN = 0 V
−
1.10
−
2.30
1.70
0.25
1.50
0.15
0.25
1.60
0.25
1.40
0.15
0.25
−
2.90
2.30
0.55
2.10
0.45
−
V
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
mA
HS
ton
tc(on)
toff
VPN = 600 V, VDD = 15 V, Ic = 50 A
Tj = 25°C
IN = 0 V ´ 5 V, Inductive Load
See Figure 3
−
(Note 6)
tc(off)
trr
−
−
LS
ton
VPN = 600 V, VDD = 15 V, Ic = 50 A
Tj = 25°C
1.00
−
2.20
0.55
2.00
0.45
−
tc(on)
toff
IN = 0 V ´ 5 V, Inductive Load
See Figure 3
−
(Note 6)
tc(off)
trr
−
−
Ices
Collector−Emitter Leakage
Current
Vce = Vces
−
1
CONTROL PART
IQDDH
Quiescent VDD Supply
Current
VDD(UH,VH,WH) = 15 V,
HIN(U,V,W) = 0 V
VDD(UH) − VSS(H),
VDD(VH) − VSS(H),
VDD(WH) − VSS(H)
−
−
0.30
mA
IQDDL
IPDDH
VDD(L) = 15 V,
LIN(U,V,W) = 0 V
VDD(L) − VSS(L)
−
−
−
−
3.50
0.40
mA
mA
Operating VDD Supply
Current
VDD(UH,VH,WH) = 15 V,
FPWM = 20 kHz,
VDD(UH) − VSS(H),
VDD(VH) − VSS(H),
Duty = 50%, Applied to one VDD(WH) − VSS(H)
PWM Signal
Input for High−Side
IPDDL
VDD(L) = 15 V,
VDD(L) − VSS(L)
−
−
7.50
mA
FPWM = 20 kHz,
Duty = 50%, Applied to one
PWM Signal Input for
Low−Side
IQBS
IPBS
Quiescent VBS Supply
Current
VDD = VBS = 15 V,
HIN(U,V,W) = 0 V
VB(U) − VS(U),
VB(V) − VS(V),
VB(W) − VS(W)
−
−
−
−
0.30
6.50
mA
mA
Operating VBS Supply
Current
VDD = VBS = 15 V,
FPWM = 20 kHz,
VB(U) − VS(U),
VB(V) − VS(V),
Duty = 50%, Applied to one VB(W) − VS(W)
PWM Signal Input for
High−Side
VFOH
Fault Output Voltage
VDD = 15 V, CIN = 0 V,
4.90
−
−
V
VFO Circuit: 10 kW to 5 V Pull−up
VFOL
ISEN
VDD = 15 V, CIN = 1 V, IFO = 1 mA
−
−
−
0.95
−
V
Sensing Current of Each
Sense IGBT
VDD = 15 V, LIN = 5 V,
Rsc = 0 W,
Ic = 50 A
22
mA
No Connection of Shunt
Resistor at NU, NV, NW
Terminal
VSC(ref)
ISC
Short Circuit Trip Level
VDD = 15 V
CIN − VSS(L)
0.46
75
0.48
−
0.50
−
V
A
Short Circuit Current Level
for Trip
Rsc = 18 W ( 1%), No Connection of Shunt
Resistor at NU, NV, NW Terminal (Note 7)
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NFAL5012L5B
ELECTRICAL CHARACTERISTICS (Tj = 25°C unless otherwise specified.) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CONTROL PART
UVDDD
UVDDR
UVBSD
UVBSR
VIN(ON)
VIN(OFF)
VTS
Supply Circuit Under−Voltage Detection Level
10.3
10.8
10.0
10.5
−
−
12.5
13.0
12.0
12.5
2.6
V
V
V
V
V
V
V
Protection
Reset Level
−
Detection Level
Reset Level
−
−
−
ON Threshold Voltage
OFF Threshold Voltage
Applied between HIN(U,V,W) − VSS(H),
LIN(U,V,W) − VSS(L)
0.8
−
−
Voltage Output for LVIC
Temperature Sensing Unit
VDD(L) = 15 V, TLVIC = 25°C
See Figure 6 and 7 (Note 8)
0.909
1.030
1.151
tFOD
Fault-Out Pulse Width
CFOD = 22 nF (Note 9)
1.6
−
−
ms
BOOTSTRAP DIODE/RESISTOR PART
VF
Forward Voltage
If = 0.1 A, Tj = 25°C
See Figure 8
2.1
2.5
2.9
V
RBOOT
Bootstrap Resistor
12.5
15.5
18.5
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. ton and toff include the propagation delay of the internal drive IC. tc(on) and tc(off) are the switching times of IGBT under the given gate-driving
condition internally. For the detailed information, please see Figure 3.
7. Short-circuit current protection functions only at the low-sides because the sense current is divided from main current at low-side IGBTs.
Inserting the shunt resistor for monitoring the phase current at NU, NV, NW terminal, the trip level of the short-circuit current is changed.
8. TLVIC is the temperature of LVIC itself. VTS is only for sensing temperature of LVIC and cannot shutdown IGBTs automatically. The
relationship between VTS voltage output and LVIC temperature is described in Figure 6. It is recommended to add a ceramic capacitor of
10 nF or more between VTS and VSS (Signal Ground) to make the VTS more stable as described in Figure 7. Refer to the application note
for this products about usage of VTS.
9. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation:
6
tFOD = 0.1 × 10 × CFOD [s].
100% Ic 100% Ic
trr
Vce
Ic
Ic
Vce
VIN
VIN
ton
toff
tc(on)
tc(off)
10% Ic
VIN(ON)
VIN(OFF)
10% Vce
10% Ic
90% Ic 10% Vce
(a) turn-on
(b) turn-off
Figure 3. Switching Time Definition
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NFAL5012L5B
One−Leg Diagram of SPM
IC
P
CBS
VB
OUT
VS
VDD
VSS
IN
LS Switching
VPN
HS Switching
U,V,W
V
Inductor
600V
LS Switching
IN
VDD
VFO
CFOD
CIN
VIN
HS Switching
OUT
5 V
0 V
VDD
V
10 kΩ
VSS
NU, NV, NW
15 V
V
RSC
5 V
Figure 4. Example Circuit of Switching Test
Inductive Load, VPN = 600 V, VDD = 15 V, T = 1505C
Inductive Load, VPN = 600 V, VDD = 15 V, T = 255C
j
j
9000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
IGBT Turn−on, Eon
IGBT Turn−off, Eoff
FWD Turn−off, Erec
IGBT Turn−on, Eon
IGBT Turn−off, Eoff
FWD Turn−off, Erec
8000
7000
6000
5000
4000
3000
2000
1000
0
0
5
10
15
20
25
30
35
40
45
50
55
0
5
10
15
20
25
30
35
40
45
50
55
Collector Current, Ic [A]
Collector Current, Ic [A]
Figure 5. Switching Loss Characteristics
4.0
3.5
3.0
2.5
2.0
1.5
1.0
2.687
2.566
2.445
40
45
50
55
60
65
70
75
80
85
90
95 100 105 110 115 120 125 130
LVIC Temperature (5C)
Figure 6. Temperature Profile of VTS
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NFAL5012L5B
VDD
VDD
A/D
Temperature
Sensing
Voltage
2.5 kW
VTS
+
−
> 10 nF is
recommended
MCU
100 kW
5.2 V
2.5 kW
GND
SPM
VSS
Figure 7. Internal Block Diagram and Interface Circuit of VTS
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.05
0.04
0.03
0.02
0.01
0.00
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VF [V]
VF [V]
Figure 8. Characteristics of Bootstrap Diode/Resistor (Right Figure is Enlarged Figure)
RECOMMENDED OPERATING RANGES
Symbol
VPN
Parameter
Supply Voltage
Conditions
Applied between P−NU, NV, NW
Min
Typ
600
Max
800
Unit
350
V
V
V
VDD
Control Supply Voltage Applied between VDD(UH,VH,WH)−VSS(H), VDD(L)−VSS(L) 13.5
15.0
15.0
16.5
18.5
VBS
High−Side Control Bias Applied between VB(U)−VS(U), VB(V)−VS(V), VB(W)−VS(W) 13.0
Voltage
dVDD/dt, Control Supply Variation
dVBS/dt
−1
−
−
+1
−
V/ms
ms
tdead
Blanking Time for
For Each Input Signal
2.0
Preventing Arm − Short
FPWM
Io
PWM Input Signal
−40°C ≤ Tc ≤ 125°C, −40°C ≤ Tj ≤ 150°C
−
−
−
−
−
−
20
25
kHz
Allowable r.m.s.
Output Current
VPN = 600 V, VDD = VBS = 15 V,
P.F = 0.8, Sinusoidal PWM
Tc ≤ 125°C, Tj ≤ 150°C (Note 10)
FPWM = 5 kHz
FPWM = 15 kHz
Arms
−
14
VSEN
Voltage for Current
Sensing
Applied between NU, NV, NW − VSS
(Including Surge Voltage)
−5.0
+5.0
V
PWIN(ON) Minimum Input Pulse
(Note 11)
1.5
2.0
−
−
−
−
ms
Width
PWIN(OFF)
VDD = VBS = 15 V, Ic ≤ 100 A, Wiring Inductance between
NU, NV, NW and DC Link N < 10 nH (Note 11)
Tj
Junction Temperature
−40
−
+150
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
10.This allowable output current value is the reference data for the safe operation of this product. This may be different from the actual application
and operating condition.
11. This product might not make output response if input pulse width is less than the recommended value.
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NFAL5012L5B
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
NFAL5012L5B
Package
Shipping
NFAL5012L5B
SPM49−CAA
6 Units/Tube
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Device Flatness
Conditions
Min
−50
0.98
10.00
10
Typ
Max
100
1.47
14.98
−
Unit
mm
See Figure 9
−
1.18
12.03
−
Mounting Torque
Mounting Screw: M4
See Figure 10
Recommended 1.18 N ⋅ m
N ⋅ m
kg ⋅ cm
s
Recommended 12.03 kg ⋅ cm
Terminal Pulling Strength
Terminal Bending Strength
Weight
Load 19.6 N
Load 9.8 N, 90 degrees Bend
2
−
−
times
g
−
44.5
−
Figure 9. Flatness Measurement Position
NOTES:
12.Do not over torque when mounting screws. Too much mounting torque may cause DBC cracks, as well as bolts and Al heat−sink
destruction.
13.Avoid one−sided tightening stress. Figure 10 shows the recommended torque order for the mounting screws. Uneven mounting can cause
the DBC substrate of package to be damaged. The pre−screwing torque is set to 20~30% of maximum torque rating.
Figure 10. Mounting Screws Torque Order
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NFAL5012L5B
TIME CHARTS OF SPMs PROTECTIVE FUNCTION
Input Signal
Protection
Circuit State
RESET
a1
SET
RESET
UVDDR
a6
UVDDD
Control
Supply Voltage
a3
a4
a2
a7
Output Current
a5
Fault Output Signal
a1: Control supply voltage rises: after the voltage rises UVDDR, the circuits start to operate when the next input is applied.
a2: Normal operation: IGBT ON and carrying current.
a3: Under−voltage detection (UVDDD).
a4: IGBT OFF in spite of control input condition.
a5: Fault output operation starts with a fixed pulse width according to the condition of the external capacitor CFOD.
a6: Under−voltage reset (UVDDR).
a7: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 11. Under-voltage Protection (Low-side)
Input Signal
Protection
RESET
b1
SET
RESET
Circuit State
UVBSR
b5
UVBSD
Control
Supply Voltage
b3
b4
b6
b2
Output Current
High−level (no fault output)
Fault Output Signal
b1: Control supply voltage rises: after the voltage reaches UVBSR, the circuits start to operate when the next input is applied.
b2: Normal operation: IGBT ON and carrying current.
b3: Under−voltage detection (UVBSD).
b4: IGBT OFF in spite of control input condition, but there is no fault output signal.
b5: Under−voltage reset (UVBSR).
b6: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 12. Under-voltage Protection (High-side)
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NFAL5012L5B
Lower Arms
Control Input
c6
c7
Protection
Circuit state
SET
RESET
c4
Internal IGBT
Gate−Emitter
Input Voltage
c3
c2
Internal delay
at protection circuit
SC current trip level
c1
c8
Output Current
SC reference voltage
Sensing Voltage
of Sense Resistor
RC filter circuit
time constant
delay
c5
Fault Output Signal
(With the external sense resistance and RC filter connection)
c1: Normal operation: IGBT ON and carrying current.
c2: Short−circuit current detection (SC trigger).
c3: All low−side IGBTs gate are hard interrupted.
c4: All low−side IGBTs turn OFF.
c5: Fault output operation starts with a fixed pulse width according to the condition of the external capacitor CFOD.
c6: Input HIGH − IGBT ON state, but during the active period of fault output, the IGBT doesn’t turn ON.
c7: Fault output operation finishes, but IGBT doesn’t turn on until triggering the next signal from LOW to HIGH.
c8: Normal operation: IGBT ON and carrying current.
Figure 13. Short-circuit Current Protection (Low-side Operation Only)
INPUT/OUTPUT INTERFACE CIRCUIT
+5V (MCU or control power)
10 kW
SPM
HIN(U), HIN(V), HIN(W)
LIN(U), LIN(V), LIN(W)
MCU
VFO
VSS
NOTE:
14.RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring impedance of the
application’s printed circuit board. The input signal section of the SPM49 product integrates 5 kW (typ.) pull−down resistor. Therefore, when
using an external filtering resistor, please pay attention to the signal voltage drop at input terminal.
Figure 14. Recommended MCU I/O Interface Circuit
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NFAL5012L5B
P (7)
R1
R1
R1
(8) HIN(U)
(9) VDD(UH)
IN
VDD
VSS
Gating UH
Gating VH
Gating WH
C4
C4
OUT
VS
HVIC
HVIC
(10) VB(U)
(11) VS(U)
VB
U (6)
C3
(12) HIN(V)
(13) VDD(VH)
IN
VDD
VSS
C4
C4
OUT
VS
(14) VB(V)
(15) VS(V)
VB
V (5)
C3
M
(16) HIN(W)
(17) VDD(WH)
(18) VSS(H)
VDC
IN
VDD
VSS
C8
C4
C4
OUT
VS
HVIC
C1 C1 C1
M
C
U
(19) VB(W)
(20) VS(W)
VB
W (4)
C3
5V line
R1
R2
C6
(26) CFOD
(27) VFO
OUT1
CFOD
VFO
IN1
Fault
A
R3
NU (3)
NV (2)
C1
C1
R1
R1
(28) LIN(U)
(29) LIN(V)
(30) LIN(W)
(22) VDD(L)
Gating UL
Gating VL
Gating WL
IN2
OUT2
OUT3
LVIC
R1
R3
IN3
E
15V line
VDD
Shunt
Resistor
C1 C1
C1
Power
GND Line
(23) VSS(L)
(24) VTS
C4
C2
VSS
VTS
Temp.
Monitoring
R3
NW (1)
C7
CIN
R4
RSC (21)
(25) CIN
Sense
Resistor
D
B
C
R5
Control
GND Line
U−Phase Current
V−Phase Current
W−Phase Current
C5
NOTES:
15.To avoid malfunction, the wiring of each input should be as short as possible (less than 2−3 cm).
16.VFO output is an open−drain type. This signal line should be pulled up to the positive side of the MCU or control power supply with a resistor
that makes IFO up to 1 mA. Please refer to Figure 14.
17.Fault out pulse width can be adjusted by capacitor C6 connected to the CFOD terminal.
18.Input signal is active−HIGH type. There is a 5 kW resistor inside the IC to pull−down each input signal line to GND. RC coupling circuits
should be adopted for the prevention of input signal oscillation. R1C1 time constant should be selected in the range 50~150 ns
(recommended R1 = 100 W, C1 = 1 nF).
19.Each wiring pattern inductance of point A should be minimized (recommend less than 10 nH). Use the shunt resistor R3 of surface mounted
(SMD) type to reduce wiring inductance. To prevent malfunction, wiring of point E should be connected to the terminal of the shunt resistor
R3 as close as possible.
20.To insert the shunt resistor to measure each phase current at NU, NV, NW terminal, it makes to change the trip level ISC about the
short-circuit current.
21.To prevent errors of the protection function, the wiring of points B, C, and D should be as short as possible. The wiring of B between CIN
filter and RSC terminal should be divided at the point that is close to the terminal of sense resistor R4.
22.For stable protection function, use the sense resistor R4 with resistance variation within 1% and low inductance value.
23.In the short−circuit protection circuit, select the R5C5 time constant in the range 1.5~2.0 ms. R5 should be selected with a minimum of
10 times larger resistance than sense resistor R4. Do enough evaluation on the real system because short-circuit protection time may
vary wiring pattern layout and value of the R5C5 time constant.
24.Each capacitor should be mounted as close to the pins of the SPM product as possible.
25.To prevent surge destruction, the wiring between the smoothing capacitor C8 and the P & GND pins should be as short as possible. The
use of a high−frequency non−inductive capacitor of around 0.1~0.22 mF between the P & GND pins is recommended.
26.Relays are used in most systems of electrical equipment in industrial application. In these cases, there should be sufficient distance
between the MCU and the relays.
27.The Zener diode or transient voltage suppressor should be adopted for the protection of ICs from the surge destruction between each
pair of control supply terminals (recommended Zener diode is 20~22 V/1 W, which has the lower Zener impedance characteristic than
about 15 W).
28.C2 of around seven times larger than bootstrap capacitor C3 is recommended.
29.Please choose the electrolytic capacitor with good temperature characteristic in C3. Choose 0.1~0.2 mF R−category ceramic capacitors
with good temperature and frequency characteristics in C4.
Figure 15. Typical Application Circuit
SPM is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DIP30, 79x30/SPM49 CAA
CASE MODGR
ISSUE A
DATE 27 JUN 2019
GENERIC
MARKING DIAGRAM*
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ZZZ = Assembly Lot Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
AT
Y
= Assembly & Test Location
= Year
W
= Work Week
NNN = Serial Number
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON98537G
DIP30, 79x30/SPM49 CAA
PAGE 1 OF 1
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