NFAM5065L4BT [ONSEMI]
智能功率模块,SPM31,650 V,50A(NTC 选件);型号: | NFAM5065L4BT |
厂家: | ONSEMI |
描述: | 智能功率模块,SPM31,650 V,50A(NTC 选件) |
文件: | 总10页 (文件大小:288K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Intelligent Power Module
(IPM), 650 V, 50 A
NFAM5065L4BT
General Description
The NFAM5065L4BT is a fully-integrated inverter power module
consisting of an independent High side gate driver, LVIC, six IGBT’s
and a temperature sensor (VTS or Thermistor (T)), suitable for driving
permanent magnet synchronous (PMSM) motors, brushless DC
(BLDC) motors and AC asynchronous motors. The IGBT’s are
configured in a three-phase bridge with separate emitter connections
for the lower legs for maximum flexibility in the choice of control
algorithm.
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The power stage has under voltage lockout protection (UVP).
Internal boost diodes are provided for high side gate boost drive.
Features
• Three-phase 650 V, 50 A IGBT Module with Independent Drivers
• Active Logic Interface
• Built-in Undervoltage Protection (UVP)
• Integrated Bootstrap Diodes and Resistors
• Separate Low-side IGBT Emitter Connections for Individual
Current Sensing of Each Phase
DIP39 54.5 x 31.0
CASE MODGC
MARKING DIAGRAM
• Temperature Sensor (VTS or Thermistor (T))
• UL1557 Certified (File No.339285)
• This Device is Pb−Free and RoHS Compliant
NFAM5065L4BT
ZZZATYWW
Typical Applications
• Industrial Drives
• Industrial Pumps
• Industrial Fans
Device marking is on package top side
• Industrial Automation
NFAM5065L4BT
= Specific Device Code
= Assembly Lot Code
= Assembly Location
= Test Location
ZZZ
A
T
Y
WW
P
U
V
W
RTH VTH
VS(U)
VB(U)
High Side
HVIC1
HS1
HS2
HS3
VDD(UH)
HIN(U)
= Year
= Work Week
VS(V)
VB(V)
High Side
HVIC2
HS1
LS1
HS2
LS2
HS3
LS3
VDD(VH)
HIN(V)
VS(W)
VB(W)
ORDERING INFORMATION
High Side
HVIC3
VDD(WH)
HIN(W)
Device
Package
Shipping
90 / Box
VTS
LIN(U)
LIN(V)
LIN(W)
VFO
NFAM5065L4BT
DIP39
54.5 x 31.0
(Pb-Free)
LS1
LS2
LS3
Low Side
LVIC
with
CFOD
CIN
Protection
VSS
VDD(L)
NU
NV
NW
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
April, 2020 − Rev. 1
NFAM5065L4BT/D
NFAM5065L4BT
APPLICATION SCHEMATIC
5V line
RTH (39)
VTH (38)
* NTC Thermistor
VB(U) (3)
VS(U) (1)
P (37)
CS
+
C1
VB
HIN(U) (6)
HIN
HOUT
HVIC1
VDD(UH) (4)
VDD
VSS
U (36)
V (35)
W (34)
VS
VB(V) (9)
VS(V) (7)
VB
HIN(V) (12)
HIN
HOUT
HVIC2
VDD(VH) (10)
VDD
VSS
VS
Motor
VB(W) (15)
VS(W) (13)
MCU
VB
HIN(W) (18)
HIN
HOUT
HVIC3
VDD(WH) (16)
VDD
VSS
VS
VTS (20)
VTS
OUT(U)
LIN(U) (21)
LIN(V) (22)
LIN(W) (23)
LIN(U)
LIN(V)
LIN(W)
NU (33)
NV (32)
NW (31)
5V line
LVIC
OUT(V)
VFO (24)
CFOD (25)
CIN (26)
VFO
CFOD
CIN
15V line
VDD(L) (28)
VDD
OUT(W)
VSS (27)
VSS
Signal for over current trip
Phase current
Figure 2. Application Schematic − Adjustable Option
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2
NFAM5065L4BT
BLOCK DIAGRAM
RTH (39)
* NTC Thermistor
VTH (38)
P (37)
VS(U) (1)
VB(U) (3)
VB
VDD(UH) (4)
HIN(U) (6)
VDD
HOUT
HVIC1
HVIC2
HVIC3
HIN
VS
VSS
U (36)
V (35)
W (34)
VS(V) (7)
VB(V)(9)
VB
VDD(VH) (10)
HIN(V) (12)
VDD
HOUT
HIN
VS
VSS
VS(W) (13)
VB(W) (15)
VB
VDD(WH) (16)
HIN(W) (18)
VDD
HOUT
HIN
VS
VSS
OUT(U)
VTS
VTS (20)
LIN(U) (21)
LIN(V) (22)
LIN(W) (23)
VFO (24)
LIN(U)
LIN(V)
LIN(W)
NU (33)
NV (32)
NW (31)
OUT(V)
VFO
CFOD
CIN
LVIC
CFOD (25)
CIN (26)
VSS
VDD
VSS (27)
OUT(W)
VDD(L) (28)
Figure 3. Equivalent Block Diagram
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3
NFAM5065L4BT
PIN FUNCTION DESCRIPTION
Pin
1
Name
VS(U)
−
Description
High-Side Bias Voltage GND for U phase IGBT Driving
Dummy
(2)
3
VB(U)
VDD(UH)
−
High-Side Bias Voltage for U phase IGBT Driving
High-Side Bias Voltage for U phase IC
Dummy
4
(5)
6
HIN(U)
VS(V)
−
Signal Input for High-Side U Phase
High-Side Bias Voltage GND for V phase IGBT Driving
Dummy
7
(8)
9
VB(V)
VDD(VH)
−
High-Side Bias Voltage for V phase IGBT Driving
High-Side Bias Voltage for V phase IC
Dummy
10
(11)
12
13
(14)
15
16
(17)
18
(19)
20
21
22
23
24
25
26
27
28
(29)
(30)
31
32
33
34
35
36
37
38
39
HIN(V)
VS(W)
−
Signal Input for High-Side V Phase
High-Side Bias Voltage GND for W phase IGBT Driving
Dummy
VB(W)
VDD(WH)
−
High-Side Bias Voltage for W phase IGBT Driving
High-Side Bias Voltage for W phase IC
Dummy
HIN(W)
−
Signal Input for High-Side W Phase
Dummy
VTS
LIN(U)
LIN(V)
LIN(W)
VFO
CFOD
CIN
Voltage Output for LVIC Temperature Sensing Unit
Signal Input for Low-Side U Phase
Signal Input for Low-Side V Phase
Signal Input for Low-Side W Phase
Fault Output
Capacitor for Fault Output Duration Selection
Input for Current Protection
VSS
VDD(L)
−
Low-Side Common Supply Ground
Low-Side Bias Voltage for IC and IGBTs Driving
Dummy
−
Dummy
NW
Negative DC-Link Input for U Phase
Negative DC-Link Input for V Phase
Negative DC-Link Input for W Phase
Output for U Phase
NV
NU
W
V
Output for V Phase
U
Output for W Phase
P
Positive DC-Link Input
VTH
RTH
Thermistor Bias Voltage (T) / Not connection
Series Resister for Thermistor (Temperature Detection) *optional for T
1. Pins of () are the dummy for internal connection. These pins should be no connection.
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4
NFAM5065L4BT
ABSOLUTE MAXIMUM RATINGS (T = 25°C) (Note 2)
C
Symbol
VPN
Rating
Conditions
Value
450
Unit
V
Supply Voltage
Supply Voltage (Surge)
P−NU, NV, NW
VPN(surge)
VPN(PROT)
P−NU, NV, NW (Note 3)
550
V
Self Protection Supply Voltage Limit
(Short−Circuit Protection Capability)
VDD = VBS = 13.5 V ~16.5 V, T = 150°C,
400
V
J
VCES < 650 V, Non−Repetitive, < 2 ms
Vces
Collector−emitter voltage
650
650
V
V
VRRM
Maximum Repetitive
Revers Voltage
Ic
Iop
Icp
Each IGBT Collector Current
Output current (peak)
30
50
A
A
A
PWM control
Each IGBT Collector
Current (Peak)
Under 1 ms Pulse Width
100
VDD
VBS
Control Supply Voltage
VDD(UH,VH,WH), VDD(L)−VSS
−0.3 to 20
−0.3 to 20
V
V
High−Side
VB(U)−VS(U), VB(V)−VS(V),
VB(W)−VS(W)
Control Bias voltage
VIN
Input Signal Voltage
HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),
LIN(W)–VSS
−0.3 to VDD
V
VFO
IFO
Fault Output Supply Voltage
Fault Output Current
VFO–VSS
−0.3 to VDD
2
V
mA
V
Sink Current at VFO pin
CIN–VSS
VCIN
Current Sensing
Input Voltage
−0.3 to VDD
Pc
Corrector Dissipation
Per One Chip
125
W
°C
T
J
Operating Junction Temperature
Storage temperature
−40 to +150
−40 to +125
−40 to +125
2500
Tstg
Tc
°C
Module Case Operation Temperature
Isolation voltage
°C
V
ISO
60 Hz, Sinusoidal, AC 1 minute,
Connection
Vrms
Pins to Heat Sink Plate
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
3. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal.
THERMAL CHARACTERISTICS
Symbol
Rating
Conditions
Min
−
Typ
−
Max
1.0
Unit
°C/W
°C/W
R
Junction-to-Case Thermal
Resistance
Inverter IGBT Part (per 1/6 module)
Inverter FWD Part (per 1/6 module)
th(j-c)Q
R
−
−
1.7
th(j-c)F
4. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
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5
NFAM5065L4BT
RECOMMENDED OPERATING CONDITIONS (Note 5)
Symbol
VPN
Rating
Supply Voltage
Conditions
P−NU, NV, NW
Min
−
Typ
300
15
Max
400
Unit
V
VDD
Gate Driver Supply
Voltages
VDD(UH,VH,WH), VDD(L)−VSS
13.5
13.0
16.5
18.5
V
VBS
VB(U)−VS(U), VB(V)−VS(V),
15
V
VB(W)−VS(W)
dVDD / dt,
dVBS / dt
Supply Voltage Variation
−1
−
1
V/ms
fPWM
DT
PWM Frequency
Dead Time
1
1.5
−
−
−
−
20
−
kHz
ms
Turn-off to Turn-on (external)
Io
Allowable r.m.s. Current
VPN = 300 V,
VDD = 15 V,
P.F. = 0.8
f
= 5 kHz
30.0
Arms
PWM
Tc ≤ 125°C,
Tj ≤ 150°C
(Note 5)
f
= 15 kHz
−
−
21.2
PWM
PWIN (on)
PWIN (off)
Allowable Input Pulse
Width
200 V ≤ VPN ≤ 400 V
13.5 V ≤ VDD ≤ 16.5 V
13.0 V ≤ VBS ≤ 18.5 V
−20°C ≤ Tc ≤ 100°C
1.0
1.5
0.6
−
−
−
−
ms
Package Mounting Torque
M3 type screw
0.7
0.9
Nm
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Allowable r.m.s current depends on the actual conditions.
6. Flatness tolerance of the heatsink should be within −50 mm to +100 mm.
ELECTRICAL CHARACTERISTICS (T = 25°C, VDD = 15 V, VBS = 15 V, unless otherwise specified.) (Note 7)
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
INVERTERSECTION
Ices
Collector-Emitter Leakage
Current
Vce = Vces, T = 25°C
−
−
−
−
−
1
mA
mA
V
J
Vce = Vces, T = 150°C
10
J
VCE(sat)
Collector-Emitter Saturation
Voltage
VDD = VBS = 15 V, IN = 5 V
1.65
2.30
Ic = 50 A, T = 25°C
J
VDD = VBS = 15 V, IN = 5 V
−
1.85
−
V
Ic = 50 A, T = 150°C
J
VF
FWDi Forward Voltage
IN = 0 V, Ic = 50 A, T = 25°C
−
−
2.00
2.00
1.50
0.40
1.80
0.25
0.25
1.50
0.30
1.70
0.25
0.25
2.40
−
V
J
IN = 0 V, Ic = 50 A, T = 150°C
V
J
ton
tc(on)
toff
Switching Times
High Side VPN = 300 V, VDD(H) = VDD(L) = 15 V
0.90
−
2.10
0.70
2.40
0.75
−
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
Ic = 50 A, T = 25°C, IN = 0 ⇔ 5 V
J
Inductive Load
−
tc(off)
trr
−
−
ton
Low Side
VPN = 300 V, VDD(H) = VDD(L) = 15 V
0.90
−
2.10
0.60
2.30
0.75
−
Ic = 50 A, T = 25°C, IN = 0 ⇔ 5 V
J
tc(on)
toff
Inductive Load
−
tc(off)
trr
−
−
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6
NFAM5065L4BT
ELECTRICAL CHARACTERISTICS (T = 25°C, VDD = 15 V, VBS = 15 V, unless otherwise specified.) (Note 7) (continued)
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DRIVER SECTION
IQDDH
Quiescent VDD Supply
Current
VDD(UH,VH,WH) = 15 V,
HIN(U,V,W) = 0 V
VDD(UH)−VSS
VDD(VH)−VSS
VDD(WH)−VSS
−
−
0.30
mA
IQDDL
IPDDH
VDD(L) = 15 V,
LIN(U,V,W) = 0 V
VDD(L)−VSS
−
−
−
−
3.50
0.40
mA
mA
Operating VCC Supply
Current
VDD(UH,VH,WH) = 15 V,
VDD(UH)−VSS
f
= 20 kHz, Duty = 50%, VDD(VH)−VSS
PWM
Applied to one PWM Signal VDD(WH)−VSS
Input for High-Side
IPDDL
VDD(L) = 15 V,
= 20 kHz, Duty = 50%,
VDD(L)−VSS
−
−
6.00
mA
f
PWM
Applied to one PWM Signal
Input for Low-Side
IQBS
IPBS
Quiescent VBS Supply
Current
VBS = 15 V,
HIN(U,V,W) = 0 V
VB(U)−VS(U)
VB(V)−VS(V)
VB(W)−VS(W)
−
−
−
−
0.30
5.00
mA
mA
Operating VBS Supply
Current
VDD = VBS = 15 V,
VB(U)−VS(U)
f
= 20 kHz, Duty = 50%, VB(V)−VS(V)
PWM
Applied to one PWM Signal VB(W)−VS(W)
Input for High-Side
VIN(ON)
VIN(OFF)
VCIN(ref)
UVDDD
UVDDR
UVBSD
UVBSR
VTS
ON Threshold Voltage
OFF Threshold Voltage
Short Circuit Trip Level
HIN(U,V,W)−VSS, LIN(U,V,W)−VSS
−
−
2.6
−
V
V
V
V
V
V
V
V
0.8
−
0.48
−
VDD = 15 V, CIN−VSS
Detection Level
0.46
10.3
10.8
10.0
10.5
0.905
0.50
12.5
13.0
12.0
12.5
1.155
Supply Circuit
Under-Voltage Protection
Reset Level
−
Detection Level
−
Reset Level
−
Voltage Output for LVIC
Temperature Sensing Unit
VTS−VSS = 10 nF, Temp. = 25°C
1.030
VFOH
VFOL
Fault Output Voltage
VDD = 0 V, CIN = 0 V,
VFO Circuit: 10 kW to 5 V Pull-up
4.9
−
−
−
−
0.95
−
V
V
VDD = 0 V, CIN = 1 V,
VFO Circuit: 10 kW to 5 V Pull-up
t
Fault-Output Pulse Width
CFOD = 22 nF
If = 0.1 A
1.6
2.4
ms
FOD
BOOTSTRAP SECTION
VF
Bootstrap Diode Forward
Voltage
3.4
30
4.6
38
5.8
46
V
RBOOT
Built-in Limiting Resistance
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25_C.
J
A
Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
8. The fault−out pulse width t
depends on the capacitance value of CFOD according to the following approximate equation:
FOD
6
t
= 0.1 × 10 × CFOD (s).
FOD
9. Values based on design and/or characterization.
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7
NFAM5065L4BT
Temperature of LVIC versus VTS Characteristics
4.0
3.5
3.0
2.5
2.0
1.5
1.0
40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130
LVIC Temperature (5C)
Figure 4. Temperature of LVIC versus VTS Characteristics
Table 1. THERMISTOR CHARACTERISTICS (INCLUDED ONLY IN NFAM5060L4BT)
Parameter
Resistance
Symbol
Condition
Min
Typ
Max
Unit
R
Tc = 25°C
46.530
1.344
4009.5
−40
47
1.406
4050
−
47.47
1.471
4090.5
+125
kW
kW
K
25
Resistance
R
Tc = 100°C
125
B-Constant (25−50°C)
Temperature range
−
−
B
−
°C
10000
1000
100
10
min
typ
max
1
−40 −30 −20 −10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
Case Temperature Tc (5C)
Figure 5. Thermistor Resistance versus Case Temperature
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
MINI DIP39, 31.0x54.5
CASE MODGC
ISSUE A
DATE 19 MAR 2019
GENERIC
MARKING DIAGRAM*
XXXXXXXXXXXXXXXXX
ZZZATYWW
XXXXX = Specific Device Code
ZZZ
AT
Y
= Assembly Lot Code
= Assembly & Test Location
= Year
*This information is generic. Please refer to device data
sheet for actual part marking. Pb−Free indicator, “G” or
microdot “G”, may or may not be present. Some products
may not follow the Generic Marking.
WW = Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON91300G
MINI DIP39, 31.0x54.5
PAGE 1 OF 1
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