NFVA35065L42 [ONSEMI]
Intelligent Power Module (IPM), ASPM27-V3, AEC-Q & AQG324, Automotive, Inverter 650V,50A, Fast Switching;
| 型号： | NFVA35065L42 |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent Power Module (IPM), ASPM27-V3, AEC-Q & AQG324, Automotive, Inverter 650V,50A, Fast Switching |
| 文件： | 总14页 (文件大小：1377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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ASPM 27 Series
Automotive 3−Phase 650 V 50 A
Smart Power Module
NFVA35065L42
General Description
®
NFVA35065L42 is an advanced Automotive SPM module
providing a fully−featured, high−performance inverter output stage
for hybrid and electric vehicles. These modules integrate optimized
gate drive of the built−in IGBTs to minimize EMI and losses, while
also providing multiple on−module protection features including
under−voltage lockouts, over−current shutdown, thermal monitoring
of drive IC, and fault reporting. The built−in, high−speed
HVIC requires only a single supply voltage and translates the
incoming logic−level gate inputs to the high−voltage, high−current
drive signals required to properly drive the module’s internal IGBTs.
Separate negative IGBT terminals are available for each phase
to support the widest variety of control algorithms.
3D Package Drawing
(Click to Activate 3D Content)
ASPM27−CCA
CASE MODCB
MARKING DIAGRAM
XX
Features
• Automotive SPM in 27 Pin DIP Package
• AEC & AQG324 Qualified and PPAP Capable
• 650 V/50 A 3−Phase IGBT Inverter with Integral Gate Drivers
and Protections
ON
XX
= onsemi Logo
= Version and Current Rate
• 175°C Guaranteed Short−Circuit Rated FS Trench IGBTs with Low
Vce(sat) and Fast Switching
XXXXXXXXXXXX = Specific Device Code
XXX
Y
WW
0000001
= Lot Number
= Year
= Work Week
= Serial Number
• Outstanding Thermal Resistance Using Al O DBC Substrate
2
3
• Separated Open−Emitter Pins from Low−Side IGBTs for
Three−Phase Current Sensing
• Single−Grounded Power Supply
• LVIC Temperature−Sensing Built−In for Temperature Monitoring
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
• Isolation Rating: 2500 V /1 min.
rms
• Pb−Free and RoHS Compliant
• UI1557 Certified (File No. E209204) and UL94V−0 Compliant
Applications
• Automotive High Voltage Auxiliary Motors
♦ Climate e−Compressors
♦ Oil / Water Pumps
♦ Super / Turbo Chargers
♦ Variety Fans
Related Resources
• AND9800 − Automotive Smart Power Module, 650 V ASPM27
Series
• AN−9086 − SPM 3 Package Mounting Guide
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
April, 2022 − Rev. 4
NFVA35065L42/D
NFVA35065L42
Integrated Power Functions
• For inverter low−side IGBTs: gate drive circuit,
Short−Circuit Protection (SCP) control supply circuit,
Under−Voltage Lock−Out Protection (UVLO)
• Fault signaling: corresponding to UVLO (low−side
supply) and SC faults
• 650 V−50 A IGBT inverter for three−phase DC/AC
power conversion (Refer to Figure 2)
Integrated Drive, Protection and System Control
Functions
• For inverter high−side IGBTs: gate drive circuit,
high−voltage isolated high−speed level shifting control
circuit, Under−Voltage Lock−Out Protection (UVLO)
• Input interface: active−HIGH interface, works with
3.3/5 V logic, Schmitt−trigger input
PIN CONFIGURATION
DD(WH)
DD(VH)
DD(UH)
Figure 1. Top View
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NFVA35065L42
PIN DESCRIPTIONS
Pin Number
Pin Name
Pin Description
1
V
Low−Side Common Bias Voltage for IC and IGBTs Driving
Common Supply Ground
DD(L)
2
COM
3
IN
Signal Input for Low−Side U−Phase
(UL)
(VL)
(WL)
4
IN
Signal Input for Low−Side V−Phase
5
IN
Signal Input for Low−Side W−Phase
6
V
FO
Fault Output
7
V
C
Output for LVIC Temperature Sensing Voltage Output
Shut Down Input for Short−Circuit Current Detection Input
Signal Input for High−Side U−Phase
TS
8
SC
9
IN
(UH)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
V
High−Side Common Bias Voltage for IC and IGBTs Driving
High−Side Bias Voltage for U−Phase IGBT Driving
High−Side Bias Voltage Ground for U−Phase IGBT Driving
Signal Input for High−Side V−Phase
DD(UH)
V
V
B(U)
S(U)
IN
(VH)
V
High−Side Common Bias Voltage for IC and IGBTs Driving
High−Side Bias Voltage for V−Phase IGBT Driving
High−Side Bias Voltage Ground for V−Phase IGBT Driving
Signal Input for High−Side W−Phase
DD(VH)
V
V
B(V)
S(V)
(WH)
IN
V
High−Side Common Bias Voltage for IC and IGBTs Driving
High−Side Bias Voltage for W−Phase IGBT Driving
High−Side Bias Voltage Ground for W−Phase IGBT Driving
Negative DC−Link Input for U−Phase
DD(WH)
V
V
B(W)
S(W)
N
N
U
Negative DC−Link Input for V−Phase
V
N
Negative DC−Link Input for W−Phase
W
U
Output for U−Phase
V
W
P
Output for V−Phase
Output for W−Phase
Positive DC−Link Input
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NFVA35065L42
INTERNAL EQUIVALENT CIRCUIT AND INPUT/OUTPUT PINS
P (27)
(19) VB(W)
VB
(18) VDD(WH)
VDD
OUT
COM
(17) IN(WH)
W (26)
VS
IN
(20) VS(W)
(15) VB(V)
VB
(14) VDD(VH)
VDD
COM
IN
OUT
VS
(13) IN(VH)
(16) VS(V)
V (25)
(11) VB(U)
VB
(10) VDD(UH)
VDD
COM
IN
OUT
VS
(9) IN(UH)
(12) VS(U)
U (24)
(8) CSC
(7) VTS
(6) VFO
OUT
OUT
CSC
VTS
VFO
NW (23)
NV (22)
NU (21)
(5) IN(WL)
(4) IN (VL)
(3) IN(UL)
IN
IN
IN
(2) COM
(1) VDD(L)
COM
VDD
OUT
NOTES:
1. Inverter low−side is composed of three IGBTs, freewheeling diodes for each IGBT, and one control IC. It has gate drive
and protection functions.
2. Inverter power side is composed of four inverter DC−link input terminals and three inverter output terminals.
3. Inverter high−side is composed of three IGBTs, freewheeling diodes, and three drive ICs for each IGBT.
Figure 2. Internal Block Diagram
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NFVA35065L42
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Conditions
Rating
Unit
INVERTER PART
V
Supply Voltage
Supply Voltage (Surge)
Applied between P−N , N , N
500
575
650
50
V
V
V
A
PN
PN(Surge)
U
V
W
V
Applied between P−N , N , N
U V
W
V
CES
Collector−Emitter Voltage
I
C
Each IGBT Collector Current
T = 100°C, V ≥ 15 V, T ≤ 175°C
C DD J
(Note 4)
I
Each IGBT Collector Current (Peak)
T
= 25°C, T ≤ 175°C, Under 1 ms Pulse
100
A
CP
C
J
Width (Note 4)
P
C
Collector Dissipation
T
C
= 25°C per One Chip (Note 4)
115
W
T
J
Operating Junction Temperature
IGBT and Diode
Driver IC
−40∼175
−40∼150
°C
CONTROL PART
V
Control Supply Voltage
Applied between V
, V −COM
DD(H) DD(L)
20
20
V
V
DD
V
High−Side Control Bias Voltage
Applied between V
−V
, V
−V
,
BS
B(U) S(U) B(V) S(V)
V
−V
B(W) S(W)
V
IN
Input Signal Voltage
Applied between IN
, IN
, IN
,
−0.3∼V +0.3
V
(UH)
(VH)
(WH)
DD
IN
, IN
, IN
−COM
(UL)
(VL)
(WL)
V
Fault Output Supply Voltage
Fault Output Current
Applied between V −COM
−0.3∼V +0.3
V
mA
V
FO
FO
DD
I
Sink Current at V pin
2
FO
FO
V
SC
Current Sensing Input Voltage
Applied between C −COM
−0.3∼V +0.3
SC
DD
TOTAL SYSTEM
t
Short Circuit Withstand Time
V
J
= V ≤ 16.5 V, V ≤ 400 V,
3
ms
SC
DD
BS
PN
T = 150°C
Non−repetitive
T
Storage Temperature
Isolation Voltage
−55∼175
°C
STG
V
60 Hz, Sinusoidal, AC 1 minute,
Connection Pins to Heat Sink Plate
2500
V
rms
ISO
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE
Symbol
Parameter
Conditions
Min.
Typ.
−
Max.
1.30
1.93
−
Unit
°C/W
°C/W
nH
R
Junction to Case Thermal Resistance Inverter IGBT part (per 1/6 module)
Inverter FWD part (per 1/6 module)
−
−
−
th(j−c)Q
R
−
th(j−c)F
L
s
Package Stray Inductance
P to N , N , N (Note 6)
24
U
V
W
4. These values had been made an acquisition by the calculation considered to design factor.
5. For the measurement point of case temperature (T ), please refer to Figure 1. DBC discoloration and Picker Circle Printing allowed, please
C
®
refer to application note AN−9190 (Impact of DBC Oxidation on SPM Module Performance).
6. Stray inductance per phase measured per IEC 60747−15.
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NFVA35065L42
ELECTRICAL CHARACTERISTICS − INVERTER PART
Symbol
Parameter
Conditions
= V = 15 V, V = 5 V,
Min.
Typ.
Max.
Unit
V
Collector − Emitter Saturation Voltage
V
C
−
1.65
2.15
V
CE(SAT)
DD
BS
IN
I
= 50 A, T = 25°C
J
V
C
= V = 15 V, V = 5 V,
2.05
2.65
V
DD
BS
IN
I
= 50 A, T = 175°C
J
V
FWDi Forward Voltage
V
V
V
= 0 V, I = 50 A, T = 25°C
−
1.75
1.70
1.20
0.20
1.30
0.15
0.14
1.00
0.20
1.15
0.25
0.14
−
2.35
2.30
1.85
0.60
1.85
0.45
−
V
V
F
IN
F
J
= 0 V, I = 50 A, T = 175°C
IN
F
J
HS
LS
t
High Side Switching Times
= 300 V, V = 15 V, I = 50 A,
0.75
−
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
mA
ON
PN
DD
C
T = 25°C
J
t
C(ON)
V
IN
= 0 V ⇔ 5 V, Inductive Load
See Figure 4
(Note 7)
t
−
OFF
t
−
C(OFF)
t
rr
−
t
Low Side Switching Times
V
PN
= 300 V, V = 15 V, I = 50 A,
0.60
−
1.60
0.65
1.65
0.60
−
ON
DD
C
T = 25°C
J
t
C(ON)
V
IN
= 0 V ⇔ 5 V, Inductive Load
See Figure 4
(Note 7)
t
−
OFF
t
−
C(OFF)
t
rr
−
I
Collector−Emitter Leakage Current
T = 25°C, V = V
J CES
−
3
CES
CE
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. t and t
include the propagation delay time of the internal drive IC. t
and t
are the switching time of IGBT itself under the
ON
OFF
C(ON)
C(OFF)
given gate driving condition internally. For the detailed information, please see Figure 3.
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Marking
Package
Packing Type
Quantity
NFVA35065L42
NFVA35065L42
ASPM27−CDA
Tube
10
100% I
100% I
C
C
t
rr
I
C
I
C
V
CE
V
CE
V
IN
V
IN
t
ON
t
OFF
t
t
c(OFF)
c(ON)
10% I
C
V
IN(ON)
V
IN(OFF)
10% V
10% I
CE
C
90% I 10% V
C
CE
(a) turn − on
(b) turn − off
Figure 3. Switching Time Definition
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NFVA35065L42
One−Leg Diagram
I
C
D
BS
C
BS
V
V
B
DD
LS Switching
COM
IN
OUT
R
BS
V
S
V
PN
HS Switching
LS Switching
U,V,W
V
Inductor
IN
300 V
V
V
VTS
DD
FO
V
IN
HS Switching
4.7 kW
OUT
5 V
0 V
V
CC
C
SC
V
COM
N
U,V,W
+15 V
V
+5 V
Figure 4. Example Circuit for Switching Test
Figure 5. Switching Loss Characteristics
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
20
40
60
80
[°C]
100
120
140
160
T
LVIC
Figure 6. Temperature Profile of VTS (Typical)
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NFVA35065L42
CONTROL PART (T = 25°C)
J
Symbol
Parameter
Quiescent V Supply Current
Conditions
Min.
Typ.
Max.
Unit
I
V
= 15 V,
(UH,VH.WH)
V
DD(H)
V
DD(L)
V
DD(H)
− COM
− COM
− COM
−
−
0.40
mA
QDDH
DD
DD(H)
IN
= 0 V
I
V
= 15 V,
−
−
−
−
4.80
0.48
mA
mA
QDDL
DD(L)
IN
= 0 V
(UL,VL,WL)
I
Operating V Supply Current
V
DD(H)
= 15 V, f
= 20 kHz,
PDDH
DD
PWM
duty = 50%, applied to one
PWM signal input for
High−Side
I
V
= 15 V, f
= 20 kHz,
V
DD(L)
− COM
−
−
8.80
mA
PDDL
DD(L)
PWM
duty = 50%, applied to one
PWM signal input for
Low−Side
I
Quiescent V Supply Current
V
= 15 V,
(UH,VH.WH)
V
V
V
− V
S(V)
− V
,
−
−
−
−
0.24
4.40
mA
mA
QBS
BS
BS
IN
B(U)
B(V)
B(W)
S(U)
= 0 V
− V
,
,
,
S(W)
I
Operating V Supply Current
V
PWM
= V = 15 V,
V
B(U)
V
B(V)
V
B(W)
− V
− V
,
,
PBS
BS
DD
BS
S(U)
S(V)
− V
f
= 20 kHz, duty = 50%,
applied to one PWM signal
input for High−Side
S(W)
V
Fault Output Voltage
V
= 15 V, V = 0 V, V Circuit: 4.7 kW to 5 V
4.5
−
−
−
V
V
FOH
DD
SC
FO
Pull−up
V
V
DD
= 15 V, V = 1 V, V Circuit: 4.7 kW to 5 V
−
0.50
FOL
SC
FO
Pull−up
V
Short Circuit Trip Level
V
= 15 V (Note 8)
C
− COM
(L)
0.45
9.80
10.3
9.00
9.50
50
0.50
−
0.55
13.3
13.8
12.5
13.0
−
V
V
SC(ref)
DD
SC
UV
Supply Circuit Under−Voltage
Protection
Detection Level
Reset Level
DDD
DDR
BSD
BSR
UV
UV
UV
−
V
Detection Level
Reset Level
−
V
−
V
t
Fault−Out Pulse Width
−
ms
mV
FOD
V
TS
LVIC Temperature Sensing
Voltage Output
V
DD(L)
= 15 V, T = 25°C (Note 9)
LVIC
540
640
740
See Figure x6
V
ON Threshold Voltage
OFF Threshold Voltage
Applied between IN
(UL,VL.WL)
− COM
(UH,VH.WH)
−
−
−
2.60
V
V
IN(ON)
IN
− COM
V
0.80
−
IN(OFF)
8. Short−circuit current protection is functioning only at the low−sides.
9. T is the temperature of LVIC itself. V is only for sensing temperature of LVIC and can not shutdown IGBTs automatically.
LVIC
TS
RECOMMENDED OPERATING CONDITIONS
Value
Typ.
300
15
Min.
−
Max.
400
Symbol
Parameter
Supply Voltage
Conditions
Unit
V
V
Applied between P − N , N , N
PN
DD
U
V
W
V
Control Supply Voltage
Applied between V
− COM, V
− COM
14.0
13.0
16.5
18.5
V
DD(H)
DD(L)
V
BS
High−Side Bias Voltage
Applied between V
− V , V
S(U) B(V)
− V ,
S(V)
15
V
B(U)
V
B(W)
− V
S(W)
dV /dt,
Control Supply Variation
−1
−
−
1
V/ms
ms
DD
dV /dt,
BS
t
Blanking Time for Preventing
Arm−Short
For Each Input Signal
−40°C ≤ T ≤ 125°C, −40°C ≤ T ≤ 150°C
2.0
−
dead
f
PWM Input Signal
−
−
−
40
5
kHz
V
PWM
C
J
V
SEN
Voltage for Current Sensing
Applied between N , N , N − COM
−5
U
V
W
(Including Surge Voltage)
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NFVA35065L42
RECOMMENDED OPERATING CONDITIONS (continued)
PW
PW
Minimum Input Pulse Width
V
= V = 15 V, I ≤ 50 A, Wiring Inductance
1.5
1.5
2.0
2.0
−40
−
−
−
−
−
−
−
ms
ms
°C
IN(ON)
DD
BS
C
between N , , and DC Link N < 10 nH
U V W
(Note 10)
IN(OFF)
PW
V
= V = 15 V, 50 A ≤ I ≤ 100 A, Wiring Induc-
−
IN(ON)
DD
BS
C
tance between N , , and DC Link N < 10 nH
U V W
PW
−
(Note 10)
IN(OFF)
T
Junction Temperature
150
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
10.This product might not make response if input pulse width is less than the recommended value.
MECHANICAL CHARACTERISTICS AND RATINGS
Value
Min.
0
Typ.
−
Max.
+150
0.8
8.1
−
Parameter
Device Flatness
Conditions
Unit
mm
See Figure 7
Mounting Torque
Mounting Screw: M3
See Figure 8
Recommended 0.7 N•m
Recommended 7.1 kg•cm
0.6
6.2
10
2
0.7
7.1
−
N•m
kg•cm
s
Terminal Pulling Strength
Terminal Bending Strength
Weight
Load 19.8 N
Load 9.8 N 90 deg. bend
−
−
times
g
−
15
−
( + )
( + )
Figure 7. Flatness Measurement Position
Pre−Screwing: 1 → 2
Final Screwing: 2 → 1
NOTES:
11. Do not make over torque when mounting screws. Much mounting torque may cause DBC cracks, as well as bolts and Al heat−sink
destruction
12.Avoid one−sided tightening stress. Figure 8 shows the recommended torque order for mounting screws. Uneven mounting can cause
the DBC substrate of package to be damaged. The pre−screwing torque is set to 20 ∼ 30% of maximum torque rating.
Figure 8. Mounting Screws Torque Order
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NFVA35065L42
Input signal
Protection
Circuit State
RESET
a1
SET
RESET
UV
DDR
a6
Control
Supply Voltage
UV
DDD
a3
a4
a2
a7
Output Current
a5
Fault Output Signal
a1: Control supply voltage rises: After the voltage rises UV
a2: Normal operation: IGBT ON and carrying current.
, the circuits start to operate when next input is applied.
DDR
a3: Under voltage detection (UV
).
DDD
a4: IGBT OFF in spite of control input condition.
a5: Fault output operation starts with a fixed pulse width.
a6: Under voltage reset (UV
).
DDR
a7: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 9. Under−Voltage Protection (Low−Side)
Input signal
Protection
RESET
b1
SET
RESET
Circuit State
UV
BSR
b5
Control
Supply Voltage
UV
BSD
b3
b4
b6
b2
Output Current
High−level (no fault output)
Fault Output Signal
b1: Control supply voltage rises: After the voltage rises UV
b2: Normal operation: IGBT ON and carrying current.
, the circuits start to operate when next input is applied.
BSR
b3: Under voltage detection (UV
).
BSD
b4: IGBT OFF in spite of control input condition, but there is no fault output signal.
b5: Under voltage reset (UV ).
BSR
b6: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 10. Under−Voltage Protection (High−Side)
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NFVA35065L42
Lower Arms
Control Input
c6
c7
Protection
Circuit State
SET
RESET
c4
c3
Internal IGBT
Gate−Emitter Voltage
c2
Internal delay
at protection circuit
SC current trip level
c8
c1
Output Current
SC reference voltage
Sensing Voltage
of Sense Resistor
RC filter circuit
time constant
delay
Fault Output Signal
c5
(with the external sense resistance and RC filter connection)
c1: Normal operation: IGBT ON and carrying current.
c2: Short circuit current detection (SC trigger).
c3: All low−side IGBT’s gate are hard interrupted.
c4: All low−side IGBTs turn OFF.
c5: Fault output operation starts with a fixed pulse width.
c6: Input HIGH: IGBT ON state, but during the active period of fault output the IGBT doesn’t turn ON.
c7: Fault output operation finishes, but IGBT doesn’t turn on until triggering next signal from LOW to HIGH.
c8: Normal operation: IGBT ON and carrying current.
Figure 11. Short−Circuit Current Protection (Low−Side Operation Only)
INPUT/OUTPUT INTERFACE CIRCUIT
+5V (MCU or Control power)
4.7 kΩ
SPM
IN
IN
, IN
, IN
(UH)
(VH)
(WH)
, IN
(VL)
, IN
(WL)
(UL)
MCU
VFO
COM
NOTE:
13.RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring impedance
of the application’s printed circuit board. The input signal section of the Motion SPM 3 product integrates 5kW (typ.) pull−down resistor.
Therefore, when using an external filtering resistor, please pay attention to the signal voltage drop at input terminal.
Figure 12. Recommended CPU I/O Interface Circuit
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NFVA35065L42
NOTES:
14.To avoid malfunction, the wiring of each input should be as short as possible. (less than 2−3 cm)
15.V output is open−drain type. The signal line should be pulled up to the positive side of the MCU or control power supply with a resistor
FO
that makes I up to 2mA. Refer to Figure 12.
FO
16.Input signal is active−HIGH type. There is a 5 kW resistor inside the IC to pull−down each input signal line to GND. RC coupling circuits
should be adopted for the prevention of input signal oscillation. R C time constant should be selected in the range 50∼150 ns.
1
1
(Recommended R = 100 W, C = 1 nF)
1
1
17.Each wiring pattern inductance of A point should be minimized (Recommended less than 10 nH). Use the shunt resistor R of surface
4
mounted (SMD) type to reduce wiring inductance. To prevent malfunction, wiring of point E should be connected to the terminal of the
shunt resistor R as close as possible.
4
18.To prevent errors of the protection function, the wiring of B, C and D point should be as short as possible.
19.In the short−circuit protection circuit, please select the R C time constant in the range 1.5∼2 ms.. Do enough evaluation on the real system
6
6
because short−circuit protection time may vary wiring pattern layout and value of the R C time constant.
6
6
20.Each capacitor should be mounted as close to the pins of the ASPM27 product as possible.
21.To prevent surge destruction, the wiring between the smoothing capacitor C and the P & GND pins should be as short as possible.
7
The use of a high−frequency non−inductive capacitor of around 0.1∼ 0.22 mF between the P & GND pins is recommended.
22.Relays are used at almost every systems of electrical equipment at industrial application. In these cases, there should be sufficient
distance between the CPU and the relays.
23.The zener diode or transient voltage suppressor should be adopted for the protection of ICs from the surge destruction between each
pair of control supply terminals (Recommended zener diode is 22 V/1 W. which has the lower zener impedance characteristic than
about 15 W).
24.C of around 7 times larger than bootstrap capacitor C is recommended.
2
3
25.Choose the electrolytic capacitor with good temperature characteristic in C . Also choose 0.1∼0.2 mF R−category ceramic capacitors
3
with good temperature and frequency characteristics in C .
4
Figure 13. Typical Application Circuit
SPM is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the
United States and/or other countries.
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
27LD MODULE PDD STD
CASE MODCB
ISSUE A
DATE 30 JAN 2023
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13500G
27LD MODULE PDD STD
PAGE 1 OF 1
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