NGB15N41CL [ONSEMI]
Ignition IGBT 15 Amps, 410 Volts; 点火IGBT 15安培， 410伏
| 型号： | NGB15N41CL |
| 厂家： | 
ONSEMI |
| 描述： | Ignition IGBT 15 Amps, 410 Volts |
| 文件： | 总11页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NGD15N41CL,
NGB15N41CL,
NGP15N41CL
Preferred Device
Ignition IGBT
15 Amps, 410 Volts
N−Channel DPAK, D2PAK and TO−220
This Logic Level Insulated Gate Bipolar Transistor (IGBT) features
monolithic circuitry integrating ESD and Over−Voltage clamped
protection for use in inductive coil drivers applications. Primary uses
include Ignition, Direct Fuel Injection, or wherever high voltage and
high current switching is required.
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15 AMPS
410 VOLTS
VCE(on) 3 2.1 V @
IC = 10 A, VGE . 4.5 V
C
Features
• Ideal for Coil−on−Plug Applications
• DPAK Package Offers Smaller Footprint and Increased Board Space
• Gate−Emitter ESD Protection
• Temperature Compensated Gate−Collector Voltage Clamp Limits
Stress Applied to Load
R
G
G
R
GE
• Integrated ESD Diode Protection
• New Design Increases Unclamped Inductive Switching (UIS) Energy
E
Per Area
• Low Threshold Voltage to Interface Power Loads to Logic or
Microprocessor Devices
• Low Saturation Voltage
4
DPAK
CASE 369C
STYLE 2
2
1
3
• High Pulsed Current Capability
• Optional Gate Resistor (R ) and Gate−Emitter Resistor (R
)
G
GE
2
4
• Pb−Free Packages are Available
D PAK
CASE 418B
STYLE 4
1
2
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
3
Rating
Collector−Emitter Voltage
Collector−Gate Voltage
Gate−Emitter Voltage
Symbol Value
Unit
V
CES
V
CER
440
440
15
V
V
V
DC
DC
DC
4
V
GE
Collector Current−Continuous
I
15
50
A
A
TO−220AB
CASE 221A
STYLE 9
C
DC
AC
@ T = 25°C − Pulsed
C
ESD (Human Body Model)
ESD
kV
R = 1500 Ω, C = 100 pF
8.0
1
ESD (Machine Model) R = 0 Ω, C = 200 pF
ESD
800
V
2
3
Total Power Dissipation @ T = 25°C
P
107
Watts
C
D
Derate above 25°C
0.71
W/°C
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Operating and Storage Temperature Range
T , T
−55 to
+175
°C
J
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 8 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
May, 2006 − Rev. 7
NGD15N41CL/D
NGD15N41CL, NGB15N41CL, NGP15N41CL
UNCLAMPED COLLECTOR−TO−EMITTER AVALANCHE CHARACTERISTICS (−55° ≤ T ≤ 175°C)
J
Characteristic
Symbol
Value
Unit
Single Pulse Collector−to−Emitter Avalanche Energy
E
mJ
AS
V
V
= 50 V, V = 5.0 V, Pk I = 16.6 A, L = 1.8 mH, Starting T = 25°C
250
200
CC
CC
GE
L
J
= 50 V, V = 5.0 V, Pk I = 15 A, L = 1.8 mH, Starting T = 125°C
GE
L
J
THERMAL CHARACTERISTICS
Characteristic
Symbol
Value
1.4
Unit
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
R
θ
JC
°C/W
DPAK (Note 1)
R
R
R
100
50
θ
JA
JA
JA
L
2
D PAK (Note 1)
θ
θ
TO−220
62.5
275
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds
T
°C
ELECTRICAL CHARACTERISTICS
Characteristic
OFF CHARACTERISTICS
Collector−Emitter Clamp Voltage
Symbol
Test Conditions
Temperature
Min
Typ
Max
Unit
BV
I
= 2.0 mA
= 10 mA
T = −40°C to
380
380
410
410
440
440
V
DC
CES
C
J
150°C
I
T = −40°C to
J
C
150°C
T = 25°C
−
−
2.0
10
1.0
0.7
12
0.1
33
36
31
13
20
40*
10
Zero Gate Voltage Collector Current
I
μA
DC
J
CES
V
V
= 350 V,
CE
T = 150°C
J
= 0 V
GE
T = −40°C
J
−
T = 25°C
J
−
2.0
25*
1.0
37
Reverse Collector−Emitter Leakage Current
Reverse Collector−Emitter Clamp Voltage
I
mA
ECS
V
= −24 V
CE
T = 150°C
J
−
T = −40°C
J
−
T = 25°C
J
27
30
25
11
B
V
V
VCES(R)
DC
I
= −75 mA
C
T = 150°C
J
40
T = −40°C
J
35
Gate−Emitter Clamp Voltage
Gate−Emitter Leakage Current
Gate Resistor
BV
I
= 5.0 mA
T = −40°C to
15
GES
G
J
DC
150°C
I
V
= 10 V
T = −40°C to
384
−
640
70
1000
−
μA
DC
GES
GE
J
150°C
R
G
−
−
T = −40°C to
Ω
J
150°C
Gate Emitter Resistor
R
T = −40°C to
J
10
16
26
Ω
k
GE
150°C
ON CHARACTERISTICS (Note 2)
T = 25°C
1.1
0.75
1.2
−
1.4
1.0
1.6
3.4
1.9
1.4
2.1*
−
Gate Threshold Voltage
V
V
DC
J
GE(th)
I
= 1.0 mA,
C
V
T = 150°C
J
= V
GE
CE
T = −40°C
J
Threshold Temperature Coefficient
(Negative)
−
−
−
mV/°C
1. When surface mounted to an FR4 board using the minimum recommended pad size.
2. Pulse Test: Pulse Width v 300 μS, Duty Cycle v 2%.
*Maximum Value of Characteristic across Temperature Range.
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2
NGD15N41CL, NGB15N41CL, NGP15N41CL
ELECTRICAL CHARACTERISTICS (continued)
Characteristic Symbol
ON CHARACTERISTICS (continued) (Note 3)
Test Conditions
Temperature
Min
Typ
Max
Unit
T = 25°C
1.0
0.9
1.1
1.3
1.2
1.4
1.4
1.5
1.4
1.3
1.3
1.4
8.0
1.6
1.5
1.65
1.8
1.7
1.8
2.0
2.0
2.0
1.9
1.9
1.95
15
1.8
1.8
Collector−to−Emitter On−Voltage
V
V
J
CE(on)
DC
I
V
= 6.0 A,
C
T = 150°C
J
= 4.0 V
GE
T = −40°C
J
1.9*
2.0*
1.9
T = 25°C
J
I
V
= 8.0 A,
C
T = 150°C
J
= 4.0 V
GE
T = −40°C
J
2.0*
2.2
T = 25°C
J
I
V
= 10 A,
C
T = 150°C
J
2.3*
2.2
= 4.0 V
GE
T = −40°C
J
T = 25°C
J
2.1
I
V
= 10 A,
C
T = 150°C
J
2.1
= 4.5 V
GE
T = −40°C
J
2.1*
25
Forward Transconductance
gfs
V
= 5.0 V, I = 6.0 A
T = −40°C to
Mhos
pF
CE
C
J
150°C
DYNAMIC CHARACTERISTICS
Input Capacitance
C
400
30
650
55
1000
100
8.0
ISS
V
= 25 V, V = 0 V
f = 1.0 MHz
T = −40°C to
CC
GE
J
Output Capacitance
C
OSS
RSS
150°C
Transfer Capacitance
C
3.0
4.5
SWITCHING CHARACTERISTICS
Turn−Off Delay Time (Inductive)
T = 25°C
−
−
−
−
−
−
−
−
−
−
−
−
4.0
4.5
6.0
10
10
10
12
12
10
10
15
15
4.0
4.0
7.0
7.0
t
V
= 300 V, I = 6.5 A
= 1.0 kΩ, L = 300 μH
μSec
μSec
μSec
J
d(off)
CC
C
R
G
T = 150°C
J
T = 25°C
J
Fall Time (Inductive)
Turn−Off Delay Time (Resistive)
Fall Time (Resistive)
Turn−On Delay Time
Rise Time
t
V
= 300 V, I = 6.5 A
f
CC
C
R
G
= 1.0 kΩ, L = 300 μH
T = 150°C
J
T = 25°C
J
3.0
3.5
8.0
12
t
t
V
= 300 V, I = 6.5 A
d(off)
CC
C
R
G
= 1.0 kΩ, R = 46 Ω,
L
T = 150°C
J
T = 25°C
J
t
V
= 300 V, I = 6.5 A
f
CC
C
R
= 1.0 kΩ, R = 46 Ω,
G
G
G
L
T = 150°C
J
T = 25°C
J
0.7
0.7
4.0
5.0
V
R
= 10 V, I = 6.5 A
d(on)
CC
C
= 1.0 kΩ, R = 1.5 Ω
L
T = 150°C
J
T = 25°C
J
t
V
R
= 10 V, I = 6.5 A
r
CC
C
= 1.0 kΩ, R = 1.5 Ω
L
T = 150°C
J
3. Pulse Test: Pulse Width v 300 μS, Duty Cycle v 2%.
*Maximum Value of Characteristic across Temperature Range.
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3
NGD15N41CL, NGB15N41CL, NGP15N41CL
TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted)
60
50
40
30
20
10
0
60
V
= 10 V
V
= 10 V
5 V
GE
GE
5 V
4.5 V
50
40
30
20
10
0
4.5 V
4 V
4 V
3.5 V
T = 25°C
T = −40°C
J
J
3.5 V
3 V
3 V
2.5 V
7
2.5 V
7
0
1
2
3
4
5
6
8
0
1
2
3
4
5
6
8
V
, COLLECTOR TO EMITTER VOLTAGE (VOLTS)
CE
V
, COLLECTOR TO EMITTER VOLTAGE (VOLTS)
CE
Figure 1. Output Characteristics
Figure 2. Output Characteristics
30
60
50
40
30
20
10
0
V
= 10 V
CE
V
= 10 V
GE
25
20
15
10
5 V
4.5 V
T = 150°C
J
4 V
3.5 V
3 V
T = 25°C
J
2.5 V
5
0
T = 150°C
J
T = −40°C
J
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
1
2
3
4
5
6
7
8
V
, COLLECTOR TO EMITTER VOLTAGE (VOLTS)
CE
V
, GATE TO EMITTER VOLTAGE (VOLTS)
GE
Figure 3. Output Characteristics
Figure 4. Transfer Characteristics
4.0
3.5
3
V
= 5 V
T = 25°C
J
GE
I
= 25 A
C
2.5
I
= 15 A
C
3.0
2.5
2.0
1.5
1.0
0.5
0.0
I
= 20 A
= 15 A
= 10 A
C
C
I
= 10 A
C
2
1.5
1
I
I
= 5 A
C
I
C
I
= 5 A
C
0.5
0
−50
−25
0
25
50
75
100
125 150
3
4
5
6
7
8
9
10
T , JUNCTION TEMPERATURE (°C)
J
GATE TO EMITTER VOLTAGE (VOLTS)
Figure 5. Collector−to−Emitter Saturation
Voltage versus Junction Temperature
Figure 6. Collector−to−Emitter Voltage versus
Gate−to−Emitter Voltage
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4
NGD15N41CL, NGB15N41CL, NGP15N41CL
10000
3
2.5
2
T = 150°C
J
I
= 15 A
C
C
iss
1000
100
10
I
= 10 A
= 5 A
C
C
oss
I
C
1.5
1
C
rss
1
0
0.5
0
0
20
40 60 80 100 120 140 160 180 200
3
4
5
6
7
8
9
10
GATE TO EMITTER VOLTAGE (VOLTS)
V
, COLLECTOR TO EMITTER VOLTAGE (VOLTS)
CE
Figure 7. Collector−to−Emitter Voltage versus
Gate−to−Emitter Voltage
Figure 8. Capacitance Variation
30
25
20
15
10
5
2
V
V
R
= 50 V
= 5 V
= 1000 Ω
1.8
1.6
1.4
1.2
CC
GE
Mean
Mean + 4 σ
Mean − 4 σ
G
L = 2 mH
L = 3 mH
1
0.8
0.6
0.4
L = 6 mH
0.2
0
0
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
−50 −25
0
25
50
75 100 125 150 175
TEMPERATURE (°C)
Figure 9. Gate Threshold Voltage versus
Temperature
Figure 10. Minimum Open Secondary Latch
Current versus Temperature
30
25
20
15
10
5
12
10
8
V
V
R
= 300 V
= 5 V
= 1000 Ω
V
V
R
= 50 V
= 5 V
= 1000 Ω
CC
GE
CC
GE
G
G
I
= 10 A
C
L = 2 mH
t
L = 300 μH
f
6
4
2
0
L = 3 mH
L = 6 mH
t
d(off)
0
−50 −25
0
25
50
75 100 125 150 175
−50 −30 −10
10
30 50 70 90 110 130 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Typical Open Secondary Latch
Current versus Temperature
Figure 12. Inductive Switching Fall Time
versus Temperature
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5
NGD15N41CL, NGB15N41CL, NGP15N41CL
10
Duty Cycle = 0.5
0.2
0.1
1
0.05
0.02
0.01
0.1
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT T
P
(pk)
1
Single Pulse
t
1
t
T
− T = P
R (t)
θ
JA
2
J(pk)
A
(pk)
R
θ
JC
≅ R(t) for t ≤ 0.2 s
DUTY CYCLE, D = t /t
1
2
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t,TIME (S)
Figure 13. Transient Thermal Resistance
(Non−normalized Junction−to−Ambient mounted on
fixture in Figure 14)
1.5″
4″
4″
0.125″
4″
Figure 14. Test Fixture for Transient Thermal Curve
(48 square inches of 1/8, thick aluminum)
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6
NGD15N41CL, NGB15N41CL, NGP15N41CL
100
10
100
DC
10
DC
100 μs
1 ms
100 μs
1
1
10 ms
1 ms
100 ms
10 ms
0.1
0.1
100 ms
0.01
0.01
1
10
100
1000
1
10
100
1000
COLLECTOR−EMITTER VOLTAGE (VOLTS)
COLLECTOR−EMITTER VOLTAGE (VOLTS)
Figure 15. Single Pulse Safe Operating Area
Figure 16. Single Pulse Safe Operating Area
(Mounted on an Infinite Heatsink at TA = 255C)
(Mounted on an Infinite Heatsink at TA = 1255C)
100
10
100
10
t = 1 ms, D = 0.05
1
t = 1 ms, D = 0.05
1
t = 2 ms, D = 0.10
1
t = 2 ms, D = 0.10
1
t = 3 ms, D = 0.30
1
t = 3 ms, D = 0.30
1
1
1
I
(pk)
I
(pk)
t
1
t
1
0.1
0.01
0.1
t
2
t
2
DUTY CYCLE, D = t /t
DUTY CYCLE, D = t /t
1
2
1
2
0.01
1
10
100
1000
1
10
100
1000
COLLECTOR−EMITTER VOLTAGE (VOLTS)
COLLECTOR−EMITTER VOLTAGE (VOLTS)
Figure 17. Pulse Train Safe Operating Area
Figure 18. Pulse Train Safe Operating Area
(Mounted on an Infinite Heatsink at TC = 255C)
(Mounted on an Infinite Heatsink at TC = 1255C)
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7
NGD15N41CL, NGB15N41CL, NGP15N41CL
ORDERING INFORMATION
Device
†
Package Type
Shipping
NGD15N41CLT4
DPAK
2500/Tape & Reel
DPAK
(Pb−Free)
NGD15N41CLT4G
NGB15N41CLT4
2500/Tape & Reel
800/Tape & Reel
2
D PAK
2
D PAK
(Pb−Free)
NGB15N41CLT4G
NGP15N41CL
800/Tape & Reel
50 Units/Rail
TO−220
TO−220
(Pb−Free)
NGP15N41CLG
50 Units/Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
MARKING DIAGRAMS
2
DPAK
CASE 369C
STYLE 7
D PAK
CASE 418B
STYLE 4
TO−220AB
CASE 221A
STYLE 9
4
Collector
4
Collector
1
Gate
YWW
GD
15N41G
NGB
15N41CLG
AYWW
4
NGP
15N41CLG
AYWW
2
Collector
Collector
3
1
Gate
3
1
Gate
3
Emitter
Emitter
Emitter
2
Collector
2
Collector
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Device
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8
NGD15N41CL, NGB15N41CL, NGP15N41CL
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
SEATING
−T−
PLANE
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
4
2
Z
A
K
S
1
3
4.58 BSC
U
0.87
0.46
2.60
1.01
0.58
2.89
K
L
2.29 BSC
F
J
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
L
H
0.020
0.035 0.050
0.155 −−−
−−−
D 2 PL
M
STYLE 2:
PIN 1. GATE
2. DRAIN
G
0.13 (0.005)
T
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
NGD15N41CL, NGB15N41CL, NGP15N41CL
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING
C
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
E
V
W
−B−
INCHES
DIM MIN MAX
MILLIMETERS
4
MIN
MAX
A
B
C
D
E
F
G
H
J
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
4.83
0.89
1.40
8.89
A
S
1
2
3
2.54 BSC
0.080
0.018 0.025
0.090 0.110
0.110
2.03
0.46
2.29
1.32
7.11
5.00 REF
2.00 REF
0.99 REF
2.79
0.64
2.79
1.83
8.13
−T−
SEATING
PLANE
K
K
L
W
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625 14.60 15.88
0.045 0.055 1.14 1.40
J
G
M
N
P
R
S
V
H
D 3 PL
M
M
T B
0.13 (0.005)
STYLE 4:
PIN 1. GATE
2. COLLECTOR
VARIABLE
CONFIGURATION
ZONE
3. EMITTER
4. COLLECTOR
N
P
R
U
L
L
L
M
M
M
F
F
F
VIEW W−W
VIEW W−W
VIEW W−W
1
2
3
SOLDERING FOOTPRINT*
8.38
0.33
10.66
0.42
1.016
0.04
6.096
0.24
3.05
0.12
17.02
0.67
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
10
NGD15N41CL, NGB15N41CL, NGP15N41CL
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
SEATING
PLANE
−T−
C
B
F
T
S
INCHES
DIM MIN MAX
MILLIMETERS
4
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
0.508
5.97
0.00
1.15
−−−
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
−−−
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.020
0.235
0.000
0.045
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
−−−
A
K
Q
Z
1
2
3
U
H
G
H
J
K
L
N
Q
R
S
T
L
R
V
J
G
U
V
Z
D
−−− 0.080
2.04
N
STYLE 9:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NGD15N41CL/D
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